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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_cec.h 00004 * @author MCD Application Team 00005 * @brief Header file of CEC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F1xx_HAL_CEC_H 00022 #define __STM32F1xx_HAL_CEC_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx_hal_def.h" 00030 00031 #if defined (CEC) 00032 00033 /** @addtogroup STM32F1xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup CEC 00038 * @{ 00039 */ 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 /** @defgroup CEC_Exported_Types CEC Exported Types 00043 * @{ 00044 */ 00045 /** 00046 * @brief CEC Init Structure definition 00047 */ 00048 typedef struct 00049 { 00050 uint32_t TimingErrorFree; /*!< Configures the CEC Bit Timing Error Mode. 00051 This parameter can be a value of @ref CEC_BitTimingErrorMode */ 00052 uint32_t PeriodErrorFree; /*!< Configures the CEC Bit Period Error Mode. 00053 This parameter can be a value of @ref CEC_BitPeriodErrorMode */ 00054 uint16_t OwnAddress; /*!< Own addresses configuration 00055 This parameter can be a value of @ref CEC_OWN_ADDRESS */ 00056 uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */ 00057 }CEC_InitTypeDef; 00058 00059 /** 00060 * @brief HAL CEC State structures definition 00061 * @note HAL CEC State value is a combination of 2 different substates: gState and RxState. 00062 * - gState contains CEC state information related to global Handle management 00063 * and also information related to Tx operations. 00064 * gState value coding follow below described bitmap : 00065 * b7 (not used) 00066 * x : Should be set to 0 00067 * b6 Error information 00068 * 0 : No Error 00069 * 1 : Error 00070 * b5 IP initilisation status 00071 * 0 : Reset (IP not initialized) 00072 * 1 : Init done (IP initialized. HAL CEC Init function already called) 00073 * b4-b3 (not used) 00074 * xx : Should be set to 00 00075 * b2 Intrinsic process state 00076 * 0 : Ready 00077 * 1 : Busy (IP busy with some configuration or internal operations) 00078 * b1 (not used) 00079 * x : Should be set to 0 00080 * b0 Tx state 00081 * 0 : Ready (no Tx operation ongoing) 00082 * 1 : Busy (Tx operation ongoing) 00083 * - RxState contains information related to Rx operations. 00084 * RxState value coding follow below described bitmap : 00085 * b7-b6 (not used) 00086 * xx : Should be set to 00 00087 * b5 IP initilisation status 00088 * 0 : Reset (IP not initialized) 00089 * 1 : Init done (IP initialized) 00090 * b4-b2 (not used) 00091 * xxx : Should be set to 000 00092 * b1 Rx state 00093 * 0 : Ready (no Rx operation ongoing) 00094 * 1 : Busy (Rx operation ongoing) 00095 * b0 (not used) 00096 * x : Should be set to 0. 00097 */ 00098 typedef enum 00099 { 00100 HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized 00101 Value is allowed for gState and RxState */ 00102 HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use 00103 Value is allowed for gState and RxState */ 00104 HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing 00105 Value is allowed for gState only */ 00106 HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing 00107 Value is allowed for RxState only */ 00108 HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing 00109 Value is allowed for gState only */ 00110 HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing 00111 Value is allowed for gState only */ 00112 HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */ 00113 }HAL_CEC_StateTypeDef; 00114 00115 /** 00116 * @brief CEC handle Structure definition 00117 */ 00118 typedef struct __CEC_HandleTypeDef 00119 { 00120 CEC_TypeDef *Instance; /*!< CEC registers base address */ 00121 00122 CEC_InitTypeDef Init; /*!< CEC communication parameters */ 00123 00124 uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */ 00125 00126 uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */ 00127 00128 uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */ 00129 00130 HAL_LockTypeDef Lock; /*!< Locking object */ 00131 00132 HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management 00133 and also related to Tx operations. 00134 This parameter can be a value of @ref HAL_CEC_StateTypeDef */ 00135 00136 HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations. 00137 This parameter can be a value of @ref HAL_CEC_StateTypeDef */ 00138 00139 uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register 00140 in case error is reported */ 00141 00142 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 00143 void (* TxCpltCallback) ( struct __CEC_HandleTypeDef * hcec); /*!< CEC Tx Transfer completed callback */ 00144 void (* RxCpltCallback) ( struct __CEC_HandleTypeDef * hcec, uint32_t RxFrameSize); /*!< CEC Rx Transfer completed callback */ 00145 void (* ErrorCallback) ( struct __CEC_HandleTypeDef * hcec); /*!< CEC error callback */ 00146 00147 void (* MspInitCallback) ( struct __CEC_HandleTypeDef * hcec); /*!< CEC Msp Init callback */ 00148 void (* MspDeInitCallback) ( struct __CEC_HandleTypeDef * hcec); /*!< CEC Msp DeInit callback */ 00149 00150 #endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */ 00151 }CEC_HandleTypeDef; 00152 00153 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 00154 /** 00155 * @brief HAL CEC Callback ID enumeration definition 00156 */ 00157 typedef enum 00158 { 00159 HAL_CEC_TX_CPLT_CB_ID = 0x00U, /*!< CEC Tx Transfer completed callback ID */ 00160 HAL_CEC_RX_CPLT_CB_ID = 0x01U, /*!< CEC Rx Transfer completed callback ID */ 00161 HAL_CEC_ERROR_CB_ID = 0x02U, /*!< CEC error callback ID */ 00162 HAL_CEC_MSPINIT_CB_ID = 0x03U, /*!< CEC Msp Init callback ID */ 00163 HAL_CEC_MSPDEINIT_CB_ID = 0x04U /*!< CEC Msp DeInit callback ID */ 00164 }HAL_CEC_CallbackIDTypeDef; 00165 00166 /** 00167 * @brief HAL CEC Callback pointer definition 00168 */ 00169 typedef void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef * hcec); /*!< pointer to an CEC callback function */ 00170 typedef void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef * hcec, uint32_t RxFrameSize); /*!< pointer to an Rx Transfer completed callback function */ 00171 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 00172 /** 00173 * @} 00174 */ 00175 00176 /* Exported constants --------------------------------------------------------*/ 00177 /** @defgroup CEC_Exported_Constants CEC Exported Constants 00178 * @{ 00179 */ 00180 00181 /** @defgroup CEC_Error_Code CEC Error Code 00182 * @{ 00183 */ 00184 #define HAL_CEC_ERROR_NONE 0x00000000U /*!< no error */ 00185 #define HAL_CEC_ERROR_BTE CEC_ESR_BTE /*!< Bit Timing Error */ 00186 #define HAL_CEC_ERROR_BPE CEC_ESR_BPE /*!< Bit Period Error */ 00187 #define HAL_CEC_ERROR_RBTFE CEC_ESR_RBTFE /*!< Rx Block Transfer Finished Error */ 00188 #define HAL_CEC_ERROR_SBE CEC_ESR_SBE /*!< Start Bit Error */ 00189 #define HAL_CEC_ERROR_ACKE CEC_ESR_ACKE /*!< Block Acknowledge Error */ 00190 #define HAL_CEC_ERROR_LINE CEC_ESR_LINE /*!< Line Error */ 00191 #define HAL_CEC_ERROR_TBTFE CEC_ESR_TBTFE /*!< Tx Block Transfer Finished Error */ 00192 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 00193 #define HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U) /*!< Invalid Callback Error */ 00194 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 00195 /** 00196 * @} 00197 */ 00198 00199 /** @defgroup CEC_BitTimingErrorMode Bit Timing Error Mode 00200 * @{ 00201 */ 00202 #define CEC_BIT_TIMING_ERROR_MODE_STANDARD 0x00000000U /*!< Bit timing error Standard Mode */ 00203 #define CEC_BIT_TIMING_ERROR_MODE_ERRORFREE CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ 00204 /** 00205 * @} 00206 */ 00207 00208 /** @defgroup CEC_BitPeriodErrorMode Bit Period Error Mode 00209 * @{ 00210 */ 00211 #define CEC_BIT_PERIOD_ERROR_MODE_STANDARD 0x00000000U /*!< Bit period error Standard Mode */ 00212 #define CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header 00218 * @{ 00219 */ 00220 #define CEC_INITIATOR_LSB_POS 4U 00221 /** 00222 * @} 00223 */ 00224 00225 /** @defgroup CEC_OWN_ADDRESS CEC Own Address 00226 * @{ 00227 */ 00228 #define CEC_OWN_ADDRESS_NONE CEC_OWN_ADDRESS_0 /* Reset value */ 00229 #define CEC_OWN_ADDRESS_0 ((uint16_t)0x0000U) /* Logical Address 0 */ 00230 #define CEC_OWN_ADDRESS_1 ((uint16_t)0x0001U) /* Logical Address 1 */ 00231 #define CEC_OWN_ADDRESS_2 ((uint16_t)0x0002U) /* Logical Address 2 */ 00232 #define CEC_OWN_ADDRESS_3 ((uint16_t)0x0003U) /* Logical Address 3 */ 00233 #define CEC_OWN_ADDRESS_4 ((uint16_t)0x0004U) /* Logical Address 4 */ 00234 #define CEC_OWN_ADDRESS_5 ((uint16_t)0x0005U) /* Logical Address 5 */ 00235 #define CEC_OWN_ADDRESS_6 ((uint16_t)0x0006U) /* Logical Address 6 */ 00236 #define CEC_OWN_ADDRESS_7 ((uint16_t)0x0007U) /* Logical Address 7 */ 00237 #define CEC_OWN_ADDRESS_8 ((uint16_t)0x0008U) /* Logical Address 8 */ 00238 #define CEC_OWN_ADDRESS_9 ((uint16_t)0x0009U) /* Logical Address 9 */ 00239 #define CEC_OWN_ADDRESS_10 ((uint16_t)0x000AU) /* Logical Address 10 */ 00240 #define CEC_OWN_ADDRESS_11 ((uint16_t)0x000BU) /* Logical Address 11 */ 00241 #define CEC_OWN_ADDRESS_12 ((uint16_t)0x000CU) /* Logical Address 12 */ 00242 #define CEC_OWN_ADDRESS_13 ((uint16_t)0x000DU) /* Logical Address 13 */ 00243 #define CEC_OWN_ADDRESS_14 ((uint16_t)0x000EU) /* Logical Address 14 */ 00244 #define CEC_OWN_ADDRESS_15 ((uint16_t)0x000FU) /* Logical Address 15 */ 00245 /** 00246 * @} 00247 */ 00248 00249 /** @defgroup CEC_Interrupts_Definitions Interrupts definition 00250 * @{ 00251 */ 00252 #define CEC_IT_IE CEC_CFGR_IE 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup CEC_Flags_Definitions Flags definition 00258 * @{ 00259 */ 00260 #define CEC_FLAG_TSOM CEC_CSR_TSOM 00261 #define CEC_FLAG_TEOM CEC_CSR_TEOM 00262 #define CEC_FLAG_TERR CEC_CSR_TERR 00263 #define CEC_FLAG_TBTRF CEC_CSR_TBTRF 00264 #define CEC_FLAG_RSOM CEC_CSR_RSOM 00265 #define CEC_FLAG_REOM CEC_CSR_REOM 00266 #define CEC_FLAG_RERR CEC_CSR_RERR 00267 #define CEC_FLAG_RBTF CEC_CSR_RBTF 00268 /** 00269 * @} 00270 */ 00271 00272 /** 00273 * @} 00274 */ 00275 00276 /* Exported macros -----------------------------------------------------------*/ 00277 /** @defgroup CEC_Exported_Macros CEC Exported Macros 00278 * @{ 00279 */ 00280 00281 /** @brief Reset CEC handle gstate & RxState 00282 * @param __HANDLE__: CEC handle. 00283 * @retval None 00284 */ 00285 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 00286 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00287 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ 00288 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ 00289 (__HANDLE__)->MspInitCallback = NULL; \ 00290 (__HANDLE__)->MspDeInitCallback = NULL; \ 00291 } while(0) 00292 #else 00293 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00294 (__HANDLE__)->gState = HAL_CEC_STATE_RESET; \ 00295 (__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \ 00296 } while(0) 00297 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 00298 00299 /** @brief Checks whether or not the specified CEC interrupt flag is set. 00300 * @param __HANDLE__: specifies the CEC Handle. 00301 * @param __FLAG__: specifies the flag to check. 00302 * @arg CEC_FLAG_TERR: Tx Error 00303 * @arg CEC_FLAG_TBTRF:Tx Block Transfer Finished 00304 * @arg CEC_FLAG_RERR: Rx Error 00305 * @arg CEC_FLAG_RBTF: Rx Block Transfer Finished 00306 * @retval ITStatus 00307 */ 00308 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) READ_BIT((__HANDLE__)->Instance->CSR,(__FLAG__)) 00309 00310 /** @brief Clears the CEC's pending flags. 00311 * @param __HANDLE__: specifies the CEC Handle. 00312 * @param __FLAG__: specifies the flag to clear. 00313 * This parameter can be any combination of the following values: 00314 * @arg CEC_CSR_TERR: Tx Error 00315 * @arg CEC_FLAG_TBTRF: Tx Block Transfer Finished 00316 * @arg CEC_CSR_RERR: Rx Error 00317 * @arg CEC_CSR_RBTF: Rx Block Transfer Finished 00318 * @retval none 00319 */ 00320 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 00321 do { \ 00322 uint32_t tmp = 0x0U; \ 00323 tmp = (__HANDLE__)->Instance->CSR & 0x00000002U; \ 00324 (__HANDLE__)->Instance->CSR &= (uint32_t)(((~(uint32_t)(__FLAG__)) & 0xFFFFFFFCU) | tmp);\ 00325 } while(0U) 00326 00327 /** @brief Enables the specified CEC interrupt. 00328 * @param __HANDLE__: specifies the CEC Handle. 00329 * @param __INTERRUPT__: specifies the CEC interrupt to enable. 00330 * This parameter can be: 00331 * @arg CEC_IT_IE : Interrupt Enable. 00332 * @retval none 00333 */ 00334 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__)) 00335 00336 /** @brief Disables the specified CEC interrupt. 00337 * @param __HANDLE__: specifies the CEC Handle. 00338 * @param __INTERRUPT__: specifies the CEC interrupt to disable. 00339 * This parameter can be: 00340 * @arg CEC_IT_IE : Interrupt Enable 00341 * @retval none 00342 */ 00343 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__)) 00344 00345 /** @brief Checks whether or not the specified CEC interrupt is enabled. 00346 * @param __HANDLE__: specifies the CEC Handle. 00347 * @param __INTERRUPT__: specifies the CEC interrupt to check. 00348 * This parameter can be: 00349 * @arg CEC_IT_IE : Interrupt Enable 00350 * @retval FlagStatus 00351 */ 00352 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) READ_BIT((__HANDLE__)->Instance->CFGR, (__INTERRUPT__)) 00353 00354 /** @brief Enables the CEC device 00355 * @param __HANDLE__: specifies the CEC Handle. 00356 * @retval none 00357 */ 00358 #define __HAL_CEC_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE) 00359 00360 /** @brief Disables the CEC device 00361 * @param __HANDLE__: specifies the CEC Handle. 00362 * @retval none 00363 */ 00364 #define __HAL_CEC_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_PE) 00365 00366 /** @brief Set Transmission Start flag 00367 * @param __HANDLE__: specifies the CEC Handle. 00368 * @retval none 00369 */ 00370 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM) 00371 00372 /** @brief Set Transmission End flag 00373 * @param __HANDLE__: specifies the CEC Handle. 00374 * @retval none 00375 */ 00376 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM) 00377 00378 /** @brief Get Transmission Start flag 00379 * @param __HANDLE__: specifies the CEC Handle. 00380 * @retval FlagStatus 00381 */ 00382 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TSOM) 00383 00384 /** @brief Get Transmission End flag 00385 * @param __HANDLE__: specifies the CEC Handle. 00386 * @retval FlagStatus 00387 */ 00388 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) READ_BIT((__HANDLE__)->Instance->CSR, CEC_CSR_TEOM) 00389 00390 /** @brief Clear OAR register 00391 * @param __HANDLE__: specifies the CEC Handle. 00392 * @retval none 00393 */ 00394 #define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->OAR, CEC_OAR_OA) 00395 00396 /** @brief Set OAR register 00397 * @param __HANDLE__: specifies the CEC Handle. 00398 * @param __ADDRESS__: Own Address value. 00399 * @retval none 00400 */ 00401 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) MODIFY_REG((__HANDLE__)->Instance->OAR, CEC_OAR_OA, (__ADDRESS__)); 00402 00403 /** 00404 * @} 00405 */ 00406 00407 /* Exported functions --------------------------------------------------------*/ 00408 /** @addtogroup CEC_Exported_Functions CEC Exported Functions 00409 * @{ 00410 */ 00411 00412 /** @addtogroup CEC_Exported_Functions_Group1 Initialization and de-initialization functions 00413 * @brief Initialization and Configuration functions 00414 * @{ 00415 */ 00416 /* Initialization and de-initialization functions ****************************/ 00417 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec); 00418 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec); 00419 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress); 00420 void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec); 00421 void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec); 00422 #if (USE_HAL_CEC_REGISTER_CALLBACKS == 1) 00423 HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID, pCEC_CallbackTypeDef pCallback); 00424 HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID); 00425 00426 HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback); 00427 HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec); 00428 #endif /* USE_HAL_CEC_REGISTER_CALLBACKS */ 00429 /** 00430 * @} 00431 */ 00432 00433 /** @addtogroup CEC_Exported_Functions_Group2 Input and Output operation functions 00434 * @brief CEC Transmit/Receive functions 00435 * @{ 00436 */ 00437 /* I/O operation functions ***************************************************/ 00438 HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size); 00439 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec); 00440 void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer); 00441 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec); 00442 void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec); 00443 void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize); 00444 void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec); 00445 /** 00446 * @} 00447 */ 00448 00449 /** @defgroup CEC_Exported_Functions_Group3 Peripheral Control functions 00450 * @brief CEC control functions 00451 * @{ 00452 */ 00453 /* Peripheral State and Error functions ***************************************/ 00454 HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec); 00455 uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec); 00456 /** 00457 * @} 00458 */ 00459 00460 /** 00461 * @} 00462 */ 00463 00464 /* Private types -------------------------------------------------------------*/ 00465 /** @defgroup CEC_Private_Types CEC Private Types 00466 * @{ 00467 */ 00468 00469 /** 00470 * @} 00471 */ 00472 00473 /* Private variables ---------------------------------------------------------*/ 00474 /** @defgroup CEC_Private_Variables CEC Private Variables 00475 * @{ 00476 */ 00477 00478 /** 00479 * @} 00480 */ 00481 00482 /* Private constants ---------------------------------------------------------*/ 00483 /** @defgroup CEC_Private_Constants CEC Private Constants 00484 * @{ 00485 */ 00486 00487 /** 00488 * @} 00489 */ 00490 00491 /* Private macros ------------------------------------------------------------*/ 00492 /** @defgroup CEC_Private_Macros CEC Private Macros 00493 * @{ 00494 */ 00495 #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BIT_TIMING_ERROR_MODE_STANDARD) || \ 00496 ((MODE) == CEC_BIT_TIMING_ERROR_MODE_ERRORFREE)) 00497 00498 #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BIT_PERIOD_ERROR_MODE_STANDARD) || \ 00499 ((MODE) == CEC_BIT_PERIOD_ERROR_MODE_FLEXIBLE)) 00500 00501 /** @brief Check CEC message size. 00502 * The message size is the payload size: without counting the header, 00503 * it varies from 0 byte (ping operation, one header only, no payload) to 00504 * 15 bytes (1 opcode and up to 14 operands following the header). 00505 * @param __SIZE__: CEC message size. 00506 * @retval Test result (TRUE or FALSE). 00507 */ 00508 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U) 00509 /** @brief Check CEC device Own Address Register (OAR) setting. 00510 * @param __ADDRESS__: CEC own address. 00511 * @retval Test result (TRUE or FALSE). 00512 */ 00513 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU) 00514 00515 /** @brief Check CEC initiator or destination logical address setting. 00516 * Initiator and destination addresses are coded over 4 bits. 00517 * @param __ADDRESS__: CEC initiator or logical address. 00518 * @retval Test result (TRUE or FALSE). 00519 */ 00520 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0000000FU) 00521 00522 00523 00524 /** 00525 * @} 00526 */ 00527 /* Private functions ---------------------------------------------------------*/ 00528 /** @defgroup CEC_Private_Functions CEC Private Functions 00529 * @{ 00530 */ 00531 00532 /** 00533 * @} 00534 */ 00535 00536 /** 00537 * @} 00538 */ 00539 00540 /** 00541 * @} 00542 */ 00543 00544 #endif /* CEC */ 00545 00546 #ifdef __cplusplus 00547 } 00548 #endif 00549 00550 #endif /* __STM32F1xx_HAL_CEC_H */ 00551 00552 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1