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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F1xx_HAL_CORTEX_H 00022 #define __STM32F1xx_HAL_CORTEX_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx_hal_def.h" 00030 00031 /** @addtogroup STM32F1xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup CORTEX 00036 * @{ 00037 */ 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup CORTEX_Exported_Types Cortex Exported Types 00040 * @{ 00041 */ 00042 00043 #if (__MPU_PRESENT == 1U) 00044 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 00045 * @brief MPU Region initialization structure 00046 * @{ 00047 */ 00048 typedef struct 00049 { 00050 uint8_t Enable; /*!< Specifies the status of the region. 00051 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 00052 uint8_t Number; /*!< Specifies the number of the region to protect. 00053 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 00054 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 00055 uint8_t Size; /*!< Specifies the size of the region to protect. 00056 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 00057 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 00058 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00059 uint8_t TypeExtField; /*!< Specifies the TEX field level. 00060 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 00061 uint8_t AccessPermission; /*!< Specifies the region access permission type. 00062 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 00063 uint8_t DisableExec; /*!< Specifies the instruction access status. 00064 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 00065 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 00066 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 00067 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 00068 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 00069 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 00070 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 00071 }MPU_Region_InitTypeDef; 00072 /** 00073 * @} 00074 */ 00075 #endif /* __MPU_PRESENT */ 00076 00077 /** 00078 * @} 00079 */ 00080 00081 /* Exported constants --------------------------------------------------------*/ 00082 00083 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 00084 * @{ 00085 */ 00086 00087 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 00088 * @{ 00089 */ 00090 #define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority 00091 4 bits for subpriority */ 00092 #define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority 00093 3 bits for subpriority */ 00094 #define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority 00095 2 bits for subpriority */ 00096 #define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority 00097 1 bits for subpriority */ 00098 #define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority 00099 0 bits for subpriority */ 00100 /** 00101 * @} 00102 */ 00103 00104 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 00105 * @{ 00106 */ 00107 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U 00108 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U 00109 00110 /** 00111 * @} 00112 */ 00113 00114 #if (__MPU_PRESENT == 1) 00115 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control 00116 * @{ 00117 */ 00118 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 00119 #define MPU_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk 00120 #define MPU_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk 00121 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 00122 00123 /** 00124 * @} 00125 */ 00126 00127 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 00128 * @{ 00129 */ 00130 #define MPU_REGION_ENABLE ((uint8_t)0x01) 00131 #define MPU_REGION_DISABLE ((uint8_t)0x00) 00132 /** 00133 * @} 00134 */ 00135 00136 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 00137 * @{ 00138 */ 00139 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 00140 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 00141 /** 00142 * @} 00143 */ 00144 00145 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 00146 * @{ 00147 */ 00148 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 00149 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 00150 /** 00151 * @} 00152 */ 00153 00154 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 00155 * @{ 00156 */ 00157 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 00158 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 00159 /** 00160 * @} 00161 */ 00162 00163 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 00164 * @{ 00165 */ 00166 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 00167 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 00168 /** 00169 * @} 00170 */ 00171 00172 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels 00173 * @{ 00174 */ 00175 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 00176 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 00177 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 00178 /** 00179 * @} 00180 */ 00181 00182 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 00183 * @{ 00184 */ 00185 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 00186 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 00187 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 00188 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 00189 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 00190 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 00191 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 00192 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 00193 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 00194 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 00195 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 00196 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 00197 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 00198 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 00199 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 00200 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 00201 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 00202 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 00203 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 00204 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 00205 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 00206 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 00207 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 00208 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 00209 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 00210 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 00211 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 00212 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 00218 * @{ 00219 */ 00220 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 00221 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 00222 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 00223 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 00224 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 00225 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 00226 /** 00227 * @} 00228 */ 00229 00230 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 00231 * @{ 00232 */ 00233 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 00234 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 00235 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 00236 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 00237 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 00238 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 00239 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 00240 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 00241 /** 00242 * @} 00243 */ 00244 #endif /* __MPU_PRESENT */ 00245 00246 /** 00247 * @} 00248 */ 00249 00250 00251 /* Exported Macros -----------------------------------------------------------*/ 00252 00253 /* Exported functions --------------------------------------------------------*/ 00254 /** @addtogroup CORTEX_Exported_Functions 00255 * @{ 00256 */ 00257 00258 /** @addtogroup CORTEX_Exported_Functions_Group1 00259 * @{ 00260 */ 00261 /* Initialization and de-initialization functions *****************************/ 00262 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 00263 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 00264 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 00265 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 00266 void HAL_NVIC_SystemReset(void); 00267 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 00268 /** 00269 * @} 00270 */ 00271 00272 /** @addtogroup CORTEX_Exported_Functions_Group2 00273 * @{ 00274 */ 00275 /* Peripheral Control functions ***********************************************/ 00276 uint32_t HAL_NVIC_GetPriorityGrouping(void); 00277 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 00278 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 00279 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 00280 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 00281 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 00282 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 00283 void HAL_SYSTICK_IRQHandler(void); 00284 void HAL_SYSTICK_Callback(void); 00285 00286 #if (__MPU_PRESENT == 1U) 00287 void HAL_MPU_Enable(uint32_t MPU_Control); 00288 void HAL_MPU_Disable(void); 00289 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 00290 #endif /* __MPU_PRESENT */ 00291 /** 00292 * @} 00293 */ 00294 00295 /** 00296 * @} 00297 */ 00298 00299 /* Private types -------------------------------------------------------------*/ 00300 /* Private variables ---------------------------------------------------------*/ 00301 /* Private constants ---------------------------------------------------------*/ 00302 /* Private macros ------------------------------------------------------------*/ 00303 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 00304 * @{ 00305 */ 00306 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 00307 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 00308 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 00309 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 00310 ((GROUP) == NVIC_PRIORITYGROUP_4)) 00311 00312 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 00313 00314 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U) 00315 00316 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= (IRQn_Type)0x00U) 00317 00318 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 00319 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 00320 00321 #if (__MPU_PRESENT == 1U) 00322 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 00323 ((STATE) == MPU_REGION_DISABLE)) 00324 00325 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 00326 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 00327 00328 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 00329 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 00330 00331 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 00332 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 00333 00334 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 00335 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 00336 00337 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 00338 ((TYPE) == MPU_TEX_LEVEL1) || \ 00339 ((TYPE) == MPU_TEX_LEVEL2)) 00340 00341 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 00342 ((TYPE) == MPU_REGION_PRIV_RW) || \ 00343 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 00344 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 00345 ((TYPE) == MPU_REGION_PRIV_RO) || \ 00346 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 00347 00348 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 00349 ((NUMBER) == MPU_REGION_NUMBER1) || \ 00350 ((NUMBER) == MPU_REGION_NUMBER2) || \ 00351 ((NUMBER) == MPU_REGION_NUMBER3) || \ 00352 ((NUMBER) == MPU_REGION_NUMBER4) || \ 00353 ((NUMBER) == MPU_REGION_NUMBER5) || \ 00354 ((NUMBER) == MPU_REGION_NUMBER6) || \ 00355 ((NUMBER) == MPU_REGION_NUMBER7)) 00356 00357 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 00358 ((SIZE) == MPU_REGION_SIZE_64B) || \ 00359 ((SIZE) == MPU_REGION_SIZE_128B) || \ 00360 ((SIZE) == MPU_REGION_SIZE_256B) || \ 00361 ((SIZE) == MPU_REGION_SIZE_512B) || \ 00362 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 00363 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 00364 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 00365 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 00366 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 00367 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 00368 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 00369 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 00370 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 00371 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 00372 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 00373 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 00374 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 00375 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 00376 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 00377 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 00378 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 00379 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 00380 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 00381 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 00382 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 00383 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 00384 ((SIZE) == MPU_REGION_SIZE_4GB)) 00385 00386 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 00387 #endif /* __MPU_PRESENT */ 00388 00389 /** 00390 * @} 00391 */ 00392 00393 /* Private functions ---------------------------------------------------------*/ 00394 00395 /** 00396 * @} 00397 */ 00398 00399 /** 00400 * @} 00401 */ 00402 00403 #ifdef __cplusplus 00404 } 00405 #endif 00406 00407 #endif /* __STM32F1xx_HAL_CORTEX_H */ 00408 00409 00410 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1