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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F1xx_HAL_DMA_H 00022 #define __STM32F1xx_HAL_DMA_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx_hal_def.h" 00030 00031 /** @addtogroup STM32F1xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup DMA 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 00041 /** @defgroup DMA_Exported_Types DMA Exported Types 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief DMA Configuration Structure definition 00047 */ 00048 typedef struct 00049 { 00050 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00051 from memory to memory or from peripheral to memory. 00052 This parameter can be a value of @ref DMA_Data_transfer_direction */ 00053 00054 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 00055 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 00056 00057 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 00058 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 00059 00060 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 00061 This parameter can be a value of @ref DMA_Peripheral_data_size */ 00062 00063 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 00064 This parameter can be a value of @ref DMA_Memory_data_size */ 00065 00066 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 00067 This parameter can be a value of @ref DMA_mode 00068 @note The circular buffer mode cannot be used if the memory-to-memory 00069 data transfer is configured on the selected Channel */ 00070 00071 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 00072 This parameter can be a value of @ref DMA_Priority_level */ 00073 } DMA_InitTypeDef; 00074 00075 /** 00076 * @brief HAL DMA State structures definition 00077 */ 00078 typedef enum 00079 { 00080 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 00081 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 00082 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 00083 HAL_DMA_STATE_TIMEOUT = 0x03U /*!< DMA timeout state */ 00084 }HAL_DMA_StateTypeDef; 00085 00086 /** 00087 * @brief HAL DMA Error Code structure definition 00088 */ 00089 typedef enum 00090 { 00091 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 00092 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 00093 }HAL_DMA_LevelCompleteTypeDef; 00094 00095 /** 00096 * @brief HAL DMA Callback ID structure definition 00097 */ 00098 typedef enum 00099 { 00100 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 00101 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 00102 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 00103 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 00104 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 00105 00106 }HAL_DMA_CallbackIDTypeDef; 00107 00108 /** 00109 * @brief DMA handle Structure definition 00110 */ 00111 typedef struct __DMA_HandleTypeDef 00112 { 00113 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 00114 00115 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 00116 00117 HAL_LockTypeDef Lock; /*!< DMA locking object */ 00118 00119 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 00120 00121 void *Parent; /*!< Parent object state */ 00122 00123 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 00124 00125 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 00126 00127 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 00128 00129 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 00130 00131 __IO uint32_t ErrorCode; /*!< DMA Error code */ 00132 00133 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 00134 00135 uint32_t ChannelIndex; /*!< DMA Channel Index */ 00136 00137 } DMA_HandleTypeDef; 00138 /** 00139 * @} 00140 */ 00141 00142 /* Exported constants --------------------------------------------------------*/ 00143 00144 /** @defgroup DMA_Exported_Constants DMA Exported Constants 00145 * @{ 00146 */ 00147 00148 /** @defgroup DMA_Error_Code DMA Error Code 00149 * @{ 00150 */ 00151 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 00152 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 00153 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< no ongoing transfer */ 00154 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00155 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 00156 /** 00157 * @} 00158 */ 00159 00160 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 00161 * @{ 00162 */ 00163 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00164 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */ 00165 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_CCR_MEM2MEM) /*!< Memory to memory direction */ 00166 00167 /** 00168 * @} 00169 */ 00170 00171 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 00172 * @{ 00173 */ 00174 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */ 00175 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 00176 /** 00177 * @} 00178 */ 00179 00180 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 00181 * @{ 00182 */ 00183 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */ 00184 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 00185 /** 00186 * @} 00187 */ 00188 00189 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 00190 * @{ 00191 */ 00192 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 00193 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 00194 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 00195 /** 00196 * @} 00197 */ 00198 00199 /** @defgroup DMA_Memory_data_size DMA Memory data size 00200 * @{ 00201 */ 00202 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 00203 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 00204 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment: Word */ 00205 /** 00206 * @} 00207 */ 00208 00209 /** @defgroup DMA_mode DMA mode 00210 * @{ 00211 */ 00212 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 00213 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ 00214 /** 00215 * @} 00216 */ 00217 00218 /** @defgroup DMA_Priority_level DMA Priority level 00219 * @{ 00220 */ 00221 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 00222 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ 00223 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ 00224 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ 00225 /** 00226 * @} 00227 */ 00228 00229 00230 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 00231 * @{ 00232 */ 00233 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) 00234 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) 00235 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup DMA_flag_definitions DMA flag definitions 00241 * @{ 00242 */ 00243 #define DMA_FLAG_GL1 0x00000001U 00244 #define DMA_FLAG_TC1 0x00000002U 00245 #define DMA_FLAG_HT1 0x00000004U 00246 #define DMA_FLAG_TE1 0x00000008U 00247 #define DMA_FLAG_GL2 0x00000010U 00248 #define DMA_FLAG_TC2 0x00000020U 00249 #define DMA_FLAG_HT2 0x00000040U 00250 #define DMA_FLAG_TE2 0x00000080U 00251 #define DMA_FLAG_GL3 0x00000100U 00252 #define DMA_FLAG_TC3 0x00000200U 00253 #define DMA_FLAG_HT3 0x00000400U 00254 #define DMA_FLAG_TE3 0x00000800U 00255 #define DMA_FLAG_GL4 0x00001000U 00256 #define DMA_FLAG_TC4 0x00002000U 00257 #define DMA_FLAG_HT4 0x00004000U 00258 #define DMA_FLAG_TE4 0x00008000U 00259 #define DMA_FLAG_GL5 0x00010000U 00260 #define DMA_FLAG_TC5 0x00020000U 00261 #define DMA_FLAG_HT5 0x00040000U 00262 #define DMA_FLAG_TE5 0x00080000U 00263 #define DMA_FLAG_GL6 0x00100000U 00264 #define DMA_FLAG_TC6 0x00200000U 00265 #define DMA_FLAG_HT6 0x00400000U 00266 #define DMA_FLAG_TE6 0x00800000U 00267 #define DMA_FLAG_GL7 0x01000000U 00268 #define DMA_FLAG_TC7 0x02000000U 00269 #define DMA_FLAG_HT7 0x04000000U 00270 #define DMA_FLAG_TE7 0x08000000U 00271 /** 00272 * @} 00273 */ 00274 00275 /** 00276 * @} 00277 */ 00278 00279 00280 /* Exported macros -----------------------------------------------------------*/ 00281 /** @defgroup DMA_Exported_Macros DMA Exported Macros 00282 * @{ 00283 */ 00284 00285 /** @brief Reset DMA handle state. 00286 * @param __HANDLE__: DMA handle 00287 * @retval None 00288 */ 00289 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 00290 00291 /** 00292 * @brief Enable the specified DMA Channel. 00293 * @param __HANDLE__: DMA handle 00294 * @retval None 00295 */ 00296 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) 00297 00298 /** 00299 * @brief Disable the specified DMA Channel. 00300 * @param __HANDLE__: DMA handle 00301 * @retval None 00302 */ 00303 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN)) 00304 00305 00306 /* Interrupt & Flag management */ 00307 00308 /** 00309 * @brief Enables the specified DMA Channel interrupts. 00310 * @param __HANDLE__: DMA handle 00311 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 00312 * This parameter can be any combination of the following values: 00313 * @arg DMA_IT_TC: Transfer complete interrupt mask 00314 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00315 * @arg DMA_IT_TE: Transfer error interrupt mask 00316 * @retval None 00317 */ 00318 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__))) 00319 00320 /** 00321 * @brief Disable the specified DMA Channel interrupts. 00322 * @param __HANDLE__: DMA handle 00323 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 00324 * This parameter can be any combination of the following values: 00325 * @arg DMA_IT_TC: Transfer complete interrupt mask 00326 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00327 * @arg DMA_IT_TE: Transfer error interrupt mask 00328 * @retval None 00329 */ 00330 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__))) 00331 00332 /** 00333 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 00334 * @param __HANDLE__: DMA handle 00335 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 00336 * This parameter can be one of the following values: 00337 * @arg DMA_IT_TC: Transfer complete interrupt mask 00338 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00339 * @arg DMA_IT_TE: Transfer error interrupt mask 00340 * @retval The state of DMA_IT (SET or RESET). 00341 */ 00342 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00343 00344 /** 00345 * @brief Return the number of remaining data units in the current DMA Channel transfer. 00346 * @param __HANDLE__: DMA handle 00347 * @retval The number of remaining data units in the current DMA Channel transfer. 00348 */ 00349 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 00350 00351 /** 00352 * @} 00353 */ 00354 00355 /* Include DMA HAL Extension module */ 00356 #include "stm32f1xx_hal_dma_ex.h" 00357 00358 /* Exported functions --------------------------------------------------------*/ 00359 /** @addtogroup DMA_Exported_Functions 00360 * @{ 00361 */ 00362 00363 /** @addtogroup DMA_Exported_Functions_Group1 00364 * @{ 00365 */ 00366 /* Initialization and de-initialization functions *****************************/ 00367 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 00368 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 00369 /** 00370 * @} 00371 */ 00372 00373 /** @addtogroup DMA_Exported_Functions_Group2 00374 * @{ 00375 */ 00376 /* IO operation functions *****************************************************/ 00377 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00378 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00379 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 00380 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 00381 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); 00382 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 00383 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 00384 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 00385 00386 /** 00387 * @} 00388 */ 00389 00390 /** @addtogroup DMA_Exported_Functions_Group3 00391 * @{ 00392 */ 00393 /* Peripheral State and Error functions ***************************************/ 00394 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 00395 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 00396 /** 00397 * @} 00398 */ 00399 00400 /** 00401 * @} 00402 */ 00403 00404 /* Private macros ------------------------------------------------------------*/ 00405 /** @defgroup DMA_Private_Macros DMA Private Macros 00406 * @{ 00407 */ 00408 00409 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 00410 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 00411 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 00412 00413 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 00414 00415 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 00416 ((STATE) == DMA_PINC_DISABLE)) 00417 00418 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 00419 ((STATE) == DMA_MINC_DISABLE)) 00420 00421 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 00422 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 00423 ((SIZE) == DMA_PDATAALIGN_WORD)) 00424 00425 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 00426 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 00427 ((SIZE) == DMA_MDATAALIGN_WORD )) 00428 00429 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 00430 ((MODE) == DMA_CIRCULAR)) 00431 00432 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 00433 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 00434 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 00435 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 00436 00437 /** 00438 * @} 00439 */ 00440 00441 /* Private functions ---------------------------------------------------------*/ 00442 00443 /** 00444 * @} 00445 */ 00446 00447 /** 00448 * @} 00449 */ 00450 00451 #ifdef __cplusplus 00452 } 00453 #endif 00454 00455 #endif /* __STM32F1xx_HAL_DMA_H */ 00456 00457 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1