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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_eth.h 00004 * @author MCD Application Team 00005 * @brief Header file of ETH HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F1xx_HAL_ETH_H 00022 #define __STM32F1xx_HAL_ETH_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx_hal_def.h" 00030 00031 #if defined (ETH) 00032 00033 /** @addtogroup STM32F1xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup ETH 00038 * @{ 00039 */ 00040 00041 /** @addtogroup ETH_Private_Macros 00042 * @{ 00043 */ 00044 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) 00045 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ 00046 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 00047 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ 00048 ((SPEED) == ETH_SPEED_100M)) 00049 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ 00050 ((MODE) == ETH_MODE_HALFDUPLEX)) 00051 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 00052 ((MODE) == ETH_RXINTERRUPT_MODE)) 00053 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ 00054 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 00055 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ 00056 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 00057 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ 00058 ((CMD) == ETH_WATCHDOG_DISABLE)) 00059 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ 00060 ((CMD) == ETH_JABBER_DISABLE)) 00061 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ 00062 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ 00063 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ 00064 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ 00065 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ 00066 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ 00067 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ 00068 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 00069 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ 00070 ((CMD) == ETH_CARRIERSENCE_DISABLE)) 00071 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ 00072 ((CMD) == ETH_RECEIVEOWN_DISABLE)) 00073 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ 00074 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 00075 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ 00076 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 00077 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ 00078 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 00079 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ 00080 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 00081 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ 00082 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ 00083 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ 00084 ((LIMIT) == ETH_BACKOFFLIMIT_1)) 00085 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ 00086 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 00087 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ 00088 ((CMD) == ETH_RECEIVEAll_DISABLE)) 00089 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ 00090 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ 00091 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 00092 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ 00093 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ 00094 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 00095 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ 00096 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 00097 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ 00098 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 00099 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ 00100 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 00101 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 00102 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ 00103 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ 00104 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 00105 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 00106 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ 00107 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 00108 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) 00109 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ 00110 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 00111 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ 00112 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ 00113 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ 00114 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 00115 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ 00116 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 00117 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ 00118 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 00119 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ 00120 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 00121 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ 00122 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 00123 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) 00124 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ 00125 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ 00126 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 00127 ((ADDRESS) == ETH_MAC_ADDRESS3)) 00128 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ 00129 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 00130 ((ADDRESS) == ETH_MAC_ADDRESS3)) 00131 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ 00132 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 00133 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ 00134 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ 00135 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ 00136 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ 00137 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ 00138 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 00139 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ 00140 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 00141 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ 00142 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 00143 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ 00144 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 00145 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ 00146 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 00147 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ 00148 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ 00149 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ 00150 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ 00151 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ 00152 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ 00153 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ 00154 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 00155 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ 00156 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 00157 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ 00158 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 00159 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ 00160 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ 00161 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ 00162 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 00163 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ 00164 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 00165 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ 00166 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 00167 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ 00168 ((CMD) == ETH_FIXEDBURST_DISABLE)) 00169 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ 00170 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ 00171 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ 00172 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ 00173 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ 00174 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ 00175 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ 00176 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ 00177 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ 00178 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ 00179 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ 00180 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 00181 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ 00182 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ 00183 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ 00184 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ 00185 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ 00186 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ 00187 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ 00188 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ 00189 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ 00190 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ 00191 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ 00192 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 00193 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) 00194 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ 00195 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ 00196 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ 00197 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ 00198 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 00199 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ 00200 ((FLAG) == ETH_DMATXDESC_IC) || \ 00201 ((FLAG) == ETH_DMATXDESC_LS) || \ 00202 ((FLAG) == ETH_DMATXDESC_FS) || \ 00203 ((FLAG) == ETH_DMATXDESC_DC) || \ 00204 ((FLAG) == ETH_DMATXDESC_DP) || \ 00205 ((FLAG) == ETH_DMATXDESC_TTSE) || \ 00206 ((FLAG) == ETH_DMATXDESC_TER) || \ 00207 ((FLAG) == ETH_DMATXDESC_TCH) || \ 00208 ((FLAG) == ETH_DMATXDESC_TTSS) || \ 00209 ((FLAG) == ETH_DMATXDESC_IHE) || \ 00210 ((FLAG) == ETH_DMATXDESC_ES) || \ 00211 ((FLAG) == ETH_DMATXDESC_JT) || \ 00212 ((FLAG) == ETH_DMATXDESC_FF) || \ 00213 ((FLAG) == ETH_DMATXDESC_PCE) || \ 00214 ((FLAG) == ETH_DMATXDESC_LCA) || \ 00215 ((FLAG) == ETH_DMATXDESC_NC) || \ 00216 ((FLAG) == ETH_DMATXDESC_LCO) || \ 00217 ((FLAG) == ETH_DMATXDESC_EC) || \ 00218 ((FLAG) == ETH_DMATXDESC_VF) || \ 00219 ((FLAG) == ETH_DMATXDESC_CC) || \ 00220 ((FLAG) == ETH_DMATXDESC_ED) || \ 00221 ((FLAG) == ETH_DMATXDESC_UF) || \ 00222 ((FLAG) == ETH_DMATXDESC_DB)) 00223 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ 00224 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 00225 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ 00226 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ 00227 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ 00228 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 00229 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) 00230 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ 00231 ((FLAG) == ETH_DMARXDESC_AFM) || \ 00232 ((FLAG) == ETH_DMARXDESC_ES) || \ 00233 ((FLAG) == ETH_DMARXDESC_DE) || \ 00234 ((FLAG) == ETH_DMARXDESC_SAF) || \ 00235 ((FLAG) == ETH_DMARXDESC_LE) || \ 00236 ((FLAG) == ETH_DMARXDESC_OE) || \ 00237 ((FLAG) == ETH_DMARXDESC_VLAN) || \ 00238 ((FLAG) == ETH_DMARXDESC_FS) || \ 00239 ((FLAG) == ETH_DMARXDESC_LS) || \ 00240 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ 00241 ((FLAG) == ETH_DMARXDESC_LC) || \ 00242 ((FLAG) == ETH_DMARXDESC_FT) || \ 00243 ((FLAG) == ETH_DMARXDESC_RWT) || \ 00244 ((FLAG) == ETH_DMARXDESC_RE) || \ 00245 ((FLAG) == ETH_DMARXDESC_DBE) || \ 00246 ((FLAG) == ETH_DMARXDESC_CE) || \ 00247 ((FLAG) == ETH_DMARXDESC_MAMPCE)) 00248 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ 00249 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 00250 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 00251 ((FLAG) == ETH_PMT_FLAG_MPR)) 00252 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) 00253 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 00254 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ 00255 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ 00256 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 00257 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 00258 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 00259 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 00260 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 00261 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 00262 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 00263 ((FLAG) == ETH_DMA_FLAG_T)) 00264 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) 00265 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 00266 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 00267 ((IT) == ETH_MAC_IT_PMT)) 00268 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 00269 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 00270 ((FLAG) == ETH_MAC_FLAG_PMT)) 00271 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) 00272 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 00273 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 00274 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 00275 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 00276 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 00277 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 00278 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 00279 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 00280 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 00281 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ 00282 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 00283 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ 00284 ((IT) != 0x00U)) 00285 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 00286 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 00287 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 00288 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ 00289 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 00290 00291 /** 00292 * @} 00293 */ 00294 00295 /** @addtogroup ETH_Private_Defines 00296 * @{ 00297 */ 00298 /* Delay to wait when writing to some Ethernet registers */ 00299 #define ETH_REG_WRITE_DELAY 0x00000001U 00300 00301 /* ETHERNET Errors */ 00302 #define ETH_SUCCESS 0U 00303 #define ETH_ERROR 1U 00304 00305 /* ETHERNET DMA Tx descriptors Collision Count Shift */ 00306 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U 00307 00308 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ 00309 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U 00310 00311 /* ETHERNET DMA Rx descriptors Frame Length Shift */ 00312 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U 00313 00314 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ 00315 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U 00316 00317 /* ETHERNET DMA Rx descriptors Frame length Shift */ 00318 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U 00319 00320 /* ETHERNET MAC address offsets */ 00321 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ 00322 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ 00323 00324 /* ETHERNET MACMIIAR register Mask */ 00325 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U 00326 00327 /* ETHERNET MACCR register Mask */ 00328 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU 00329 00330 /* ETHERNET MACFCR register Mask */ 00331 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U 00332 00333 /* ETHERNET DMAOMR register Mask */ 00334 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U 00335 00336 /* ETHERNET Remote Wake-up frame register length */ 00337 #define ETH_WAKEUP_REGISTER_LENGTH 8U 00338 00339 /* ETHERNET Missed frames counter Shift */ 00340 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U 00341 /** 00342 * @} 00343 */ 00344 00345 /* Exported types ------------------------------------------------------------*/ 00346 /** @defgroup ETH_Exported_Types ETH Exported Types 00347 * @{ 00348 */ 00349 00350 /** 00351 * @brief HAL State structures definition 00352 */ 00353 typedef enum 00354 { 00355 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ 00356 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00357 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 00358 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ 00359 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 00360 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ 00361 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ 00362 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ 00363 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00364 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 00365 } HAL_ETH_StateTypeDef; 00366 00367 /** 00368 * @brief ETH Init Structure definition 00369 */ 00370 00371 typedef struct 00372 { 00373 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 00374 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 00375 and the mode (half/full-duplex). 00376 This parameter can be a value of @ref ETH_AutoNegotiation */ 00377 00378 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 00379 This parameter can be a value of @ref ETH_Speed */ 00380 00381 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 00382 This parameter can be a value of @ref ETH_Duplex_Mode */ 00383 00384 uint16_t PhyAddress; /*!< Ethernet PHY address. 00385 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 00386 00387 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 00388 00389 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. 00390 This parameter can be a value of @ref ETH_Rx_Mode */ 00391 00392 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. 00393 This parameter can be a value of @ref ETH_Checksum_Mode */ 00394 00395 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. 00396 This parameter can be a value of @ref ETH_Media_Interface */ 00397 00398 } ETH_InitTypeDef; 00399 00400 00401 /** 00402 * @brief ETH MAC Configuration Structure definition 00403 */ 00404 00405 typedef struct 00406 { 00407 uint32_t Watchdog; /*!< Selects or not the Watchdog timer 00408 When enabled, the MAC allows no more then 2048 bytes to be received. 00409 When disabled, the MAC can receive up to 16384 bytes. 00410 This parameter can be a value of @ref ETH_Watchdog */ 00411 00412 uint32_t Jabber; /*!< Selects or not Jabber timer 00413 When enabled, the MAC allows no more then 2048 bytes to be sent. 00414 When disabled, the MAC can send up to 16384 bytes. 00415 This parameter can be a value of @ref ETH_Jabber */ 00416 00417 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. 00418 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 00419 00420 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. 00421 This parameter can be a value of @ref ETH_Carrier_Sense */ 00422 00423 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, 00424 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 00425 in Half-Duplex mode. 00426 This parameter can be a value of @ref ETH_Receive_Own */ 00427 00428 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. 00429 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 00430 00431 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 00432 This parameter can be a value of @ref ETH_Checksum_Offload */ 00433 00434 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 00435 when a collision occurs (Half-Duplex mode). 00436 This parameter can be a value of @ref ETH_Retry_Transmission */ 00437 00438 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. 00439 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 00440 00441 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 00442 This parameter can be a value of @ref ETH_Back_Off_Limit */ 00443 00444 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). 00445 This parameter can be a value of @ref ETH_Deferral_Check */ 00446 00447 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). 00448 This parameter can be a value of @ref ETH_Receive_All */ 00449 00450 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. 00451 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 00452 00453 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 00454 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 00455 00456 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. 00457 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 00458 00459 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. 00460 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 00461 00462 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode 00463 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 00464 00465 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. 00466 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 00467 00468 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. 00469 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 00470 00471 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. 00472 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 00473 00474 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. 00475 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 00476 00477 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 00478 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ 00479 00480 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. 00481 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 00482 00483 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 00484 automatic retransmission of PAUSE Frame. 00485 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 00486 00487 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 00488 unicast address and unique multicast address). 00489 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 00490 00491 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 00492 disable its transmitter for a specified time (Pause Time) 00493 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 00494 00495 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 00496 or the MAC back-pressure operation (Half-Duplex mode) 00497 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 00498 00499 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 00500 comparison and filtering. 00501 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 00502 00503 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 00504 00505 } ETH_MACInitTypeDef; 00506 00507 /** 00508 * @brief ETH DMA Configuration Structure definition 00509 */ 00510 00511 typedef struct 00512 { 00513 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. 00514 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 00515 00516 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. 00517 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 00518 00519 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. 00520 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 00521 00522 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. 00523 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 00524 00525 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 00526 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 00527 00528 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. 00529 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 00530 00531 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 00532 and length less than 64 bytes) including pad-bytes and CRC) 00533 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 00534 00535 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 00536 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 00537 00538 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 00539 frame of Transmit data even before obtaining the status for the first frame. 00540 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 00541 00542 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. 00543 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 00544 00545 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. 00546 This parameter can be a value of @ref ETH_Fixed_Burst */ 00547 00548 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 00549 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 00550 00551 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 00552 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 00553 00554 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 00555 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 00556 00557 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. 00558 This parameter can be a value of @ref ETH_DMA_Arbitration */ 00559 } ETH_DMAInitTypeDef; 00560 00561 00562 /** 00563 * @brief ETH DMA Descriptors data structure definition 00564 */ 00565 00566 typedef struct 00567 { 00568 __IO uint32_t Status; /*!< Status */ 00569 00570 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 00571 00572 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 00573 00574 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 00575 00576 } ETH_DMADescTypeDef; 00577 00578 /** 00579 * @brief Received Frame Informations structure definition 00580 */ 00581 typedef struct 00582 { 00583 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ 00584 00585 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ 00586 00587 uint32_t SegCount; /*!< Segment count */ 00588 00589 uint32_t length; /*!< Frame length */ 00590 00591 uint32_t buffer; /*!< Frame buffer */ 00592 00593 } ETH_DMARxFrameInfos; 00594 00595 /** 00596 * @brief ETH Handle Structure definition 00597 */ 00598 00599 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00600 typedef struct __ETH_HandleTypeDef 00601 #else 00602 typedef struct 00603 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00604 { 00605 ETH_TypeDef *Instance; /*!< Register base address */ 00606 00607 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 00608 00609 uint32_t LinkStatus; /*!< Ethernet link status */ 00610 00611 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ 00612 00613 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ 00614 00615 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ 00616 00617 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ 00618 00619 HAL_LockTypeDef Lock; /*!< ETH Lock */ 00620 00621 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00622 00623 void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */ 00624 void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */ 00625 void (* DMAErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< DMA Error Callback */ 00626 void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */ 00627 void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */ 00628 00629 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00630 00631 } ETH_HandleTypeDef; 00632 00633 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 00634 /** 00635 * @brief HAL ETH Callback ID enumeration definition 00636 */ 00637 typedef enum 00638 { 00639 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ 00640 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ 00641 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ 00642 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ 00643 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ 00644 00645 } HAL_ETH_CallbackIDTypeDef; 00646 00647 /** 00648 * @brief HAL ETH Callback pointer definition 00649 */ 00650 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */ 00651 00652 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 00653 00654 /** 00655 * @} 00656 */ 00657 00658 /* Exported constants --------------------------------------------------------*/ 00659 /** @defgroup ETH_Exported_Constants ETH Exported Constants 00660 * @{ 00661 */ 00662 00663 /** @defgroup ETH_Buffers_setting ETH Buffers setting 00664 * @{ 00665 */ 00666 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ 00667 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 00668 #define ETH_CRC 4U /*!< Ethernet CRC */ 00669 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ 00670 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 00671 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 00672 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 00673 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 00674 00675 /* Ethernet driver receive buffers are organized in a chained linked-list, when 00676 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 00677 to the driver receive buffers memory. 00678 00679 Depending on the size of the received ethernet packet and the size of 00680 each ethernet driver receive buffer, the received packet can take one or more 00681 ethernet driver receive buffer. 00682 00683 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 00684 and the total count of the driver receive buffers ETH_RXBUFNB. 00685 00686 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 00687 example, they can be reconfigured in the application layer to fit the application 00688 needs */ 00689 00690 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 00691 packet */ 00692 #ifndef ETH_RX_BUF_SIZE 00693 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 00694 #endif 00695 00696 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 00697 #ifndef ETH_RXBUFNB 00698 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 00699 #endif 00700 00701 00702 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 00703 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 00704 driver transmit buffers memory to the TxFIFO. 00705 00706 Depending on the size of the Ethernet packet to be transmitted and the size of 00707 each ethernet driver transmit buffer, the packet to be transmitted can take 00708 one or more ethernet driver transmit buffer. 00709 00710 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 00711 and the total count of the driver transmit buffers ETH_TXBUFNB. 00712 00713 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 00714 example, they can be reconfigured in the application layer to fit the application 00715 needs */ 00716 00717 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 00718 packet */ 00719 #ifndef ETH_TX_BUF_SIZE 00720 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 00721 #endif 00722 00723 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 00724 #ifndef ETH_TXBUFNB 00725 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 00726 #endif 00727 00728 /** 00729 * @} 00730 */ 00731 00732 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor 00733 * @{ 00734 */ 00735 00736 /* 00737 DMA Tx Descriptor 00738 ----------------------------------------------------------------------------------------------- 00739 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 00740 ----------------------------------------------------------------------------------------------- 00741 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 00742 ----------------------------------------------------------------------------------------------- 00743 TDES2 | Buffer1 Address [31:0] | 00744 ----------------------------------------------------------------------------------------------- 00745 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 00746 ----------------------------------------------------------------------------------------------- 00747 */ 00748 00749 /** 00750 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 00751 */ 00752 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 00753 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ 00754 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ 00755 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ 00756 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ 00757 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ 00758 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ 00759 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ 00760 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ 00761 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ 00762 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 00763 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 00764 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ 00765 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ 00766 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ 00767 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ 00768 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 00769 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ 00770 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 00771 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ 00772 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 00773 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 00774 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 00775 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 00776 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ 00777 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ 00778 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ 00779 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ 00780 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ 00781 00782 /** 00783 * @brief Bit definition of TDES1 register 00784 */ 00785 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ 00786 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ 00787 00788 /** 00789 * @brief Bit definition of TDES2 register 00790 */ 00791 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 00792 00793 /** 00794 * @brief Bit definition of TDES3 register 00795 */ 00796 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 00797 00798 /** 00799 * @} 00800 */ 00801 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 00802 * @{ 00803 */ 00804 00805 /* 00806 DMA Rx Descriptor 00807 -------------------------------------------------------------------------------------------------------------------- 00808 RDES0 | OWN(31) | Status [30:0] | 00809 --------------------------------------------------------------------------------------------------------------------- 00810 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 00811 --------------------------------------------------------------------------------------------------------------------- 00812 RDES2 | Buffer1 Address [31:0] | 00813 --------------------------------------------------------------------------------------------------------------------- 00814 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 00815 --------------------------------------------------------------------------------------------------------------------- 00816 */ 00817 00818 /** 00819 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 00820 */ 00821 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 00822 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ 00823 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ 00824 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 00825 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ 00826 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ 00827 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ 00828 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ 00829 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ 00830 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ 00831 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ 00832 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 00833 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ 00834 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ 00835 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 00836 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ 00837 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 00838 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ 00839 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 00840 00841 /** 00842 * @brief Bit definition of RDES1 register 00843 */ 00844 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ 00845 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ 00846 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ 00847 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ 00848 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ 00849 00850 /** 00851 * @brief Bit definition of RDES2 register 00852 */ 00853 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 00854 00855 /** 00856 * @brief Bit definition of RDES3 register 00857 */ 00858 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 00859 00860 /** 00861 * @} 00862 */ 00863 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 00864 * @{ 00865 */ 00866 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U 00867 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U 00868 00869 /** 00870 * @} 00871 */ 00872 /** @defgroup ETH_Speed ETH Speed 00873 * @{ 00874 */ 00875 #define ETH_SPEED_10M 0x00000000U 00876 #define ETH_SPEED_100M 0x00004000U 00877 00878 /** 00879 * @} 00880 */ 00881 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 00882 * @{ 00883 */ 00884 #define ETH_MODE_FULLDUPLEX 0x00000800U 00885 #define ETH_MODE_HALFDUPLEX 0x00000000U 00886 /** 00887 * @} 00888 */ 00889 /** @defgroup ETH_Rx_Mode ETH Rx Mode 00890 * @{ 00891 */ 00892 #define ETH_RXPOLLING_MODE 0x00000000U 00893 #define ETH_RXINTERRUPT_MODE 0x00000001U 00894 /** 00895 * @} 00896 */ 00897 00898 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 00899 * @{ 00900 */ 00901 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U 00902 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U 00903 /** 00904 * @} 00905 */ 00906 00907 /** @defgroup ETH_Media_Interface ETH Media Interface 00908 * @{ 00909 */ 00910 #define ETH_MEDIA_INTERFACE_MII 0x00000000U 00911 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL) 00912 00913 /** 00914 * @} 00915 */ 00916 00917 /** @defgroup ETH_Watchdog ETH Watchdog 00918 * @{ 00919 */ 00920 #define ETH_WATCHDOG_ENABLE 0x00000000U 00921 #define ETH_WATCHDOG_DISABLE 0x00800000U 00922 /** 00923 * @} 00924 */ 00925 00926 /** @defgroup ETH_Jabber ETH Jabber 00927 * @{ 00928 */ 00929 #define ETH_JABBER_ENABLE 0x00000000U 00930 #define ETH_JABBER_DISABLE 0x00400000U 00931 /** 00932 * @} 00933 */ 00934 00935 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 00936 * @{ 00937 */ 00938 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ 00939 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ 00940 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ 00941 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ 00942 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ 00943 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ 00944 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ 00945 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ 00946 /** 00947 * @} 00948 */ 00949 00950 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 00951 * @{ 00952 */ 00953 #define ETH_CARRIERSENCE_ENABLE 0x00000000U 00954 #define ETH_CARRIERSENCE_DISABLE 0x00010000U 00955 /** 00956 * @} 00957 */ 00958 00959 /** @defgroup ETH_Receive_Own ETH Receive Own 00960 * @{ 00961 */ 00962 #define ETH_RECEIVEOWN_ENABLE 0x00000000U 00963 #define ETH_RECEIVEOWN_DISABLE 0x00002000U 00964 /** 00965 * @} 00966 */ 00967 00968 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 00969 * @{ 00970 */ 00971 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U 00972 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U 00973 /** 00974 * @} 00975 */ 00976 00977 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 00978 * @{ 00979 */ 00980 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U 00981 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U 00982 /** 00983 * @} 00984 */ 00985 00986 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 00987 * @{ 00988 */ 00989 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U 00990 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U 00991 /** 00992 * @} 00993 */ 00994 00995 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 00996 * @{ 00997 */ 00998 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U 00999 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U 01000 /** 01001 * @} 01002 */ 01003 01004 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 01005 * @{ 01006 */ 01007 #define ETH_BACKOFFLIMIT_10 0x00000000U 01008 #define ETH_BACKOFFLIMIT_8 0x00000020U 01009 #define ETH_BACKOFFLIMIT_4 0x00000040U 01010 #define ETH_BACKOFFLIMIT_1 0x00000060U 01011 /** 01012 * @} 01013 */ 01014 01015 /** @defgroup ETH_Deferral_Check ETH Deferral Check 01016 * @{ 01017 */ 01018 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U 01019 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U 01020 /** 01021 * @} 01022 */ 01023 01024 /** @defgroup ETH_Receive_All ETH Receive All 01025 * @{ 01026 */ 01027 #define ETH_RECEIVEALL_ENABLE 0x80000000U 01028 #define ETH_RECEIVEAll_DISABLE 0x00000000U 01029 /** 01030 * @} 01031 */ 01032 01033 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 01034 * @{ 01035 */ 01036 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U 01037 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U 01038 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U 01039 /** 01040 * @} 01041 */ 01042 01043 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 01044 * @{ 01045 */ 01046 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ 01047 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 01048 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ 01049 /** 01050 * @} 01051 */ 01052 01053 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 01054 * @{ 01055 */ 01056 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U 01057 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U 01058 /** 01059 * @} 01060 */ 01061 01062 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 01063 * @{ 01064 */ 01065 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U 01066 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U 01067 /** 01068 * @} 01069 */ 01070 01071 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 01072 * @{ 01073 */ 01074 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U 01075 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U 01076 /** 01077 * @} 01078 */ 01079 01080 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 01081 * @{ 01082 */ 01083 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U 01084 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U 01085 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U 01086 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U 01087 /** 01088 * @} 01089 */ 01090 01091 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 01092 * @{ 01093 */ 01094 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U 01095 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U 01096 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U 01097 /** 01098 * @} 01099 */ 01100 01101 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 01102 * @{ 01103 */ 01104 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U 01105 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U 01106 /** 01107 * @} 01108 */ 01109 01110 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 01111 * @{ 01112 */ 01113 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ 01114 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ 01115 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ 01116 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ 01117 /** 01118 * @} 01119 */ 01120 01121 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 01122 * @{ 01123 */ 01124 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U 01125 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U 01126 /** 01127 * @} 01128 */ 01129 01130 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 01131 * @{ 01132 */ 01133 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U 01134 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U 01135 /** 01136 * @} 01137 */ 01138 01139 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 01140 * @{ 01141 */ 01142 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U 01143 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U 01144 /** 01145 * @} 01146 */ 01147 01148 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 01149 * @{ 01150 */ 01151 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U 01152 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 01153 /** 01154 * @} 01155 */ 01156 01157 /** @defgroup ETH_MAC_addresses ETH MAC addresses 01158 * @{ 01159 */ 01160 #define ETH_MAC_ADDRESS0 0x00000000U 01161 #define ETH_MAC_ADDRESS1 0x00000008U 01162 #define ETH_MAC_ADDRESS2 0x00000010U 01163 #define ETH_MAC_ADDRESS3 0x00000018U 01164 /** 01165 * @} 01166 */ 01167 01168 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 01169 * @{ 01170 */ 01171 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U 01172 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U 01173 /** 01174 * @} 01175 */ 01176 01177 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 01178 * @{ 01179 */ 01180 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ 01181 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ 01182 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ 01183 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ 01184 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ 01185 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ 01186 /** 01187 * @} 01188 */ 01189 01190 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame 01191 * @{ 01192 */ 01193 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U 01194 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U 01195 /** 01196 * @} 01197 */ 01198 01199 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 01200 * @{ 01201 */ 01202 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U 01203 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U 01204 /** 01205 * @} 01206 */ 01207 01208 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame 01209 * @{ 01210 */ 01211 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U 01212 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U 01213 /** 01214 * @} 01215 */ 01216 01217 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward 01218 * @{ 01219 */ 01220 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U 01221 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U 01222 /** 01223 * @} 01224 */ 01225 01226 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 01227 * @{ 01228 */ 01229 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 01230 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 01231 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 01232 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 01233 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 01234 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 01235 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 01236 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 01237 /** 01238 * @} 01239 */ 01240 01241 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames 01242 * @{ 01243 */ 01244 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U 01245 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U 01246 /** 01247 * @} 01248 */ 01249 01250 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames 01251 * @{ 01252 */ 01253 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U 01254 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U 01255 /** 01256 * @} 01257 */ 01258 01259 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 01260 * @{ 01261 */ 01262 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 01263 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 01264 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 01265 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 01266 /** 01267 * @} 01268 */ 01269 01270 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate 01271 * @{ 01272 */ 01273 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U 01274 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U 01275 /** 01276 * @} 01277 */ 01278 01279 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 01280 * @{ 01281 */ 01282 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U 01283 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U 01284 /** 01285 * @} 01286 */ 01287 01288 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst 01289 * @{ 01290 */ 01291 #define ETH_FIXEDBURST_ENABLE 0x00010000U 01292 #define ETH_FIXEDBURST_DISABLE 0x00000000U 01293 /** 01294 * @} 01295 */ 01296 01297 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 01298 * @{ 01299 */ 01300 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 01301 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 01302 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 01303 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 01304 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 01305 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 01306 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 01307 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 01308 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 01309 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 01310 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 01311 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 01312 /** 01313 * @} 01314 */ 01315 01316 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 01317 * @{ 01318 */ 01319 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 01320 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 01321 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 01322 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 01323 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 01324 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 01325 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 01326 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 01327 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 01328 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 01329 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 01330 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 01331 01332 /** 01333 * @} 01334 */ 01335 01336 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 01337 * @{ 01338 */ 01339 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U 01340 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U 01341 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U 01342 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U 01343 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U 01344 /** 01345 * @} 01346 */ 01347 01348 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 01349 * @{ 01350 */ 01351 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ 01352 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ 01353 /** 01354 * @} 01355 */ 01356 01357 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 01358 * @{ 01359 */ 01360 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ 01361 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ 01362 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 01363 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 01364 /** 01365 * @} 01366 */ 01367 01368 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 01369 * @{ 01370 */ 01371 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ 01372 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ 01373 /** 01374 * @} 01375 */ 01376 01377 /** @defgroup ETH_PMT_Flags ETH PMT Flags 01378 * @{ 01379 */ 01380 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ 01381 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ 01382 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ 01383 /** 01384 * @} 01385 */ 01386 01387 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 01388 * @{ 01389 */ 01390 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ 01391 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ 01392 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ 01393 /** 01394 * @} 01395 */ 01396 01397 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 01398 * @{ 01399 */ 01400 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ 01401 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ 01402 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ 01403 /** 01404 * @} 01405 */ 01406 01407 /** @defgroup ETH_MAC_Flags ETH MAC Flags 01408 * @{ 01409 */ 01410 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ 01411 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ 01412 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ 01413 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ 01414 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ 01415 /** 01416 * @} 01417 */ 01418 01419 /** @defgroup ETH_DMA_Flags ETH DMA Flags 01420 * @{ 01421 */ 01422 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 01423 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 01424 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 01425 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 01426 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ 01427 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ 01428 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ 01429 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ 01430 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ 01431 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ 01432 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ 01433 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ 01434 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ 01435 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ 01436 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ 01437 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ 01438 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ 01439 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ 01440 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ 01441 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ 01442 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ 01443 /** 01444 * @} 01445 */ 01446 01447 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 01448 * @{ 01449 */ 01450 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ 01451 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ 01452 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ 01453 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ 01454 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ 01455 /** 01456 * @} 01457 */ 01458 01459 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 01460 * @{ 01461 */ 01462 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 01463 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 01464 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 01465 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ 01466 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ 01467 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ 01468 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ 01469 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ 01470 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ 01471 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ 01472 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ 01473 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ 01474 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ 01475 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ 01476 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ 01477 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ 01478 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ 01479 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ 01480 /** 01481 * @} 01482 */ 01483 01484 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 01485 * @{ 01486 */ 01487 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ 01488 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ 01489 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ 01490 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ 01491 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ 01492 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ 01493 01494 /** 01495 * @} 01496 */ 01497 01498 01499 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 01500 * @{ 01501 */ 01502 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ 01503 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ 01504 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ 01505 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ 01506 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ 01507 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ 01508 01509 /** 01510 * @} 01511 */ 01512 01513 /** @defgroup ETH_DMA_overflow ETH DMA overflow 01514 * @{ 01515 */ 01516 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ 01517 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ 01518 /** 01519 * @} 01520 */ 01521 01522 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP 01523 * @{ 01524 */ 01525 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ 01526 01527 /** 01528 * @} 01529 */ 01530 01531 /** 01532 * @} 01533 */ 01534 01535 /* Exported macro ------------------------------------------------------------*/ 01536 /** @defgroup ETH_Exported_Macros ETH Exported Macros 01537 * @brief macros to handle interrupts and specific clock configurations 01538 * @{ 01539 */ 01540 01541 /** @brief Reset ETH handle state 01542 * @param __HANDLE__: specifies the ETH handle. 01543 * @retval None 01544 */ 01545 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 01546 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ 01547 (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ 01548 (__HANDLE__)->MspInitCallback = NULL; \ 01549 (__HANDLE__)->MspDeInitCallback = NULL; \ 01550 } while(0) 01551 #else 01552 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 01553 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ 01554 01555 /** 01556 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. 01557 * @param __HANDLE__: ETH Handle 01558 * @param __FLAG__: specifies the flag of TDES0 to check. 01559 * @retval the ETH_DMATxDescFlag (SET or RESET). 01560 */ 01561 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 01562 01563 /** 01564 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. 01565 * @param __HANDLE__: ETH Handle 01566 * @param __FLAG__: specifies the flag of RDES0 to check. 01567 * @retval the ETH_DMATxDescFlag (SET or RESET). 01568 */ 01569 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 01570 01571 /** 01572 * @brief Enables the specified DMA Rx Desc receive interrupt. 01573 * @param __HANDLE__: ETH Handle 01574 * @retval None 01575 */ 01576 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 01577 01578 /** 01579 * @brief Disables the specified DMA Rx Desc receive interrupt. 01580 * @param __HANDLE__: ETH Handle 01581 * @retval None 01582 */ 01583 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 01584 01585 /** 01586 * @brief Set the specified DMA Rx Desc Own bit. 01587 * @param __HANDLE__: ETH Handle 01588 * @retval None 01589 */ 01590 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 01591 01592 /** 01593 * @brief Returns the specified ETHERNET DMA Tx Desc collision count. 01594 * @param __HANDLE__: ETH Handle 01595 * @retval The Transmit descriptor collision counter value. 01596 */ 01597 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 01598 01599 /** 01600 * @brief Set the specified DMA Tx Desc Own bit. 01601 * @param __HANDLE__: ETH Handle 01602 * @retval None 01603 */ 01604 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 01605 01606 /** 01607 * @brief Enables the specified DMA Tx Desc Transmit interrupt. 01608 * @param __HANDLE__: ETH Handle 01609 * @retval None 01610 */ 01611 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 01612 01613 /** 01614 * @brief Disables the specified DMA Tx Desc Transmit interrupt. 01615 * @param __HANDLE__: ETH Handle 01616 * @retval None 01617 */ 01618 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 01619 01620 /** 01621 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. 01622 * @param __HANDLE__: ETH Handle 01623 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. 01624 * This parameter can be one of the following values: 01625 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass 01626 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum 01627 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present 01628 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header 01629 * @retval None 01630 */ 01631 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 01632 01633 /** 01634 * @brief Enables the DMA Tx Desc CRC. 01635 * @param __HANDLE__: ETH Handle 01636 * @retval None 01637 */ 01638 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 01639 01640 /** 01641 * @brief Disables the DMA Tx Desc CRC. 01642 * @param __HANDLE__: ETH Handle 01643 * @retval None 01644 */ 01645 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 01646 01647 /** 01648 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. 01649 * @param __HANDLE__: ETH Handle 01650 * @retval None 01651 */ 01652 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 01653 01654 /** 01655 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. 01656 * @param __HANDLE__: ETH Handle 01657 * @retval None 01658 */ 01659 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 01660 01661 /** 01662 * @brief Enables the specified ETHERNET MAC interrupts. 01663 * @param __HANDLE__ : ETH Handle 01664 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 01665 * enabled or disabled. 01666 * This parameter can be any combination of the following values: 01667 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 01668 * @arg ETH_MAC_IT_PMT : PMT interrupt 01669 * @retval None 01670 */ 01671 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 01672 01673 /** 01674 * @brief Disables the specified ETHERNET MAC interrupts. 01675 * @param __HANDLE__ : ETH Handle 01676 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be 01677 * enabled or disabled. 01678 * This parameter can be any combination of the following values: 01679 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 01680 * @arg ETH_MAC_IT_PMT : PMT interrupt 01681 * @retval None 01682 */ 01683 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 01684 01685 /** 01686 * @brief Initiate a Pause Control Frame (Full-duplex only). 01687 * @param __HANDLE__: ETH Handle 01688 * @retval None 01689 */ 01690 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 01691 01692 /** 01693 * @brief Checks whether the ETHERNET flow control busy bit is set or not. 01694 * @param __HANDLE__: ETH Handle 01695 * @retval The new state of flow control busy status bit (SET or RESET). 01696 */ 01697 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 01698 01699 /** 01700 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). 01701 * @param __HANDLE__: ETH Handle 01702 * @retval None 01703 */ 01704 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 01705 01706 /** 01707 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). 01708 * @param __HANDLE__: ETH Handle 01709 * @retval None 01710 */ 01711 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 01712 01713 /** 01714 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 01715 * @param __HANDLE__: ETH Handle 01716 * @param __FLAG__: specifies the flag to check. 01717 * This parameter can be one of the following values: 01718 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag 01719 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag 01720 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag 01721 * @arg ETH_MAC_FLAG_MMC : MMC flag 01722 * @arg ETH_MAC_FLAG_PMT : PMT flag 01723 * @retval The state of ETHERNET MAC flag. 01724 */ 01725 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 01726 01727 /** 01728 * @brief Enables the specified ETHERNET DMA interrupts. 01729 * @param __HANDLE__ : ETH Handle 01730 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 01731 * enabled @ref ETH_DMA_Interrupts 01732 * @retval None 01733 */ 01734 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 01735 01736 /** 01737 * @brief Disables the specified ETHERNET DMA interrupts. 01738 * @param __HANDLE__ : ETH Handle 01739 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be 01740 * disabled. @ref ETH_DMA_Interrupts 01741 * @retval None 01742 */ 01743 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 01744 01745 /** 01746 * @brief Clears the ETHERNET DMA IT pending bit. 01747 * @param __HANDLE__ : ETH Handle 01748 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 01749 * @retval None 01750 */ 01751 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 01752 01753 /** 01754 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 01755 * @param __HANDLE__: ETH Handle 01756 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags 01757 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 01758 */ 01759 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 01760 01761 /** 01762 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 01763 * @param __HANDLE__: ETH Handle 01764 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags 01765 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 01766 */ 01767 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 01768 01769 /** 01770 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. 01771 * @param __HANDLE__: ETH Handle 01772 * @param __OVERFLOW__: specifies the DMA overflow flag to check. 01773 * This parameter can be one of the following values: 01774 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter 01775 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter 01776 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). 01777 */ 01778 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 01779 01780 /** 01781 * @brief Set the DMA Receive status watchdog timer register value 01782 * @param __HANDLE__: ETH Handle 01783 * @param __VALUE__: DMA Receive status watchdog timer register value 01784 * @retval None 01785 */ 01786 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 01787 01788 /** 01789 * @brief Enables any unicast packet filtered by the MAC address 01790 * recognition to be a wake-up frame. 01791 * @param __HANDLE__: ETH Handle. 01792 * @retval None 01793 */ 01794 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 01795 01796 /** 01797 * @brief Disables any unicast packet filtered by the MAC address 01798 * recognition to be a wake-up frame. 01799 * @param __HANDLE__: ETH Handle. 01800 * @retval None 01801 */ 01802 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 01803 01804 /** 01805 * @brief Enables the MAC Wake-Up Frame Detection. 01806 * @param __HANDLE__: ETH Handle. 01807 * @retval None 01808 */ 01809 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 01810 01811 /** 01812 * @brief Disables the MAC Wake-Up Frame Detection. 01813 * @param __HANDLE__: ETH Handle. 01814 * @retval None 01815 */ 01816 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 01817 01818 /** 01819 * @brief Enables the MAC Magic Packet Detection. 01820 * @param __HANDLE__: ETH Handle. 01821 * @retval None 01822 */ 01823 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 01824 01825 /** 01826 * @brief Disables the MAC Magic Packet Detection. 01827 * @param __HANDLE__: ETH Handle. 01828 * @retval None 01829 */ 01830 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 01831 01832 /** 01833 * @brief Enables the MAC Power Down. 01834 * @param __HANDLE__: ETH Handle 01835 * @retval None 01836 */ 01837 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 01838 01839 /** 01840 * @brief Disables the MAC Power Down. 01841 * @param __HANDLE__: ETH Handle 01842 * @retval None 01843 */ 01844 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 01845 01846 /** 01847 * @brief Checks whether the specified ETHERNET PMT flag is set or not. 01848 * @param __HANDLE__: ETH Handle. 01849 * @param __FLAG__: specifies the flag to check. 01850 * This parameter can be one of the following values: 01851 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 01852 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received 01853 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received 01854 * @retval The new state of ETHERNET PMT Flag (SET or RESET). 01855 */ 01856 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 01857 01858 /** 01859 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) 01860 * @param __HANDLE__: ETH Handle. 01861 * @retval None 01862 */ 01863 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 01864 01865 /** 01866 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) 01867 * @param __HANDLE__: ETH Handle. 01868 * @retval None 01869 */ 01870 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ 01871 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U) 01872 01873 /** 01874 * @brief Enables the MMC Counter Freeze. 01875 * @param __HANDLE__: ETH Handle. 01876 * @retval None 01877 */ 01878 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 01879 01880 /** 01881 * @brief Disables the MMC Counter Freeze. 01882 * @param __HANDLE__: ETH Handle. 01883 * @retval None 01884 */ 01885 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 01886 01887 /** 01888 * @brief Enables the MMC Reset On Read. 01889 * @param __HANDLE__: ETH Handle. 01890 * @retval None 01891 */ 01892 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 01893 01894 /** 01895 * @brief Disables the MMC Reset On Read. 01896 * @param __HANDLE__: ETH Handle. 01897 * @retval None 01898 */ 01899 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 01900 01901 /** 01902 * @brief Enables the MMC Counter Stop Rollover. 01903 * @param __HANDLE__: ETH Handle. 01904 * @retval None 01905 */ 01906 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 01907 01908 /** 01909 * @brief Disables the MMC Counter Stop Rollover. 01910 * @param __HANDLE__: ETH Handle. 01911 * @retval None 01912 */ 01913 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 01914 01915 /** 01916 * @brief Resets the MMC Counters. 01917 * @param __HANDLE__: ETH Handle. 01918 * @retval None 01919 */ 01920 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 01921 01922 /** 01923 * @brief Enables the specified ETHERNET MMC Rx interrupts. 01924 * @param __HANDLE__: ETH Handle. 01925 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 01926 * This parameter can be one of the following values: 01927 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 01928 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 01929 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 01930 * @retval None 01931 */ 01932 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) 01933 /** 01934 * @brief Disables the specified ETHERNET MMC Rx interrupts. 01935 * @param __HANDLE__: ETH Handle. 01936 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 01937 * This parameter can be one of the following values: 01938 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 01939 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 01940 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 01941 * @retval None 01942 */ 01943 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) 01944 /** 01945 * @brief Enables the specified ETHERNET MMC Tx interrupts. 01946 * @param __HANDLE__: ETH Handle. 01947 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 01948 * This parameter can be one of the following values: 01949 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 01950 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 01951 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 01952 * @retval None 01953 */ 01954 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 01955 01956 /** 01957 * @brief Disables the specified ETHERNET MMC Tx interrupts. 01958 * @param __HANDLE__: ETH Handle. 01959 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 01960 * This parameter can be one of the following values: 01961 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 01962 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 01963 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 01964 * @retval None 01965 */ 01966 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 01967 01968 /** 01969 * @brief Enables the ETH External interrupt line. 01970 * @retval None 01971 */ 01972 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 01973 01974 /** 01975 * @brief Disables the ETH External interrupt line. 01976 * @retval None 01977 */ 01978 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 01979 01980 /** 01981 * @brief Enable event on ETH External event line. 01982 * @retval None. 01983 */ 01984 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 01985 01986 /** 01987 * @brief Disable event on ETH External event line 01988 * @retval None. 01989 */ 01990 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 01991 01992 /** 01993 * @brief Get flag of the ETH External interrupt line. 01994 * @retval None 01995 */ 01996 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 01997 01998 /** 01999 * @brief Clear flag of the ETH External interrupt line. 02000 * @retval None 02001 */ 02002 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 02003 02004 /** 02005 * @brief Enables rising edge trigger to the ETH External interrupt line. 02006 * @retval None 02007 */ 02008 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 02009 02010 /** 02011 * @brief Disables the rising edge trigger to the ETH External interrupt line. 02012 * @retval None 02013 */ 02014 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 02015 02016 /** 02017 * @brief Enables falling edge trigger to the ETH External interrupt line. 02018 * @retval None 02019 */ 02020 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 02021 02022 /** 02023 * @brief Disables falling edge trigger to the ETH External interrupt line. 02024 * @retval None 02025 */ 02026 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 02027 02028 /** 02029 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. 02030 * @retval None 02031 */ 02032 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ 02033 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ 02034 }while(0U) 02035 02036 /** 02037 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. 02038 * @retval None 02039 */ 02040 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 02041 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 02042 }while(0U) 02043 02044 /** 02045 * @brief Generate a Software interrupt on selected EXTI line. 02046 * @retval None. 02047 */ 02048 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 02049 02050 /** 02051 * @} 02052 */ 02053 /* Exported functions --------------------------------------------------------*/ 02054 02055 /** @addtogroup ETH_Exported_Functions 02056 * @{ 02057 */ 02058 02059 /* Initialization and de-initialization functions ****************************/ 02060 02061 /** @addtogroup ETH_Exported_Functions_Group1 02062 * @{ 02063 */ 02064 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 02065 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 02066 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 02067 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 02068 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); 02069 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 02070 /* Callbacks Register/UnRegister functions ***********************************/ 02071 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) 02072 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); 02073 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); 02074 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ 02075 02076 /** 02077 * @} 02078 */ 02079 /* IO operation functions ****************************************************/ 02080 02081 /** @addtogroup ETH_Exported_Functions_Group2 02082 * @{ 02083 */ 02084 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); 02085 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); 02086 /* Communication with PHY functions*/ 02087 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); 02088 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); 02089 /* Non-Blocking mode: Interrupt */ 02090 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); 02091 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 02092 /* Callback in non blocking modes (Interrupt) */ 02093 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 02094 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 02095 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 02096 /** 02097 * @} 02098 */ 02099 02100 /* Peripheral Control functions **********************************************/ 02101 02102 /** @addtogroup ETH_Exported_Functions_Group3 02103 * @{ 02104 */ 02105 02106 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 02107 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 02108 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); 02109 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); 02110 /** 02111 * @} 02112 */ 02113 02114 /* Peripheral State functions ************************************************/ 02115 02116 /** @addtogroup ETH_Exported_Functions_Group4 02117 * @{ 02118 */ 02119 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 02120 /** 02121 * @} 02122 */ 02123 02124 /** 02125 * @} 02126 */ 02127 02128 /** 02129 * @} 02130 */ 02131 02132 /** 02133 * @} 02134 */ 02135 02136 #endif /* ETH */ 02137 02138 #ifdef __cplusplus 02139 } 02140 #endif 02141 02142 #endif /* __STM32F1xx_HAL_ETH_H */ 02143 02144 02145 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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