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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_hal_nand.h 00004 * @author MCD Application Team 00005 * @brief Header file of NAND HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F1xx_HAL_NAND_H 00022 #define STM32F1xx_HAL_NAND_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 #if defined(FSMC_BANK3) 00029 00030 /* Includes ------------------------------------------------------------------*/ 00031 #include "stm32f1xx_ll_fsmc.h" 00032 00033 /** @addtogroup STM32F1xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup NAND 00038 * @{ 00039 */ 00040 00041 /* Exported typedef ----------------------------------------------------------*/ 00042 /* Exported types ------------------------------------------------------------*/ 00043 /** @defgroup NAND_Exported_Types NAND Exported Types 00044 * @{ 00045 */ 00046 00047 /** 00048 * @brief HAL NAND State structures definition 00049 */ 00050 typedef enum 00051 { 00052 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 00053 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 00054 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 00055 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 00056 } HAL_NAND_StateTypeDef; 00057 00058 /** 00059 * @brief NAND Memory electronic signature Structure definition 00060 */ 00061 typedef struct 00062 { 00063 /*<! NAND memory electronic signature maker and device IDs */ 00064 00065 uint8_t Maker_Id; 00066 00067 uint8_t Device_Id; 00068 00069 uint8_t Third_Id; 00070 00071 uint8_t Fourth_Id; 00072 } NAND_IDTypeDef; 00073 00074 /** 00075 * @brief NAND Memory address Structure definition 00076 */ 00077 typedef struct 00078 { 00079 uint16_t Page; /*!< NAND memory Page address */ 00080 00081 uint16_t Plane; /*!< NAND memory Zone address */ 00082 00083 uint16_t Block; /*!< NAND memory Block address */ 00084 00085 } NAND_AddressTypeDef; 00086 00087 /** 00088 * @brief NAND Memory info Structure definition 00089 */ 00090 typedef struct 00091 { 00092 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 00093 for 8 bits addressing or words for 16 bits addressing */ 00094 00095 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 00096 for 8 bits addressing or words for 16 bits addressing */ 00097 00098 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 00099 00100 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 00101 00102 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 00103 00104 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 00105 00106 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 00107 parameter is mandatory for some NAND parts after the read 00108 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 00109 Example: Toshiba THTH58BYG3S0HBAI6. 00110 This parameter could be ENABLE or DISABLE 00111 Please check the Read Mode sequnece in the NAND device datasheet */ 00112 } NAND_DeviceConfigTypeDef; 00113 00114 /** 00115 * @brief NAND handle Structure definition 00116 */ 00117 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00118 typedef struct __NAND_HandleTypeDef 00119 #else 00120 typedef struct 00121 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00122 { 00123 FSMC_NAND_TypeDef *Instance; /*!< Register base address */ 00124 00125 FSMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 00126 00127 HAL_LockTypeDef Lock; /*!< NAND locking object */ 00128 00129 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 00130 00131 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ 00132 00133 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00134 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ 00135 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ 00136 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ 00137 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00138 } NAND_HandleTypeDef; 00139 00140 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00141 /** 00142 * @brief HAL NAND Callback ID enumeration definition 00143 */ 00144 typedef enum 00145 { 00146 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ 00147 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ 00148 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ 00149 } HAL_NAND_CallbackIDTypeDef; 00150 00151 /** 00152 * @brief HAL NAND Callback pointer definition 00153 */ 00154 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); 00155 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00156 00157 /** 00158 * @} 00159 */ 00160 00161 /* Exported constants --------------------------------------------------------*/ 00162 /* Exported macro ------------------------------------------------------------*/ 00163 /** @defgroup NAND_Exported_Macros NAND Exported Macros 00164 * @{ 00165 */ 00166 00167 /** @brief Reset NAND handle state 00168 * @param __HANDLE__ specifies the NAND handle. 00169 * @retval None 00170 */ 00171 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00172 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ 00173 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ 00174 (__HANDLE__)->MspInitCallback = NULL; \ 00175 (__HANDLE__)->MspDeInitCallback = NULL; \ 00176 } while(0) 00177 #else 00178 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 00179 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00180 00181 /** 00182 * @} 00183 */ 00184 00185 /* Exported functions --------------------------------------------------------*/ 00186 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 00187 * @{ 00188 */ 00189 00190 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 00191 * @{ 00192 */ 00193 00194 /* Initialization/de-initialization functions ********************************/ 00195 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FSMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, 00196 FSMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 00197 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 00198 00199 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 00200 00201 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 00202 00203 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 00204 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 00205 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 00206 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 00207 00208 /** 00209 * @} 00210 */ 00211 00212 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 00213 * @{ 00214 */ 00215 00216 /* IO operation functions ****************************************************/ 00217 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 00218 00219 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 00220 uint32_t NumPageToRead); 00221 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 00222 uint32_t NumPageToWrite); 00223 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00224 uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 00225 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00226 uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 00227 00228 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 00229 uint32_t NumPageToRead); 00230 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 00231 uint32_t NumPageToWrite); 00232 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00233 uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 00234 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00235 uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 00236 00237 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00238 00239 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00240 00241 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00242 /* NAND callback registering/unregistering */ 00243 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, 00244 pNAND_CallbackTypeDef pCallback); 00245 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); 00246 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00247 00248 /** 00249 * @} 00250 */ 00251 00252 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 00253 * @{ 00254 */ 00255 00256 /* NAND Control functions ****************************************************/ 00257 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 00258 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 00259 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 00260 00261 /** 00262 * @} 00263 */ 00264 00265 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 00266 * @{ 00267 */ 00268 /* NAND State functions *******************************************************/ 00269 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); 00270 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); 00271 /** 00272 * @} 00273 */ 00274 00275 /** 00276 * @} 00277 */ 00278 00279 /* Private types -------------------------------------------------------------*/ 00280 /* Private variables ---------------------------------------------------------*/ 00281 /* Private constants ---------------------------------------------------------*/ 00282 /** @defgroup NAND_Private_Constants NAND Private Constants 00283 * @{ 00284 */ 00285 #define NAND_DEVICE1 0x70000000UL 00286 #define NAND_DEVICE2 0x80000000UL 00287 #define NAND_WRITE_TIMEOUT 0x01000000UL 00288 00289 #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ 00290 #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ 00291 00292 #define NAND_CMD_AREA_A ((uint8_t)0x00) 00293 #define NAND_CMD_AREA_B ((uint8_t)0x01) 00294 #define NAND_CMD_AREA_C ((uint8_t)0x50) 00295 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) 00296 00297 #define NAND_CMD_WRITE0 ((uint8_t)0x80) 00298 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) 00299 #define NAND_CMD_ERASE0 ((uint8_t)0x60) 00300 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) 00301 #define NAND_CMD_READID ((uint8_t)0x90) 00302 #define NAND_CMD_STATUS ((uint8_t)0x70) 00303 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) 00304 #define NAND_CMD_RESET ((uint8_t)0xFF) 00305 00306 /* NAND memory status */ 00307 #define NAND_VALID_ADDRESS 0x00000100UL 00308 #define NAND_INVALID_ADDRESS 0x00000200UL 00309 #define NAND_TIMEOUT_ERROR 0x00000400UL 00310 #define NAND_BUSY 0x00000000UL 00311 #define NAND_ERROR 0x00000001UL 00312 #define NAND_READY 0x00000040UL 00313 /** 00314 * @} 00315 */ 00316 00317 /* Private macros ------------------------------------------------------------*/ 00318 /** @defgroup NAND_Private_Macros NAND Private Macros 00319 * @{ 00320 */ 00321 00322 /** 00323 * @brief NAND memory address computation. 00324 * @param __ADDRESS__ NAND memory address. 00325 * @param __HANDLE__ NAND handle. 00326 * @retval NAND Raw address value 00327 */ 00328 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ 00329 (((__ADDRESS__)->Block + \ 00330 (((__ADDRESS__)->Plane) * \ 00331 ((__HANDLE__)->Config.PlaneSize))) * \ 00332 ((__HANDLE__)->Config.BlockSize))) 00333 00334 /** 00335 * @brief NAND memory Column address computation. 00336 * @param __HANDLE__ NAND handle. 00337 * @retval NAND Raw address value 00338 */ 00339 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 00340 00341 /** 00342 * @brief NAND memory address cycling. 00343 * @param __ADDRESS__ NAND memory address. 00344 * @retval NAND address cycling value. 00345 */ 00346 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 00347 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 00348 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 00349 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 00350 00351 /** 00352 * @brief NAND memory Columns cycling. 00353 * @param __ADDRESS__ NAND memory address. 00354 * @retval NAND Column address cycling value. 00355 */ 00356 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ 00357 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 00358 00359 /** 00360 * @} 00361 */ 00362 00363 /** 00364 * @} 00365 */ 00366 00367 /** 00368 * @} 00369 */ 00370 00371 /** 00372 * @} 00373 */ 00374 00375 #endif /* FSMC_BANK3 */ 00376 00377 #ifdef __cplusplus 00378 } 00379 #endif 00380 00381 #endif /* STM32F1xx_HAL_NAND_H */ 00382 00383 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1