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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @brief Header file of BUS LL module. 00006 00007 @verbatim 00008 ##### RCC Limitations ##### 00009 ============================================================================== 00010 [..] 00011 A delay between an RCC peripheral clock enable and the effective peripheral 00012 enabling should be taken into account in order to manage the peripheral read/write 00013 from/to registers. 00014 (+) This delay depends on the peripheral mapping. 00015 (++) AHB & APB peripherals, 1 dummy read is necessary 00016 00017 [..] 00018 Workarounds: 00019 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00020 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 00021 00022 @endverbatim 00023 ****************************************************************************** 00024 * @attention 00025 * 00026 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00027 * All rights reserved.</center></h2> 00028 * 00029 * This software component is licensed by ST under BSD 3-Clause license, 00030 * the "License"; You may not use this file except in compliance with the 00031 * License. You may obtain a copy of the License at: 00032 * opensource.org/licenses/BSD-3-Clause 00033 * 00034 ****************************************************************************** 00035 */ 00036 00037 /* Define to prevent recursive inclusion -------------------------------------*/ 00038 #ifndef __STM32F1xx_LL_BUS_H 00039 #define __STM32F1xx_LL_BUS_H 00040 00041 #ifdef __cplusplus 00042 extern "C" { 00043 #endif 00044 00045 /* Includes ------------------------------------------------------------------*/ 00046 #include "stm32f1xx.h" 00047 00048 /** @addtogroup STM32F1xx_LL_Driver 00049 * @{ 00050 */ 00051 00052 #if defined(RCC) 00053 00054 /** @defgroup BUS_LL BUS 00055 * @{ 00056 */ 00057 00058 /* Private types -------------------------------------------------------------*/ 00059 /* Private variables ---------------------------------------------------------*/ 00060 00061 /* Private constants ---------------------------------------------------------*/ 00062 #if defined(RCC_AHBRSTR_OTGFSRST) || defined(RCC_AHBRSTR_ETHMACRST) 00063 #define RCC_AHBRSTR_SUPPORT 00064 #endif /* RCC_AHBRSTR_OTGFSRST || RCC_AHBRSTR_ETHMACRST */ 00065 00066 /* Private macros ------------------------------------------------------------*/ 00067 00068 /* Exported types ------------------------------------------------------------*/ 00069 /* Exported constants --------------------------------------------------------*/ 00070 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00071 * @{ 00072 */ 00073 00074 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00075 * @{ 00076 */ 00077 #define LL_AHB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00078 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN 00079 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMA1EN 00080 #if defined(DMA2) 00081 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHBENR_DMA2EN 00082 #endif /*DMA2*/ 00083 #if defined(ETH) 00084 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHBENR_ETHMACEN 00085 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHBENR_ETHMACRXEN 00086 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHBENR_ETHMACTXEN 00087 #endif /*ETH*/ 00088 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLITFEN 00089 #if defined(FSMC_Bank1) 00090 #define LL_AHB1_GRP1_PERIPH_FSMC RCC_AHBENR_FSMCEN 00091 #endif /*FSMC_Bank1*/ 00092 #if defined(USB_OTG_FS) 00093 #define LL_AHB1_GRP1_PERIPH_OTGFS RCC_AHBENR_OTGFSEN 00094 #endif /*USB_OTG_FS*/ 00095 #if defined(SDIO) 00096 #define LL_AHB1_GRP1_PERIPH_SDIO RCC_AHBENR_SDIOEN 00097 #endif /*SDIO*/ 00098 #define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN 00099 /** 00100 * @} 00101 */ 00102 00103 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00104 * @{ 00105 */ 00106 #define LL_APB1_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00107 #define LL_APB1_GRP1_PERIPH_BKP RCC_APB1ENR_BKPEN 00108 #if defined(CAN1) 00109 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN 00110 #endif /*CAN1*/ 00111 #if defined(CAN2) 00112 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN 00113 #endif /*CAN2*/ 00114 #if defined(CEC) 00115 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN 00116 #endif /*CEC*/ 00117 #if defined(DAC) 00118 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN 00119 #endif /*DAC*/ 00120 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN 00121 #if defined(I2C2) 00122 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN 00123 #endif /*I2C2*/ 00124 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN 00125 #if defined(SPI2) 00126 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN 00127 #endif /*SPI2*/ 00128 #if defined(SPI3) 00129 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN 00130 #endif /*SPI3*/ 00131 #if defined(TIM12) 00132 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN 00133 #endif /*TIM12*/ 00134 #if defined(TIM13) 00135 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN 00136 #endif /*TIM13*/ 00137 #if defined(TIM14) 00138 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN 00139 #endif /*TIM14*/ 00140 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN 00141 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN 00142 #if defined(TIM4) 00143 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN 00144 #endif /*TIM4*/ 00145 #if defined(TIM5) 00146 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN 00147 #endif /*TIM5*/ 00148 #if defined(TIM6) 00149 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN 00150 #endif /*TIM6*/ 00151 #if defined(TIM7) 00152 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN 00153 #endif /*TIM7*/ 00154 #if defined(UART4) 00155 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN 00156 #endif /*UART4*/ 00157 #if defined(UART5) 00158 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN 00159 #endif /*UART5*/ 00160 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN 00161 #if defined(USART3) 00162 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN 00163 #endif /*USART3*/ 00164 #if defined(USB) 00165 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR_USBEN 00166 #endif /*USB*/ 00167 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN 00168 /** 00169 * @} 00170 */ 00171 00172 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 00173 * @{ 00174 */ 00175 #define LL_APB2_GRP1_PERIPH_ALL (uint32_t)0xFFFFFFFFU 00176 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN 00177 #if defined(ADC2) 00178 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN 00179 #endif /*ADC2*/ 00180 #if defined(ADC3) 00181 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN 00182 #endif /*ADC3*/ 00183 #define LL_APB2_GRP1_PERIPH_AFIO RCC_APB2ENR_AFIOEN 00184 #define LL_APB2_GRP1_PERIPH_GPIOA RCC_APB2ENR_IOPAEN 00185 #define LL_APB2_GRP1_PERIPH_GPIOB RCC_APB2ENR_IOPBEN 00186 #define LL_APB2_GRP1_PERIPH_GPIOC RCC_APB2ENR_IOPCEN 00187 #define LL_APB2_GRP1_PERIPH_GPIOD RCC_APB2ENR_IOPDEN 00188 #if defined(GPIOE) 00189 #define LL_APB2_GRP1_PERIPH_GPIOE RCC_APB2ENR_IOPEEN 00190 #endif /*GPIOE*/ 00191 #if defined(GPIOF) 00192 #define LL_APB2_GRP1_PERIPH_GPIOF RCC_APB2ENR_IOPFEN 00193 #endif /*GPIOF*/ 00194 #if defined(GPIOG) 00195 #define LL_APB2_GRP1_PERIPH_GPIOG RCC_APB2ENR_IOPGEN 00196 #endif /*GPIOG*/ 00197 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 00198 #if defined(TIM10) 00199 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN 00200 #endif /*TIM10*/ 00201 #if defined(TIM11) 00202 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN 00203 #endif /*TIM11*/ 00204 #if defined(TIM15) 00205 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN 00206 #endif /*TIM15*/ 00207 #if defined(TIM16) 00208 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN 00209 #endif /*TIM16*/ 00210 #if defined(TIM17) 00211 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN 00212 #endif /*TIM17*/ 00213 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 00214 #if defined(TIM8) 00215 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 00216 #endif /*TIM8*/ 00217 #if defined(TIM9) 00218 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN 00219 #endif /*TIM9*/ 00220 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 00221 /** 00222 * @} 00223 */ 00224 00225 /** 00226 * @} 00227 */ 00228 00229 /* Exported macro ------------------------------------------------------------*/ 00230 00231 /* Exported functions --------------------------------------------------------*/ 00232 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 00233 * @{ 00234 */ 00235 00236 /** @defgroup BUS_LL_EF_AHB1 AHB1 00237 * @{ 00238 */ 00239 00240 /** 00241 * @brief Enable AHB1 peripherals clock. 00242 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_EnableClock\n 00243 * AHBENR DMA1EN LL_AHB1_GRP1_EnableClock\n 00244 * AHBENR DMA2EN LL_AHB1_GRP1_EnableClock\n 00245 * AHBENR ETHMACEN LL_AHB1_GRP1_EnableClock\n 00246 * AHBENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n 00247 * AHBENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n 00248 * AHBENR FLITFEN LL_AHB1_GRP1_EnableClock\n 00249 * AHBENR FSMCEN LL_AHB1_GRP1_EnableClock\n 00250 * AHBENR OTGFSEN LL_AHB1_GRP1_EnableClock\n 00251 * AHBENR SDIOEN LL_AHB1_GRP1_EnableClock\n 00252 * AHBENR SRAMEN LL_AHB1_GRP1_EnableClock 00253 * @param Periphs This parameter can be a combination of the following values: 00254 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00255 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00256 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) 00257 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00258 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00259 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00260 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00261 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) 00262 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) 00263 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) 00264 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM 00265 * 00266 * (*) value not defined in all devices. 00267 * @retval None 00268 */ 00269 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 00270 { 00271 __IO uint32_t tmpreg; 00272 SET_BIT(RCC->AHBENR, Periphs); 00273 /* Delay after an RCC peripheral clock enabling */ 00274 tmpreg = READ_BIT(RCC->AHBENR, Periphs); 00275 (void)tmpreg; 00276 } 00277 00278 /** 00279 * @brief Check if AHB1 peripheral clock is enabled or not 00280 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 00281 * AHBENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 00282 * AHBENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 00283 * AHBENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n 00284 * AHBENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n 00285 * AHBENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n 00286 * AHBENR FLITFEN LL_AHB1_GRP1_IsEnabledClock\n 00287 * AHBENR FSMCEN LL_AHB1_GRP1_IsEnabledClock\n 00288 * AHBENR OTGFSEN LL_AHB1_GRP1_IsEnabledClock\n 00289 * AHBENR SDIOEN LL_AHB1_GRP1_IsEnabledClock\n 00290 * AHBENR SRAMEN LL_AHB1_GRP1_IsEnabledClock 00291 * @param Periphs This parameter can be a combination of the following values: 00292 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00293 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00294 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) 00295 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00296 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00297 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00298 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00299 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) 00300 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) 00301 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) 00302 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM 00303 * 00304 * (*) value not defined in all devices. 00305 * @retval State of Periphs (1 or 0). 00306 */ 00307 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 00308 { 00309 return (READ_BIT(RCC->AHBENR, Periphs) == Periphs); 00310 } 00311 00312 /** 00313 * @brief Disable AHB1 peripherals clock. 00314 * @rmtoll AHBENR CRCEN LL_AHB1_GRP1_DisableClock\n 00315 * AHBENR DMA1EN LL_AHB1_GRP1_DisableClock\n 00316 * AHBENR DMA2EN LL_AHB1_GRP1_DisableClock\n 00317 * AHBENR ETHMACEN LL_AHB1_GRP1_DisableClock\n 00318 * AHBENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n 00319 * AHBENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n 00320 * AHBENR FLITFEN LL_AHB1_GRP1_DisableClock\n 00321 * AHBENR FSMCEN LL_AHB1_GRP1_DisableClock\n 00322 * AHBENR OTGFSEN LL_AHB1_GRP1_DisableClock\n 00323 * AHBENR SDIOEN LL_AHB1_GRP1_DisableClock\n 00324 * AHBENR SRAMEN LL_AHB1_GRP1_DisableClock 00325 * @param Periphs This parameter can be a combination of the following values: 00326 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00327 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00328 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 (*) 00329 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00330 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*) 00331 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*) 00332 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00333 * @arg @ref LL_AHB1_GRP1_PERIPH_FSMC (*) 00334 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) 00335 * @arg @ref LL_AHB1_GRP1_PERIPH_SDIO (*) 00336 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM 00337 * 00338 * (*) value not defined in all devices. 00339 * @retval None 00340 */ 00341 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 00342 { 00343 CLEAR_BIT(RCC->AHBENR, Periphs); 00344 } 00345 00346 #if defined(RCC_AHBRSTR_SUPPORT) 00347 /** 00348 * @brief Force AHB1 peripherals reset. 00349 * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n 00350 * AHBRSTR OTGFSRST LL_AHB1_GRP1_ForceReset 00351 * @param Periphs This parameter can be a combination of the following values: 00352 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00353 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00354 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) 00355 * 00356 * (*) value not defined in all devices. 00357 * @retval None 00358 */ 00359 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 00360 { 00361 SET_BIT(RCC->AHBRSTR, Periphs); 00362 } 00363 00364 /** 00365 * @brief Release AHB1 peripherals reset. 00366 * @rmtoll AHBRSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n 00367 * AHBRSTR OTGFSRST LL_AHB1_GRP1_ReleaseReset 00368 * @param Periphs This parameter can be a combination of the following values: 00369 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00370 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*) 00371 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGFS (*) 00372 * 00373 * (*) value not defined in all devices. 00374 * @retval None 00375 */ 00376 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 00377 { 00378 CLEAR_BIT(RCC->AHBRSTR, Periphs); 00379 } 00380 #endif /* RCC_AHBRSTR_SUPPORT */ 00381 00382 /** 00383 * @} 00384 */ 00385 00386 /** @defgroup BUS_LL_EF_APB1 APB1 00387 * @{ 00388 */ 00389 00390 /** 00391 * @brief Enable APB1 peripherals clock. 00392 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_EnableClock\n 00393 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n 00394 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n 00395 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n 00396 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n 00397 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n 00398 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n 00399 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n 00400 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n 00401 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n 00402 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n 00403 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n 00404 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n 00405 * APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n 00406 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n 00407 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n 00408 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n 00409 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n 00410 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n 00411 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n 00412 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n 00413 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n 00414 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n 00415 * APB1ENR USBEN LL_APB1_GRP1_EnableClock\n 00416 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock 00417 * @param Periphs This parameter can be a combination of the following values: 00418 * @arg @ref LL_APB1_GRP1_PERIPH_BKP 00419 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 00420 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 00421 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 00422 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 00423 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00424 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 00425 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00426 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 00427 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 00428 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 00429 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 00430 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 00431 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00432 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00433 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 00434 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 00435 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 00436 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 00437 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 00438 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 00439 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00440 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 00441 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 00442 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00443 * 00444 * (*) value not defined in all devices. 00445 * @retval None 00446 */ 00447 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 00448 { 00449 __IO uint32_t tmpreg; 00450 SET_BIT(RCC->APB1ENR, Periphs); 00451 /* Delay after an RCC peripheral clock enabling */ 00452 tmpreg = READ_BIT(RCC->APB1ENR, Periphs); 00453 (void)tmpreg; 00454 } 00455 00456 /** 00457 * @brief Check if APB1 peripheral clock is enabled or not 00458 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_IsEnabledClock\n 00459 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n 00460 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n 00461 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n 00462 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n 00463 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n 00464 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n 00465 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n 00466 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n 00467 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n 00468 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n 00469 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n 00470 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n 00471 * APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n 00472 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n 00473 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n 00474 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n 00475 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n 00476 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n 00477 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n 00478 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n 00479 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n 00480 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n 00481 * APB1ENR USBEN LL_APB1_GRP1_IsEnabledClock\n 00482 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock 00483 * @param Periphs This parameter can be a combination of the following values: 00484 * @arg @ref LL_APB1_GRP1_PERIPH_BKP 00485 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 00486 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 00487 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 00488 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 00489 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00490 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 00491 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00492 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 00493 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 00494 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 00495 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 00496 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 00497 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00498 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00499 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 00500 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 00501 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 00502 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 00503 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 00504 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 00505 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00506 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 00507 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 00508 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00509 * 00510 * (*) value not defined in all devices. 00511 * @retval State of Periphs (1 or 0). 00512 */ 00513 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 00514 { 00515 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs); 00516 } 00517 00518 /** 00519 * @brief Disable APB1 peripherals clock. 00520 * @rmtoll APB1ENR BKPEN LL_APB1_GRP1_DisableClock\n 00521 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n 00522 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n 00523 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n 00524 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n 00525 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n 00526 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n 00527 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n 00528 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n 00529 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n 00530 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n 00531 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n 00532 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n 00533 * APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n 00534 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n 00535 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n 00536 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n 00537 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n 00538 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n 00539 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n 00540 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n 00541 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n 00542 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n 00543 * APB1ENR USBEN LL_APB1_GRP1_DisableClock\n 00544 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock 00545 * @param Periphs This parameter can be a combination of the following values: 00546 * @arg @ref LL_APB1_GRP1_PERIPH_BKP 00547 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 00548 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 00549 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 00550 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 00551 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00552 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 00553 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00554 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 00555 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 00556 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 00557 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 00558 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 00559 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00560 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00561 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 00562 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 00563 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 00564 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 00565 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 00566 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 00567 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00568 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 00569 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 00570 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00571 * 00572 * (*) value not defined in all devices. 00573 * @retval None 00574 */ 00575 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 00576 { 00577 CLEAR_BIT(RCC->APB1ENR, Periphs); 00578 } 00579 00580 /** 00581 * @brief Force APB1 peripherals reset. 00582 * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ForceReset\n 00583 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n 00584 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n 00585 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n 00586 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n 00587 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n 00588 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n 00589 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n 00590 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n 00591 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n 00592 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n 00593 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n 00594 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n 00595 * APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n 00596 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n 00597 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n 00598 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n 00599 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n 00600 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n 00601 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n 00602 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n 00603 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n 00604 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n 00605 * APB1RSTR USBRST LL_APB1_GRP1_ForceReset\n 00606 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset 00607 * @param Periphs This parameter can be a combination of the following values: 00608 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 00609 * @arg @ref LL_APB1_GRP1_PERIPH_BKP 00610 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 00611 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 00612 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 00613 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 00614 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00615 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 00616 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00617 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 00618 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 00619 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 00620 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 00621 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 00622 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00623 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00624 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 00625 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 00626 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 00627 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 00628 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 00629 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 00630 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00631 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 00632 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 00633 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00634 * 00635 * (*) value not defined in all devices. 00636 * @retval None 00637 */ 00638 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 00639 { 00640 SET_BIT(RCC->APB1RSTR, Periphs); 00641 } 00642 00643 /** 00644 * @brief Release APB1 peripherals reset. 00645 * @rmtoll APB1RSTR BKPRST LL_APB1_GRP1_ReleaseReset\n 00646 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n 00647 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n 00648 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n 00649 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n 00650 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n 00651 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n 00652 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n 00653 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n 00654 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n 00655 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n 00656 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n 00657 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n 00658 * APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n 00659 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n 00660 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n 00661 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n 00662 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n 00663 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n 00664 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n 00665 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n 00666 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n 00667 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n 00668 * APB1RSTR USBRST LL_APB1_GRP1_ReleaseReset\n 00669 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset 00670 * @param Periphs This parameter can be a combination of the following values: 00671 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 00672 * @arg @ref LL_APB1_GRP1_PERIPH_BKP 00673 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 (*) 00674 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 00675 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*) 00676 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 (*) 00677 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 00678 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 00679 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 00680 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 00681 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 (*) 00682 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12 (*) 00683 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13 (*) 00684 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14 (*) 00685 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 00686 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 00687 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 00688 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 00689 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 (*) 00690 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 (*) 00691 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 00692 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 00693 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 00694 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 00695 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 00696 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 00697 * 00698 * (*) value not defined in all devices. 00699 * @retval None 00700 */ 00701 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 00702 { 00703 CLEAR_BIT(RCC->APB1RSTR, Periphs); 00704 } 00705 00706 /** 00707 * @} 00708 */ 00709 00710 /** @defgroup BUS_LL_EF_APB2 APB2 00711 * @{ 00712 */ 00713 00714 /** 00715 * @brief Enable APB2 peripherals clock. 00716 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n 00717 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n 00718 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n 00719 * APB2ENR AFIOEN LL_APB2_GRP1_EnableClock\n 00720 * APB2ENR IOPAEN LL_APB2_GRP1_EnableClock\n 00721 * APB2ENR IOPBEN LL_APB2_GRP1_EnableClock\n 00722 * APB2ENR IOPCEN LL_APB2_GRP1_EnableClock\n 00723 * APB2ENR IOPDEN LL_APB2_GRP1_EnableClock\n 00724 * APB2ENR IOPEEN LL_APB2_GRP1_EnableClock\n 00725 * APB2ENR IOPFEN LL_APB2_GRP1_EnableClock\n 00726 * APB2ENR IOPGEN LL_APB2_GRP1_EnableClock\n 00727 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 00728 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n 00729 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n 00730 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n 00731 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n 00732 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n 00733 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 00734 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 00735 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n 00736 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock 00737 * @param Periphs This parameter can be a combination of the following values: 00738 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 00739 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 00740 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 00741 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO 00742 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA 00743 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB 00744 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC 00745 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD 00746 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) 00747 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) 00748 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) 00749 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 00750 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 00751 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) 00752 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) 00753 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) 00754 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 00755 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 00756 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 00757 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) 00758 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 00759 * 00760 * (*) value not defined in all devices. 00761 * @retval None 00762 */ 00763 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 00764 { 00765 __IO uint32_t tmpreg; 00766 SET_BIT(RCC->APB2ENR, Periphs); 00767 /* Delay after an RCC peripheral clock enabling */ 00768 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 00769 (void)tmpreg; 00770 } 00771 00772 /** 00773 * @brief Check if APB2 peripheral clock is enabled or not 00774 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n 00775 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n 00776 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n 00777 * APB2ENR AFIOEN LL_APB2_GRP1_IsEnabledClock\n 00778 * APB2ENR IOPAEN LL_APB2_GRP1_IsEnabledClock\n 00779 * APB2ENR IOPBEN LL_APB2_GRP1_IsEnabledClock\n 00780 * APB2ENR IOPCEN LL_APB2_GRP1_IsEnabledClock\n 00781 * APB2ENR IOPDEN LL_APB2_GRP1_IsEnabledClock\n 00782 * APB2ENR IOPEEN LL_APB2_GRP1_IsEnabledClock\n 00783 * APB2ENR IOPFEN LL_APB2_GRP1_IsEnabledClock\n 00784 * APB2ENR IOPGEN LL_APB2_GRP1_IsEnabledClock\n 00785 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 00786 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n 00787 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n 00788 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n 00789 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n 00790 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n 00791 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 00792 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 00793 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n 00794 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock 00795 * @param Periphs This parameter can be a combination of the following values: 00796 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 00797 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 00798 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 00799 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO 00800 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA 00801 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB 00802 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC 00803 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD 00804 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) 00805 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) 00806 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) 00807 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 00808 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 00809 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) 00810 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) 00811 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) 00812 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 00813 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 00814 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 00815 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) 00816 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 00817 * 00818 * (*) value not defined in all devices. 00819 * @retval State of Periphs (1 or 0). 00820 */ 00821 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 00822 { 00823 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); 00824 } 00825 00826 /** 00827 * @brief Disable APB2 peripherals clock. 00828 * @rmtoll APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n 00829 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n 00830 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n 00831 * APB2ENR AFIOEN LL_APB2_GRP1_DisableClock\n 00832 * APB2ENR IOPAEN LL_APB2_GRP1_DisableClock\n 00833 * APB2ENR IOPBEN LL_APB2_GRP1_DisableClock\n 00834 * APB2ENR IOPCEN LL_APB2_GRP1_DisableClock\n 00835 * APB2ENR IOPDEN LL_APB2_GRP1_DisableClock\n 00836 * APB2ENR IOPEEN LL_APB2_GRP1_DisableClock\n 00837 * APB2ENR IOPFEN LL_APB2_GRP1_DisableClock\n 00838 * APB2ENR IOPGEN LL_APB2_GRP1_DisableClock\n 00839 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 00840 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n 00841 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n 00842 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n 00843 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n 00844 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n 00845 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 00846 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 00847 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n 00848 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock 00849 * @param Periphs This parameter can be a combination of the following values: 00850 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 00851 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 00852 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 00853 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO 00854 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA 00855 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB 00856 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC 00857 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD 00858 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) 00859 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) 00860 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) 00861 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 00862 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 00863 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) 00864 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) 00865 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) 00866 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 00867 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 00868 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 00869 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) 00870 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 00871 * 00872 * (*) value not defined in all devices. 00873 * @retval None 00874 */ 00875 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 00876 { 00877 CLEAR_BIT(RCC->APB2ENR, Periphs); 00878 } 00879 00880 /** 00881 * @brief Force APB2 peripherals reset. 00882 * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ForceReset\n 00883 * APB2RSTR ADC2RST LL_APB2_GRP1_ForceReset\n 00884 * APB2RSTR ADC3RST LL_APB2_GRP1_ForceReset\n 00885 * APB2RSTR AFIORST LL_APB2_GRP1_ForceReset\n 00886 * APB2RSTR IOPARST LL_APB2_GRP1_ForceReset\n 00887 * APB2RSTR IOPBRST LL_APB2_GRP1_ForceReset\n 00888 * APB2RSTR IOPCRST LL_APB2_GRP1_ForceReset\n 00889 * APB2RSTR IOPDRST LL_APB2_GRP1_ForceReset\n 00890 * APB2RSTR IOPERST LL_APB2_GRP1_ForceReset\n 00891 * APB2RSTR IOPFRST LL_APB2_GRP1_ForceReset\n 00892 * APB2RSTR IOPGRST LL_APB2_GRP1_ForceReset\n 00893 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 00894 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n 00895 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n 00896 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n 00897 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n 00898 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n 00899 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 00900 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 00901 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n 00902 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset 00903 * @param Periphs This parameter can be a combination of the following values: 00904 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 00905 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 00906 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 00907 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 00908 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO 00909 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA 00910 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB 00911 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC 00912 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD 00913 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) 00914 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) 00915 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) 00916 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 00917 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 00918 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) 00919 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) 00920 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) 00921 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 00922 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 00923 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 00924 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) 00925 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 00926 * 00927 * (*) value not defined in all devices. 00928 * @retval None 00929 */ 00930 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 00931 { 00932 SET_BIT(RCC->APB2RSTR, Periphs); 00933 } 00934 00935 /** 00936 * @brief Release APB2 peripherals reset. 00937 * @rmtoll APB2RSTR ADC1RST LL_APB2_GRP1_ReleaseReset\n 00938 * APB2RSTR ADC2RST LL_APB2_GRP1_ReleaseReset\n 00939 * APB2RSTR ADC3RST LL_APB2_GRP1_ReleaseReset\n 00940 * APB2RSTR AFIORST LL_APB2_GRP1_ReleaseReset\n 00941 * APB2RSTR IOPARST LL_APB2_GRP1_ReleaseReset\n 00942 * APB2RSTR IOPBRST LL_APB2_GRP1_ReleaseReset\n 00943 * APB2RSTR IOPCRST LL_APB2_GRP1_ReleaseReset\n 00944 * APB2RSTR IOPDRST LL_APB2_GRP1_ReleaseReset\n 00945 * APB2RSTR IOPERST LL_APB2_GRP1_ReleaseReset\n 00946 * APB2RSTR IOPFRST LL_APB2_GRP1_ReleaseReset\n 00947 * APB2RSTR IOPGRST LL_APB2_GRP1_ReleaseReset\n 00948 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 00949 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n 00950 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n 00951 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n 00952 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n 00953 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n 00954 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 00955 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 00956 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n 00957 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset 00958 * @param Periphs This parameter can be a combination of the following values: 00959 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 00960 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1 00961 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2 (*) 00962 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3 (*) 00963 * @arg @ref LL_APB2_GRP1_PERIPH_AFIO 00964 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOA 00965 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOB 00966 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOC 00967 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOD 00968 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOE (*) 00969 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOF (*) 00970 * @arg @ref LL_APB2_GRP1_PERIPH_GPIOG (*) 00971 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 00972 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10 (*) 00973 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11 (*) 00974 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 (*) 00975 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 (*) 00976 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 00977 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 00978 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 00979 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9 (*) 00980 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 00981 * 00982 * (*) value not defined in all devices. 00983 * @retval None 00984 */ 00985 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 00986 { 00987 CLEAR_BIT(RCC->APB2RSTR, Periphs); 00988 } 00989 00990 /** 00991 * @} 00992 */ 00993 00994 00995 /** 00996 * @} 00997 */ 00998 00999 /** 01000 * @} 01001 */ 01002 01003 #endif /* defined(RCC) */ 01004 01005 /** 01006 * @} 01007 */ 01008 01009 #ifdef __cplusplus 01010 } 01011 #endif 01012 01013 #endif /* __STM32F1xx_LL_BUS_H */ 01014 01015 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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