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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_ll_dac.h 00004 * @author MCD Application Team 00005 * @brief Header file of DAC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F1xx_LL_DAC_H 00022 #define STM32F1xx_LL_DAC_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx.h" 00030 00031 /** @addtogroup STM32F1xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined(DAC) 00036 00037 /** @defgroup DAC_LL DAC 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 00044 /* Private constants ---------------------------------------------------------*/ 00045 /** @defgroup DAC_LL_Private_Constants DAC Private Constants 00046 * @{ 00047 */ 00048 00049 /* Internal masks for DAC channels definition */ 00050 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ 00051 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ 00052 /* - channel bits position into register SWTRIG */ 00053 /* - channel register offset of data holding register DHRx */ 00054 /* - channel register offset of data output register DORx */ 00055 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers 00056 CR, MCR, CCR, SHHR, SHRR of channel 1 */ 00057 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers 00058 CR, MCR, CCR, SHHR, SHRR of channel 2 */ 00059 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) 00060 00061 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ 00062 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ 00063 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) 00064 00065 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ 00066 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus 00067 DHR12Rx channel 1 (shifted left of 20 bits) */ 00068 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus 00069 DHR12Rx channel 1 (shifted left of 24 bits) */ 00070 00071 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus 00072 DHR12Rx channel 1 (shifted left of 16 bits) */ 00073 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus 00074 DHR12Rx channel 1 (shifted left of 20 bits) */ 00075 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus 00076 DHR12Rx channel 1 (shifted left of 24 bits) */ 00077 00078 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL 00079 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL 00080 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL 00081 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ 00082 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) 00083 00084 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ 00085 00086 #define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus 00087 DORx channel 2 (shifted left of 28 bits) */ 00088 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) 00089 00090 00091 00092 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, 00093 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ 00094 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted 00095 to position 0 */ 00096 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted 00097 to position 0 */ 00098 00099 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx 00100 channel 1 or 2 versus DHR12Rx channel 1 00101 (shifted left of 16 bits) */ 00102 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx 00103 channel 1 or 2 versus DHR12Rx channel 1 00104 (shifted left of 20 bits) */ 00105 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx 00106 channel 1 or 2 versus DHR12Rx channel 1 00107 (shifted left of 24 bits) */ 00108 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx 00109 channel 1 or 2 versus DORx channel 1 00110 (shifted left of 28 bits) */ 00111 00112 /* DAC registers bits positions */ 00113 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos 00114 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos 00115 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos 00116 00117 /* Miscellaneous data */ 00118 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 00119 bits (voltage range determined by analog voltage 00120 references Vref+ and Vref-, refer to reference manual) */ 00121 00122 /** 00123 * @} 00124 */ 00125 00126 00127 /* Private macros ------------------------------------------------------------*/ 00128 /** @defgroup DAC_LL_Private_Macros DAC Private Macros 00129 * @{ 00130 */ 00131 00132 /** 00133 * @brief Driver macro reserved for internal use: set a pointer to 00134 * a register from a register basis from which an offset 00135 * is applied. 00136 * @param __REG__ Register basis from which the offset is applied. 00137 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 00138 * @retval Pointer to register address 00139 */ 00140 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00141 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) 00142 00143 /** 00144 * @} 00145 */ 00146 00147 00148 /* Exported types ------------------------------------------------------------*/ 00149 #if defined(USE_FULL_LL_DRIVER) 00150 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure 00151 * @{ 00152 */ 00153 00154 /** 00155 * @brief Structure definition of some features of DAC instance. 00156 */ 00157 typedef struct 00158 { 00159 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: 00160 internal (SW start) or from external peripheral 00161 (timer event, external interrupt line). 00162 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE 00163 00164 This feature can be modified afterwards using unitary 00165 function @ref LL_DAC_SetTriggerSource(). */ 00166 00167 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00168 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE 00169 00170 This feature can be modified afterwards using unitary 00171 function @ref LL_DAC_SetWaveAutoGeneration(). */ 00172 00173 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00174 If waveform automatic generation mode is set to noise, this parameter 00175 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS 00176 If waveform automatic generation mode is set to triangle, 00177 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE 00178 @note If waveform automatic generation mode is disabled, 00179 this parameter is discarded. 00180 00181 This feature can be modified afterwards using unitary 00182 function @ref LL_DAC_SetWaveNoiseLFSR(), 00183 @ref LL_DAC_SetWaveTriangleAmplitude() 00184 depending on the wave automatic generation selected. */ 00185 00186 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. 00187 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER 00188 00189 This feature can be modified afterwards using unitary 00190 function @ref LL_DAC_SetOutputBuffer(). */ 00191 } LL_DAC_InitTypeDef; 00192 00193 /** 00194 * @} 00195 */ 00196 #endif /* USE_FULL_LL_DRIVER */ 00197 00198 /* Exported constants --------------------------------------------------------*/ 00199 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants 00200 * @{ 00201 */ 00202 00203 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags 00204 * @brief Flags defines which can be used with LL_DAC_ReadReg function 00205 * @{ 00206 */ 00207 /* DAC channel 1 flags */ 00208 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ 00209 00210 /* DAC channel 2 flags */ 00211 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ 00212 00213 /** 00214 * @} 00215 */ 00216 00217 /** @defgroup DAC_LL_EC_IT DAC interruptions 00218 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions 00219 * @{ 00220 */ 00221 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ 00222 00223 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ 00224 00225 /** 00226 * @} 00227 */ 00228 00229 /** @defgroup DAC_LL_EC_CHANNEL DAC channels 00230 * @{ 00231 */ 00232 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ 00233 00234 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ 00235 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source 00241 * @{ 00242 */ 00243 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ 00244 #define LL_DAC_TRIG_EXT_TIM3_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM3 TRGO. */ 00245 #define LL_DAC_TRIG_EXT_TIM15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ 00246 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ 00247 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ 00248 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ 00249 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ 00250 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ 00251 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ 00252 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode 00258 * @{ 00259 */ 00260 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ 00261 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ 00262 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ 00263 /** 00264 * @} 00265 */ 00266 00267 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits 00268 * @{ 00269 */ 00270 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ 00271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ 00272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ 00273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ 00274 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ 00275 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ 00276 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ 00277 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ 00278 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ 00279 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ 00280 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ 00281 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ 00282 /** 00283 * @} 00284 */ 00285 00286 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude 00287 * @{ 00288 */ 00289 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ 00290 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ 00291 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ 00292 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ 00293 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ 00294 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ 00295 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ 00296 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ 00297 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ 00298 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ 00299 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ 00300 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ 00301 /** 00302 * @} 00303 */ 00304 00305 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer 00306 * @{ 00307 */ 00308 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ 00309 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ 00310 /** 00311 * @} 00312 */ 00313 00314 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution 00315 * @{ 00316 */ 00317 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ 00318 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ 00319 /** 00320 * @} 00321 */ 00322 00323 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose 00324 * @{ 00325 */ 00326 /* List of DAC registers intended to be used (most commonly) with */ 00327 /* DMA transfer. */ 00328 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ 00329 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ 00330 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ 00331 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ 00332 /** 00333 * @} 00334 */ 00335 00336 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays 00337 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, 00338 * not timeout values. 00339 * For details on delays values, refer to descriptions in source code 00340 * above each literal definition. 00341 * @{ 00342 */ 00343 00344 /* Delay for DAC channel voltage settling time from DAC channel startup */ 00345 /* (transition from disable to enable). */ 00346 /* Note: DAC channel startup time depends on board application environment: */ 00347 /* impedance connected to DAC channel output. */ 00348 /* The delay below is specified under conditions: */ 00349 /* - voltage maximum transition (lowest to highest value) */ 00350 /* - until voltage reaches final value +-1LSB */ 00351 /* - DAC channel output buffer enabled */ 00352 /* - load impedance of 5kOhm (min), 50pF (max) */ 00353 /* Literal set to maximum value (refer to device datasheet, */ 00354 /* parameter "tWAKEUP"). */ 00355 /* Unit: us */ 00356 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 00357 00358 /* Delay for DAC channel voltage settling time. */ 00359 /* Note: DAC channel startup time depends on board application environment: */ 00360 /* impedance connected to DAC channel output. */ 00361 /* The delay below is specified under conditions: */ 00362 /* - voltage maximum transition (lowest to highest value) */ 00363 /* - until voltage reaches final value +-1LSB */ 00364 /* - DAC channel output buffer enabled */ 00365 /* - load impedance of 5kOhm min, 50pF max */ 00366 /* Literal set to maximum value (refer to device datasheet, */ 00367 /* parameter "tSETTLING"). */ 00368 /* Unit: us */ 00369 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL /*!< Delay for DAC channel voltage settling time */ 00370 00371 /** 00372 * @} 00373 */ 00374 00375 /** 00376 * @} 00377 */ 00378 00379 /* Exported macro ------------------------------------------------------------*/ 00380 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros 00381 * @{ 00382 */ 00383 00384 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros 00385 * @{ 00386 */ 00387 00388 /** 00389 * @brief Write a value in DAC register 00390 * @param __INSTANCE__ DAC Instance 00391 * @param __REG__ Register to be written 00392 * @param __VALUE__ Value to be written in the register 00393 * @retval None 00394 */ 00395 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00396 00397 /** 00398 * @brief Read a value in DAC register 00399 * @param __INSTANCE__ DAC Instance 00400 * @param __REG__ Register to be read 00401 * @retval Register value 00402 */ 00403 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00404 00405 /** 00406 * @} 00407 */ 00408 00409 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro 00410 * @{ 00411 */ 00412 00413 /** 00414 * @brief Helper macro to get DAC channel number in decimal format 00415 * from literals LL_DAC_CHANNEL_x. 00416 * Example: 00417 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) 00418 * will return decimal number "1". 00419 * @note The input can be a value from functions where a channel 00420 * number is returned. 00421 * @param __CHANNEL__ This parameter can be one of the following values: 00422 * @arg @ref LL_DAC_CHANNEL_1 00423 * @arg @ref LL_DAC_CHANNEL_2 00424 * @retval 1...2 00425 */ 00426 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 00427 ((__CHANNEL__) & DAC_SWTR_CHX_MASK) 00428 00429 /** 00430 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x 00431 * from number in decimal format. 00432 * Example: 00433 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) 00434 * will return a data equivalent to "LL_DAC_CHANNEL_1". 00435 * @note If the input parameter does not correspond to a DAC channel, 00436 * this macro returns value '0'. 00437 * @param __DECIMAL_NB__ 1...2 00438 * @retval Returned value can be one of the following values: 00439 * @arg @ref LL_DAC_CHANNEL_1 00440 * @arg @ref LL_DAC_CHANNEL_2 00441 */ 00442 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ 00443 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) 00444 00445 /** 00446 * @brief Helper macro to define the DAC conversion data full-scale digital 00447 * value corresponding to the selected DAC resolution. 00448 * @note DAC conversion data full-scale corresponds to voltage range 00449 * determined by analog voltage references Vref+ and Vref- 00450 * (refer to reference manual). 00451 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00452 * @arg @ref LL_DAC_RESOLUTION_12B 00453 * @arg @ref LL_DAC_RESOLUTION_8B 00454 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 00455 */ 00456 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00457 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) 00458 00459 /** 00460 * @brief Helper macro to calculate the DAC conversion data (unit: digital 00461 * value) corresponding to a voltage (unit: mVolt). 00462 * @note This helper macro is intended to provide input data in voltage 00463 * rather than digital value, 00464 * to be used with LL DAC functions such as 00465 * @ref LL_DAC_ConvertData12RightAligned(). 00466 * @note Analog reference voltage (Vref+) must be either known from 00467 * user board environment or can be calculated using ADC measurement 00468 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 00469 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 00470 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel 00471 * (unit: mVolt). 00472 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00473 * @arg @ref LL_DAC_RESOLUTION_12B 00474 * @arg @ref LL_DAC_RESOLUTION_8B 00475 * @retval DAC conversion data (unit: digital value) 00476 */ 00477 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ 00478 __DAC_VOLTAGE__,\ 00479 __DAC_RESOLUTION__) \ 00480 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00481 / (__VREFANALOG_VOLTAGE__) \ 00482 ) 00483 00484 /** 00485 * @} 00486 */ 00487 00488 /** 00489 * @} 00490 */ 00491 00492 00493 /* Exported functions --------------------------------------------------------*/ 00494 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions 00495 * @{ 00496 */ 00497 /** 00498 * @brief Set the conversion trigger source for the selected DAC channel. 00499 * @note For conversion trigger source to be effective, DAC trigger 00500 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00501 * @note To set conversion trigger source, DAC channel must be disabled. 00502 * Otherwise, the setting is discarded. 00503 * @note Availability of parameters of trigger sources from timer 00504 * depends on timers availability on the selected device. 00505 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n 00506 * CR TSEL2 LL_DAC_SetTriggerSource 00507 * @param DACx DAC instance 00508 * @param DAC_Channel This parameter can be one of the following values: 00509 * @arg @ref LL_DAC_CHANNEL_1 00510 * @arg @ref LL_DAC_CHANNEL_2 00511 * @param TriggerSource This parameter can be one of the following values: 00512 * @arg @ref LL_DAC_TRIG_SOFTWARE 00513 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00514 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO 00515 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00516 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00517 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00518 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00519 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO 00520 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00521 * @retval None 00522 */ 00523 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) 00524 { 00525 MODIFY_REG(DACx->CR, 00526 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00527 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00528 } 00529 00530 /** 00531 * @brief Get the conversion trigger source for the selected DAC channel. 00532 * @note For conversion trigger source to be effective, DAC trigger 00533 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00534 * @note Availability of parameters of trigger sources from timer 00535 * depends on timers availability on the selected device. 00536 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n 00537 * CR TSEL2 LL_DAC_GetTriggerSource 00538 * @param DACx DAC instance 00539 * @param DAC_Channel This parameter can be one of the following values: 00540 * @arg @ref LL_DAC_CHANNEL_1 00541 * @arg @ref LL_DAC_CHANNEL_2 00542 * @retval Returned value can be one of the following values: 00543 * @arg @ref LL_DAC_TRIG_SOFTWARE 00544 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00545 * @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO 00546 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00547 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00548 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00549 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00550 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO 00551 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00552 */ 00553 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00554 { 00555 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00556 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00557 ); 00558 } 00559 00560 /** 00561 * @brief Set the waveform automatic generation mode 00562 * for the selected DAC channel. 00563 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n 00564 * CR WAVE2 LL_DAC_SetWaveAutoGeneration 00565 * @param DACx DAC instance 00566 * @param DAC_Channel This parameter can be one of the following values: 00567 * @arg @ref LL_DAC_CHANNEL_1 00568 * @arg @ref LL_DAC_CHANNEL_2 00569 * @param WaveAutoGeneration This parameter can be one of the following values: 00570 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00571 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00572 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00573 * @retval None 00574 */ 00575 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) 00576 { 00577 MODIFY_REG(DACx->CR, 00578 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00579 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00580 } 00581 00582 /** 00583 * @brief Get the waveform automatic generation mode 00584 * for the selected DAC channel. 00585 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n 00586 * CR WAVE2 LL_DAC_GetWaveAutoGeneration 00587 * @param DACx DAC instance 00588 * @param DAC_Channel This parameter can be one of the following values: 00589 * @arg @ref LL_DAC_CHANNEL_1 00590 * @arg @ref LL_DAC_CHANNEL_2 00591 * @retval Returned value can be one of the following values: 00592 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00593 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00594 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00595 */ 00596 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00597 { 00598 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00599 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00600 ); 00601 } 00602 00603 /** 00604 * @brief Set the noise waveform generation for the selected DAC channel: 00605 * Noise mode and parameters LFSR (linear feedback shift register). 00606 * @note For wave generation to be effective, DAC channel 00607 * wave generation mode must be enabled using 00608 * function @ref LL_DAC_SetWaveAutoGeneration(). 00609 * @note This setting can be set when the selected DAC channel is disabled 00610 * (otherwise, the setting operation is ignored). 00611 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n 00612 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR 00613 * @param DACx DAC instance 00614 * @param DAC_Channel This parameter can be one of the following values: 00615 * @arg @ref LL_DAC_CHANNEL_1 00616 * @arg @ref LL_DAC_CHANNEL_2 00617 * @param NoiseLFSRMask This parameter can be one of the following values: 00618 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00619 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00620 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00621 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00622 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00623 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00624 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00625 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00626 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00627 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00628 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00629 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00630 * @retval None 00631 */ 00632 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) 00633 { 00634 MODIFY_REG(DACx->CR, 00635 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00636 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00637 } 00638 00639 /** 00640 * @brief Get the noise waveform generation for the selected DAC channel: 00641 * Noise mode and parameters LFSR (linear feedback shift register). 00642 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n 00643 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR 00644 * @param DACx DAC instance 00645 * @param DAC_Channel This parameter can be one of the following values: 00646 * @arg @ref LL_DAC_CHANNEL_1 00647 * @arg @ref LL_DAC_CHANNEL_2 00648 * @retval Returned value can be one of the following values: 00649 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00650 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00651 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00652 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00653 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00654 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00655 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00656 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00657 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00658 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00659 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00660 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00661 */ 00662 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00663 { 00664 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00665 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00666 ); 00667 } 00668 00669 /** 00670 * @brief Set the triangle waveform generation for the selected DAC channel: 00671 * triangle mode and amplitude. 00672 * @note For wave generation to be effective, DAC channel 00673 * wave generation mode must be enabled using 00674 * function @ref LL_DAC_SetWaveAutoGeneration(). 00675 * @note This setting can be set when the selected DAC channel is disabled 00676 * (otherwise, the setting operation is ignored). 00677 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n 00678 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude 00679 * @param DACx DAC instance 00680 * @param DAC_Channel This parameter can be one of the following values: 00681 * @arg @ref LL_DAC_CHANNEL_1 00682 * @arg @ref LL_DAC_CHANNEL_2 00683 * @param TriangleAmplitude This parameter can be one of the following values: 00684 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00685 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00686 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00687 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00688 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00689 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00690 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00691 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00692 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00693 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00694 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00695 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00696 * @retval None 00697 */ 00698 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, 00699 uint32_t TriangleAmplitude) 00700 { 00701 MODIFY_REG(DACx->CR, 00702 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00703 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00704 } 00705 00706 /** 00707 * @brief Get the triangle waveform generation for the selected DAC channel: 00708 * triangle mode and amplitude. 00709 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n 00710 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude 00711 * @param DACx DAC instance 00712 * @param DAC_Channel This parameter can be one of the following values: 00713 * @arg @ref LL_DAC_CHANNEL_1 00714 * @arg @ref LL_DAC_CHANNEL_2 00715 * @retval Returned value can be one of the following values: 00716 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00717 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00718 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00719 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00720 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00721 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00722 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00723 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00724 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00725 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00726 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00727 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00728 */ 00729 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00730 { 00731 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00732 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00733 ); 00734 } 00735 00736 /** 00737 * @brief Set the output buffer for the selected DAC channel. 00738 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n 00739 * CR BOFF2 LL_DAC_SetOutputBuffer 00740 * @param DACx DAC instance 00741 * @param DAC_Channel This parameter can be one of the following values: 00742 * @arg @ref LL_DAC_CHANNEL_1 00743 * @arg @ref LL_DAC_CHANNEL_2 00744 * @param OutputBuffer This parameter can be one of the following values: 00745 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 00746 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 00747 * @retval None 00748 */ 00749 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) 00750 { 00751 MODIFY_REG(DACx->CR, 00752 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00753 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00754 } 00755 00756 /** 00757 * @brief Get the output buffer state for the selected DAC channel. 00758 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n 00759 * CR BOFF2 LL_DAC_GetOutputBuffer 00760 * @param DACx DAC instance 00761 * @param DAC_Channel This parameter can be one of the following values: 00762 * @arg @ref LL_DAC_CHANNEL_1 00763 * @arg @ref LL_DAC_CHANNEL_2 00764 * @retval Returned value can be one of the following values: 00765 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 00766 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 00767 */ 00768 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00769 { 00770 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00771 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00772 ); 00773 } 00774 00775 /** 00776 * @} 00777 */ 00778 00779 /** @defgroup DAC_LL_EF_DMA_Management DMA Management 00780 * @{ 00781 */ 00782 00783 /** 00784 * @brief Enable DAC DMA transfer request of the selected channel. 00785 * @note To configure DMA source address (peripheral address), 00786 * use function @ref LL_DAC_DMA_GetRegAddr(). 00787 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n 00788 * CR DMAEN2 LL_DAC_EnableDMAReq 00789 * @param DACx DAC instance 00790 * @param DAC_Channel This parameter can be one of the following values: 00791 * @arg @ref LL_DAC_CHANNEL_1 00792 * @arg @ref LL_DAC_CHANNEL_2 00793 * @retval None 00794 */ 00795 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00796 { 00797 SET_BIT(DACx->CR, 00798 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00799 } 00800 00801 /** 00802 * @brief Disable DAC DMA transfer request of the selected channel. 00803 * @note To configure DMA source address (peripheral address), 00804 * use function @ref LL_DAC_DMA_GetRegAddr(). 00805 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n 00806 * CR DMAEN2 LL_DAC_DisableDMAReq 00807 * @param DACx DAC instance 00808 * @param DAC_Channel This parameter can be one of the following values: 00809 * @arg @ref LL_DAC_CHANNEL_1 00810 * @arg @ref LL_DAC_CHANNEL_2 00811 * @retval None 00812 */ 00813 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00814 { 00815 CLEAR_BIT(DACx->CR, 00816 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00817 } 00818 00819 /** 00820 * @brief Get DAC DMA transfer request state of the selected channel. 00821 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) 00822 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n 00823 * CR DMAEN2 LL_DAC_IsDMAReqEnabled 00824 * @param DACx DAC instance 00825 * @param DAC_Channel This parameter can be one of the following values: 00826 * @arg @ref LL_DAC_CHANNEL_1 00827 * @arg @ref LL_DAC_CHANNEL_2 00828 * @retval State of bit (1 or 0). 00829 */ 00830 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00831 { 00832 return ((READ_BIT(DACx->CR, 00833 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00834 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 00835 } 00836 00837 /** 00838 * @brief Function to help to configure DMA transfer to DAC: retrieve the 00839 * DAC register address from DAC instance and a list of DAC registers 00840 * intended to be used (most commonly) with DMA transfer. 00841 * @note These DAC registers are data holding registers: 00842 * when DAC conversion is requested, DAC generates a DMA transfer 00843 * request to have data available in DAC data holding registers. 00844 * @note This macro is intended to be used with LL DMA driver, refer to 00845 * function "LL_DMA_ConfigAddresses()". 00846 * Example: 00847 * LL_DMA_ConfigAddresses(DMA1, 00848 * LL_DMA_CHANNEL_1, 00849 * (uint32_t)&< array or variable >, 00850 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, 00851 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), 00852 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 00853 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00854 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00855 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00856 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 00857 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 00858 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr 00859 * @param DACx DAC instance 00860 * @param DAC_Channel This parameter can be one of the following values: 00861 * @arg @ref LL_DAC_CHANNEL_1 00862 * @arg @ref LL_DAC_CHANNEL_2 00863 * @param Register This parameter can be one of the following values: 00864 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED 00865 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED 00866 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED 00867 * @retval DAC register address 00868 */ 00869 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) 00870 { 00871 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ 00872 /* DAC channel selected. */ 00873 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) 00874 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); 00875 } 00876 /** 00877 * @} 00878 */ 00879 00880 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels 00881 * @{ 00882 */ 00883 00884 /** 00885 * @brief Enable DAC selected channel. 00886 * @rmtoll CR EN1 LL_DAC_Enable\n 00887 * CR EN2 LL_DAC_Enable 00888 * @note After enable from off state, DAC channel requires a delay 00889 * for output voltage to reach accuracy +/- 1 LSB. 00890 * Refer to device datasheet, parameter "tWAKEUP". 00891 * @param DACx DAC instance 00892 * @param DAC_Channel This parameter can be one of the following values: 00893 * @arg @ref LL_DAC_CHANNEL_1 00894 * @arg @ref LL_DAC_CHANNEL_2 00895 * @retval None 00896 */ 00897 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00898 { 00899 SET_BIT(DACx->CR, 00900 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00901 } 00902 00903 /** 00904 * @brief Disable DAC selected channel. 00905 * @rmtoll CR EN1 LL_DAC_Disable\n 00906 * CR EN2 LL_DAC_Disable 00907 * @param DACx DAC instance 00908 * @param DAC_Channel This parameter can be one of the following values: 00909 * @arg @ref LL_DAC_CHANNEL_1 00910 * @arg @ref LL_DAC_CHANNEL_2 00911 * @retval None 00912 */ 00913 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00914 { 00915 CLEAR_BIT(DACx->CR, 00916 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00917 } 00918 00919 /** 00920 * @brief Get DAC enable state of the selected channel. 00921 * (0: DAC channel is disabled, 1: DAC channel is enabled) 00922 * @rmtoll CR EN1 LL_DAC_IsEnabled\n 00923 * CR EN2 LL_DAC_IsEnabled 00924 * @param DACx DAC instance 00925 * @param DAC_Channel This parameter can be one of the following values: 00926 * @arg @ref LL_DAC_CHANNEL_1 00927 * @arg @ref LL_DAC_CHANNEL_2 00928 * @retval State of bit (1 or 0). 00929 */ 00930 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00931 { 00932 return ((READ_BIT(DACx->CR, 00933 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00934 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 00935 } 00936 00937 /** 00938 * @brief Enable DAC trigger of the selected channel. 00939 * @note - If DAC trigger is disabled, DAC conversion is performed 00940 * automatically once the data holding register is updated, 00941 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 00942 * @ref LL_DAC_ConvertData12RightAligned(), ... 00943 * - If DAC trigger is enabled, DAC conversion is performed 00944 * only when a hardware of software trigger event is occurring. 00945 * Select trigger source using 00946 * function @ref LL_DAC_SetTriggerSource(). 00947 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n 00948 * CR TEN2 LL_DAC_EnableTrigger 00949 * @param DACx DAC instance 00950 * @param DAC_Channel This parameter can be one of the following values: 00951 * @arg @ref LL_DAC_CHANNEL_1 00952 * @arg @ref LL_DAC_CHANNEL_2 00953 * @retval None 00954 */ 00955 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00956 { 00957 SET_BIT(DACx->CR, 00958 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00959 } 00960 00961 /** 00962 * @brief Disable DAC trigger of the selected channel. 00963 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n 00964 * CR TEN2 LL_DAC_DisableTrigger 00965 * @param DACx DAC instance 00966 * @param DAC_Channel This parameter can be one of the following values: 00967 * @arg @ref LL_DAC_CHANNEL_1 00968 * @arg @ref LL_DAC_CHANNEL_2 00969 * @retval None 00970 */ 00971 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00972 { 00973 CLEAR_BIT(DACx->CR, 00974 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00975 } 00976 00977 /** 00978 * @brief Get DAC trigger state of the selected channel. 00979 * (0: DAC trigger is disabled, 1: DAC trigger is enabled) 00980 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n 00981 * CR TEN2 LL_DAC_IsTriggerEnabled 00982 * @param DACx DAC instance 00983 * @param DAC_Channel This parameter can be one of the following values: 00984 * @arg @ref LL_DAC_CHANNEL_1 00985 * @arg @ref LL_DAC_CHANNEL_2 00986 * @retval State of bit (1 or 0). 00987 */ 00988 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00989 { 00990 return ((READ_BIT(DACx->CR, 00991 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00992 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 00993 } 00994 00995 /** 00996 * @brief Trig DAC conversion by software for the selected DAC channel. 00997 * @note Preliminarily, DAC trigger must be set to software trigger 00998 * using function 00999 * @ref LL_DAC_Init() 01000 * @ref LL_DAC_SetTriggerSource() 01001 * with parameter "LL_DAC_TRIGGER_SOFTWARE". 01002 * and DAC trigger must be enabled using 01003 * function @ref LL_DAC_EnableTrigger(). 01004 * @note For devices featuring DAC with 2 channels: this function 01005 * can perform a SW start of both DAC channels simultaneously. 01006 * Two channels can be selected as parameter. 01007 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) 01008 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n 01009 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion 01010 * @param DACx DAC instance 01011 * @param DAC_Channel This parameter can a combination of the following values: 01012 * @arg @ref LL_DAC_CHANNEL_1 01013 * @arg @ref LL_DAC_CHANNEL_2 01014 * @retval None 01015 */ 01016 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01017 { 01018 SET_BIT(DACx->SWTRIGR, 01019 (DAC_Channel & DAC_SWTR_CHX_MASK)); 01020 } 01021 01022 /** 01023 * @brief Set the data to be loaded in the data holding register 01024 * in format 12 bits left alignment (LSB aligned on bit 0), 01025 * for the selected DAC channel. 01026 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n 01027 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned 01028 * @param DACx DAC instance 01029 * @param DAC_Channel This parameter can be one of the following values: 01030 * @arg @ref LL_DAC_CHANNEL_1 01031 * @arg @ref LL_DAC_CHANNEL_2 01032 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01033 * @retval None 01034 */ 01035 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01036 { 01037 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) 01038 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01039 01040 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); 01041 } 01042 01043 /** 01044 * @brief Set the data to be loaded in the data holding register 01045 * in format 12 bits left alignment (MSB aligned on bit 15), 01046 * for the selected DAC channel. 01047 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n 01048 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned 01049 * @param DACx DAC instance 01050 * @param DAC_Channel This parameter can be one of the following values: 01051 * @arg @ref LL_DAC_CHANNEL_1 01052 * @arg @ref LL_DAC_CHANNEL_2 01053 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01054 * @retval None 01055 */ 01056 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01057 { 01058 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) 01059 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01060 01061 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); 01062 } 01063 01064 /** 01065 * @brief Set the data to be loaded in the data holding register 01066 * in format 8 bits left alignment (LSB aligned on bit 0), 01067 * for the selected DAC channel. 01068 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n 01069 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned 01070 * @param DACx DAC instance 01071 * @param DAC_Channel This parameter can be one of the following values: 01072 * @arg @ref LL_DAC_CHANNEL_1 01073 * @arg @ref LL_DAC_CHANNEL_2 01074 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 01075 * @retval None 01076 */ 01077 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01078 { 01079 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) 01080 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01081 01082 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); 01083 } 01084 01085 01086 /** 01087 * @brief Set the data to be loaded in the data holding register 01088 * in format 12 bits left alignment (LSB aligned on bit 0), 01089 * for both DAC channels. 01090 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n 01091 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned 01092 * @param DACx DAC instance 01093 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01094 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01095 * @retval None 01096 */ 01097 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01098 uint32_t DataChannel2) 01099 { 01100 MODIFY_REG(DACx->DHR12RD, 01101 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), 01102 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01103 } 01104 01105 /** 01106 * @brief Set the data to be loaded in the data holding register 01107 * in format 12 bits left alignment (MSB aligned on bit 15), 01108 * for both DAC channels. 01109 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n 01110 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned 01111 * @param DACx DAC instance 01112 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01113 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01114 * @retval None 01115 */ 01116 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01117 uint32_t DataChannel2) 01118 { 01119 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ 01120 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ 01121 /* the 4 LSB must be taken into account for the shift value. */ 01122 MODIFY_REG(DACx->DHR12LD, 01123 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), 01124 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); 01125 } 01126 01127 /** 01128 * @brief Set the data to be loaded in the data holding register 01129 * in format 8 bits left alignment (LSB aligned on bit 0), 01130 * for both DAC channels. 01131 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n 01132 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned 01133 * @param DACx DAC instance 01134 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF 01135 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF 01136 * @retval None 01137 */ 01138 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01139 uint32_t DataChannel2) 01140 { 01141 MODIFY_REG(DACx->DHR8RD, 01142 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), 01143 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01144 } 01145 01146 01147 /** 01148 * @brief Retrieve output data currently generated for the selected DAC channel. 01149 * @note Whatever alignment and resolution settings 01150 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01151 * @ref LL_DAC_ConvertData12RightAligned(), ...), 01152 * output data format is 12 bits right aligned (LSB aligned on bit 0). 01153 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n 01154 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData 01155 * @param DACx DAC instance 01156 * @param DAC_Channel This parameter can be one of the following values: 01157 * @arg @ref LL_DAC_CHANNEL_1 01158 * @arg @ref LL_DAC_CHANNEL_2 01159 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01160 */ 01161 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01162 { 01163 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) 01164 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); 01165 01166 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); 01167 } 01168 01169 /** 01170 * @} 01171 */ 01172 01173 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management 01174 * @{ 01175 */ 01176 01177 #if defined(DAC_SR_DMAUDR1) 01178 /** 01179 * @brief Get DAC underrun flag for DAC channel 1 01180 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 01181 * @param DACx DAC instance 01182 * @retval State of bit (1 or 0). 01183 */ 01184 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) 01185 { 01186 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); 01187 } 01188 #endif /* DAC_SR_DMAUDR1 */ 01189 01190 #if defined(DAC_SR_DMAUDR2) 01191 /** 01192 * @brief Get DAC underrun flag for DAC channel 2 01193 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 01194 * @param DACx DAC instance 01195 * @retval State of bit (1 or 0). 01196 */ 01197 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) 01198 { 01199 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); 01200 } 01201 #endif /* DAC_SR_DMAUDR2 */ 01202 01203 #if defined(DAC_SR_DMAUDR1) 01204 /** 01205 * @brief Clear DAC underrun flag for DAC channel 1 01206 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 01207 * @param DACx DAC instance 01208 * @retval None 01209 */ 01210 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) 01211 { 01212 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); 01213 } 01214 #endif /* DAC_SR_DMAUDR1 */ 01215 01216 #if defined(DAC_SR_DMAUDR2) 01217 /** 01218 * @brief Clear DAC underrun flag for DAC channel 2 01219 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 01220 * @param DACx DAC instance 01221 * @retval None 01222 */ 01223 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) 01224 { 01225 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); 01226 } 01227 #endif /* DAC_SR_DMAUDR2 */ 01228 01229 /** 01230 * @} 01231 */ 01232 01233 /** @defgroup DAC_LL_EF_IT_Management IT management 01234 * @{ 01235 */ 01236 01237 #if defined(DAC_CR_DMAUDRIE1) 01238 /** 01239 * @brief Enable DMA underrun interrupt for DAC channel 1 01240 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 01241 * @param DACx DAC instance 01242 * @retval None 01243 */ 01244 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) 01245 { 01246 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01247 } 01248 #endif /* DAC_CR_DMAUDRIE1 */ 01249 01250 #if defined(DAC_CR_DMAUDRIE2) 01251 /** 01252 * @brief Enable DMA underrun interrupt for DAC channel 2 01253 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 01254 * @param DACx DAC instance 01255 * @retval None 01256 */ 01257 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) 01258 { 01259 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01260 } 01261 #endif /* DAC_CR_DMAUDRIE2 */ 01262 01263 #if defined(DAC_CR_DMAUDRIE1) 01264 /** 01265 * @brief Disable DMA underrun interrupt for DAC channel 1 01266 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 01267 * @param DACx DAC instance 01268 * @retval None 01269 */ 01270 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) 01271 { 01272 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01273 } 01274 #endif /* DAC_CR_DMAUDRIE1 */ 01275 01276 #if defined(DAC_CR_DMAUDRIE2) 01277 /** 01278 * @brief Disable DMA underrun interrupt for DAC channel 2 01279 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 01280 * @param DACx DAC instance 01281 * @retval None 01282 */ 01283 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) 01284 { 01285 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01286 } 01287 #endif /* DAC_CR_DMAUDRIE2 */ 01288 01289 #if defined(DAC_CR_DMAUDRIE1) 01290 /** 01291 * @brief Get DMA underrun interrupt for DAC channel 1 01292 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 01293 * @param DACx DAC instance 01294 * @retval State of bit (1 or 0). 01295 */ 01296 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) 01297 { 01298 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); 01299 } 01300 #endif /* DAC_CR_DMAUDRIE1 */ 01301 01302 #if defined(DAC_CR_DMAUDRIE2) 01303 /** 01304 * @brief Get DMA underrun interrupt for DAC channel 2 01305 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 01306 * @param DACx DAC instance 01307 * @retval State of bit (1 or 0). 01308 */ 01309 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) 01310 { 01311 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); 01312 } 01313 #endif /* DAC_CR_DMAUDRIE2 */ 01314 01315 /** 01316 * @} 01317 */ 01318 01319 #if defined(USE_FULL_LL_DRIVER) 01320 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions 01321 * @{ 01322 */ 01323 01324 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); 01325 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); 01326 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); 01327 01328 /** 01329 * @} 01330 */ 01331 #endif /* USE_FULL_LL_DRIVER */ 01332 01333 /** 01334 * @} 01335 */ 01336 01337 /** 01338 * @} 01339 */ 01340 01341 #endif /* DAC */ 01342 01343 /** 01344 * @} 01345 */ 01346 01347 #ifdef __cplusplus 01348 } 01349 #endif 01350 01351 #endif /* STM32F1xx_LL_DAC_H */ 01352 01353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1