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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_ll_gpio.h 00004 * @author MCD Application Team 00005 * @brief Header file of GPIO LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F1xx_LL_GPIO_H 00022 #define STM32F1xx_LL_GPIO_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f1xx.h" 00030 00031 /** @addtogroup STM32F1xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) 00036 00037 /** @defgroup GPIO_LL GPIO 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 /* Private constants ---------------------------------------------------------*/ 00044 00045 /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants 00046 * @{ 00047 */ 00048 /* Defines used for Pin Mask Initialization */ 00049 #define GPIO_PIN_MASK_POS 8U 00050 #define GPIO_PIN_NB 16U 00051 /** 00052 * @} 00053 */ 00054 00055 /* Private macros ------------------------------------------------------------*/ 00056 #if defined(USE_FULL_LL_DRIVER) 00057 /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros 00058 * @{ 00059 */ 00060 00061 /** 00062 * @} 00063 */ 00064 #endif /*USE_FULL_LL_DRIVER*/ 00065 00066 /* Exported types ------------------------------------------------------------*/ 00067 #if defined(USE_FULL_LL_DRIVER) 00068 /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures 00069 * @{ 00070 */ 00071 00072 /** 00073 * @brief LL GPIO Init Structure definition 00074 */ 00075 typedef struct 00076 { 00077 uint32_t Pin; /*!< Specifies the GPIO pins to be configured. 00078 This parameter can be any value of @ref GPIO_LL_EC_PIN */ 00079 00080 uint32_t Mode; /*!< Specifies the operating mode for the selected pins. 00081 This parameter can be a value of @ref GPIO_LL_EC_MODE. 00082 00083 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ 00084 00085 uint32_t Speed; /*!< Specifies the speed for the selected pins. 00086 This parameter can be a value of @ref GPIO_LL_EC_SPEED. 00087 00088 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ 00089 00090 uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. 00091 This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. 00092 00093 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ 00094 00095 uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. 00096 This parameter can be a value of @ref GPIO_LL_EC_PULL. 00097 00098 GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ 00099 } LL_GPIO_InitTypeDef; 00100 00101 /** 00102 * @} 00103 */ 00104 #endif /* USE_FULL_LL_DRIVER */ 00105 00106 /* Exported constants --------------------------------------------------------*/ 00107 /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants 00108 * @{ 00109 */ 00110 00111 /** @defgroup GPIO_LL_EC_PIN PIN 00112 * @{ 00113 */ 00114 #define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */ 00115 #define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */ 00116 #define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */ 00117 #define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */ 00118 #define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */ 00119 #define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */ 00120 #define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */ 00121 #define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */ 00122 #define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */ 00123 #define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */ 00124 #define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */ 00125 #define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */ 00126 #define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */ 00127 #define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */ 00128 #define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */ 00129 #define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */ 00130 #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ 00131 LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ 00132 LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ 00133 LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ 00134 LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ 00135 LL_GPIO_PIN_15) /*!< Select all pins */ 00136 /** 00137 * @} 00138 */ 00139 00140 /** @defgroup GPIO_LL_EC_MODE Mode 00141 * @{ 00142 */ 00143 #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */ 00144 #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */ 00145 #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */ 00146 #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */ 00147 #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */ 00148 /** 00149 * @} 00150 */ 00151 00152 /** @defgroup GPIO_LL_EC_OUTPUT Output Type 00153 * @{ 00154 */ 00155 #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */ 00156 #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */ 00157 /** 00158 * @} 00159 */ 00160 00161 /** @defgroup GPIO_LL_EC_SPEED Output Speed 00162 * @{ 00163 */ 00164 #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */ 00165 #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */ 00166 #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */ 00167 /** 00168 * @} 00169 */ 00170 00171 #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */ 00172 #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */ 00173 #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */ 00174 00175 /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down 00176 * @{ 00177 */ 00178 #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */ 00179 #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */ 00180 00181 /** 00182 * @} 00183 */ 00184 00185 /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin 00186 * @{ 00187 */ 00188 00189 #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ 00190 #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ 00191 #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ 00192 #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ 00193 #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ 00194 #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ 00195 #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ 00196 #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ 00197 #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ 00198 #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ 00199 #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ 00200 #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ 00201 #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ 00202 #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ 00203 #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ 00204 #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ 00205 00206 /** 00207 * @} 00208 */ 00209 00210 /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port 00211 * @{ 00212 */ 00213 00214 #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ 00215 #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ 00216 #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ 00217 #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ 00218 #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ 00219 00220 /** 00221 * @} 00222 */ 00223 00224 /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT 00225 * @{ 00226 */ 00227 #define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */ 00228 #define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */ 00229 #define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */ 00230 #define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */ 00231 #define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */ 00232 #define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */ 00233 #define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */ 00234 /** 00235 * @} 00236 */ 00237 00238 /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE 00239 * @{ 00240 */ 00241 #define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ 00242 #define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ 00243 #define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ 00244 #define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ 00245 #define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ 00246 #define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ 00247 #define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ 00248 #define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ 00249 #define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ 00250 #define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ 00251 #define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ 00252 #define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ 00253 #define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ 00254 #define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ 00255 #define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ 00256 #define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ 00257 /** 00258 * @} 00259 */ 00260 00261 /** 00262 * @} 00263 */ 00264 00265 /* Exported macro ------------------------------------------------------------*/ 00266 /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros 00267 * @{ 00268 */ 00269 00270 /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros 00271 * @{ 00272 */ 00273 00274 /** 00275 * @brief Write a value in GPIO register 00276 * @param __INSTANCE__ GPIO Instance 00277 * @param __REG__ Register to be written 00278 * @param __VALUE__ Value to be written in the register 00279 * @retval None 00280 */ 00281 #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00282 00283 /** 00284 * @brief Read a value in GPIO register 00285 * @param __INSTANCE__ GPIO Instance 00286 * @param __REG__ Register to be read 00287 * @retval Register value 00288 */ 00289 #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00290 /** 00291 * @} 00292 */ 00293 00294 /** 00295 * @} 00296 */ 00297 00298 /* Exported functions --------------------------------------------------------*/ 00299 /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions 00300 * @{ 00301 */ 00302 00303 /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration 00304 * @{ 00305 */ 00306 00307 /** 00308 * @brief Configure gpio mode for a dedicated pin on dedicated port. 00309 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, 00310 * Alternate function Output. 00311 * @note Warning: only one pin can be passed as parameter. 00312 * @rmtoll CRL CNFy LL_GPIO_SetPinMode 00313 * @rmtoll CRL MODEy LL_GPIO_SetPinMode 00314 * @rmtoll CRH CNFy LL_GPIO_SetPinMode 00315 * @rmtoll CRH MODEy LL_GPIO_SetPinMode 00316 * @param GPIOx GPIO Port 00317 * @param Pin This parameter can be one of the following values: 00318 * @arg @ref LL_GPIO_PIN_0 00319 * @arg @ref LL_GPIO_PIN_1 00320 * @arg @ref LL_GPIO_PIN_2 00321 * @arg @ref LL_GPIO_PIN_3 00322 * @arg @ref LL_GPIO_PIN_4 00323 * @arg @ref LL_GPIO_PIN_5 00324 * @arg @ref LL_GPIO_PIN_6 00325 * @arg @ref LL_GPIO_PIN_7 00326 * @arg @ref LL_GPIO_PIN_8 00327 * @arg @ref LL_GPIO_PIN_9 00328 * @arg @ref LL_GPIO_PIN_10 00329 * @arg @ref LL_GPIO_PIN_11 00330 * @arg @ref LL_GPIO_PIN_12 00331 * @arg @ref LL_GPIO_PIN_13 00332 * @arg @ref LL_GPIO_PIN_14 00333 * @arg @ref LL_GPIO_PIN_15 00334 * @param Mode This parameter can be one of the following values: 00335 * @arg @ref LL_GPIO_MODE_ANALOG 00336 * @arg @ref LL_GPIO_MODE_FLOATING 00337 * @arg @ref LL_GPIO_MODE_INPUT 00338 * @arg @ref LL_GPIO_MODE_OUTPUT 00339 * @arg @ref LL_GPIO_MODE_ALTERNATE 00340 * @retval None 00341 */ 00342 __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) 00343 { 00344 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); 00345 MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U))); 00346 } 00347 00348 /** 00349 * @brief Return gpio mode for a dedicated pin on dedicated port. 00350 * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, 00351 * Alternate function Output. 00352 * @note Warning: only one pin can be passed as parameter. 00353 * @rmtoll CRL CNFy LL_GPIO_GetPinMode 00354 * @rmtoll CRL MODEy LL_GPIO_GetPinMode 00355 * @rmtoll CRH CNFy LL_GPIO_GetPinMode 00356 * @rmtoll CRH MODEy LL_GPIO_GetPinMode 00357 * @param GPIOx GPIO Port 00358 * @param Pin This parameter can be one of the following values: 00359 * @arg @ref LL_GPIO_PIN_0 00360 * @arg @ref LL_GPIO_PIN_1 00361 * @arg @ref LL_GPIO_PIN_2 00362 * @arg @ref LL_GPIO_PIN_3 00363 * @arg @ref LL_GPIO_PIN_4 00364 * @arg @ref LL_GPIO_PIN_5 00365 * @arg @ref LL_GPIO_PIN_6 00366 * @arg @ref LL_GPIO_PIN_7 00367 * @arg @ref LL_GPIO_PIN_8 00368 * @arg @ref LL_GPIO_PIN_9 00369 * @arg @ref LL_GPIO_PIN_10 00370 * @arg @ref LL_GPIO_PIN_11 00371 * @arg @ref LL_GPIO_PIN_12 00372 * @arg @ref LL_GPIO_PIN_13 00373 * @arg @ref LL_GPIO_PIN_14 00374 * @arg @ref LL_GPIO_PIN_15 00375 * @retval Returned value can be one of the following values: 00376 * @arg @ref LL_GPIO_MODE_ANALOG 00377 * @arg @ref LL_GPIO_MODE_FLOATING 00378 * @arg @ref LL_GPIO_MODE_INPUT 00379 * @arg @ref LL_GPIO_MODE_OUTPUT 00380 * @arg @ref LL_GPIO_MODE_ALTERNATE 00381 */ 00382 __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) 00383 { 00384 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); 00385 return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); 00386 } 00387 00388 /** 00389 * @brief Configure gpio speed for a dedicated pin on dedicated port. 00390 * @note I/O speed can be Low, Medium or Fast speed. 00391 * @note Warning: only one pin can be passed as parameter. 00392 * @note Refer to datasheet for frequency specifications and the power 00393 * supply and load conditions for each speed. 00394 * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed 00395 * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed 00396 * @param GPIOx GPIO Port 00397 * @param Pin This parameter can be one of the following values: 00398 * @arg @ref LL_GPIO_PIN_0 00399 * @arg @ref LL_GPIO_PIN_1 00400 * @arg @ref LL_GPIO_PIN_2 00401 * @arg @ref LL_GPIO_PIN_3 00402 * @arg @ref LL_GPIO_PIN_4 00403 * @arg @ref LL_GPIO_PIN_5 00404 * @arg @ref LL_GPIO_PIN_6 00405 * @arg @ref LL_GPIO_PIN_7 00406 * @arg @ref LL_GPIO_PIN_8 00407 * @arg @ref LL_GPIO_PIN_9 00408 * @arg @ref LL_GPIO_PIN_10 00409 * @arg @ref LL_GPIO_PIN_11 00410 * @arg @ref LL_GPIO_PIN_12 00411 * @arg @ref LL_GPIO_PIN_13 00412 * @arg @ref LL_GPIO_PIN_14 00413 * @arg @ref LL_GPIO_PIN_15 00414 * @param Speed This parameter can be one of the following values: 00415 * @arg @ref LL_GPIO_SPEED_FREQ_LOW 00416 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM 00417 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH 00418 * @retval None 00419 */ 00420 __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) 00421 { 00422 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); 00423 MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)), 00424 (Speed << (POSITION_VAL(Pin) * 4U))); 00425 } 00426 00427 /** 00428 * @brief Return gpio speed for a dedicated pin on dedicated port. 00429 * @note I/O speed can be Low, Medium, Fast or High speed. 00430 * @note Warning: only one pin can be passed as parameter. 00431 * @note Refer to datasheet for frequency specifications and the power 00432 * supply and load conditions for each speed. 00433 * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed 00434 * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed 00435 * @param GPIOx GPIO Port 00436 * @param Pin This parameter can be one of the following values: 00437 * @arg @ref LL_GPIO_PIN_0 00438 * @arg @ref LL_GPIO_PIN_1 00439 * @arg @ref LL_GPIO_PIN_2 00440 * @arg @ref LL_GPIO_PIN_3 00441 * @arg @ref LL_GPIO_PIN_4 00442 * @arg @ref LL_GPIO_PIN_5 00443 * @arg @ref LL_GPIO_PIN_6 00444 * @arg @ref LL_GPIO_PIN_7 00445 * @arg @ref LL_GPIO_PIN_8 00446 * @arg @ref LL_GPIO_PIN_9 00447 * @arg @ref LL_GPIO_PIN_10 00448 * @arg @ref LL_GPIO_PIN_11 00449 * @arg @ref LL_GPIO_PIN_12 00450 * @arg @ref LL_GPIO_PIN_13 00451 * @arg @ref LL_GPIO_PIN_14 00452 * @arg @ref LL_GPIO_PIN_15 00453 * @retval Returned value can be one of the following values: 00454 * @arg @ref LL_GPIO_SPEED_FREQ_LOW 00455 * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM 00456 * @arg @ref LL_GPIO_SPEED_FREQ_HIGH 00457 */ 00458 __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) 00459 { 00460 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); 00461 return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); 00462 } 00463 00464 /** 00465 * @brief Configure gpio output type for several pins on dedicated port. 00466 * @note Output type as to be set when gpio pin is in output or 00467 * alternate modes. Possible type are Push-pull or Open-drain. 00468 * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType 00469 * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType 00470 * @param GPIOx GPIO Port 00471 * @param Pin This parameter can be a combination of the following values: 00472 * @arg @ref LL_GPIO_PIN_0 00473 * @arg @ref LL_GPIO_PIN_1 00474 * @arg @ref LL_GPIO_PIN_2 00475 * @arg @ref LL_GPIO_PIN_3 00476 * @arg @ref LL_GPIO_PIN_4 00477 * @arg @ref LL_GPIO_PIN_5 00478 * @arg @ref LL_GPIO_PIN_6 00479 * @arg @ref LL_GPIO_PIN_7 00480 * @arg @ref LL_GPIO_PIN_8 00481 * @arg @ref LL_GPIO_PIN_9 00482 * @arg @ref LL_GPIO_PIN_10 00483 * @arg @ref LL_GPIO_PIN_11 00484 * @arg @ref LL_GPIO_PIN_12 00485 * @arg @ref LL_GPIO_PIN_13 00486 * @arg @ref LL_GPIO_PIN_14 00487 * @arg @ref LL_GPIO_PIN_15 00488 * @arg @ref LL_GPIO_PIN_ALL 00489 * @param OutputType This parameter can be one of the following values: 00490 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL 00491 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN 00492 * @retval None 00493 */ 00494 __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) 00495 { 00496 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); 00497 MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)), 00498 (OutputType << (POSITION_VAL(Pin) * 4U))); 00499 } 00500 00501 /** 00502 * @brief Return gpio output type for several pins on dedicated port. 00503 * @note Output type as to be set when gpio pin is in output or 00504 * alternate modes. Possible type are Push-pull or Open-drain. 00505 * @note Warning: only one pin can be passed as parameter. 00506 * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType 00507 * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType 00508 * @param GPIOx GPIO Port 00509 * @param Pin This parameter can be one of the following values: 00510 * @arg @ref LL_GPIO_PIN_0 00511 * @arg @ref LL_GPIO_PIN_1 00512 * @arg @ref LL_GPIO_PIN_2 00513 * @arg @ref LL_GPIO_PIN_3 00514 * @arg @ref LL_GPIO_PIN_4 00515 * @arg @ref LL_GPIO_PIN_5 00516 * @arg @ref LL_GPIO_PIN_6 00517 * @arg @ref LL_GPIO_PIN_7 00518 * @arg @ref LL_GPIO_PIN_8 00519 * @arg @ref LL_GPIO_PIN_9 00520 * @arg @ref LL_GPIO_PIN_10 00521 * @arg @ref LL_GPIO_PIN_11 00522 * @arg @ref LL_GPIO_PIN_12 00523 * @arg @ref LL_GPIO_PIN_13 00524 * @arg @ref LL_GPIO_PIN_14 00525 * @arg @ref LL_GPIO_PIN_15 00526 * @arg @ref LL_GPIO_PIN_ALL 00527 * @retval Returned value can be one of the following values: 00528 * @arg @ref LL_GPIO_OUTPUT_PUSHPULL 00529 * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN 00530 */ 00531 __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) 00532 { 00533 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); 00534 return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); 00535 00536 } 00537 00538 /** 00539 * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. 00540 * @note Warning: only one pin can be passed as parameter. 00541 * @rmtoll ODR ODR LL_GPIO_SetPinPull 00542 * @param GPIOx GPIO Port 00543 * @param Pin This parameter can be one of the following values: 00544 * @arg @ref LL_GPIO_PIN_0 00545 * @arg @ref LL_GPIO_PIN_1 00546 * @arg @ref LL_GPIO_PIN_2 00547 * @arg @ref LL_GPIO_PIN_3 00548 * @arg @ref LL_GPIO_PIN_4 00549 * @arg @ref LL_GPIO_PIN_5 00550 * @arg @ref LL_GPIO_PIN_6 00551 * @arg @ref LL_GPIO_PIN_7 00552 * @arg @ref LL_GPIO_PIN_8 00553 * @arg @ref LL_GPIO_PIN_9 00554 * @arg @ref LL_GPIO_PIN_10 00555 * @arg @ref LL_GPIO_PIN_11 00556 * @arg @ref LL_GPIO_PIN_12 00557 * @arg @ref LL_GPIO_PIN_13 00558 * @arg @ref LL_GPIO_PIN_14 00559 * @arg @ref LL_GPIO_PIN_15 00560 * @param Pull This parameter can be one of the following values: 00561 * @arg @ref LL_GPIO_PULL_DOWN 00562 * @arg @ref LL_GPIO_PULL_UP 00563 * @retval None 00564 */ 00565 __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) 00566 { 00567 MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); 00568 } 00569 00570 /** 00571 * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port 00572 * @note Warning: only one pin can be passed as parameter. 00573 * @rmtoll ODR ODR LL_GPIO_GetPinPull 00574 * @param GPIOx GPIO Port 00575 * @param Pin This parameter can be one of the following values: 00576 * @arg @ref LL_GPIO_PIN_0 00577 * @arg @ref LL_GPIO_PIN_1 00578 * @arg @ref LL_GPIO_PIN_2 00579 * @arg @ref LL_GPIO_PIN_3 00580 * @arg @ref LL_GPIO_PIN_4 00581 * @arg @ref LL_GPIO_PIN_5 00582 * @arg @ref LL_GPIO_PIN_6 00583 * @arg @ref LL_GPIO_PIN_7 00584 * @arg @ref LL_GPIO_PIN_8 00585 * @arg @ref LL_GPIO_PIN_9 00586 * @arg @ref LL_GPIO_PIN_10 00587 * @arg @ref LL_GPIO_PIN_11 00588 * @arg @ref LL_GPIO_PIN_12 00589 * @arg @ref LL_GPIO_PIN_13 00590 * @arg @ref LL_GPIO_PIN_14 00591 * @arg @ref LL_GPIO_PIN_15 00592 * @retval Returned value can be one of the following values: 00593 * @arg @ref LL_GPIO_PULL_DOWN 00594 * @arg @ref LL_GPIO_PULL_UP 00595 */ 00596 __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) 00597 { 00598 return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); 00599 } 00600 00601 /** 00602 * @brief Lock configuration of several pins for a dedicated port. 00603 * @note When the lock sequence has been applied on a port bit, the 00604 * value of this port bit can no longer be modified until the 00605 * next reset. 00606 * @note Each lock bit freezes a specific configuration register 00607 * (control and alternate function registers). 00608 * @rmtoll LCKR LCKK LL_GPIO_LockPin 00609 * @param GPIOx GPIO Port 00610 * @param PinMask This parameter can be a combination of the following values: 00611 * @arg @ref LL_GPIO_PIN_0 00612 * @arg @ref LL_GPIO_PIN_1 00613 * @arg @ref LL_GPIO_PIN_2 00614 * @arg @ref LL_GPIO_PIN_3 00615 * @arg @ref LL_GPIO_PIN_4 00616 * @arg @ref LL_GPIO_PIN_5 00617 * @arg @ref LL_GPIO_PIN_6 00618 * @arg @ref LL_GPIO_PIN_7 00619 * @arg @ref LL_GPIO_PIN_8 00620 * @arg @ref LL_GPIO_PIN_9 00621 * @arg @ref LL_GPIO_PIN_10 00622 * @arg @ref LL_GPIO_PIN_11 00623 * @arg @ref LL_GPIO_PIN_12 00624 * @arg @ref LL_GPIO_PIN_13 00625 * @arg @ref LL_GPIO_PIN_14 00626 * @arg @ref LL_GPIO_PIN_15 00627 * @arg @ref LL_GPIO_PIN_ALL 00628 * @retval None 00629 */ 00630 __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) 00631 { 00632 __IO uint32_t temp; 00633 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 00634 WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 00635 WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 00636 temp = READ_REG(GPIOx->LCKR); 00637 (void) temp; 00638 } 00639 00640 /** 00641 * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. 00642 * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked 00643 * @param GPIOx GPIO Port 00644 * @param PinMask This parameter can be a combination of the following values: 00645 * @arg @ref LL_GPIO_PIN_0 00646 * @arg @ref LL_GPIO_PIN_1 00647 * @arg @ref LL_GPIO_PIN_2 00648 * @arg @ref LL_GPIO_PIN_3 00649 * @arg @ref LL_GPIO_PIN_4 00650 * @arg @ref LL_GPIO_PIN_5 00651 * @arg @ref LL_GPIO_PIN_6 00652 * @arg @ref LL_GPIO_PIN_7 00653 * @arg @ref LL_GPIO_PIN_8 00654 * @arg @ref LL_GPIO_PIN_9 00655 * @arg @ref LL_GPIO_PIN_10 00656 * @arg @ref LL_GPIO_PIN_11 00657 * @arg @ref LL_GPIO_PIN_12 00658 * @arg @ref LL_GPIO_PIN_13 00659 * @arg @ref LL_GPIO_PIN_14 00660 * @arg @ref LL_GPIO_PIN_15 00661 * @arg @ref LL_GPIO_PIN_ALL 00662 * @retval State of bit (1 or 0). 00663 */ 00664 __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) 00665 { 00666 return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 00667 } 00668 00669 /** 00670 * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. 00671 * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked 00672 * @param GPIOx GPIO Port 00673 * @retval State of bit (1 or 0). 00674 */ 00675 __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) 00676 { 00677 return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); 00678 } 00679 00680 /** 00681 * @} 00682 */ 00683 00684 /** @defgroup GPIO_LL_EF_Data_Access Data Access 00685 * @{ 00686 */ 00687 00688 /** 00689 * @brief Return full input data register value for a dedicated port. 00690 * @rmtoll IDR IDy LL_GPIO_ReadInputPort 00691 * @param GPIOx GPIO Port 00692 * @retval Input data register value of port 00693 */ 00694 __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) 00695 { 00696 return (READ_REG(GPIOx->IDR)); 00697 } 00698 00699 /** 00700 * @brief Return if input data level for several pins of dedicated port is high or low. 00701 * @rmtoll IDR IDy LL_GPIO_IsInputPinSet 00702 * @param GPIOx GPIO Port 00703 * @param PinMask This parameter can be a combination of the following values: 00704 * @arg @ref LL_GPIO_PIN_0 00705 * @arg @ref LL_GPIO_PIN_1 00706 * @arg @ref LL_GPIO_PIN_2 00707 * @arg @ref LL_GPIO_PIN_3 00708 * @arg @ref LL_GPIO_PIN_4 00709 * @arg @ref LL_GPIO_PIN_5 00710 * @arg @ref LL_GPIO_PIN_6 00711 * @arg @ref LL_GPIO_PIN_7 00712 * @arg @ref LL_GPIO_PIN_8 00713 * @arg @ref LL_GPIO_PIN_9 00714 * @arg @ref LL_GPIO_PIN_10 00715 * @arg @ref LL_GPIO_PIN_11 00716 * @arg @ref LL_GPIO_PIN_12 00717 * @arg @ref LL_GPIO_PIN_13 00718 * @arg @ref LL_GPIO_PIN_14 00719 * @arg @ref LL_GPIO_PIN_15 00720 * @arg @ref LL_GPIO_PIN_ALL 00721 * @retval State of bit (1 or 0). 00722 */ 00723 __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) 00724 { 00725 return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 00726 } 00727 00728 /** 00729 * @brief Write output data register for the port. 00730 * @rmtoll ODR ODy LL_GPIO_WriteOutputPort 00731 * @param GPIOx GPIO Port 00732 * @param PortValue Level value for each pin of the port 00733 * @retval None 00734 */ 00735 __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) 00736 { 00737 WRITE_REG(GPIOx->ODR, PortValue); 00738 } 00739 00740 /** 00741 * @brief Return full output data register value for a dedicated port. 00742 * @rmtoll ODR ODy LL_GPIO_ReadOutputPort 00743 * @param GPIOx GPIO Port 00744 * @retval Output data register value of port 00745 */ 00746 __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) 00747 { 00748 return (uint32_t)(READ_REG(GPIOx->ODR)); 00749 } 00750 00751 /** 00752 * @brief Return if input data level for several pins of dedicated port is high or low. 00753 * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet 00754 * @param GPIOx GPIO Port 00755 * @param PinMask This parameter can be a combination of the following values: 00756 * @arg @ref LL_GPIO_PIN_0 00757 * @arg @ref LL_GPIO_PIN_1 00758 * @arg @ref LL_GPIO_PIN_2 00759 * @arg @ref LL_GPIO_PIN_3 00760 * @arg @ref LL_GPIO_PIN_4 00761 * @arg @ref LL_GPIO_PIN_5 00762 * @arg @ref LL_GPIO_PIN_6 00763 * @arg @ref LL_GPIO_PIN_7 00764 * @arg @ref LL_GPIO_PIN_8 00765 * @arg @ref LL_GPIO_PIN_9 00766 * @arg @ref LL_GPIO_PIN_10 00767 * @arg @ref LL_GPIO_PIN_11 00768 * @arg @ref LL_GPIO_PIN_12 00769 * @arg @ref LL_GPIO_PIN_13 00770 * @arg @ref LL_GPIO_PIN_14 00771 * @arg @ref LL_GPIO_PIN_15 00772 * @arg @ref LL_GPIO_PIN_ALL 00773 * @retval State of bit (1 or 0). 00774 */ 00775 __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) 00776 { 00777 return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); 00778 } 00779 00780 /** 00781 * @brief Set several pins to high level on dedicated gpio port. 00782 * @rmtoll BSRR BSy LL_GPIO_SetOutputPin 00783 * @param GPIOx GPIO Port 00784 * @param PinMask This parameter can be a combination of the following values: 00785 * @arg @ref LL_GPIO_PIN_0 00786 * @arg @ref LL_GPIO_PIN_1 00787 * @arg @ref LL_GPIO_PIN_2 00788 * @arg @ref LL_GPIO_PIN_3 00789 * @arg @ref LL_GPIO_PIN_4 00790 * @arg @ref LL_GPIO_PIN_5 00791 * @arg @ref LL_GPIO_PIN_6 00792 * @arg @ref LL_GPIO_PIN_7 00793 * @arg @ref LL_GPIO_PIN_8 00794 * @arg @ref LL_GPIO_PIN_9 00795 * @arg @ref LL_GPIO_PIN_10 00796 * @arg @ref LL_GPIO_PIN_11 00797 * @arg @ref LL_GPIO_PIN_12 00798 * @arg @ref LL_GPIO_PIN_13 00799 * @arg @ref LL_GPIO_PIN_14 00800 * @arg @ref LL_GPIO_PIN_15 00801 * @arg @ref LL_GPIO_PIN_ALL 00802 * @retval None 00803 */ 00804 __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) 00805 { 00806 WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); 00807 } 00808 00809 /** 00810 * @brief Set several pins to low level on dedicated gpio port. 00811 * @rmtoll BRR BRy LL_GPIO_ResetOutputPin 00812 * @param GPIOx GPIO Port 00813 * @param PinMask This parameter can be a combination of the following values: 00814 * @arg @ref LL_GPIO_PIN_0 00815 * @arg @ref LL_GPIO_PIN_1 00816 * @arg @ref LL_GPIO_PIN_2 00817 * @arg @ref LL_GPIO_PIN_3 00818 * @arg @ref LL_GPIO_PIN_4 00819 * @arg @ref LL_GPIO_PIN_5 00820 * @arg @ref LL_GPIO_PIN_6 00821 * @arg @ref LL_GPIO_PIN_7 00822 * @arg @ref LL_GPIO_PIN_8 00823 * @arg @ref LL_GPIO_PIN_9 00824 * @arg @ref LL_GPIO_PIN_10 00825 * @arg @ref LL_GPIO_PIN_11 00826 * @arg @ref LL_GPIO_PIN_12 00827 * @arg @ref LL_GPIO_PIN_13 00828 * @arg @ref LL_GPIO_PIN_14 00829 * @arg @ref LL_GPIO_PIN_15 00830 * @arg @ref LL_GPIO_PIN_ALL 00831 * @retval None 00832 */ 00833 __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) 00834 { 00835 WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); 00836 } 00837 00838 /** 00839 * @brief Toggle data value for several pin of dedicated port. 00840 * @rmtoll ODR ODy LL_GPIO_TogglePin 00841 * @param GPIOx GPIO Port 00842 * @param PinMask This parameter can be a combination of the following values: 00843 * @arg @ref LL_GPIO_PIN_0 00844 * @arg @ref LL_GPIO_PIN_1 00845 * @arg @ref LL_GPIO_PIN_2 00846 * @arg @ref LL_GPIO_PIN_3 00847 * @arg @ref LL_GPIO_PIN_4 00848 * @arg @ref LL_GPIO_PIN_5 00849 * @arg @ref LL_GPIO_PIN_6 00850 * @arg @ref LL_GPIO_PIN_7 00851 * @arg @ref LL_GPIO_PIN_8 00852 * @arg @ref LL_GPIO_PIN_9 00853 * @arg @ref LL_GPIO_PIN_10 00854 * @arg @ref LL_GPIO_PIN_11 00855 * @arg @ref LL_GPIO_PIN_12 00856 * @arg @ref LL_GPIO_PIN_13 00857 * @arg @ref LL_GPIO_PIN_14 00858 * @arg @ref LL_GPIO_PIN_15 00859 * @arg @ref LL_GPIO_PIN_ALL 00860 * @retval None 00861 */ 00862 __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) 00863 { 00864 uint32_t odr = READ_REG(GPIOx->ODR); 00865 uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); 00866 WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask)); 00867 } 00868 00869 /** 00870 * @} 00871 */ 00872 00873 /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping 00874 * @brief This section propose definition to remap the alternate function to some other port/pins. 00875 * @{ 00876 */ 00877 00878 /** 00879 * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. 00880 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1 00881 * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) 00882 * @retval None 00883 */ 00884 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void) 00885 { 00886 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG); 00887 } 00888 00889 /** 00890 * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. 00891 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1 00892 * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) 00893 * @retval None 00894 */ 00895 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void) 00896 { 00897 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 00898 } 00899 00900 /** 00901 * @brief Check if SPI1 has been remaped or not 00902 * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1 00903 * @retval State of bit (1 or 0). 00904 */ 00905 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void) 00906 { 00907 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP)); 00908 } 00909 00910 /** 00911 * @brief Enable the remapping of I2C1 alternate function SCL and SDA. 00912 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1 00913 * @note ENABLE: Remap (SCL/PB8, SDA/PB9) 00914 * @retval None 00915 */ 00916 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void) 00917 { 00918 SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG); 00919 } 00920 00921 /** 00922 * @brief Disable the remapping of I2C1 alternate function SCL and SDA. 00923 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1 00924 * @note DISABLE: No remap (SCL/PB6, SDA/PB7) 00925 * @retval None 00926 */ 00927 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void) 00928 { 00929 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 00930 } 00931 00932 /** 00933 * @brief Check if I2C1 has been remaped or not 00934 * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1 00935 * @retval State of bit (1 or 0). 00936 */ 00937 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void) 00938 { 00939 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP)); 00940 } 00941 00942 /** 00943 * @brief Enable the remapping of USART1 alternate function TX and RX. 00944 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1 00945 * @note ENABLE: Remap (TX/PB6, RX/PB7) 00946 * @retval None 00947 */ 00948 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void) 00949 { 00950 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG); 00951 } 00952 00953 /** 00954 * @brief Disable the remapping of USART1 alternate function TX and RX. 00955 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1 00956 * @note DISABLE: No remap (TX/PA9, RX/PA10) 00957 * @retval None 00958 */ 00959 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void) 00960 { 00961 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 00962 } 00963 00964 /** 00965 * @brief Check if USART1 has been remaped or not 00966 * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1 00967 * @retval State of bit (1 or 0). 00968 */ 00969 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void) 00970 { 00971 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP)); 00972 } 00973 00974 /** 00975 * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. 00976 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2 00977 * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) 00978 * @retval None 00979 */ 00980 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void) 00981 { 00982 SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG); 00983 } 00984 00985 /** 00986 * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. 00987 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2 00988 * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) 00989 * @retval None 00990 */ 00991 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void) 00992 { 00993 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 00994 } 00995 00996 /** 00997 * @brief Check if USART2 has been remaped or not 00998 * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2 00999 * @retval State of bit (1 or 0). 01000 */ 01001 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void) 01002 { 01003 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP)); 01004 } 01005 01006 #if defined (AFIO_MAPR_USART3_REMAP) 01007 /** 01008 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 01009 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3 01010 * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) 01011 * @retval None 01012 */ 01013 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void) 01014 { 01015 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); 01016 } 01017 01018 /** 01019 * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 01020 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3 01021 * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) 01022 * @retval None 01023 */ 01024 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void) 01025 { 01026 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); 01027 } 01028 01029 /** 01030 * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. 01031 * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3 01032 * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) 01033 * @retval None 01034 */ 01035 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void) 01036 { 01037 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); 01038 } 01039 #endif 01040 01041 /** 01042 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 01043 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1 01044 * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) 01045 * @retval None 01046 */ 01047 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void) 01048 { 01049 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); 01050 } 01051 01052 /** 01053 * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 01054 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1 01055 * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 01056 * @retval None 01057 */ 01058 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void) 01059 { 01060 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); 01061 } 01062 01063 /** 01064 * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) 01065 * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1 01066 * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 01067 * @retval None 01068 */ 01069 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void) 01070 { 01071 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); 01072 } 01073 01074 /** 01075 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 01076 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2 01077 * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) 01078 * @retval None 01079 */ 01080 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void) 01081 { 01082 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); 01083 } 01084 01085 /** 01086 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 01087 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2 01088 * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) 01089 * @retval None 01090 */ 01091 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void) 01092 { 01093 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG)); 01094 } 01095 01096 /** 01097 * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 01098 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2 01099 * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) 01100 * @retval None 01101 */ 01102 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void) 01103 { 01104 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG)); 01105 } 01106 01107 /** 01108 * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) 01109 * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2 01110 * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) 01111 * @retval None 01112 */ 01113 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void) 01114 { 01115 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); 01116 } 01117 01118 /** 01119 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 01120 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3 01121 * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) 01122 * @note TIM3_ETR on PE0 is not re-mapped. 01123 * @retval None 01124 */ 01125 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void) 01126 { 01127 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); 01128 } 01129 01130 /** 01131 * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 01132 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3 01133 * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) 01134 * @note TIM3_ETR on PE0 is not re-mapped. 01135 * @retval None 01136 */ 01137 __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void) 01138 { 01139 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); 01140 } 01141 01142 /** 01143 * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 01144 * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3 01145 * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) 01146 * @note TIM3_ETR on PE0 is not re-mapped. 01147 * @retval None 01148 */ 01149 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void) 01150 { 01151 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); 01152 } 01153 01154 #if defined(AFIO_MAPR_TIM4_REMAP) 01155 /** 01156 * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. 01157 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4 01158 * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) 01159 * @note TIM4_ETR on PE0 is not re-mapped. 01160 * @retval None 01161 */ 01162 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void) 01163 { 01164 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG); 01165 } 01166 /** 01167 * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. 01168 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4 01169 * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) 01170 * @note TIM4_ETR on PE0 is not re-mapped. 01171 * @retval None 01172 */ 01173 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void) 01174 { 01175 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01176 } 01177 01178 /** 01179 * @brief Check if TIM4 has been remaped or not 01180 * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4 01181 * @retval State of bit (1 or 0). 01182 */ 01183 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void) 01184 { 01185 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP)); 01186 } 01187 #endif 01188 01189 #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) 01190 01191 /** 01192 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 01193 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1 01194 * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 01195 * @retval None 01196 */ 01197 __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void) 01198 { 01199 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG)); 01200 } 01201 01202 /** 01203 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 01204 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1 01205 * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) 01206 * @retval None 01207 */ 01208 __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void) 01209 { 01210 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG)); 01211 } 01212 01213 /** 01214 * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. 01215 * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1 01216 * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 01217 * @retval None 01218 */ 01219 __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void) 01220 { 01221 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG)); 01222 } 01223 #endif 01224 01225 /** 01226 * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used 01227 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 01228 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 01229 * on 100-pin and 144-pin packages, no need for remapping). 01230 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01 01231 * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. 01232 * @retval None 01233 */ 01234 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void) 01235 { 01236 SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG); 01237 } 01238 01239 /** 01240 * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used 01241 * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and 01242 * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available 01243 * on 100-pin and 144-pin packages, no need for remapping). 01244 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01 01245 * @note DISABLE: No remapping of PD0 and PD1 01246 * @retval None 01247 */ 01248 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void) 01249 { 01250 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01251 } 01252 01253 /** 01254 * @brief Check if PD01 has been remaped or not 01255 * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01 01256 * @retval State of bit (1 or 0). 01257 */ 01258 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void) 01259 { 01260 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP)); 01261 } 01262 01263 #if defined(AFIO_MAPR_TIM5CH4_IREMAP) 01264 /** 01265 * @brief Enable the remapping of TIM5CH4. 01266 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4 01267 * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. 01268 * @note This function is available only in high density value line devices. 01269 * @retval None 01270 */ 01271 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void) 01272 { 01273 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG); 01274 } 01275 01276 /** 01277 * @brief Disable the remapping of TIM5CH4. 01278 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4 01279 * @note DISABLE: TIM5_CH4 is connected to PA3 01280 * @note This function is available only in high density value line devices. 01281 * @retval None 01282 */ 01283 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void) 01284 { 01285 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01286 } 01287 01288 /** 01289 * @brief Check if TIM5CH4 has been remaped or not 01290 * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4 01291 * @retval State of bit (1 or 0). 01292 */ 01293 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void) 01294 { 01295 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP)); 01296 } 01297 #endif 01298 01299 #if defined(AFIO_MAPR_ETH_REMAP) 01300 /** 01301 * @brief Enable the remapping of Ethernet MAC connections with the PHY. 01302 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH 01303 * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) 01304 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01305 * @retval None 01306 */ 01307 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void) 01308 { 01309 SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG); 01310 } 01311 01312 /** 01313 * @brief Disable the remapping of Ethernet MAC connections with the PHY. 01314 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH 01315 * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) 01316 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01317 * @retval None 01318 */ 01319 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void) 01320 { 01321 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01322 } 01323 01324 /** 01325 * @brief Check if ETH has been remaped or not 01326 * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH 01327 * @retval State of bit (1 or 0). 01328 */ 01329 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void) 01330 { 01331 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP)); 01332 } 01333 #endif 01334 01335 #if defined(AFIO_MAPR_CAN2_REMAP) 01336 01337 /** 01338 * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. 01339 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2 01340 * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) 01341 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01342 * @retval None 01343 */ 01344 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void) 01345 { 01346 SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG); 01347 } 01348 /** 01349 * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. 01350 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2 01351 * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) 01352 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01353 * @retval None 01354 */ 01355 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void) 01356 { 01357 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01358 } 01359 01360 /** 01361 * @brief Check if CAN2 has been remaped or not 01362 * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2 01363 * @retval State of bit (1 or 0). 01364 */ 01365 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void) 01366 { 01367 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP)); 01368 } 01369 #endif 01370 01371 #if defined(AFIO_MAPR_MII_RMII_SEL) 01372 /** 01373 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. 01374 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII 01375 * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY 01376 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01377 * @retval None 01378 */ 01379 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void) 01380 { 01381 SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG); 01382 } 01383 01384 /** 01385 * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. 01386 * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII 01387 * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY 01388 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01389 * @retval None 01390 */ 01391 __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void) 01392 { 01393 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01394 } 01395 #endif 01396 01397 #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP) 01398 /** 01399 * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). 01400 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ 01401 * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. 01402 * @retval None 01403 */ 01404 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void) 01405 { 01406 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); 01407 } 01408 01409 /** 01410 * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). 01411 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ 01412 * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 01413 * @retval None 01414 */ 01415 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void) 01416 { 01417 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01418 } 01419 01420 /** 01421 * @brief Check if ADC1_ETRGINJ has been remaped or not 01422 * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ 01423 * @retval State of bit (1 or 0). 01424 */ 01425 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void) 01426 { 01427 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP)); 01428 } 01429 #endif 01430 01431 #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP) 01432 /** 01433 * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). 01434 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG 01435 * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. 01436 * @retval None 01437 */ 01438 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void) 01439 { 01440 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); 01441 } 01442 01443 /** 01444 * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). 01445 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG 01446 * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 01447 * @retval None 01448 */ 01449 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void) 01450 { 01451 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01452 } 01453 01454 /** 01455 * @brief Check if ADC1_ETRGREG has been remaped or not 01456 * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG 01457 * @retval State of bit (1 or 0). 01458 */ 01459 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void) 01460 { 01461 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP)); 01462 } 01463 #endif 01464 01465 #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) 01466 01467 /** 01468 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). 01469 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ 01470 * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. 01471 * @retval None 01472 */ 01473 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void) 01474 { 01475 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); 01476 } 01477 01478 /** 01479 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). 01480 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ 01481 * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 01482 * @retval None 01483 */ 01484 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void) 01485 { 01486 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01487 } 01488 01489 /** 01490 * @brief Check if ADC2_ETRGINJ has been remaped or not 01491 * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ 01492 * @retval State of bit (1 or 0). 01493 */ 01494 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void) 01495 { 01496 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP)); 01497 } 01498 #endif 01499 01500 #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) 01501 01502 /** 01503 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 01504 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG 01505 * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. 01506 * @retval None 01507 */ 01508 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void) 01509 { 01510 SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); 01511 } 01512 01513 /** 01514 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 01515 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG 01516 * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 01517 * @retval None 01518 */ 01519 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void) 01520 { 01521 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01522 } 01523 01524 /** 01525 * @brief Check if ADC2_ETRGREG has been remaped or not 01526 * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG 01527 * @retval State of bit (1 or 0). 01528 */ 01529 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void) 01530 { 01531 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP)); 01532 } 01533 #endif 01534 01535 /** 01536 * @brief Enable the Serial wire JTAG configuration 01537 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ 01538 * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State 01539 * @retval None 01540 */ 01541 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void) 01542 { 01543 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); 01544 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET); 01545 } 01546 01547 /** 01548 * @brief Enable the Serial wire JTAG configuration 01549 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST 01550 * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST 01551 * @retval None 01552 */ 01553 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void) 01554 { 01555 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); 01556 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST); 01557 } 01558 01559 /** 01560 * @brief Enable the Serial wire JTAG configuration 01561 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG 01562 * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled 01563 * @retval None 01564 */ 01565 __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void) 01566 { 01567 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); 01568 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); 01569 } 01570 01571 /** 01572 * @brief Disable the Serial wire JTAG configuration 01573 * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ 01574 * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled 01575 * @retval None 01576 */ 01577 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void) 01578 { 01579 CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); 01580 SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE); 01581 } 01582 01583 #if defined(AFIO_MAPR_SPI3_REMAP) 01584 01585 /** 01586 * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. 01587 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3 01588 * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) 01589 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01590 * @retval None 01591 */ 01592 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void) 01593 { 01594 SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG); 01595 } 01596 01597 /** 01598 * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. 01599 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3 01600 * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). 01601 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01602 * @retval None 01603 */ 01604 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void) 01605 { 01606 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01607 } 01608 01609 /** 01610 * @brief Check if SPI3 has been remaped or not 01611 * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP 01612 * @retval State of bit (1 or 0). 01613 */ 01614 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void) 01615 { 01616 return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP)); 01617 } 01618 #endif 01619 01620 #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) 01621 01622 /** 01623 * @brief Control of TIM2_ITR1 internal mapping. 01624 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB 01625 * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. 01626 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01627 * @retval None 01628 */ 01629 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void) 01630 { 01631 SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG); 01632 } 01633 01634 /** 01635 * @brief Control of TIM2_ITR1 internal mapping. 01636 * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH 01637 * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. 01638 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01639 * @retval None 01640 */ 01641 __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void) 01642 { 01643 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01644 } 01645 #endif 01646 01647 #if defined(AFIO_MAPR_PTP_PPS_REMAP) 01648 01649 /** 01650 * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 01651 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS 01652 * @note ENABLE: PTP_PPS is output on PB5 pin. 01653 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01654 * @retval None 01655 */ 01656 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void) 01657 { 01658 SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG); 01659 } 01660 01661 /** 01662 * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). 01663 * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS 01664 * @note DISABLE: PTP_PPS not output on PB5 pin. 01665 * @note This bit is available only in connectivity line devices and is reserved otherwise. 01666 * @retval None 01667 */ 01668 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void) 01669 { 01670 MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); 01671 } 01672 #endif 01673 01674 #if defined(AFIO_MAPR2_TIM9_REMAP) 01675 01676 /** 01677 * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. 01678 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9 01679 * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). 01680 * @retval None 01681 */ 01682 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void) 01683 { 01684 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); 01685 } 01686 01687 /** 01688 * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. 01689 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9 01690 * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). 01691 * @retval None 01692 */ 01693 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void) 01694 { 01695 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); 01696 } 01697 01698 /** 01699 * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not 01700 * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9 01701 * @retval State of bit (1 or 0). 01702 */ 01703 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void) 01704 { 01705 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP)); 01706 } 01707 #endif 01708 01709 #if defined(AFIO_MAPR2_TIM10_REMAP) 01710 01711 /** 01712 * @brief Enable the remapping of TIM10_CH1. 01713 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10 01714 * @note ENABLE: Remap (TIM10_CH1 on PF6). 01715 * @retval None 01716 */ 01717 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void) 01718 { 01719 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); 01720 } 01721 01722 /** 01723 * @brief Disable the remapping of TIM10_CH1. 01724 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10 01725 * @note DISABLE: No remap (TIM10_CH1 on PB8). 01726 * @retval None 01727 */ 01728 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void) 01729 { 01730 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); 01731 } 01732 01733 /** 01734 * @brief Check if TIM10_CH1 has been remaped or not 01735 * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10 01736 * @retval State of bit (1 or 0). 01737 */ 01738 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void) 01739 { 01740 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP)); 01741 } 01742 #endif 01743 01744 #if defined(AFIO_MAPR2_TIM11_REMAP) 01745 /** 01746 * @brief Enable the remapping of TIM11_CH1. 01747 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11 01748 * @note ENABLE: Remap (TIM11_CH1 on PF7). 01749 * @retval None 01750 */ 01751 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void) 01752 { 01753 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); 01754 } 01755 01756 /** 01757 * @brief Disable the remapping of TIM11_CH1. 01758 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11 01759 * @note DISABLE: No remap (TIM11_CH1 on PB9). 01760 * @retval None 01761 */ 01762 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void) 01763 { 01764 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); 01765 } 01766 01767 /** 01768 * @brief Check if TIM11_CH1 has been remaped or not 01769 * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11 01770 * @retval State of bit (1 or 0). 01771 */ 01772 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void) 01773 { 01774 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP)); 01775 } 01776 #endif 01777 01778 #if defined(AFIO_MAPR2_TIM13_REMAP) 01779 01780 /** 01781 * @brief Enable the remapping of TIM13_CH1. 01782 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13 01783 * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). 01784 * @retval None 01785 */ 01786 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void) 01787 { 01788 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); 01789 } 01790 01791 /** 01792 * @brief Disable the remapping of TIM13_CH1. 01793 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13 01794 * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). 01795 * @retval None 01796 */ 01797 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void) 01798 { 01799 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); 01800 } 01801 01802 /** 01803 * @brief Check if TIM13_CH1 has been remaped or not 01804 * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13 01805 * @retval State of bit (1 or 0). 01806 */ 01807 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void) 01808 { 01809 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP)); 01810 } 01811 #endif 01812 01813 #if defined(AFIO_MAPR2_TIM14_REMAP) 01814 01815 /** 01816 * @brief Enable the remapping of TIM14_CH1. 01817 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14 01818 * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). 01819 * @retval None 01820 */ 01821 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void) 01822 { 01823 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); 01824 } 01825 01826 /** 01827 * @brief Disable the remapping of TIM14_CH1. 01828 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14 01829 * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). 01830 * @retval None 01831 */ 01832 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void) 01833 { 01834 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); 01835 } 01836 01837 /** 01838 * @brief Check if TIM14_CH1 has been remaped or not 01839 * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14 01840 * @retval State of bit (1 or 0). 01841 */ 01842 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void) 01843 { 01844 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP)); 01845 } 01846 #endif 01847 01848 #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) 01849 01850 /** 01851 * @brief Controls the use of the optional FSMC_NADV signal. 01852 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV 01853 * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. 01854 * @retval None 01855 */ 01856 __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void) 01857 { 01858 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); 01859 } 01860 01861 /** 01862 * @brief Controls the use of the optional FSMC_NADV signal. 01863 * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV 01864 * @note CONNECTED: The NADV signal is connected to the output (default). 01865 * @retval None 01866 */ 01867 __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void) 01868 { 01869 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); 01870 } 01871 #endif 01872 01873 #if defined(AFIO_MAPR2_TIM15_REMAP) 01874 01875 /** 01876 * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. 01877 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15 01878 * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). 01879 * @retval None 01880 */ 01881 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void) 01882 { 01883 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); 01884 } 01885 /** 01886 * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. 01887 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15 01888 * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). 01889 * @retval None 01890 */ 01891 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void) 01892 { 01893 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); 01894 } 01895 01896 /** 01897 * @brief Check if TIM15_CH1 has been remaped or not 01898 * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15 01899 * @retval State of bit (1 or 0). 01900 */ 01901 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void) 01902 { 01903 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP)); 01904 } 01905 #endif 01906 01907 #if defined(AFIO_MAPR2_TIM16_REMAP) 01908 01909 /** 01910 * @brief Enable the remapping of TIM16_CH1. 01911 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16 01912 * @note ENABLE: Remap (TIM16_CH1 on PA6). 01913 * @retval None 01914 */ 01915 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void) 01916 { 01917 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); 01918 } 01919 01920 /** 01921 * @brief Disable the remapping of TIM16_CH1. 01922 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16 01923 * @note DISABLE: No remap (TIM16_CH1 on PB8). 01924 * @retval None 01925 */ 01926 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void) 01927 { 01928 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); 01929 } 01930 01931 /** 01932 * @brief Check if TIM16_CH1 has been remaped or not 01933 * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16 01934 * @retval State of bit (1 or 0). 01935 */ 01936 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void) 01937 { 01938 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP)); 01939 } 01940 #endif 01941 01942 #if defined(AFIO_MAPR2_TIM17_REMAP) 01943 01944 /** 01945 * @brief Enable the remapping of TIM17_CH1. 01946 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17 01947 * @note ENABLE: Remap (TIM17_CH1 on PA7). 01948 * @retval None 01949 */ 01950 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void) 01951 { 01952 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); 01953 } 01954 01955 /** 01956 * @brief Disable the remapping of TIM17_CH1. 01957 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17 01958 * @note DISABLE: No remap (TIM17_CH1 on PB9). 01959 * @retval None 01960 */ 01961 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void) 01962 { 01963 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); 01964 } 01965 01966 /** 01967 * @brief Check if TIM17_CH1 has been remaped or not 01968 * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17 01969 * @retval State of bit (1 or 0). 01970 */ 01971 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void) 01972 { 01973 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP)); 01974 } 01975 #endif 01976 01977 #if defined(AFIO_MAPR2_CEC_REMAP) 01978 01979 /** 01980 * @brief Enable the remapping of CEC. 01981 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC 01982 * @note ENABLE: Remap (CEC on PB10). 01983 * @retval None 01984 */ 01985 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void) 01986 { 01987 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); 01988 } 01989 01990 /** 01991 * @brief Disable the remapping of CEC. 01992 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC 01993 * @note DISABLE: No remap (CEC on PB8). 01994 * @retval None 01995 */ 01996 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void) 01997 { 01998 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); 01999 } 02000 02001 /** 02002 * @brief Check if CEC has been remaped or not 02003 * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC 02004 * @retval State of bit (1 or 0). 02005 */ 02006 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void) 02007 { 02008 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP)); 02009 } 02010 #endif 02011 02012 #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) 02013 02014 /** 02015 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. 02016 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA 02017 * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) 02018 * @retval None 02019 */ 02020 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void) 02021 { 02022 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); 02023 } 02024 02025 /** 02026 * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. 02027 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA 02028 * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). 02029 * @retval None 02030 */ 02031 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void) 02032 { 02033 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); 02034 } 02035 02036 /** 02037 * @brief Check if TIM1DMA has been remaped or not 02038 * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA 02039 * @retval State of bit (1 or 0). 02040 */ 02041 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void) 02042 { 02043 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP)); 02044 } 02045 #endif 02046 02047 #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) 02048 02049 /** 02050 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. 02051 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA 02052 * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) 02053 * @retval None 02054 */ 02055 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void) 02056 { 02057 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); 02058 } 02059 02060 /** 02061 * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. 02062 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA 02063 * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) 02064 * @retval None 02065 */ 02066 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void) 02067 { 02068 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); 02069 } 02070 02071 /** 02072 * @brief Check if TIM67DACDMA has been remaped or not 02073 * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA 02074 * @retval State of bit (1 or 0). 02075 */ 02076 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void) 02077 { 02078 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP)); 02079 } 02080 #endif 02081 02082 #if defined(AFIO_MAPR2_TIM12_REMAP) 02083 02084 /** 02085 * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. 02086 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12 02087 * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). 02088 * @note This bit is available only in high density value line devices. 02089 * @retval None 02090 */ 02091 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void) 02092 { 02093 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); 02094 } 02095 02096 /** 02097 * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. 02098 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12 02099 * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). 02100 * @note This bit is available only in high density value line devices. 02101 * @retval None 02102 */ 02103 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void) 02104 { 02105 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); 02106 } 02107 02108 /** 02109 * @brief Check if TIM12_CH1 has been remaped or not 02110 * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12 02111 * @retval State of bit (1 or 0). 02112 */ 02113 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void) 02114 { 02115 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP)); 02116 } 02117 #endif 02118 02119 #if defined(AFIO_MAPR2_MISC_REMAP) 02120 02121 /** 02122 * @brief Miscellaneous features remapping. 02123 * This bit is set and cleared by software. It controls miscellaneous features. 02124 * The DMA2 channel 5 interrupt position in the vector table. 02125 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). 02126 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC 02127 * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is 02128 * selected as DAC Trigger 3, TIM15 triggers TIM1/3. 02129 * @note This bit is available only in high density value line devices. 02130 * @retval None 02131 */ 02132 __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void) 02133 { 02134 SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); 02135 } 02136 02137 /** 02138 * @brief Miscellaneous features remapping. 02139 * This bit is set and cleared by software. It controls miscellaneous features. 02140 * The DMA2 channel 5 interrupt position in the vector table. 02141 * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). 02142 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC 02143 * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO 02144 * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. 02145 * @note This bit is available only in high density value line devices. 02146 * @retval None 02147 */ 02148 __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void) 02149 { 02150 CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); 02151 } 02152 02153 /** 02154 * @brief Check if MISC has been remaped or not 02155 * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC 02156 * @retval State of bit (1 or 0). 02157 */ 02158 __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void) 02159 { 02160 return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP)); 02161 } 02162 #endif 02163 02164 /** 02165 * @} 02166 */ 02167 02168 /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration 02169 * @brief This section propose definition to Configure EVENTOUT Cortex feature . 02170 * @{ 02171 */ 02172 02173 /** 02174 * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. 02175 * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n 02176 * EVCR PIN LL_GPIO_AF_ConfigEventout 02177 * @param LL_GPIO_PortSource This parameter can be one of the following values: 02178 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A 02179 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B 02180 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C 02181 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D 02182 * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E 02183 * @param LL_GPIO_PinSource This parameter can be one of the following values: 02184 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0 02185 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1 02186 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2 02187 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3 02188 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4 02189 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5 02190 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6 02191 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7 02192 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8 02193 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9 02194 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10 02195 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11 02196 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12 02197 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13 02198 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14 02199 * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15 02200 * @retval None 02201 */ 02202 __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource) 02203 { 02204 MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource)); 02205 } 02206 02207 /** 02208 * @brief Enables the Event Output. 02209 * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout 02210 * @retval None 02211 */ 02212 __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void) 02213 { 02214 SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 02215 } 02216 02217 /** 02218 * @brief Disables the Event Output. 02219 * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout 02220 * @retval None 02221 */ 02222 __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void) 02223 { 02224 CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); 02225 } 02226 02227 /** 02228 * @} 02229 */ 02230 /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt 02231 * @brief This section Configure source input for the EXTI external interrupt . 02232 * @{ 02233 */ 02234 02235 /** 02236 * @brief Configure source input for the EXTI external interrupt. 02237 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n 02238 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n 02239 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n 02240 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource 02241 * @param Port This parameter can be one of the following values: 02242 * @arg @ref LL_GPIO_AF_EXTI_PORTA 02243 * @arg @ref LL_GPIO_AF_EXTI_PORTB 02244 * @arg @ref LL_GPIO_AF_EXTI_PORTC 02245 * @arg @ref LL_GPIO_AF_EXTI_PORTD 02246 * @arg @ref LL_GPIO_AF_EXTI_PORTE 02247 * @arg @ref LL_GPIO_AF_EXTI_PORTF 02248 * @arg @ref LL_GPIO_AF_EXTI_PORTG 02249 * @param Line This parameter can be one of the following values: 02250 * @arg @ref LL_GPIO_AF_EXTI_LINE0 02251 * @arg @ref LL_GPIO_AF_EXTI_LINE1 02252 * @arg @ref LL_GPIO_AF_EXTI_LINE2 02253 * @arg @ref LL_GPIO_AF_EXTI_LINE3 02254 * @arg @ref LL_GPIO_AF_EXTI_LINE4 02255 * @arg @ref LL_GPIO_AF_EXTI_LINE5 02256 * @arg @ref LL_GPIO_AF_EXTI_LINE6 02257 * @arg @ref LL_GPIO_AF_EXTI_LINE7 02258 * @arg @ref LL_GPIO_AF_EXTI_LINE8 02259 * @arg @ref LL_GPIO_AF_EXTI_LINE9 02260 * @arg @ref LL_GPIO_AF_EXTI_LINE10 02261 * @arg @ref LL_GPIO_AF_EXTI_LINE11 02262 * @arg @ref LL_GPIO_AF_EXTI_LINE12 02263 * @arg @ref LL_GPIO_AF_EXTI_LINE13 02264 * @arg @ref LL_GPIO_AF_EXTI_LINE14 02265 * @arg @ref LL_GPIO_AF_EXTI_LINE15 02266 * @retval None 02267 */ 02268 __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line) 02269 { 02270 MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); 02271 } 02272 02273 /** 02274 * @brief Get the configured defined for specific EXTI Line 02275 * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n 02276 * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n 02277 * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n 02278 * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource 02279 * @param Line This parameter can be one of the following values: 02280 * @arg @ref LL_GPIO_AF_EXTI_LINE0 02281 * @arg @ref LL_GPIO_AF_EXTI_LINE1 02282 * @arg @ref LL_GPIO_AF_EXTI_LINE2 02283 * @arg @ref LL_GPIO_AF_EXTI_LINE3 02284 * @arg @ref LL_GPIO_AF_EXTI_LINE4 02285 * @arg @ref LL_GPIO_AF_EXTI_LINE5 02286 * @arg @ref LL_GPIO_AF_EXTI_LINE6 02287 * @arg @ref LL_GPIO_AF_EXTI_LINE7 02288 * @arg @ref LL_GPIO_AF_EXTI_LINE8 02289 * @arg @ref LL_GPIO_AF_EXTI_LINE9 02290 * @arg @ref LL_GPIO_AF_EXTI_LINE10 02291 * @arg @ref LL_GPIO_AF_EXTI_LINE11 02292 * @arg @ref LL_GPIO_AF_EXTI_LINE12 02293 * @arg @ref LL_GPIO_AF_EXTI_LINE13 02294 * @arg @ref LL_GPIO_AF_EXTI_LINE14 02295 * @arg @ref LL_GPIO_AF_EXTI_LINE15 02296 * @retval Returned value can be one of the following values: 02297 * @arg @ref LL_GPIO_AF_EXTI_PORTA 02298 * @arg @ref LL_GPIO_AF_EXTI_PORTB 02299 * @arg @ref LL_GPIO_AF_EXTI_PORTC 02300 * @arg @ref LL_GPIO_AF_EXTI_PORTD 02301 * @arg @ref LL_GPIO_AF_EXTI_PORTE 02302 * @arg @ref LL_GPIO_AF_EXTI_PORTF 02303 * @arg @ref LL_GPIO_AF_EXTI_PORTG 02304 */ 02305 __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line) 02306 { 02307 return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); 02308 } 02309 02310 /** 02311 * @} 02312 */ 02313 02314 #if defined(USE_FULL_LL_DRIVER) 02315 /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions 02316 * @{ 02317 */ 02318 02319 ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); 02320 ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); 02321 void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); 02322 02323 /** 02324 * @} 02325 */ 02326 #endif /* USE_FULL_LL_DRIVER */ 02327 02328 /** 02329 * @} 02330 */ 02331 02332 /** 02333 * @} 02334 */ 02335 02336 #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */ 02337 /** 02338 * @} 02339 */ 02340 02341 #ifdef __cplusplus 02342 } 02343 #endif 02344 02345 #endif /* STM32F1xx_LL_GPIO_H */ 02346 02347 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1