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STM32F103xB HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f1xx_ll_system.h 00004 * @author MCD Application Team 00005 * @brief Header file of SYSTEM LL module. 00006 @verbatim 00007 ============================================================================== 00008 ##### How to use this driver ##### 00009 ============================================================================== 00010 [..] 00011 The LL SYSTEM driver contains a set of generic APIs that can be 00012 used by user: 00013 (+) Some of the FLASH features need to be handled in the SYSTEM file. 00014 (+) Access to DBGCMU registers 00015 (+) Access to SYSCFG registers 00016 00017 @endverbatim 00018 ****************************************************************************** 00019 * @attention 00020 * 00021 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00022 * All rights reserved.</center></h2> 00023 * 00024 * This software component is licensed by ST under BSD 3-Clause license, 00025 * the "License"; You may not use this file except in compliance with the 00026 * License. You may obtain a copy of the License at: 00027 * opensource.org/licenses/BSD-3-Clause 00028 * 00029 ****************************************************************************** 00030 */ 00031 00032 /* Define to prevent recursive inclusion -------------------------------------*/ 00033 #ifndef __STM32F1xx_LL_SYSTEM_H 00034 #define __STM32F1xx_LL_SYSTEM_H 00035 00036 #ifdef __cplusplus 00037 extern "C" { 00038 #endif 00039 00040 /* Includes ------------------------------------------------------------------*/ 00041 #include "stm32f1xx.h" 00042 00043 /** @addtogroup STM32F1xx_LL_Driver 00044 * @{ 00045 */ 00046 00047 #if defined (FLASH) || defined (DBGMCU) 00048 00049 /** @defgroup SYSTEM_LL SYSTEM 00050 * @{ 00051 */ 00052 00053 /* Private types -------------------------------------------------------------*/ 00054 /* Private variables ---------------------------------------------------------*/ 00055 00056 /* Private constants ---------------------------------------------------------*/ 00057 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants 00058 * @{ 00059 */ 00060 00061 /** 00062 * @} 00063 */ 00064 00065 /* Private macros ------------------------------------------------------------*/ 00066 00067 /* Exported types ------------------------------------------------------------*/ 00068 /* Exported constants --------------------------------------------------------*/ 00069 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants 00070 * @{ 00071 */ 00072 00073 00074 00075 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment 00076 * @{ 00077 */ 00078 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ 00079 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ 00080 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ 00081 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ 00082 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ 00083 /** 00084 * @} 00085 */ 00086 00087 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP 00088 * @{ 00089 */ 00090 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ 00091 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ 00092 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ 00093 #if defined(DBGMCU_CR_DBG_TIM5_STOP) 00094 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ 00095 #endif /* DBGMCU_CR_DBG_TIM5_STOP */ 00096 #if defined(DBGMCU_CR_DBG_TIM6_STOP) 00097 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ 00098 #endif /* DBGMCU_CR_DBG_TIM6_STOP */ 00099 #if defined(DBGMCU_CR_DBG_TIM7_STOP) 00100 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ 00101 #endif /* DBGMCU_CR_DBG_TIM7_STOP */ 00102 #if defined(DBGMCU_CR_DBG_TIM12_STOP) 00103 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ 00104 #endif /* DBGMCU_CR_DBG_TIM12_STOP */ 00105 #if defined(DBGMCU_CR_DBG_TIM13_STOP) 00106 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ 00107 #endif /* DBGMCU_CR_DBG_TIM13_STOP */ 00108 #if defined(DBGMCU_CR_DBG_TIM14_STOP) 00109 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ 00110 #endif /* DBGMCU_CR_DBG_TIM14_STOP */ 00111 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ 00112 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ 00113 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ 00114 #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) 00115 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ 00116 #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ 00117 #if defined(DBGMCU_CR_DBG_CAN1_STOP) 00118 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ 00119 #endif /* DBGMCU_CR_DBG_CAN1_STOP */ 00120 #if defined(DBGMCU_CR_DBG_CAN2_STOP) 00121 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ 00122 #endif /* DBGMCU_CR_DBG_CAN2_STOP */ 00123 /** 00124 * @} 00125 */ 00126 00127 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP 00128 * @{ 00129 */ 00130 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ 00131 #if defined(DBGMCU_CR_DBG_TIM8_STOP) 00132 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ 00133 #endif /* DBGMCU_CR_DBG_CAN1_STOP */ 00134 #if defined(DBGMCU_CR_DBG_TIM9_STOP) 00135 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ 00136 #endif /* DBGMCU_CR_DBG_TIM9_STOP */ 00137 #if defined(DBGMCU_CR_DBG_TIM10_STOP) 00138 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ 00139 #endif /* DBGMCU_CR_DBG_TIM10_STOP */ 00140 #if defined(DBGMCU_CR_DBG_TIM11_STOP) 00141 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ 00142 #endif /* DBGMCU_CR_DBG_TIM11_STOP */ 00143 #if defined(DBGMCU_CR_DBG_TIM15_STOP) 00144 #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ 00145 #endif /* DBGMCU_CR_DBG_TIM15_STOP */ 00146 #if defined(DBGMCU_CR_DBG_TIM16_STOP) 00147 #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ 00148 #endif /* DBGMCU_CR_DBG_TIM16_STOP */ 00149 #if defined(DBGMCU_CR_DBG_TIM17_STOP) 00150 #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ 00151 #endif /* DBGMCU_CR_DBG_TIM17_STOP */ 00152 /** 00153 * @} 00154 */ 00155 00156 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY 00157 * @{ 00158 */ 00159 #if defined(FLASH_ACR_LATENCY) 00160 #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ 00161 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ 00162 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ 00163 #else 00164 #endif /* FLASH_ACR_LATENCY */ 00165 /** 00166 * @} 00167 */ 00168 00169 /** 00170 * @} 00171 */ 00172 00173 /* Exported macro ------------------------------------------------------------*/ 00174 00175 /* Exported functions --------------------------------------------------------*/ 00176 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions 00177 * @{ 00178 */ 00179 00180 00181 00182 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU 00183 * @{ 00184 */ 00185 00186 /** 00187 * @brief Return the device identifier 00188 * @note For Low Density devices, the device ID is 0x412 00189 * @note For Medium Density devices, the device ID is 0x410 00190 * @note For High Density devices, the device ID is 0x414 00191 * @note For XL Density devices, the device ID is 0x430 00192 * @note For Connectivity Line devices, the device ID is 0x418 00193 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID 00194 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF 00195 */ 00196 __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) 00197 { 00198 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); 00199 } 00200 00201 /** 00202 * @brief Return the device revision identifier 00203 * @note This field indicates the revision of the device. 00204 For example, it is read as revA -> 0x1000,for Low Density devices 00205 For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices 00206 For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices 00207 For example, it is read as revA or 1 -> 0x1003,for XL Density devices 00208 For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices 00209 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID 00210 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF 00211 */ 00212 __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) 00213 { 00214 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); 00215 } 00216 00217 /** 00218 * @brief Enable the Debug Module during SLEEP mode 00219 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode 00220 * @retval None 00221 */ 00222 __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) 00223 { 00224 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 00225 } 00226 00227 /** 00228 * @brief Disable the Debug Module during SLEEP mode 00229 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode 00230 * @retval None 00231 */ 00232 __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) 00233 { 00234 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); 00235 } 00236 00237 /** 00238 * @brief Enable the Debug Module during STOP mode 00239 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode 00240 * @retval None 00241 */ 00242 __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) 00243 { 00244 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 00245 } 00246 00247 /** 00248 * @brief Disable the Debug Module during STOP mode 00249 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode 00250 * @retval None 00251 */ 00252 __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) 00253 { 00254 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); 00255 } 00256 00257 /** 00258 * @brief Enable the Debug Module during STANDBY mode 00259 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode 00260 * @retval None 00261 */ 00262 __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) 00263 { 00264 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 00265 } 00266 00267 /** 00268 * @brief Disable the Debug Module during STANDBY mode 00269 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode 00270 * @retval None 00271 */ 00272 __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) 00273 { 00274 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); 00275 } 00276 00277 /** 00278 * @brief Set Trace pin assignment control 00279 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n 00280 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment 00281 * @param PinAssignment This parameter can be one of the following values: 00282 * @arg @ref LL_DBGMCU_TRACE_NONE 00283 * @arg @ref LL_DBGMCU_TRACE_ASYNCH 00284 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 00285 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 00286 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 00287 * @retval None 00288 */ 00289 __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) 00290 { 00291 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); 00292 } 00293 00294 /** 00295 * @brief Get Trace pin assignment control 00296 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n 00297 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment 00298 * @retval Returned value can be one of the following values: 00299 * @arg @ref LL_DBGMCU_TRACE_NONE 00300 * @arg @ref LL_DBGMCU_TRACE_ASYNCH 00301 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 00302 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 00303 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 00304 */ 00305 __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) 00306 { 00307 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); 00308 } 00309 00310 /** 00311 * @brief Freeze APB1 peripherals (group1 peripherals) 00312 * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00313 * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00314 * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00315 * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00316 * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00317 * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00318 * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00319 * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00320 * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00321 * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00322 * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00323 * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00324 * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00325 * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00326 * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n 00327 * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph 00328 * @param Periphs This parameter can be a combination of the following values: 00329 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 00330 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP 00331 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP 00332 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 00333 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 00334 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP 00335 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP 00336 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP 00337 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP 00338 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP 00339 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP 00340 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 00341 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) 00342 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) 00343 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) 00344 * 00345 * (*) value not defined in all devices. 00346 * @retval None 00347 */ 00348 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) 00349 { 00350 SET_BIT(DBGMCU->CR, Periphs); 00351 } 00352 00353 /** 00354 * @brief Unfreeze APB1 peripherals (group1 peripherals) 00355 * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00356 * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00357 * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00358 * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00359 * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00360 * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00361 * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00362 * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00363 * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00364 * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00365 * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00366 * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00367 * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00368 * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00369 * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n 00370 * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph 00371 * @param Periphs This parameter can be a combination of the following values: 00372 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP 00373 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP 00374 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP 00375 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP 00376 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP 00377 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP 00378 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP 00379 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP 00380 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP 00381 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP 00382 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP 00383 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP 00384 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP 00385 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) 00386 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) 00387 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) 00388 * 00389 * (*) value not defined in all devices. 00390 * @retval None 00391 */ 00392 __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) 00393 { 00394 CLEAR_BIT(DBGMCU->CR, Periphs); 00395 } 00396 00397 /** 00398 * @brief Freeze APB2 peripherals 00399 * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00400 * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00401 * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00402 * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00403 * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00404 * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00405 * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00406 * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph 00407 * @param Periphs This parameter can be a combination of the following values: 00408 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 00409 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) 00410 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) 00411 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) 00412 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) 00413 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) 00414 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) 00415 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) 00416 * 00417 * (*) value not defined in all devices. 00418 * @retval None 00419 */ 00420 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) 00421 { 00422 SET_BIT(DBGMCU->CR, Periphs); 00423 } 00424 00425 /** 00426 * @brief Unfreeze APB2 peripherals 00427 * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00428 * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00429 * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00430 * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00431 * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00432 * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00433 * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n 00434 * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph 00435 * @param Periphs This parameter can be a combination of the following values: 00436 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP 00437 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) 00438 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) 00439 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) 00440 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) 00441 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) 00442 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) 00443 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) 00444 * 00445 * (*) value not defined in all devices. 00446 * @retval None 00447 */ 00448 __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) 00449 { 00450 CLEAR_BIT(DBGMCU->CR, Periphs); 00451 } 00452 /** 00453 * @} 00454 */ 00455 00456 #if defined(FLASH_ACR_LATENCY) 00457 /** @defgroup SYSTEM_LL_EF_FLASH FLASH 00458 * @{ 00459 */ 00460 00461 /** 00462 * @brief Set FLASH Latency 00463 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency 00464 * @param Latency This parameter can be one of the following values: 00465 * @arg @ref LL_FLASH_LATENCY_0 00466 * @arg @ref LL_FLASH_LATENCY_1 00467 * @arg @ref LL_FLASH_LATENCY_2 00468 * @retval None 00469 */ 00470 __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) 00471 { 00472 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); 00473 } 00474 00475 /** 00476 * @brief Get FLASH Latency 00477 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency 00478 * @retval Returned value can be one of the following values: 00479 * @arg @ref LL_FLASH_LATENCY_0 00480 * @arg @ref LL_FLASH_LATENCY_1 00481 * @arg @ref LL_FLASH_LATENCY_2 00482 */ 00483 __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) 00484 { 00485 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); 00486 } 00487 00488 /** 00489 * @brief Enable Prefetch 00490 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch 00491 * @retval None 00492 */ 00493 __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) 00494 { 00495 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); 00496 } 00497 00498 /** 00499 * @brief Disable Prefetch 00500 * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch 00501 * @retval None 00502 */ 00503 __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) 00504 { 00505 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); 00506 } 00507 00508 /** 00509 * @brief Check if Prefetch buffer is enabled 00510 * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled 00511 * @retval State of bit (1 or 0). 00512 */ 00513 __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) 00514 { 00515 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); 00516 } 00517 00518 #endif /* FLASH_ACR_LATENCY */ 00519 /** 00520 * @brief Enable Flash Half Cycle Access 00521 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess 00522 * @retval None 00523 */ 00524 __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) 00525 { 00526 SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); 00527 } 00528 00529 /** 00530 * @brief Disable Flash Half Cycle Access 00531 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess 00532 * @retval None 00533 */ 00534 __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) 00535 { 00536 CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); 00537 } 00538 00539 /** 00540 * @brief Check if Flash Half Cycle Access is enabled or not 00541 * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled 00542 * @retval State of bit (1 or 0). 00543 */ 00544 __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) 00545 { 00546 return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); 00547 } 00548 00549 00550 /** 00551 * @} 00552 */ 00553 00554 /** 00555 * @} 00556 */ 00557 00558 /** 00559 * @} 00560 */ 00561 00562 #endif /* defined (FLASH) || defined (DBGMCU) */ 00563 00564 /** 00565 * @} 00566 */ 00567 00568 #ifdef __cplusplus 00569 } 00570 #endif 00571 00572 #endif /* __STM32F1xx_LL_SYSTEM_H */ 00573 00574 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1