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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dfsdm.h 00004 * @author MCD Application Team 00005 * @brief Header file of DFSDM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F4xx_HAL_DFSDM_H 00022 #define __STM32F4xx_HAL_DFSDM_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 #if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00029 /* Includes ------------------------------------------------------------------*/ 00030 #include "stm32f4xx_hal_def.h" 00031 00032 /** @addtogroup STM32F4xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @addtogroup DFSDM 00037 * @{ 00038 */ 00039 00040 /* Exported types ------------------------------------------------------------*/ 00041 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief HAL DFSDM Channel states definition 00047 */ 00048 typedef enum 00049 { 00050 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 00051 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 00052 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 00053 }HAL_DFSDM_Channel_StateTypeDef; 00054 00055 /** 00056 * @brief DFSDM channel output clock structure definition 00057 */ 00058 typedef struct 00059 { 00060 FunctionalState Activation; /*!< Output clock enable/disable */ 00061 uint32_t Selection; /*!< Output clock is system clock or audio clock. 00062 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 00063 uint32_t Divider; /*!< Output clock divider. 00064 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 00065 }DFSDM_Channel_OutputClockTypeDef; 00066 00067 /** 00068 * @brief DFSDM channel input structure definition 00069 */ 00070 typedef struct 00071 { 00072 uint32_t Multiplexer; /*!< Input is external serial inputs or internal register. 00073 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 00074 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 00075 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 00076 uint32_t Pins; /*!< Input pins are taken from same or following channel. 00077 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 00078 }DFSDM_Channel_InputTypeDef; 00079 00080 /** 00081 * @brief DFSDM channel serial interface structure definition 00082 */ 00083 typedef struct 00084 { 00085 uint32_t Type; /*!< SPI or Manchester modes. 00086 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 00087 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 00088 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 00089 }DFSDM_Channel_SerialInterfaceTypeDef; 00090 00091 /** 00092 * @brief DFSDM channel analog watchdog structure definition 00093 */ 00094 typedef struct 00095 { 00096 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 00097 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 00098 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 00099 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 00100 }DFSDM_Channel_AwdTypeDef; 00101 00102 /** 00103 * @brief DFSDM channel init structure definition 00104 */ 00105 typedef struct 00106 { 00107 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 00108 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 00109 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 00110 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 00111 int32_t Offset; /*!< DFSDM channel offset. 00112 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00113 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 00114 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 00115 }DFSDM_Channel_InitTypeDef; 00116 00117 /** 00118 * @brief DFSDM channel handle structure definition 00119 */ 00120 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00121 typedef struct __DFSDM_Channel_HandleTypeDef 00122 #else 00123 typedef struct 00124 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 00125 { 00126 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 00127 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 00128 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 00129 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00130 void (*CkabCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 00131 void (*ScdCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 00132 void (*MspInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 00133 void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 00134 #endif 00135 }DFSDM_Channel_HandleTypeDef; 00136 00137 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00138 /** 00139 * @brief DFSDM channel callback ID enumeration definition 00140 */ 00141 typedef enum 00142 { 00143 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 00144 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 00145 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 00146 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 00147 }HAL_DFSDM_Channel_CallbackIDTypeDef; 00148 00149 /** 00150 * @brief DFSDM channel callback pointer definition 00151 */ 00152 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00153 #endif 00154 /** 00155 * @brief HAL DFSDM Filter states definition 00156 */ 00157 typedef enum 00158 { 00159 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 00160 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 00161 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 00162 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 00163 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 00164 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 00165 }HAL_DFSDM_Filter_StateTypeDef; 00166 00167 /** 00168 * @brief DFSDM filter regular conversion parameters structure definition 00169 */ 00170 typedef struct 00171 { 00172 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 00173 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 00174 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 00175 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 00176 }DFSDM_Filter_RegularParamTypeDef; 00177 00178 /** 00179 * @brief DFSDM filter injected conversion parameters structure definition 00180 */ 00181 typedef struct 00182 { 00183 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 00184 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 00185 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 00186 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 00187 uint32_t ExtTrigger; /*!< External trigger. 00188 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 00189 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 00190 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 00191 }DFSDM_Filter_InjectedParamTypeDef; 00192 00193 /** 00194 * @brief DFSDM filter parameters structure definition 00195 */ 00196 typedef struct 00197 { 00198 uint32_t SincOrder; /*!< Sinc filter order. 00199 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 00200 uint32_t Oversampling; /*!< Filter oversampling ratio. 00201 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 00202 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 00203 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 00204 }DFSDM_Filter_FilterParamTypeDef; 00205 00206 /** 00207 * @brief DFSDM filter init structure definition 00208 */ 00209 typedef struct 00210 { 00211 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 00212 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 00213 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 00214 }DFSDM_Filter_InitTypeDef; 00215 00216 /** 00217 * @brief DFSDM filter handle structure definition 00218 */ 00219 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00220 typedef struct __DFSDM_Filter_HandleTypeDef 00221 #else 00222 typedef struct 00223 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 00224 { 00225 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 00226 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 00227 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 00228 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 00229 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 00230 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 00231 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 00232 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 00233 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 00234 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 00235 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 00236 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 00237 uint32_t ErrorCode; /*!< DFSDM filter error code */ 00238 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00239 void (*AwdCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00240 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 00241 void (*RegConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 00242 void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 00243 void (*InjConvCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 00244 void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 00245 void (*ErrorCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 00246 void (*MspInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 00247 void (*MspDeInitCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 00248 #endif 00249 }DFSDM_Filter_HandleTypeDef; 00250 00251 /** 00252 * @brief DFSDM filter analog watchdog parameters structure definition 00253 */ 00254 typedef struct 00255 { 00256 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 00257 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 00258 uint32_t Channel; /*!< Analog watchdog channel selection. 00259 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 00260 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 00261 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00262 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 00263 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00264 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 00265 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 00266 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 00267 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 00268 }DFSDM_Filter_AwdParamTypeDef; 00269 00270 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00271 /** 00272 * @brief DFSDM filter callback ID enumeration definition 00273 */ 00274 typedef enum 00275 { 00276 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 00277 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 00278 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 00279 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 00280 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 00281 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 00282 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 00283 }HAL_DFSDM_Filter_CallbackIDTypeDef; 00284 00285 /** 00286 * @brief DFSDM filter callback pointer definition 00287 */ 00288 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00289 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 00290 #endif 00291 00292 /** 00293 * @} 00294 */ 00295 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 00296 /** 00297 * @brief Synchronization parameters structure definition for STM32F413xx/STM32F423xx devices 00298 */ 00299 typedef struct 00300 { 00301 uint32_t DFSDM1ClockIn; /*!< Source selection for DFSDM1_Ckin. 00302 This parameter can be a value of @ref DFSDM_1_CLOCKIN_SELECTION*/ 00303 uint32_t DFSDM2ClockIn; /*!< Source selection for DFSDM2_Ckin. 00304 This parameter can be a value of @ref DFSDM_2_CLOCKIN_SELECTION*/ 00305 uint32_t DFSDM1ClockOut; /*!< Source selection for DFSDM1_Ckout. 00306 This parameter can be a value of @ref DFSDM_1_CLOCKOUT_SELECTION*/ 00307 uint32_t DFSDM2ClockOut; /*!< Source selection for DFSDM2_Ckout. 00308 This parameter can be a value of @ref DFSDM_2_CLOCKOUT_SELECTION*/ 00309 uint32_t DFSDM1BitClkDistribution; /*!< Distribution of the DFSDM1 bitstream clock gated by TIM4 OC1 or TIM4 OC2. 00310 This parameter can be a value of @ref DFSDM_1_BIT_STREAM_DISTRIBUTION 00311 @note The DFSDM2 audio gated by TIM4 OC2 can be injected on CKIN0 or CKIN2 00312 @note The DFSDM2 audio gated by TIM4 OC1 can be injected on CKIN1 or CKIN3 */ 00313 uint32_t DFSDM2BitClkDistribution; /*!< Distribution of the DFSDM2 bitstream clock gated by TIM3 OC1 or TIM3 OC2 or TIM3 OC3 or TIM3 OC4. 00314 This parameter can be a value of @ref DFSDM_2_BIT_STREAM_DISTRIBUTION 00315 @note The DFSDM2 audio gated by TIM3 OC4 can be injected on CKIN0 or CKIN4 00316 @note The DFSDM2 audio gated by TIM3 OC3 can be injected on CKIN1 or CKIN5 00317 @note The DFSDM2 audio gated by TIM3 OC2 can be injected on CKIN2 or CKIN6 00318 @note The DFSDM2 audio gated by TIM3 OC1 can be injected on CKIN3 or CKIN7 */ 00319 uint32_t DFSDM1DataDistribution; /*!< Source selection for DatIn0 and DatIn2 of DFSDM1. 00320 This parameter can be a value of @ref DFSDM_1_DATA_DISTRIBUTION */ 00321 uint32_t DFSDM2DataDistribution; /*!< Source selection for DatIn0, DatIn2, DatIn4 and DatIn6 of DFSDM2. 00322 This parameter can be a value of @ref DFSDM_2_DATA_DISTRIBUTION */ 00323 }DFSDM_MultiChannelConfigTypeDef; 00324 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ 00325 /** 00326 * @} 00327 */ 00328 00329 /* End of exported types -----------------------------------------------------*/ 00330 00331 /* Exported constants --------------------------------------------------------*/ 00332 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 00333 * @{ 00334 */ 00335 00336 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 00337 * @{ 00338 */ 00339 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ 00340 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ 00341 /** 00342 * @} 00343 */ 00344 00345 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 00346 * @{ 00347 */ 00348 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ 00349 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 00350 /** 00351 * @} 00352 */ 00353 00354 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 00355 * @{ 00356 */ 00357 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ 00358 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 00359 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 00365 * @{ 00366 */ 00367 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ 00368 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 00369 /** 00370 * @} 00371 */ 00372 00373 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 00374 * @{ 00375 */ 00376 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ 00377 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 00378 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 00379 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 00380 /** 00381 * @} 00382 */ 00383 00384 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 00385 * @{ 00386 */ 00387 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ 00388 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 00389 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 00390 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 00391 /** 00392 * @} 00393 */ 00394 00395 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 00396 * @{ 00397 */ 00398 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 00399 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 00400 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 00401 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 00402 /** 00403 * @} 00404 */ 00405 00406 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 00407 * @{ 00408 */ 00409 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ 00410 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ 00411 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ 00412 /** 00413 * @} 00414 */ 00415 00416 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 00417 * @{ 00418 */ 00419 #if defined(STM32F413xx) || defined(STM32F423xx) 00420 /* Trigger for stm32f413xx and STM32f423xx devices */ 00421 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For All DFSDM1/2 filters */ 00422 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For All DFSDM1/2 filters */ 00423 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For All DFSDM1/2 filters */ 00424 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */ 00425 #define DFSDM_FILTER_EXT_TRIG_TIM2_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM2 filter 3 */ 00426 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0, 1 and 2 */ 00427 #define DFSDM_FILTER_EXT_TRIG_TIM11_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM2 filter 3 */ 00428 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1 and DFSDM2 filter 0 and 1 */ 00429 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM2 filter 2 and 3*/ 00430 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For All DFSDM1/2 filters */ 00431 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For All DFSDM1/2 filters */ 00432 #else 00433 /* Trigger for stm32f412xx devices */ 00434 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM1 filter 0 and 1*/ 00435 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM1 filter 0 and 1*/ 00436 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM1 filter 0 and 1*/ 00437 #define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM1 filter 0 and 1*/ 00438 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM1 filter 0 and 1*/ 00439 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/ 00440 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM1 filter 0 and 1*/ 00441 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM1 filter 0 and 1*/ 00442 #endif 00443 /** 00444 * @} 00445 */ 00446 00447 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 00448 * @{ 00449 */ 00450 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 00451 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 00452 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 00453 /** 00454 * @} 00455 */ 00456 00457 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 00458 * @{ 00459 */ 00460 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 00461 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 00462 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 00463 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 00464 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 00465 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 00466 /** 00467 * @} 00468 */ 00469 00470 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 00471 * @{ 00472 */ 00473 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ 00474 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 00475 /** 00476 * @} 00477 */ 00478 00479 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 00480 * @{ 00481 */ 00482 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ 00483 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ 00484 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ 00485 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ 00486 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00487 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ 00488 #endif 00489 /** 00490 * @} 00491 */ 00492 00493 /** @defgroup DFSDM_BreakSignals DFSDM break signals 00494 * @{ 00495 */ 00496 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ 00497 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ 00498 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ 00499 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ 00500 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ 00501 /** 00502 * @} 00503 */ 00504 00505 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 00506 * @{ 00507 */ 00508 /* DFSDM Channels ------------------------------------------------------------*/ 00509 /* The DFSDM channels are defined as follows: 00510 - in 16-bit LSB the channel mask is set 00511 - in 16-bit MSB the channel number is set 00512 e.g. for channel 3 definition: 00513 - the channel mask is 0x00000008 (bit 3 is set) 00514 - the channel number 3 is 0x00030000 00515 --> Consequently, channel 3 definition is 0x00000008 | 0x00030000 = 0x00030008 */ 00516 #define DFSDM_CHANNEL_0 0x00000001U 00517 #define DFSDM_CHANNEL_1 0x00010002U 00518 #define DFSDM_CHANNEL_2 0x00020004U 00519 #define DFSDM_CHANNEL_3 0x00030008U 00520 #define DFSDM_CHANNEL_4 0x00040010U /* only for stmm32f413xx and stm32f423xx devices */ 00521 #define DFSDM_CHANNEL_5 0x00050020U /* only for stmm32f413xx and stm32f423xx devices */ 00522 #define DFSDM_CHANNEL_6 0x00060040U /* only for stmm32f413xx and stm32f423xx devices */ 00523 #define DFSDM_CHANNEL_7 0x00070080U /* only for stmm32f413xx and stm32f423xx devices */ 00524 /** 00525 * @} 00526 */ 00527 00528 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 00529 * @{ 00530 */ 00531 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ 00532 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ 00533 /** 00534 * @} 00535 */ 00536 00537 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 00538 * @{ 00539 */ 00540 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ 00541 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ 00542 /** 00543 * @} 00544 */ 00545 00546 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 00547 /** @defgroup DFSDM_1_CLOCKOUT_SELECTION DFSDM1 ClockOut Selection 00548 * @{ 00549 */ 00550 #define DFSDM1_CKOUT_DFSDM2_CKOUT 0x00000080U 00551 #define DFSDM1_CKOUT_DFSDM1 0x00000000U 00552 /** 00553 * @} 00554 */ 00555 00556 /** @defgroup DFSDM_2_CLOCKOUT_SELECTION DFSDM2 ClockOut Selection 00557 * @{ 00558 */ 00559 #define DFSDM2_CKOUT_DFSDM2_CKOUT 0x00040000U 00560 #define DFSDM2_CKOUT_DFSDM2 0x00000000U 00561 /** 00562 * @} 00563 */ 00564 00565 /** @defgroup DFSDM_1_CLOCKIN_SELECTION DFSDM1 ClockIn Selection 00566 * @{ 00567 */ 00568 #define DFSDM1_CKIN_DFSDM2_CKOUT 0x00000040U 00569 #define DFSDM1_CKIN_PAD 0x00000000U 00570 /** 00571 * @} 00572 */ 00573 00574 /** @defgroup DFSDM_2_CLOCKIN_SELECTION DFSDM2 ClockIn Selection 00575 * @{ 00576 */ 00577 #define DFSDM2_CKIN_DFSDM2_CKOUT 0x00020000U 00578 #define DFSDM2_CKIN_PAD 0x00000000U 00579 /** 00580 * @} 00581 */ 00582 00583 /** @defgroup DFSDM_1_BIT_STREAM_DISTRIBUTION DFSDM1 Bit Stream Distribution 00584 * @{ 00585 */ 00586 #define DFSDM1_T4_OC2_BITSTREAM_CKIN0 0x00000000U /* TIM4_OC2 to CLKIN0 */ 00587 #define DFSDM1_T4_OC2_BITSTREAM_CKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL /* TIM4_OC2 to CLKIN2 */ 00588 #define DFSDM1_T4_OC1_BITSTREAM_CKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL /* TIM4_OC1 to CLKIN3 */ 00589 #define DFSDM1_T4_OC1_BITSTREAM_CKIN1 0x00000000U /* TIM4_OC1 to CLKIN1 */ 00590 /** 00591 * @} 00592 */ 00593 00594 /** @defgroup DFSDM_2_BIT_STREAM_DISTRIBUTION DFSDM12 Bit Stream Distribution 00595 * @{ 00596 */ 00597 #define DFSDM2_T3_OC4_BITSTREAM_CKIN0 0x00000000U /* TIM3_OC4 to CKIN0 */ 00598 #define DFSDM2_T3_OC4_BITSTREAM_CKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL /* TIM3_OC4 to CKIN4 */ 00599 #define DFSDM2_T3_OC3_BITSTREAM_CKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL /* TIM3_OC3 to CKIN5 */ 00600 #define DFSDM2_T3_OC3_BITSTREAM_CKIN1 0x00000000U /* TIM3_OC3 to CKIN1 */ 00601 #define DFSDM2_T3_OC2_BITSTREAM_CKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL /* TIM3_OC2to CKIN6 */ 00602 #define DFSDM2_T3_OC2_BITSTREAM_CKIN2 0x00000000U /* TIM3_OC2 to CKIN2 */ 00603 #define DFSDM2_T3_OC1_BITSTREAM_CKIN3 0x00000000U /* TIM3_OC1 to CKIN3 */ 00604 #define DFSDM2_T3_OC1_BITSTREAM_CKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL /* TIM3_OC1 to CKIN7 */ 00605 /** 00606 * @} 00607 */ 00608 00609 /** @defgroup DFSDM_1_DATA_DISTRIBUTION DFSDM1 Data Distribution 00610 * @{ 00611 */ 00612 #define DFSDM1_DATIN0_TO_DATIN0_PAD 0x00000000U 00613 #define DFSDM1_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM1D0SEL 00614 #define DFSDM1_DATIN2_TO_DATIN2_PAD 0x00000000U 00615 #define DFSDM1_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM1D2SEL 00616 /** 00617 * @} 00618 */ 00619 00620 /** @defgroup DFSDM_2_DATA_DISTRIBUTION DFSDM2 Data Distribution 00621 * @{ 00622 */ 00623 #define DFSDM2_DATIN0_TO_DATIN0_PAD 0x00000000U 00624 #define DFSDM2_DATIN0_TO_DATIN1_PAD SYSCFG_MCHDLYCR_DFSDM2D0SEL 00625 #define DFSDM2_DATIN2_TO_DATIN2_PAD 0x00000000U 00626 #define DFSDM2_DATIN2_TO_DATIN3_PAD SYSCFG_MCHDLYCR_DFSDM2D2SEL 00627 #define DFSDM2_DATIN4_TO_DATIN4_PAD 0x00000000U 00628 #define DFSDM2_DATIN4_TO_DATIN5_PAD SYSCFG_MCHDLYCR_DFSDM2D4SEL 00629 #define DFSDM2_DATIN6_TO_DATIN6_PAD 0x00000000U 00630 #define DFSDM2_DATIN6_TO_DATIN7_PAD SYSCFG_MCHDLYCR_DFSDM2D6SEL 00631 /** 00632 * @} 00633 */ 00634 00635 /** @defgroup HAL_MCHDLY_CLOCK HAL MCHDLY Clock enable 00636 * @{ 00637 */ 00638 #define HAL_MCHDLY_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_MCHDLY2EN 00639 #define HAL_MCHDLY_CLOCK_DFSDM1 SYSCFG_MCHDLYCR_MCHDLY1EN 00640 /** 00641 * @} 00642 */ 00643 00644 /** @defgroup DFSDM_CLOCKIN_SOURCE DFSDM Clock In Source Selection 00645 * @{ 00646 */ 00647 #define HAL_DFSDM2_CKIN_PAD 0x00040000U 00648 #define HAL_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG 00649 #define HAL_DFSDM1_CKIN_PAD 0x00000000U 00650 #define HAL_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG 00651 /** 00652 * @} 00653 */ 00654 00655 /** @defgroup DFSDM_CLOCKOUT_SOURCE DFSDM Clock Source Selection 00656 * @{ 00657 */ 00658 #define HAL_DFSDM2_CKOUT_DFSDM2 0x10000000U 00659 #define HAL_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL 00660 #define HAL_DFSDM1_CKOUT_DFSDM1 0x00000000U 00661 #define HAL_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL 00662 /** 00663 * @} 00664 */ 00665 00666 /** @defgroup DFSDM_DATAIN0_SOURCE DFSDM Source Selection For DATAIN0 00667 * @{ 00668 */ 00669 #define HAL_DATAIN0_DFSDM2_PAD 0x10000000U 00670 #define HAL_DATAIN0_DFSDM2_DATAIN1 SYSCFG_MCHDLYCR_DFSDM2D0SEL 00671 #define HAL_DATAIN0_DFSDM1_PAD 0x00000000U 00672 #define HAL_DATAIN0_DFSDM1_DATAIN1 SYSCFG_MCHDLYCR_DFSDM1D0SEL 00673 /** 00674 * @} 00675 */ 00676 00677 /** @defgroup DFSDM_DATAIN2_SOURCE DFSDM Source Selection For DATAIN2 00678 * @{ 00679 */ 00680 #define HAL_DATAIN2_DFSDM2_PAD 0x10000000U 00681 #define HAL_DATAIN2_DFSDM2_DATAIN3 SYSCFG_MCHDLYCR_DFSDM2D2SEL 00682 #define HAL_DATAIN2_DFSDM1_PAD 0x00000000U 00683 #define HAL_DATAIN2_DFSDM1_DATAIN3 SYSCFG_MCHDLYCR_DFSDM1D2SEL 00684 /** 00685 * @} 00686 */ 00687 00688 /** @defgroup DFSDM_DATAIN4_SOURCE DFSDM Source Selection For DATAIN4 00689 * @{ 00690 */ 00691 #define HAL_DATAIN4_DFSDM2_PAD 0x00000000U 00692 #define HAL_DATAIN4_DFSDM2_DATAIN5 SYSCFG_MCHDLYCR_DFSDM2D4SEL 00693 /** 00694 * @} 00695 */ 00696 00697 /** @defgroup DFSDM_DATAIN6_SOURCE DFSDM Source Selection For DATAIN6 00698 * @{ 00699 */ 00700 #define HAL_DATAIN6_DFSDM2_PAD 0x00000000U 00701 #define HAL_DATAIN6_DFSDM2_DATAIN7 SYSCFG_MCHDLYCR_DFSDM2D6SEL 00702 /** 00703 * @} 00704 */ 00705 00706 /** @defgroup DFSDM1_CLKIN_SOURCE DFSDM1 Source Selection For CLKIN 00707 * @{ 00708 */ 00709 #define HAL_DFSDM1_CLKIN0_TIM4OC2 0x01000000U 00710 #define HAL_DFSDM1_CLKIN2_TIM4OC2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL 00711 #define HAL_DFSDM1_CLKIN1_TIM4OC1 0x02000000U 00712 #define HAL_DFSDM1_CLKIN3_TIM4OC1 SYSCFG_MCHDLYCR_DFSDM1CK13SEL 00713 /** 00714 * @} 00715 */ 00716 00717 /** @defgroup DFSDM2_CLKIN_SOURCE DFSDM2 Source Selection For CLKIN 00718 * @{ 00719 */ 00720 #define HAL_DFSDM2_CLKIN0_TIM3OC4 0x04000000U 00721 #define HAL_DFSDM2_CLKIN4_TIM3OC4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL 00722 #define HAL_DFSDM2_CLKIN1_TIM3OC3 0x08000000U 00723 #define HAL_DFSDM2_CLKIN5_TIM3OC3 SYSCFG_MCHDLYCR_DFSDM2CK15SEL 00724 #define HAL_DFSDM2_CLKIN2_TIM3OC2 0x10000000U 00725 #define HAL_DFSDM2_CLKIN6_TIM3OC2 SYSCFG_MCHDLYCR_DFSDM2CK26SEL 00726 #define HAL_DFSDM2_CLKIN3_TIM3OC1 0x00000000U 00727 #define HAL_DFSDM2_CLKIN7_TIM3OC1 SYSCFG_MCHDLYCR_DFSDM2CK37SEL 00728 /** 00729 * @} 00730 */ 00731 00732 #endif /* SYSCFG_MCHDLYCR_BSCKSEL*/ 00733 /** 00734 * @} 00735 */ 00736 /* End of exported constants -------------------------------------------------*/ 00737 00738 /* Exported macros -----------------------------------------------------------*/ 00739 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 00740 * @{ 00741 */ 00742 00743 /** @brief Reset DFSDM channel handle state. 00744 * @param __HANDLE__ DFSDM channel handle. 00745 * @retval None 00746 */ 00747 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00748 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00749 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 00750 (__HANDLE__)->MspInitCallback = NULL; \ 00751 (__HANDLE__)->MspDeInitCallback = NULL; \ 00752 } while(0) 00753 #else 00754 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 00755 #endif 00756 00757 /** @brief Reset DFSDM filter handle state. 00758 * @param __HANDLE__ DFSDM filter handle. 00759 * @retval None 00760 */ 00761 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00762 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00763 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 00764 (__HANDLE__)->MspInitCallback = NULL; \ 00765 (__HANDLE__)->MspDeInitCallback = NULL; \ 00766 } while(0) 00767 #else 00768 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 00769 #endif 00770 00771 /** 00772 * @} 00773 */ 00774 /* End of exported macros ----------------------------------------------------*/ 00775 00776 /* Exported functions --------------------------------------------------------*/ 00777 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 00778 * @{ 00779 */ 00780 00781 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 00782 * @{ 00783 */ 00784 /* Channel initialization and de-initialization functions *********************/ 00785 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00786 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00787 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00788 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00789 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00790 /* Channel callbacks register/unregister functions ****************************/ 00791 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 00792 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 00793 pDFSDM_Channel_CallbackTypeDef pCallback); 00794 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 00795 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 00796 #endif 00797 /** 00798 * @} 00799 */ 00800 00801 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 00802 * @{ 00803 */ 00804 /* Channel operation functions ************************************************/ 00805 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00806 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00807 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00808 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00809 00810 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 00811 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 00812 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00813 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00814 00815 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00816 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 00817 00818 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 00819 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 00820 00821 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00822 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00823 /** 00824 * @} 00825 */ 00826 00827 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 00828 * @{ 00829 */ 00830 /* Channel state function *****************************************************/ 00831 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00832 /** 00833 * @} 00834 */ 00835 00836 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 00837 * @{ 00838 */ 00839 /* Filter initialization and de-initialization functions *********************/ 00840 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00841 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00842 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00843 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00844 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00845 /* Filter callbacks register/unregister functions ****************************/ 00846 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00847 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 00848 pDFSDM_Filter_CallbackTypeDef pCallback); 00849 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00850 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 00851 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00852 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 00853 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00854 #endif 00855 /** 00856 * @} 00857 */ 00858 00859 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 00860 * @{ 00861 */ 00862 /* Filter control functions *********************/ 00863 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00864 uint32_t Channel, 00865 uint32_t ContinuousMode); 00866 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00867 uint32_t Channel); 00868 /** 00869 * @} 00870 */ 00871 00872 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 00873 * @{ 00874 */ 00875 /* Filter operation functions *********************/ 00876 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00877 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00878 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 00879 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 00880 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00881 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00882 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00883 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00884 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00885 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 00886 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 00887 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00888 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00889 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00890 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00891 DFSDM_Filter_AwdParamTypeDef* awdParam); 00892 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00893 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 00894 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00895 00896 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00897 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00898 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00899 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel); 00900 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00901 00902 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00903 00904 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 00905 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 00906 00907 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00908 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00909 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00910 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00911 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 00912 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00913 /** 00914 * @} 00915 */ 00916 00917 /** @addtogroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 00918 * @{ 00919 */ 00920 /* Filter state functions *****************************************************/ 00921 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00922 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00923 /** 00924 * @} 00925 */ 00926 /** @addtogroup DFSDM_Exported_Functions_Group5_Filter MultiChannel operation functions 00927 * @{ 00928 */ 00929 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 00930 void HAL_DFSDM_ConfigMultiChannelDelay(DFSDM_MultiChannelConfigTypeDef* mchdlystruct); 00931 void HAL_DFSDM_BitstreamClock_Start(void); 00932 void HAL_DFSDM_BitstreamClock_Stop(void); 00933 void HAL_DFSDM_DisableDelayClock(uint32_t MCHDLY); 00934 void HAL_DFSDM_EnableDelayClock(uint32_t MCHDLY); 00935 void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source); 00936 void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source); 00937 void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source); 00938 void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source); 00939 void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source); 00940 void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source); 00941 void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source); 00942 #endif /* SYSCFG_MCHDLYCR_BSCKSEL */ 00943 /** 00944 * @} 00945 */ 00946 /** 00947 * @} 00948 */ 00949 /* End of exported functions -------------------------------------------------*/ 00950 00951 /* Private macros ------------------------------------------------------------*/ 00952 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 00953 * @{ 00954 */ 00955 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 00956 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 00957 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) 00958 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 00959 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 00960 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 00961 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 00962 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 00963 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 00964 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 00965 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 00966 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 00967 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 00968 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 00969 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 00970 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 00971 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 00972 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 00973 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 00974 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 00975 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 00976 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 00977 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) 00978 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 00979 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) 00980 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) 00981 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 00982 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 00983 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 00984 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 00985 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 00986 #if defined (STM32F413xx) || defined (STM32F423xx) 00987 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 00988 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 00989 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 00990 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ 00991 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM2_TRGO) || \ 00992 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 00993 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM11_OC1) || \ 00994 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 00995 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 00996 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 00997 #define IS_DFSDM_DELAY_CLOCK(CLOCK) (((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM2) || \ 00998 ((CLOCK) == HAL_MCHDLY_CLOCK_DFSDM1)) 00999 #else 01000 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 01001 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 01002 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 01003 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \ 01004 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 01005 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 01006 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 01007 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 01008 #endif 01009 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 01010 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 01011 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 01012 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 01013 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 01014 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 01015 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 01016 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 01017 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 01018 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) 01019 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) 01020 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 01021 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 01022 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 01023 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0x0FU) 01024 #if defined(DFSDM2_Channel0) 01025 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 01026 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 01027 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 01028 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 01029 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 01030 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 01031 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 01032 ((CHANNEL) == DFSDM_CHANNEL_7)) 01033 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) 01034 #else 01035 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 01036 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 01037 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 01038 ((CHANNEL) == DFSDM_CHANNEL_3)) 01039 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) 01040 #endif 01041 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 01042 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 01043 #if defined(DFSDM2_Channel0) 01044 #define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \ 01045 ((INSTANCE) == DFSDM1_Channel1) || \ 01046 ((INSTANCE) == DFSDM1_Channel2) || \ 01047 ((INSTANCE) == DFSDM1_Channel3)) 01048 #define IS_DFSDM1_FILTER_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \ 01049 ((INSTANCE) == DFSDM1_Filter1)) 01050 #endif /* DFSDM2_Channel0 */ 01051 01052 #if defined(SYSCFG_MCHDLYCR_BSCKSEL) 01053 #define IS_DFSDM_CLOCKIN_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKIN_PAD) || \ 01054 ((SELECTION) == HAL_DFSDM2_CKIN_DM) || \ 01055 ((SELECTION) == HAL_DFSDM1_CKIN_PAD) || \ 01056 ((SELECTION) == HAL_DFSDM1_CKIN_DM)) 01057 #define IS_DFSDM_CLOCKOUT_SELECTION(SELECTION) (((SELECTION) == HAL_DFSDM2_CKOUT_DFSDM2) || \ 01058 ((SELECTION) == HAL_DFSDM2_CKOUT_M27) || \ 01059 ((SELECTION) == HAL_DFSDM1_CKOUT_DFSDM1) || \ 01060 ((SELECTION) == HAL_DFSDM1_CKOUT_M27)) 01061 #define IS_DFSDM_DATAIN0_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN0_DFSDM2_PAD) || \ 01062 ((SELECTION) == HAL_DATAIN0_DFSDM2_DATAIN1) || \ 01063 ((SELECTION) == HAL_DATAIN0_DFSDM1_PAD) || \ 01064 ((SELECTION) == HAL_DATAIN0_DFSDM1_DATAIN1)) 01065 #define IS_DFSDM_DATAIN2_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN2_DFSDM2_PAD) || \ 01066 ((SELECTION) == HAL_DATAIN2_DFSDM2_DATAIN3) || \ 01067 ((SELECTION) == HAL_DATAIN2_DFSDM1_PAD) || \ 01068 ((SELECTION) == HAL_DATAIN2_DFSDM1_DATAIN3)) 01069 #define IS_DFSDM_DATAIN4_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN4_DFSDM2_PAD) || \ 01070 ((SELECTION) == HAL_DATAIN4_DFSDM2_DATAIN5)) 01071 #define IS_DFSDM_DATAIN6_SRC_SELECTION(SELECTION) (((SELECTION) == HAL_DATAIN6_DFSDM2_PAD) || \ 01072 ((SELECTION) == HAL_DATAIN6_DFSDM2_DATAIN7)) 01073 #define IS_DFSDM_BITSTREM_CLK_DISTRIBUTION(DISTRIBUTION) (((DISTRIBUTION) == HAL_DFSDM1_CLKIN0_TIM4OC2) || \ 01074 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN2_TIM4OC2) || \ 01075 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN1_TIM4OC1) || \ 01076 ((DISTRIBUTION) == HAL_DFSDM1_CLKIN3_TIM4OC1) || \ 01077 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN0_TIM3OC4) || \ 01078 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN4_TIM3OC4) || \ 01079 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN1_TIM3OC3)|| \ 01080 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN5_TIM3OC3) || \ 01081 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN2_TIM3OC2) || \ 01082 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN6_TIM3OC2) || \ 01083 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN3_TIM3OC1)|| \ 01084 ((DISTRIBUTION) == HAL_DFSDM2_CLKIN7_TIM3OC1)) 01085 #define IS_DFSDM_DFSDM1_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM1_CKOUT_DFSDM2_CKOUT) || \ 01086 ((CLKOUT) == DFSDM1_CKOUT_DFSDM1)) 01087 #define IS_DFSDM_DFSDM2_CLKOUT(CLKOUT) (((CLKOUT) == DFSDM2_CKOUT_DFSDM2_CKOUT) || \ 01088 ((CLKOUT) == DFSDM2_CKOUT_DFSDM2)) 01089 #define IS_DFSDM_DFSDM1_CLKIN(CLKIN) (((CLKIN) == DFSDM1_CKIN_DFSDM2_CKOUT) || \ 01090 ((CLKIN) == DFSDM1_CKIN_PAD)) 01091 #define IS_DFSDM_DFSDM2_CLKIN(CLKIN) (((CLKIN) == DFSDM2_CKIN_DFSDM2_CKOUT) || \ 01092 ((CLKIN) == DFSDM2_CKIN_PAD)) 01093 #define IS_DFSDM_DFSDM1_BIT_CLK(CLK) (((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN0) || \ 01094 ((CLK) == DFSDM1_T4_OC2_BITSTREAM_CKIN2) || \ 01095 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN3) || \ 01096 ((CLK) == DFSDM1_T4_OC1_BITSTREAM_CKIN1) || \ 01097 ((CLK) <= 0x30U)) 01098 01099 #define IS_DFSDM_DFSDM2_BIT_CLK(CLK) (((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN0) || \ 01100 ((CLK) == DFSDM2_T3_OC4_BITSTREAM_CKIN4) || \ 01101 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN5) || \ 01102 ((CLK) == DFSDM2_T3_OC3_BITSTREAM_CKIN1) || \ 01103 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN6) || \ 01104 ((CLK) == DFSDM2_T3_OC2_BITSTREAM_CKIN2) || \ 01105 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN3) || \ 01106 ((CLK) == DFSDM2_T3_OC1_BITSTREAM_CKIN7)|| \ 01107 ((CLK) <= 0x1E000U)) 01108 01109 #define IS_DFSDM_DFSDM1_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN0_PAD )|| \ 01110 ((DISTRIBUTION) == DFSDM1_DATIN0_TO_DATIN1_PAD) || \ 01111 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN2_PAD) || \ 01112 ((DISTRIBUTION) == DFSDM1_DATIN2_TO_DATIN3_PAD)|| \ 01113 ((DISTRIBUTION) <= 0xCU)) 01114 01115 #define IS_DFSDM_DFSDM2_DATA_DISTRIBUTION(DISTRIBUTION)(((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN0_PAD)|| \ 01116 ((DISTRIBUTION) == DFSDM2_DATIN0_TO_DATIN1_PAD)|| \ 01117 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN2_PAD)|| \ 01118 ((DISTRIBUTION) == DFSDM2_DATIN2_TO_DATIN3_PAD)|| \ 01119 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN4_PAD)|| \ 01120 ((DISTRIBUTION) == DFSDM2_DATIN4_TO_DATIN5_PAD)|| \ 01121 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN6_PAD)|| \ 01122 ((DISTRIBUTION) == DFSDM2_DATIN6_TO_DATIN7_PAD)|| \ 01123 ((DISTRIBUTION) <= 0x1D00U)) 01124 #endif /* (SYSCFG_MCHDLYCR_BSCKSEL) */ 01125 /** 01126 * @} 01127 */ 01128 /* End of private macros -----------------------------------------------------*/ 01129 01130 /** 01131 * @} 01132 */ 01133 01134 /** 01135 * @} 01136 */ 01137 #endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 01138 #ifdef __cplusplus 01139 } 01140 #endif 01141 01142 #endif /* __STM32F4xx_HAL_DFSDM_H */ 01143 01144 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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