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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dma2d.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA2D HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F4xx_HAL_DMA2D_H 00022 #define STM32F4xx_HAL_DMA2D_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx_hal_def.h" 00030 00031 /** @addtogroup STM32F4xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (DMA2D) 00036 00037 /** @addtogroup DMA2D DMA2D 00038 * @brief DMA2D HAL module driver 00039 * @{ 00040 */ 00041 00042 /* Exported types ------------------------------------------------------------*/ 00043 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 00044 * @{ 00045 */ 00046 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 00047 00048 /** 00049 * @brief DMA2D CLUT Structure definition 00050 */ 00051 typedef struct 00052 { 00053 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 00054 00055 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 00056 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 00057 00058 uint32_t Size; /*!< Configures the DMA2D CLUT size. 00059 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 00060 } DMA2D_CLUTCfgTypeDef; 00061 00062 /** 00063 * @brief DMA2D Init structure definition 00064 */ 00065 typedef struct 00066 { 00067 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 00068 This parameter can be one value of @ref DMA2D_Mode. */ 00069 00070 uint32_t ColorMode; /*!< Configures the color format of the output image. 00071 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 00072 00073 uint32_t OutputOffset; /*!< Specifies the Offset value. 00074 This parameter must be a number between 00075 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00076 00077 00078 00079 00080 } DMA2D_InitTypeDef; 00081 00082 00083 /** 00084 * @brief DMA2D Layer structure definition 00085 */ 00086 typedef struct 00087 { 00088 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 00089 This parameter must be a number between 00090 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00091 00092 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 00093 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 00094 00095 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 00096 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 00097 00098 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 00099 in case of A8 or A4 color mode. 00100 This parameter must be a number between Min_Data = 0x00 00101 and Max_Data = 0xFF except for the color modes detailed below. 00102 @note In case of A8 or A4 color mode (ARGB), 00103 this parameter must be a number between 00104 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 00105 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 00106 - InputAlpha[16:23] is the red value RED[0:7] 00107 - InputAlpha[8:15] is the green value GREEN[0:7] 00108 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 00109 00110 00111 } DMA2D_LayerCfgTypeDef; 00112 00113 /** 00114 * @brief HAL DMA2D State structures definition 00115 */ 00116 typedef enum 00117 { 00118 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 00119 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00120 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00121 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00122 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 00123 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 00124 } HAL_DMA2D_StateTypeDef; 00125 00126 /** 00127 * @brief DMA2D handle Structure definition 00128 */ 00129 typedef struct __DMA2D_HandleTypeDef 00130 { 00131 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 00132 00133 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 00134 00135 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 00136 00137 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 00138 00139 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00140 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 00141 00142 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 00143 00144 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 00145 00146 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 00147 00148 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 00149 00150 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 00151 00152 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 00153 00154 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 00155 00156 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 00157 } DMA2D_HandleTypeDef; 00158 00159 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00160 /** 00161 * @brief HAL DMA2D Callback pointer definition 00162 */ 00163 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 00164 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00165 /** 00166 * @} 00167 */ 00168 00169 /* Exported constants --------------------------------------------------------*/ 00170 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 00171 * @{ 00172 */ 00173 00174 /** @defgroup DMA2D_Error_Code DMA2D Error Code 00175 * @{ 00176 */ 00177 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 00178 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 00179 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 00180 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 00181 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00182 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00183 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 00184 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 00185 00186 /** 00187 * @} 00188 */ 00189 00190 /** @defgroup DMA2D_Mode DMA2D Mode 00191 * @{ 00192 */ 00193 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 00194 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 00195 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 00196 #define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */ 00197 /** 00198 * @} 00199 */ 00200 00201 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 00202 * @{ 00203 */ 00204 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 00205 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 00206 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 00207 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 00208 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 00209 /** 00210 * @} 00211 */ 00212 00213 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 00214 * @{ 00215 */ 00216 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 00217 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 00218 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 00219 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 00220 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 00221 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 00222 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 00223 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 00224 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 00225 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 00226 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 00232 * @{ 00233 */ 00234 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 00235 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 00236 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 00237 with original alpha channel value */ 00238 /** 00239 * @} 00240 */ 00241 00242 00243 00244 00245 00246 00247 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 00248 * @{ 00249 */ 00250 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 00251 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 00252 /** 00253 * @} 00254 */ 00255 00256 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 00257 * @{ 00258 */ 00259 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 00260 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 00261 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 00262 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 00263 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 00264 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 00265 /** 00266 * @} 00267 */ 00268 00269 /** @defgroup DMA2D_Flags DMA2D Flags 00270 * @{ 00271 */ 00272 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 00273 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 00274 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 00275 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 00276 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 00277 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 00278 /** 00279 * @} 00280 */ 00281 00282 /** @defgroup DMA2D_Aliases DMA2D API Aliases 00283 * @{ 00284 */ 00285 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort 00286 for compatibility with legacy code */ 00287 /** 00288 * @} 00289 */ 00290 00291 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00292 /** 00293 * @brief HAL DMA2D common Callback ID enumeration definition 00294 */ 00295 typedef enum 00296 { 00297 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 00298 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 00299 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 00300 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 00301 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 00302 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 00303 } HAL_DMA2D_CallbackIDTypeDef; 00304 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00305 00306 00307 /** 00308 * @} 00309 */ 00310 /* Exported macros ------------------------------------------------------------*/ 00311 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 00312 * @{ 00313 */ 00314 00315 /** @brief Reset DMA2D handle state 00316 * @param __HANDLE__ specifies the DMA2D handle. 00317 * @retval None 00318 */ 00319 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00320 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00321 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 00322 (__HANDLE__)->MspInitCallback = NULL; \ 00323 (__HANDLE__)->MspDeInitCallback = NULL; \ 00324 }while(0) 00325 #else 00326 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 00327 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00328 00329 00330 /** 00331 * @brief Enable the DMA2D. 00332 * @param __HANDLE__ DMA2D handle 00333 * @retval None. 00334 */ 00335 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 00336 00337 00338 /* Interrupt & Flag management */ 00339 /** 00340 * @brief Get the DMA2D pending flags. 00341 * @param __HANDLE__ DMA2D handle 00342 * @param __FLAG__ flag to check. 00343 * This parameter can be any combination of the following values: 00344 * @arg DMA2D_FLAG_CE: Configuration error flag 00345 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00346 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00347 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00348 * @arg DMA2D_FLAG_TC: Transfer complete flag 00349 * @arg DMA2D_FLAG_TE: Transfer error flag 00350 * @retval The state of FLAG. 00351 */ 00352 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 00353 00354 /** 00355 * @brief Clear the DMA2D pending flags. 00356 * @param __HANDLE__ DMA2D handle 00357 * @param __FLAG__ specifies the flag to clear. 00358 * This parameter can be any combination of the following values: 00359 * @arg DMA2D_FLAG_CE: Configuration error flag 00360 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00361 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00362 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00363 * @arg DMA2D_FLAG_TC: Transfer complete flag 00364 * @arg DMA2D_FLAG_TE: Transfer error flag 00365 * @retval None 00366 */ 00367 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 00368 00369 /** 00370 * @brief Enable the specified DMA2D interrupts. 00371 * @param __HANDLE__ DMA2D handle 00372 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 00373 * This parameter can be any combination of the following values: 00374 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00375 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00376 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00377 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00378 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00379 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00380 * @retval None 00381 */ 00382 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 00383 00384 /** 00385 * @brief Disable the specified DMA2D interrupts. 00386 * @param __HANDLE__ DMA2D handle 00387 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 00388 * This parameter can be any combination of the following values: 00389 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00390 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00391 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00392 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00393 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00394 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00395 * @retval None 00396 */ 00397 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 00398 00399 /** 00400 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 00401 * @param __HANDLE__ DMA2D handle 00402 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 00403 * This parameter can be one of the following values: 00404 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00405 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00406 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00407 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00408 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00409 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00410 * @retval The state of INTERRUPT source. 00411 */ 00412 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 00413 00414 /** 00415 * @} 00416 */ 00417 00418 /* Exported functions --------------------------------------------------------*/ 00419 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 00420 * @{ 00421 */ 00422 00423 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 00424 * @{ 00425 */ 00426 00427 /* Initialization and de-initialization functions *******************************/ 00428 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 00429 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 00430 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 00431 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 00432 /* Callbacks Register/UnRegister functions ***********************************/ 00433 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00434 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 00435 pDMA2D_CallbackTypeDef pCallback); 00436 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 00437 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00438 00439 /** 00440 * @} 00441 */ 00442 00443 00444 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 00445 * @{ 00446 */ 00447 00448 /* IO operation functions *******************************************************/ 00449 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 00450 uint32_t Height); 00451 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 00452 uint32_t DstAddress, uint32_t Width, uint32_t Height); 00453 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 00454 uint32_t Height); 00455 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 00456 uint32_t DstAddress, uint32_t Width, uint32_t Height); 00457 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 00458 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 00459 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 00460 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00461 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 00462 uint32_t LayerIdx); 00463 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 00464 uint32_t LayerIdx); 00465 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00466 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00467 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00468 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00469 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00470 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 00471 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 00472 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 00473 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 00474 00475 /** 00476 * @} 00477 */ 00478 00479 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 00480 * @{ 00481 */ 00482 00483 /* Peripheral Control functions *************************************************/ 00484 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00485 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00486 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 00487 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00488 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00489 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 00490 00491 /** 00492 * @} 00493 */ 00494 00495 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 00496 * @{ 00497 */ 00498 00499 /* Peripheral State functions ***************************************************/ 00500 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 00501 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 00502 00503 /** 00504 * @} 00505 */ 00506 00507 /** 00508 * @} 00509 */ 00510 00511 /* Private constants ---------------------------------------------------------*/ 00512 00513 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 00514 * @{ 00515 */ 00516 00517 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 00518 * @{ 00519 */ 00520 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 00521 /** 00522 * @} 00523 */ 00524 00525 /** @defgroup DMA2D_Color_Value DMA2D Color Value 00526 * @{ 00527 */ 00528 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 00529 /** 00530 * @} 00531 */ 00532 00533 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 00534 * @{ 00535 */ 00536 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 00537 /** 00538 * @} 00539 */ 00540 00541 /** @defgroup DMA2D_Layers DMA2D Layers 00542 * @{ 00543 */ 00544 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 00545 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 00546 /** 00547 * @} 00548 */ 00549 00550 /** @defgroup DMA2D_Offset DMA2D Offset 00551 * @{ 00552 */ 00553 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 00554 /** 00555 * @} 00556 */ 00557 00558 /** @defgroup DMA2D_Size DMA2D Size 00559 * @{ 00560 */ 00561 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 00562 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 00563 /** 00564 * @} 00565 */ 00566 00567 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 00568 * @{ 00569 */ 00570 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 00571 /** 00572 * @} 00573 */ 00574 00575 /** 00576 * @} 00577 */ 00578 00579 00580 /* Private macros ------------------------------------------------------------*/ 00581 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 00582 * @{ 00583 */ 00584 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 00585 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 00586 00587 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 00588 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 00589 00590 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 00591 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 00592 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 00593 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 00594 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 00595 00596 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 00597 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 00598 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 00599 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 00600 00601 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 00602 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 00603 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 00604 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 00605 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 00606 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 00607 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 00608 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 00609 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 00610 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 00611 ((INPUT_CM) == DMA2D_INPUT_A4)) 00612 00613 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 00614 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 00615 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 00616 00617 00618 00619 00620 00621 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 00622 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 00623 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 00624 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 00625 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 00626 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 00627 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 00628 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 00629 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 00630 /** 00631 * @} 00632 */ 00633 00634 /** 00635 * @} 00636 */ 00637 00638 #endif /* defined (DMA2D) */ 00639 00640 /** 00641 * @} 00642 */ 00643 00644 #ifdef __cplusplus 00645 } 00646 #endif 00647 00648 #endif /* STM32F4xx_HAL_DMA2D_H */ 00649 00650 00651 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1