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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F4xx_HAL_DMA_H 00022 #define __STM32F4xx_HAL_DMA_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx_hal_def.h" 00030 00031 /** @addtogroup STM32F4xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup DMA 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 00041 /** @defgroup DMA_Exported_Types DMA Exported Types 00042 * @brief DMA Exported Types 00043 * @{ 00044 */ 00045 00046 /** 00047 * @brief DMA Configuration Structure definition 00048 */ 00049 typedef struct 00050 { 00051 uint32_t Channel; /*!< Specifies the channel used for the specified stream. 00052 This parameter can be a value of @ref DMA_Channel_selection */ 00053 00054 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00055 from memory to memory or from peripheral to memory. 00056 This parameter can be a value of @ref DMA_Data_transfer_direction */ 00057 00058 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 00059 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 00060 00061 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 00062 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 00063 00064 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 00065 This parameter can be a value of @ref DMA_Peripheral_data_size */ 00066 00067 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 00068 This parameter can be a value of @ref DMA_Memory_data_size */ 00069 00070 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx. 00071 This parameter can be a value of @ref DMA_mode 00072 @note The circular buffer mode cannot be used if the memory-to-memory 00073 data transfer is configured on the selected Stream */ 00074 00075 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx. 00076 This parameter can be a value of @ref DMA_Priority_level */ 00077 00078 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 00079 This parameter can be a value of @ref DMA_FIFO_direct_mode 00080 @note The Direct mode (FIFO mode disabled) cannot be used if the 00081 memory-to-memory data transfer is configured on the selected stream */ 00082 00083 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 00084 This parameter can be a value of @ref DMA_FIFO_threshold_level */ 00085 00086 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 00087 It specifies the amount of data to be transferred in a single non interruptible 00088 transaction. 00089 This parameter can be a value of @ref DMA_Memory_burst 00090 @note The burst mode is possible only if the address Increment mode is enabled. */ 00091 00092 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 00093 It specifies the amount of data to be transferred in a single non interruptible 00094 transaction. 00095 This parameter can be a value of @ref DMA_Peripheral_burst 00096 @note The burst mode is possible only if the address Increment mode is enabled. */ 00097 }DMA_InitTypeDef; 00098 00099 00100 /** 00101 * @brief HAL DMA State structures definition 00102 */ 00103 typedef enum 00104 { 00105 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 00106 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 00107 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 00108 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 00109 HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */ 00110 HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */ 00111 }HAL_DMA_StateTypeDef; 00112 00113 /** 00114 * @brief HAL DMA Error Code structure definition 00115 */ 00116 typedef enum 00117 { 00118 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 00119 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 00120 }HAL_DMA_LevelCompleteTypeDef; 00121 00122 /** 00123 * @brief HAL DMA Error Code structure definition 00124 */ 00125 typedef enum 00126 { 00127 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 00128 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */ 00129 HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */ 00130 HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */ 00131 HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */ 00132 HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */ 00133 HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */ 00134 }HAL_DMA_CallbackIDTypeDef; 00135 00136 /** 00137 * @brief DMA handle Structure definition 00138 */ 00139 typedef struct __DMA_HandleTypeDef 00140 { 00141 DMA_Stream_TypeDef *Instance; /*!< Register base address */ 00142 00143 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 00144 00145 HAL_LockTypeDef Lock; /*!< DMA locking object */ 00146 00147 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 00148 00149 void *Parent; /*!< Parent object state */ 00150 00151 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 00152 00153 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 00154 00155 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */ 00156 00157 void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */ 00158 00159 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 00160 00161 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */ 00162 00163 __IO uint32_t ErrorCode; /*!< DMA Error code */ 00164 00165 uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */ 00166 00167 uint32_t StreamIndex; /*!< DMA Stream Index */ 00168 00169 }DMA_HandleTypeDef; 00170 00171 /** 00172 * @} 00173 */ 00174 00175 /* Exported constants --------------------------------------------------------*/ 00176 00177 /** @defgroup DMA_Exported_Constants DMA Exported Constants 00178 * @brief DMA Exported constants 00179 * @{ 00180 */ 00181 00182 /** @defgroup DMA_Error_Code DMA Error Code 00183 * @brief DMA Error Code 00184 * @{ 00185 */ 00186 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 00187 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 00188 #define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */ 00189 #define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */ 00190 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00191 #define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */ 00192 #define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */ 00193 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup DMA_Channel_selection DMA Channel selection 00199 * @brief DMA channel selection 00200 * @{ 00201 */ 00202 #define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ 00203 #define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */ 00204 #define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */ 00205 #define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */ 00206 #define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */ 00207 #define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */ 00208 #define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */ 00209 #define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */ 00210 #if defined (DMA_SxCR_CHSEL_3) 00211 #define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */ 00212 #define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */ 00213 #define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10 */ 00214 #define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11 */ 00215 #define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12 */ 00216 #define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13 */ 00217 #define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14 */ 00218 #define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15 */ 00219 #endif /* DMA_SxCR_CHSEL_3 */ 00220 /** 00221 * @} 00222 */ 00223 00224 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 00225 * @brief DMA data transfer direction 00226 * @{ 00227 */ 00228 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00229 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */ 00230 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */ 00231 /** 00232 * @} 00233 */ 00234 00235 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 00236 * @brief DMA peripheral incremented mode 00237 * @{ 00238 */ 00239 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */ 00240 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */ 00241 /** 00242 * @} 00243 */ 00244 00245 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 00246 * @brief DMA memory incremented mode 00247 * @{ 00248 */ 00249 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */ 00250 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */ 00251 /** 00252 * @} 00253 */ 00254 00255 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 00256 * @brief DMA peripheral data size 00257 * @{ 00258 */ 00259 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */ 00260 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */ 00261 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */ 00262 /** 00263 * @} 00264 */ 00265 00266 /** @defgroup DMA_Memory_data_size DMA Memory data size 00267 * @brief DMA memory data size 00268 * @{ 00269 */ 00270 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */ 00271 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */ 00272 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */ 00273 /** 00274 * @} 00275 */ 00276 00277 /** @defgroup DMA_mode DMA mode 00278 * @brief DMA mode 00279 * @{ 00280 */ 00281 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 00282 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */ 00283 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */ 00284 /** 00285 * @} 00286 */ 00287 00288 /** @defgroup DMA_Priority_level DMA Priority level 00289 * @brief DMA priority levels 00290 * @{ 00291 */ 00292 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */ 00293 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */ 00294 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */ 00295 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */ 00296 /** 00297 * @} 00298 */ 00299 00300 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode 00301 * @brief DMA FIFO direct mode 00302 * @{ 00303 */ 00304 #define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ 00305 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */ 00306 /** 00307 * @} 00308 */ 00309 00310 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level 00311 * @brief DMA FIFO level 00312 * @{ 00313 */ 00314 #define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 00315 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */ 00316 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */ 00317 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */ 00318 /** 00319 * @} 00320 */ 00321 00322 /** @defgroup DMA_Memory_burst DMA Memory burst 00323 * @brief DMA memory burst 00324 * @{ 00325 */ 00326 #define DMA_MBURST_SINGLE 0x00000000U 00327 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0) 00328 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1) 00329 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST) 00330 /** 00331 * @} 00332 */ 00333 00334 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst 00335 * @brief DMA peripheral burst 00336 * @{ 00337 */ 00338 #define DMA_PBURST_SINGLE 0x00000000U 00339 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0) 00340 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1) 00341 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST) 00342 /** 00343 * @} 00344 */ 00345 00346 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 00347 * @brief DMA interrupts definition 00348 * @{ 00349 */ 00350 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE) 00351 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE) 00352 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE) 00353 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE) 00354 #define DMA_IT_FE 0x00000080U 00355 /** 00356 * @} 00357 */ 00358 00359 /** @defgroup DMA_flag_definitions DMA flag definitions 00360 * @brief DMA flag definitions 00361 * @{ 00362 */ 00363 #define DMA_FLAG_FEIF0_4 0x00000001U 00364 #define DMA_FLAG_DMEIF0_4 0x00000004U 00365 #define DMA_FLAG_TEIF0_4 0x00000008U 00366 #define DMA_FLAG_HTIF0_4 0x00000010U 00367 #define DMA_FLAG_TCIF0_4 0x00000020U 00368 #define DMA_FLAG_FEIF1_5 0x00000040U 00369 #define DMA_FLAG_DMEIF1_5 0x00000100U 00370 #define DMA_FLAG_TEIF1_5 0x00000200U 00371 #define DMA_FLAG_HTIF1_5 0x00000400U 00372 #define DMA_FLAG_TCIF1_5 0x00000800U 00373 #define DMA_FLAG_FEIF2_6 0x00010000U 00374 #define DMA_FLAG_DMEIF2_6 0x00040000U 00375 #define DMA_FLAG_TEIF2_6 0x00080000U 00376 #define DMA_FLAG_HTIF2_6 0x00100000U 00377 #define DMA_FLAG_TCIF2_6 0x00200000U 00378 #define DMA_FLAG_FEIF3_7 0x00400000U 00379 #define DMA_FLAG_DMEIF3_7 0x01000000U 00380 #define DMA_FLAG_TEIF3_7 0x02000000U 00381 #define DMA_FLAG_HTIF3_7 0x04000000U 00382 #define DMA_FLAG_TCIF3_7 0x08000000U 00383 /** 00384 * @} 00385 */ 00386 00387 /** 00388 * @} 00389 */ 00390 00391 /* Exported macro ------------------------------------------------------------*/ 00392 00393 /** @brief Reset DMA handle state 00394 * @param __HANDLE__ specifies the DMA handle. 00395 * @retval None 00396 */ 00397 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 00398 00399 /** 00400 * @brief Return the current DMA Stream FIFO filled level. 00401 * @param __HANDLE__ DMA handle 00402 * @retval The FIFO filling state. 00403 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 00404 * and not empty. 00405 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full. 00406 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full. 00407 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full. 00408 * - DMA_FIFOStatus_Empty: when FIFO is empty 00409 * - DMA_FIFOStatus_Full: when FIFO is full 00410 */ 00411 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS))) 00412 00413 /** 00414 * @brief Enable the specified DMA Stream. 00415 * @param __HANDLE__ DMA handle 00416 * @retval None 00417 */ 00418 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN) 00419 00420 /** 00421 * @brief Disable the specified DMA Stream. 00422 * @param __HANDLE__ DMA handle 00423 * @retval None 00424 */ 00425 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN) 00426 00427 /* Interrupt & Flag management */ 00428 00429 /** 00430 * @brief Return the current DMA Stream transfer complete flag. 00431 * @param __HANDLE__ DMA handle 00432 * @retval The specified transfer complete flag index. 00433 */ 00434 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 00435 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\ 00436 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\ 00437 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\ 00438 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\ 00439 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\ 00440 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\ 00441 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\ 00442 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\ 00443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\ 00444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\ 00445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\ 00446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\ 00447 DMA_FLAG_TCIF3_7) 00448 00449 /** 00450 * @brief Return the current DMA Stream half transfer complete flag. 00451 * @param __HANDLE__ DMA handle 00452 * @retval The specified half transfer complete flag index. 00453 */ 00454 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 00455 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\ 00456 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\ 00457 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\ 00458 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\ 00459 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\ 00460 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\ 00461 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\ 00462 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\ 00463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\ 00464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\ 00465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\ 00466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\ 00467 DMA_FLAG_HTIF3_7) 00468 00469 /** 00470 * @brief Return the current DMA Stream transfer error flag. 00471 * @param __HANDLE__ DMA handle 00472 * @retval The specified transfer error flag index. 00473 */ 00474 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 00475 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\ 00476 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\ 00477 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\ 00478 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\ 00479 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\ 00480 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\ 00481 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\ 00482 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\ 00483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\ 00484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\ 00485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\ 00486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\ 00487 DMA_FLAG_TEIF3_7) 00488 00489 /** 00490 * @brief Return the current DMA Stream FIFO error flag. 00491 * @param __HANDLE__ DMA handle 00492 * @retval The specified FIFO error flag index. 00493 */ 00494 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\ 00495 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\ 00496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\ 00497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\ 00498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\ 00499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\ 00500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\ 00501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\ 00502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\ 00503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\ 00504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\ 00505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\ 00506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\ 00507 DMA_FLAG_FEIF3_7) 00508 00509 /** 00510 * @brief Return the current DMA Stream direct mode error flag. 00511 * @param __HANDLE__ DMA handle 00512 * @retval The specified direct mode error flag index. 00513 */ 00514 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\ 00515 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\ 00516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\ 00517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\ 00518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\ 00519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\ 00520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\ 00521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\ 00522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\ 00523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\ 00524 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\ 00525 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\ 00526 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\ 00527 DMA_FLAG_DMEIF3_7) 00528 00529 /** 00530 * @brief Get the DMA Stream pending flags. 00531 * @param __HANDLE__ DMA handle 00532 * @param __FLAG__ Get the specified flag. 00533 * This parameter can be any combination of the following values: 00534 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 00535 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 00536 * @arg DMA_FLAG_TEIFx: Transfer error flag. 00537 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 00538 * @arg DMA_FLAG_FEIFx: FIFO error flag. 00539 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 00540 * @retval The state of FLAG (SET or RESET). 00541 */ 00542 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\ 00543 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\ 00544 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\ 00545 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__))) 00546 00547 /** 00548 * @brief Clear the DMA Stream pending flags. 00549 * @param __HANDLE__ DMA handle 00550 * @param __FLAG__ specifies the flag to clear. 00551 * This parameter can be any combination of the following values: 00552 * @arg DMA_FLAG_TCIFx: Transfer complete flag. 00553 * @arg DMA_FLAG_HTIFx: Half transfer complete flag. 00554 * @arg DMA_FLAG_TEIFx: Transfer error flag. 00555 * @arg DMA_FLAG_DMEIFx: Direct mode error flag. 00556 * @arg DMA_FLAG_FEIFx: FIFO error flag. 00557 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag. 00558 * @retval None 00559 */ 00560 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 00561 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\ 00562 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\ 00563 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__))) 00564 00565 /** 00566 * @brief Enable the specified DMA Stream interrupts. 00567 * @param __HANDLE__ DMA handle 00568 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 00569 * This parameter can be any combination of the following values: 00570 * @arg DMA_IT_TC: Transfer complete interrupt mask. 00571 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 00572 * @arg DMA_IT_TE: Transfer error interrupt mask. 00573 * @arg DMA_IT_FE: FIFO error interrupt mask. 00574 * @arg DMA_IT_DME: Direct mode error interrupt. 00575 * @retval None 00576 */ 00577 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 00578 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__))) 00579 00580 /** 00581 * @brief Disable the specified DMA Stream interrupts. 00582 * @param __HANDLE__ DMA handle 00583 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 00584 * This parameter can be any combination of the following values: 00585 * @arg DMA_IT_TC: Transfer complete interrupt mask. 00586 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 00587 * @arg DMA_IT_TE: Transfer error interrupt mask. 00588 * @arg DMA_IT_FE: FIFO error interrupt mask. 00589 * @arg DMA_IT_DME: Direct mode error interrupt. 00590 * @retval None 00591 */ 00592 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 00593 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__))) 00594 00595 /** 00596 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled. 00597 * @param __HANDLE__ DMA handle 00598 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 00599 * This parameter can be one of the following values: 00600 * @arg DMA_IT_TC: Transfer complete interrupt mask. 00601 * @arg DMA_IT_HT: Half transfer complete interrupt mask. 00602 * @arg DMA_IT_TE: Transfer error interrupt mask. 00603 * @arg DMA_IT_FE: FIFO error interrupt mask. 00604 * @arg DMA_IT_DME: Direct mode error interrupt. 00605 * @retval The state of DMA_IT. 00606 */ 00607 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \ 00608 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \ 00609 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__))) 00610 00611 /** 00612 * @brief Writes the number of data units to be transferred on the DMA Stream. 00613 * @param __HANDLE__ DMA handle 00614 * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535) 00615 * Number of data items depends only on the Peripheral data format. 00616 * 00617 * @note If Peripheral data format is Bytes: number of data units is equal 00618 * to total number of bytes to be transferred. 00619 * 00620 * @note If Peripheral data format is Half-Word: number of data units is 00621 * equal to total number of bytes to be transferred / 2. 00622 * 00623 * @note If Peripheral data format is Word: number of data units is equal 00624 * to total number of bytes to be transferred / 4. 00625 * 00626 * @retval The number of remaining data units in the current DMAy Streamx transfer. 00627 */ 00628 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__)) 00629 00630 /** 00631 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer. 00632 * @param __HANDLE__ DMA handle 00633 * 00634 * @retval The number of remaining data units in the current DMA Stream transfer. 00635 */ 00636 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR) 00637 00638 00639 /* Include DMA HAL Extension module */ 00640 #include "stm32f4xx_hal_dma_ex.h" 00641 00642 /* Exported functions --------------------------------------------------------*/ 00643 00644 /** @defgroup DMA_Exported_Functions DMA Exported Functions 00645 * @brief DMA Exported functions 00646 * @{ 00647 */ 00648 00649 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 00650 * @brief Initialization and de-initialization functions 00651 * @{ 00652 */ 00653 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 00654 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); 00655 /** 00656 * @} 00657 */ 00658 00659 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions 00660 * @brief I/O operation functions 00661 * @{ 00662 */ 00663 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00664 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00665 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 00666 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 00667 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 00668 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 00669 HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma); 00670 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); 00671 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 00672 00673 /** 00674 * @} 00675 */ 00676 00677 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions 00678 * @brief Peripheral State functions 00679 * @{ 00680 */ 00681 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 00682 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 00683 /** 00684 * @} 00685 */ 00686 /** 00687 * @} 00688 */ 00689 /* Private Constants -------------------------------------------------------------*/ 00690 /** @defgroup DMA_Private_Constants DMA Private Constants 00691 * @brief DMA private defines and constants 00692 * @{ 00693 */ 00694 /** 00695 * @} 00696 */ 00697 00698 /* Private macros ------------------------------------------------------------*/ 00699 /** @defgroup DMA_Private_Macros DMA Private Macros 00700 * @brief DMA private macros 00701 * @{ 00702 */ 00703 #if defined (DMA_SxCR_CHSEL_3) 00704 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ 00705 ((CHANNEL) == DMA_CHANNEL_1) || \ 00706 ((CHANNEL) == DMA_CHANNEL_2) || \ 00707 ((CHANNEL) == DMA_CHANNEL_3) || \ 00708 ((CHANNEL) == DMA_CHANNEL_4) || \ 00709 ((CHANNEL) == DMA_CHANNEL_5) || \ 00710 ((CHANNEL) == DMA_CHANNEL_6) || \ 00711 ((CHANNEL) == DMA_CHANNEL_7) || \ 00712 ((CHANNEL) == DMA_CHANNEL_8) || \ 00713 ((CHANNEL) == DMA_CHANNEL_9) || \ 00714 ((CHANNEL) == DMA_CHANNEL_10)|| \ 00715 ((CHANNEL) == DMA_CHANNEL_11)|| \ 00716 ((CHANNEL) == DMA_CHANNEL_12)|| \ 00717 ((CHANNEL) == DMA_CHANNEL_13)|| \ 00718 ((CHANNEL) == DMA_CHANNEL_14)|| \ 00719 ((CHANNEL) == DMA_CHANNEL_15)) 00720 #else 00721 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \ 00722 ((CHANNEL) == DMA_CHANNEL_1) || \ 00723 ((CHANNEL) == DMA_CHANNEL_2) || \ 00724 ((CHANNEL) == DMA_CHANNEL_3) || \ 00725 ((CHANNEL) == DMA_CHANNEL_4) || \ 00726 ((CHANNEL) == DMA_CHANNEL_5) || \ 00727 ((CHANNEL) == DMA_CHANNEL_6) || \ 00728 ((CHANNEL) == DMA_CHANNEL_7)) 00729 #endif /* DMA_SxCR_CHSEL_3 */ 00730 00731 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 00732 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 00733 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 00734 00735 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U)) 00736 00737 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 00738 ((STATE) == DMA_PINC_DISABLE)) 00739 00740 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 00741 ((STATE) == DMA_MINC_DISABLE)) 00742 00743 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 00744 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 00745 ((SIZE) == DMA_PDATAALIGN_WORD)) 00746 00747 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 00748 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 00749 ((SIZE) == DMA_MDATAALIGN_WORD )) 00750 00751 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 00752 ((MODE) == DMA_CIRCULAR) || \ 00753 ((MODE) == DMA_PFCTRL)) 00754 00755 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 00756 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 00757 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 00758 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 00759 00760 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \ 00761 ((STATE) == DMA_FIFOMODE_ENABLE)) 00762 00763 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \ 00764 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \ 00765 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \ 00766 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL)) 00767 00768 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \ 00769 ((BURST) == DMA_MBURST_INC4) || \ 00770 ((BURST) == DMA_MBURST_INC8) || \ 00771 ((BURST) == DMA_MBURST_INC16)) 00772 00773 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \ 00774 ((BURST) == DMA_PBURST_INC4) || \ 00775 ((BURST) == DMA_PBURST_INC8) || \ 00776 ((BURST) == DMA_PBURST_INC16)) 00777 /** 00778 * @} 00779 */ 00780 00781 /* Private functions ---------------------------------------------------------*/ 00782 /** @defgroup DMA_Private_Functions DMA Private Functions 00783 * @brief DMA private functions 00784 * @{ 00785 */ 00786 /** 00787 * @} 00788 */ 00789 00790 /** 00791 * @} 00792 */ 00793 00794 /** 00795 * @} 00796 */ 00797 00798 #ifdef __cplusplus 00799 } 00800 #endif 00801 00802 #endif /* __STM32F4xx_HAL_DMA_H */ 00803 00804 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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