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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_dsi.h 00004 * @author MCD Application Team 00005 * @brief Header file of DSI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F4xx_HAL_DSI_H 00022 #define STM32F4xx_HAL_DSI_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx_hal_def.h" 00030 00031 #if defined(DSI) 00032 00033 /** @addtogroup STM32F4xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @defgroup DSI DSI 00038 * @brief DSI HAL module driver 00039 * @{ 00040 */ 00041 00042 /* Exported types ------------------------------------------------------------*/ 00043 /** 00044 * @brief DSI Init Structure definition 00045 */ 00046 typedef struct 00047 { 00048 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control 00049 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ 00050 00051 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division 00052 The values 0 and 1 stop the TX_ESC clock generation */ 00053 00054 uint32_t NumberOfLanes; /*!< Number of lanes 00055 This parameter can be any value of @ref DSI_Number_Of_Lanes */ 00056 00057 } DSI_InitTypeDef; 00058 00059 /** 00060 * @brief DSI PLL Clock structure definition 00061 */ 00062 typedef struct 00063 { 00064 uint32_t PLLNDIV; /*!< PLL Loop Division Factor 00065 This parameter must be a value between 10 and 125 */ 00066 00067 uint32_t PLLIDF; /*!< PLL Input Division Factor 00068 This parameter can be any value of @ref DSI_PLL_IDF */ 00069 00070 uint32_t PLLODF; /*!< PLL Output Division Factor 00071 This parameter can be any value of @ref DSI_PLL_ODF */ 00072 00073 } DSI_PLLInitTypeDef; 00074 00075 /** 00076 * @brief DSI Video mode configuration 00077 */ 00078 typedef struct 00079 { 00080 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 00081 00082 uint32_t ColorCoding; /*!< Color coding for LTDC interface 00083 This parameter can be any value of @ref DSI_Color_Coding */ 00084 00085 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using 00086 18-bit configuration). 00087 This parameter can be any value of @ref DSI_LooselyPacked */ 00088 00089 uint32_t Mode; /*!< Video mode type 00090 This parameter can be any value of @ref DSI_Video_Mode_Type */ 00091 00092 uint32_t PacketSize; /*!< Video packet size */ 00093 00094 uint32_t NumberOfChunks; /*!< Number of chunks */ 00095 00096 uint32_t NullPacketSize; /*!< Null packet size */ 00097 00098 uint32_t HSPolarity; /*!< HSYNC pin polarity 00099 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 00100 00101 uint32_t VSPolarity; /*!< VSYNC pin polarity 00102 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 00103 00104 uint32_t DEPolarity; /*!< Data Enable pin polarity 00105 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 00106 00107 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ 00108 00109 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ 00110 00111 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ 00112 00113 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ 00114 00115 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ 00116 00117 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ 00118 00119 uint32_t VerticalActive; /*!< Vertical active duration */ 00120 00121 uint32_t LPCommandEnable; /*!< Low-power command enable 00122 This parameter can be any value of @ref DSI_LP_Command */ 00123 00124 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 00125 can fit in a line during VSA, VBP and VFP regions */ 00126 00127 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 00128 can fit in a line during VACT region */ 00129 00130 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable 00131 This parameter can be any value of @ref DSI_LP_HFP */ 00132 00133 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable 00134 This parameter can be any value of @ref DSI_LP_HBP */ 00135 00136 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable 00137 This parameter can be any value of @ref DSI_LP_VACT */ 00138 00139 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable 00140 This parameter can be any value of @ref DSI_LP_VFP */ 00141 00142 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable 00143 This parameter can be any value of @ref DSI_LP_VBP */ 00144 00145 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable 00146 This parameter can be any value of @ref DSI_LP_VSYNC */ 00147 00148 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable 00149 This parameter can be any value of @ref DSI_FBTA_acknowledge */ 00150 00151 } DSI_VidCfgTypeDef; 00152 00153 /** 00154 * @brief DSI Adapted command mode configuration 00155 */ 00156 typedef struct 00157 { 00158 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 00159 00160 uint32_t ColorCoding; /*!< Color coding for LTDC interface 00161 This parameter can be any value of @ref DSI_Color_Coding */ 00162 00163 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in 00164 pixels. This parameter can be any value between 0x00 and 0xFFFFU */ 00165 00166 uint32_t TearingEffectSource; /*!< Tearing effect source 00167 This parameter can be any value of @ref DSI_TearingEffectSource */ 00168 00169 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity 00170 This parameter can be any value of @ref DSI_TearingEffectPolarity */ 00171 00172 uint32_t HSPolarity; /*!< HSYNC pin polarity 00173 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 00174 00175 uint32_t VSPolarity; /*!< VSYNC pin polarity 00176 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 00177 00178 uint32_t DEPolarity; /*!< Data Enable pin polarity 00179 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 00180 00181 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted 00182 This parameter can be any value of @ref DSI_Vsync_Polarity */ 00183 00184 uint32_t AutomaticRefresh; /*!< Automatic refresh mode 00185 This parameter can be any value of @ref DSI_AutomaticRefresh */ 00186 00187 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable 00188 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ 00189 00190 } DSI_CmdCfgTypeDef; 00191 00192 /** 00193 * @brief DSI command transmission mode configuration 00194 */ 00195 typedef struct 00196 { 00197 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission 00198 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ 00199 00200 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission 00201 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ 00202 00203 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission 00204 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ 00205 00206 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission 00207 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ 00208 00209 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission 00210 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ 00211 00212 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission 00213 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ 00214 00215 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission 00216 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ 00217 00218 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission 00219 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ 00220 00221 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission 00222 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ 00223 00224 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission 00225 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ 00226 00227 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission 00228 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ 00229 00230 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission 00231 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ 00232 00233 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable 00234 This parameter can be any value of @ref DSI_AcknowledgeRequest */ 00235 00236 } DSI_LPCmdTypeDef; 00237 00238 /** 00239 * @brief DSI PHY Timings definition 00240 */ 00241 typedef struct 00242 { 00243 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed 00244 to low-power transmission */ 00245 00246 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power 00247 to high-speed transmission */ 00248 00249 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed 00250 to low-power transmission */ 00251 00252 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power 00253 to high-speed transmission */ 00254 00255 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ 00256 00257 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the 00258 Stop state */ 00259 00260 } DSI_PHY_TimerTypeDef; 00261 00262 /** 00263 * @brief DSI HOST Timeouts definition 00264 */ 00265 typedef struct 00266 { 00267 uint32_t TimeoutCkdiv; /*!< Time-out clock division */ 00268 00269 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ 00270 00271 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ 00272 00273 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ 00274 00275 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ 00276 00277 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ 00278 00279 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode 00280 This parameter can be any value of @ref DSI_HS_PrespMode */ 00281 00282 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ 00283 00284 uint32_t BTATimeout; /*!< BTA time-out */ 00285 00286 } DSI_HOST_TimeoutTypeDef; 00287 00288 /** 00289 * @brief DSI States Structure definition 00290 */ 00291 typedef enum 00292 { 00293 HAL_DSI_STATE_RESET = 0x00U, 00294 HAL_DSI_STATE_READY = 0x01U, 00295 HAL_DSI_STATE_ERROR = 0x02U, 00296 HAL_DSI_STATE_BUSY = 0x03U, 00297 HAL_DSI_STATE_TIMEOUT = 0x04U 00298 } HAL_DSI_StateTypeDef; 00299 00300 /** 00301 * @brief DSI Handle Structure definition 00302 */ 00303 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00304 typedef struct __DSI_HandleTypeDef 00305 #else 00306 typedef struct 00307 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00308 { 00309 DSI_TypeDef *Instance; /*!< Register base address */ 00310 DSI_InitTypeDef Init; /*!< DSI required parameters */ 00311 HAL_LockTypeDef Lock; /*!< DSI peripheral status */ 00312 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ 00313 __IO uint32_t ErrorCode; /*!< DSI Error code */ 00314 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ 00315 00316 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00317 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ 00318 void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ 00319 void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ 00320 00321 void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ 00322 void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ 00323 00324 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00325 00326 } DSI_HandleTypeDef; 00327 00328 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00329 /** 00330 * @brief HAL DSI Callback ID enumeration definition 00331 */ 00332 typedef enum 00333 { 00334 HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ 00335 HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ 00336 00337 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ 00338 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ 00339 HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ 00340 00341 } HAL_DSI_CallbackIDTypeDef; 00342 00343 /** 00344 * @brief HAL DSI Callback pointer definition 00345 */ 00346 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ 00347 00348 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00349 00350 /* Exported constants --------------------------------------------------------*/ 00351 /** @defgroup DSI_Exported_Constants DSI Exported Constants 00352 * @{ 00353 */ 00354 /** @defgroup DSI_DCS_Command DSI DCS Command 00355 * @{ 00356 */ 00357 #define DSI_ENTER_IDLE_MODE 0x39U 00358 #define DSI_ENTER_INVERT_MODE 0x21U 00359 #define DSI_ENTER_NORMAL_MODE 0x13U 00360 #define DSI_ENTER_PARTIAL_MODE 0x12U 00361 #define DSI_ENTER_SLEEP_MODE 0x10U 00362 #define DSI_EXIT_IDLE_MODE 0x38U 00363 #define DSI_EXIT_INVERT_MODE 0x20U 00364 #define DSI_EXIT_SLEEP_MODE 0x11U 00365 #define DSI_GET_3D_CONTROL 0x3FU 00366 #define DSI_GET_ADDRESS_MODE 0x0BU 00367 #define DSI_GET_BLUE_CHANNEL 0x08U 00368 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU 00369 #define DSI_GET_DISPLAY_MODE 0x0DU 00370 #define DSI_GET_GREEN_CHANNEL 0x07U 00371 #define DSI_GET_PIXEL_FORMAT 0x0CU 00372 #define DSI_GET_POWER_MODE 0x0AU 00373 #define DSI_GET_RED_CHANNEL 0x06U 00374 #define DSI_GET_SCANLINE 0x45U 00375 #define DSI_GET_SIGNAL_MODE 0x0EU 00376 #define DSI_NOP 0x00U 00377 #define DSI_READ_DDB_CONTINUE 0xA8U 00378 #define DSI_READ_DDB_START 0xA1U 00379 #define DSI_READ_MEMORY_CONTINUE 0x3EU 00380 #define DSI_READ_MEMORY_START 0x2EU 00381 #define DSI_SET_3D_CONTROL 0x3DU 00382 #define DSI_SET_ADDRESS_MODE 0x36U 00383 #define DSI_SET_COLUMN_ADDRESS 0x2AU 00384 #define DSI_SET_DISPLAY_OFF 0x28U 00385 #define DSI_SET_DISPLAY_ON 0x29U 00386 #define DSI_SET_GAMMA_CURVE 0x26U 00387 #define DSI_SET_PAGE_ADDRESS 0x2BU 00388 #define DSI_SET_PARTIAL_COLUMNS 0x31U 00389 #define DSI_SET_PARTIAL_ROWS 0x30U 00390 #define DSI_SET_PIXEL_FORMAT 0x3AU 00391 #define DSI_SET_SCROLL_AREA 0x33U 00392 #define DSI_SET_SCROLL_START 0x37U 00393 #define DSI_SET_TEAR_OFF 0x34U 00394 #define DSI_SET_TEAR_ON 0x35U 00395 #define DSI_SET_TEAR_SCANLINE 0x44U 00396 #define DSI_SET_VSYNC_TIMING 0x40U 00397 #define DSI_SOFT_RESET 0x01U 00398 #define DSI_WRITE_LUT 0x2DU 00399 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU 00400 #define DSI_WRITE_MEMORY_START 0x2CU 00401 /** 00402 * @} 00403 */ 00404 00405 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type 00406 * @{ 00407 */ 00408 #define DSI_VID_MODE_NB_PULSES 0U 00409 #define DSI_VID_MODE_NB_EVENTS 1U 00410 #define DSI_VID_MODE_BURST 2U 00411 /** 00412 * @} 00413 */ 00414 00415 /** @defgroup DSI_Color_Mode DSI Color Mode 00416 * @{ 00417 */ 00418 #define DSI_COLOR_MODE_FULL 0x00000000U 00419 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM 00420 /** 00421 * @} 00422 */ 00423 00424 /** @defgroup DSI_ShutDown DSI ShutDown 00425 * @{ 00426 */ 00427 #define DSI_DISPLAY_ON 0x00000000U 00428 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN 00429 /** 00430 * @} 00431 */ 00432 00433 /** @defgroup DSI_LP_Command DSI LP Command 00434 * @{ 00435 */ 00436 #define DSI_LP_COMMAND_DISABLE 0x00000000U 00437 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE 00438 /** 00439 * @} 00440 */ 00441 00442 /** @defgroup DSI_LP_HFP DSI LP HFP 00443 * @{ 00444 */ 00445 #define DSI_LP_HFP_DISABLE 0x00000000U 00446 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE 00447 /** 00448 * @} 00449 */ 00450 00451 /** @defgroup DSI_LP_HBP DSI LP HBP 00452 * @{ 00453 */ 00454 #define DSI_LP_HBP_DISABLE 0x00000000U 00455 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE 00456 /** 00457 * @} 00458 */ 00459 00460 /** @defgroup DSI_LP_VACT DSI LP VACT 00461 * @{ 00462 */ 00463 #define DSI_LP_VACT_DISABLE 0x00000000U 00464 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE 00465 /** 00466 * @} 00467 */ 00468 00469 /** @defgroup DSI_LP_VFP DSI LP VFP 00470 * @{ 00471 */ 00472 #define DSI_LP_VFP_DISABLE 0x00000000U 00473 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE 00474 /** 00475 * @} 00476 */ 00477 00478 /** @defgroup DSI_LP_VBP DSI LP VBP 00479 * @{ 00480 */ 00481 #define DSI_LP_VBP_DISABLE 0x00000000U 00482 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE 00483 /** 00484 * @} 00485 */ 00486 00487 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC 00488 * @{ 00489 */ 00490 #define DSI_LP_VSYNC_DISABLE 0x00000000U 00491 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE 00492 /** 00493 * @} 00494 */ 00495 00496 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge 00497 * @{ 00498 */ 00499 #define DSI_FBTAA_DISABLE 0x00000000U 00500 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE 00501 /** 00502 * @} 00503 */ 00504 00505 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source 00506 * @{ 00507 */ 00508 #define DSI_TE_DSILINK 0x00000000U 00509 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC 00510 /** 00511 * @} 00512 */ 00513 00514 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity 00515 * @{ 00516 */ 00517 #define DSI_TE_RISING_EDGE 0x00000000U 00518 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL 00519 /** 00520 * @} 00521 */ 00522 00523 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity 00524 * @{ 00525 */ 00526 #define DSI_VSYNC_FALLING 0x00000000U 00527 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL 00528 /** 00529 * @} 00530 */ 00531 00532 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh 00533 * @{ 00534 */ 00535 #define DSI_AR_DISABLE 0x00000000U 00536 #define DSI_AR_ENABLE DSI_WCFGR_AR 00537 /** 00538 * @} 00539 */ 00540 00541 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request 00542 * @{ 00543 */ 00544 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U 00545 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE 00546 /** 00547 * @} 00548 */ 00549 00550 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request 00551 * @{ 00552 */ 00553 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U 00554 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE 00555 /** 00556 * @} 00557 */ 00558 00559 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP 00560 * @{ 00561 */ 00562 #define DSI_LP_GSW0P_DISABLE 0x00000000U 00563 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX 00564 /** 00565 * @} 00566 */ 00567 00568 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP 00569 * @{ 00570 */ 00571 #define DSI_LP_GSW1P_DISABLE 0x00000000U 00572 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX 00573 /** 00574 * @} 00575 */ 00576 00577 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP 00578 * @{ 00579 */ 00580 #define DSI_LP_GSW2P_DISABLE 0x00000000U 00581 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX 00582 /** 00583 * @} 00584 */ 00585 00586 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP 00587 * @{ 00588 */ 00589 #define DSI_LP_GSR0P_DISABLE 0x00000000U 00590 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX 00591 /** 00592 * @} 00593 */ 00594 00595 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP 00596 * @{ 00597 */ 00598 #define DSI_LP_GSR1P_DISABLE 0x00000000U 00599 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX 00600 /** 00601 * @} 00602 */ 00603 00604 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP 00605 * @{ 00606 */ 00607 #define DSI_LP_GSR2P_DISABLE 0x00000000U 00608 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX 00609 /** 00610 * @} 00611 */ 00612 00613 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite 00614 * @{ 00615 */ 00616 #define DSI_LP_GLW_DISABLE 0x00000000U 00617 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX 00618 /** 00619 * @} 00620 */ 00621 00622 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP 00623 * @{ 00624 */ 00625 #define DSI_LP_DSW0P_DISABLE 0x00000000U 00626 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX 00627 /** 00628 * @} 00629 */ 00630 00631 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP 00632 * @{ 00633 */ 00634 #define DSI_LP_DSW1P_DISABLE 0x00000000U 00635 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX 00636 /** 00637 * @} 00638 */ 00639 00640 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP 00641 * @{ 00642 */ 00643 #define DSI_LP_DSR0P_DISABLE 0x00000000U 00644 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX 00645 /** 00646 * @} 00647 */ 00648 00649 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write 00650 * @{ 00651 */ 00652 #define DSI_LP_DLW_DISABLE 0x00000000U 00653 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX 00654 /** 00655 * @} 00656 */ 00657 00658 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet 00659 * @{ 00660 */ 00661 #define DSI_LP_MRDP_DISABLE 0x00000000U 00662 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS 00663 /** 00664 * @} 00665 */ 00666 00667 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode 00668 * @{ 00669 */ 00670 #define DSI_HS_PM_DISABLE 0x00000000U 00671 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM 00672 /** 00673 * @} 00674 */ 00675 00676 00677 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control 00678 * @{ 00679 */ 00680 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U 00681 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR 00682 /** 00683 * @} 00684 */ 00685 00686 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes 00687 * @{ 00688 */ 00689 #define DSI_ONE_DATA_LANE 0U 00690 #define DSI_TWO_DATA_LANES 1U 00691 /** 00692 * @} 00693 */ 00694 00695 /** @defgroup DSI_FlowControl DSI Flow Control 00696 * @{ 00697 */ 00698 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE 00699 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE 00700 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE 00701 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE 00702 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE 00703 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ 00704 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ 00705 DSI_FLOW_CONTROL_EOTP_TX) 00706 /** 00707 * @} 00708 */ 00709 00710 /** @defgroup DSI_Color_Coding DSI Color Coding 00711 * @{ 00712 */ 00713 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ 00714 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ 00715 #define DSI_RGB888 0x00000005U 00716 /** 00717 * @} 00718 */ 00719 00720 /** @defgroup DSI_LooselyPacked DSI Loosely Packed 00721 * @{ 00722 */ 00723 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE 00724 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U 00725 /** 00726 * @} 00727 */ 00728 00729 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity 00730 * @{ 00731 */ 00732 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U 00733 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP 00734 /** 00735 * @} 00736 */ 00737 00738 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity 00739 * @{ 00740 */ 00741 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U 00742 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP 00743 /** 00744 * @} 00745 */ 00746 00747 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity 00748 * @{ 00749 */ 00750 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U 00751 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP 00752 /** 00753 * @} 00754 */ 00755 00756 /** @defgroup DSI_PLL_IDF DSI PLL IDF 00757 * @{ 00758 */ 00759 #define DSI_PLL_IN_DIV1 0x00000001U 00760 #define DSI_PLL_IN_DIV2 0x00000002U 00761 #define DSI_PLL_IN_DIV3 0x00000003U 00762 #define DSI_PLL_IN_DIV4 0x00000004U 00763 #define DSI_PLL_IN_DIV5 0x00000005U 00764 #define DSI_PLL_IN_DIV6 0x00000006U 00765 #define DSI_PLL_IN_DIV7 0x00000007U 00766 /** 00767 * @} 00768 */ 00769 00770 /** @defgroup DSI_PLL_ODF DSI PLL ODF 00771 * @{ 00772 */ 00773 #define DSI_PLL_OUT_DIV1 0x00000000U 00774 #define DSI_PLL_OUT_DIV2 0x00000001U 00775 #define DSI_PLL_OUT_DIV4 0x00000002U 00776 #define DSI_PLL_OUT_DIV8 0x00000003U 00777 /** 00778 * @} 00779 */ 00780 00781 /** @defgroup DSI_Flags DSI Flags 00782 * @{ 00783 */ 00784 #define DSI_FLAG_TE DSI_WISR_TEIF 00785 #define DSI_FLAG_ER DSI_WISR_ERIF 00786 #define DSI_FLAG_BUSY DSI_WISR_BUSY 00787 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS 00788 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF 00789 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF 00790 #define DSI_FLAG_RRS DSI_WISR_RRS 00791 #define DSI_FLAG_RR DSI_WISR_RRIF 00792 /** 00793 * @} 00794 */ 00795 00796 /** @defgroup DSI_Interrupts DSI Interrupts 00797 * @{ 00798 */ 00799 #define DSI_IT_TE DSI_WIER_TEIE 00800 #define DSI_IT_ER DSI_WIER_ERIE 00801 #define DSI_IT_PLLL DSI_WIER_PLLLIE 00802 #define DSI_IT_PLLU DSI_WIER_PLLUIE 00803 #define DSI_IT_RR DSI_WIER_RRIE 00804 /** 00805 * @} 00806 */ 00807 00808 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type 00809 * @{ 00810 */ 00811 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ 00812 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ 00813 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ 00814 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ 00815 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ 00816 /** 00817 * @} 00818 */ 00819 00820 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type 00821 * @{ 00822 */ 00823 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ 00824 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ 00825 /** 00826 * @} 00827 */ 00828 00829 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type 00830 * @{ 00831 */ 00832 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ 00833 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ 00834 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ 00835 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ 00836 /** 00837 * @} 00838 */ 00839 00840 /** @defgroup DSI_Error_Data_Type DSI Error Data Type 00841 * @{ 00842 */ 00843 #define HAL_DSI_ERROR_NONE 0U 00844 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ 00845 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ 00846 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ 00847 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ 00848 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ 00849 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ 00850 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ 00851 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ 00852 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ 00853 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ 00854 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00855 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ 00856 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00857 /** 00858 * @} 00859 */ 00860 00861 /** @defgroup DSI_Lane_Group DSI Lane Group 00862 * @{ 00863 */ 00864 #define DSI_CLOCK_LANE 0x00000000U 00865 #define DSI_DATA_LANES 0x00000001U 00866 /** 00867 * @} 00868 */ 00869 00870 /** @defgroup DSI_Communication_Delay DSI Communication Delay 00871 * @{ 00872 */ 00873 #define DSI_SLEW_RATE_HSTX 0x00000000U 00874 #define DSI_SLEW_RATE_LPTX 0x00000001U 00875 #define DSI_HS_DELAY 0x00000002U 00876 /** 00877 * @} 00878 */ 00879 00880 /** @defgroup DSI_CustomLane DSI CustomLane 00881 * @{ 00882 */ 00883 #define DSI_SWAP_LANE_PINS 0x00000000U 00884 #define DSI_INVERT_HS_SIGNAL 0x00000001U 00885 /** 00886 * @} 00887 */ 00888 00889 /** @defgroup DSI_Lane_Select DSI Lane Select 00890 * @{ 00891 */ 00892 #define DSI_CLK_LANE 0x00000000U 00893 #define DSI_DATA_LANE0 0x00000001U 00894 #define DSI_DATA_LANE1 0x00000002U 00895 /** 00896 * @} 00897 */ 00898 00899 /** @defgroup DSI_PHY_Timing DSI PHY Timing 00900 * @{ 00901 */ 00902 #define DSI_TCLK_POST 0x00000000U 00903 #define DSI_TLPX_CLK 0x00000001U 00904 #define DSI_THS_EXIT 0x00000002U 00905 #define DSI_TLPX_DATA 0x00000003U 00906 #define DSI_THS_ZERO 0x00000004U 00907 #define DSI_THS_TRAIL 0x00000005U 00908 #define DSI_THS_PREPARE 0x00000006U 00909 #define DSI_TCLK_ZERO 0x00000007U 00910 #define DSI_TCLK_PREPARE 0x00000008U 00911 /** 00912 * @} 00913 */ 00914 00915 /** 00916 * @} 00917 */ 00918 00919 /* Exported macros -----------------------------------------------------------*/ 00920 /** @defgroup DSI_Exported_Macros DSI Exported Macros 00921 * @{ 00922 */ 00923 00924 /** 00925 * @brief Reset DSI handle state. 00926 * @param __HANDLE__ DSI handle 00927 * @retval None 00928 */ 00929 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00930 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00931 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ 00932 (__HANDLE__)->MspInitCallback = NULL; \ 00933 (__HANDLE__)->MspDeInitCallback = NULL; \ 00934 } while(0) 00935 #else 00936 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) 00937 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ 00938 00939 /** 00940 * @brief Enables the DSI host. 00941 * @param __HANDLE__ DSI handle 00942 * @retval None. 00943 */ 00944 #define __HAL_DSI_ENABLE(__HANDLE__) do { \ 00945 __IO uint32_t tmpreg = 0x00U; \ 00946 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00947 /* Delay after an DSI Host enabling */ \ 00948 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00949 UNUSED(tmpreg); \ 00950 } while(0U) 00951 00952 /** 00953 * @brief Disables the DSI host. 00954 * @param __HANDLE__ DSI handle 00955 * @retval None. 00956 */ 00957 #define __HAL_DSI_DISABLE(__HANDLE__) do { \ 00958 __IO uint32_t tmpreg = 0x00U; \ 00959 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00960 /* Delay after an DSI Host disabling */ \ 00961 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00962 UNUSED(tmpreg); \ 00963 } while(0U) 00964 00965 /** 00966 * @brief Enables the DSI wrapper. 00967 * @param __HANDLE__ DSI handle 00968 * @retval None. 00969 */ 00970 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ 00971 __IO uint32_t tmpreg = 0x00U; \ 00972 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00973 /* Delay after an DSI warpper enabling */ \ 00974 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00975 UNUSED(tmpreg); \ 00976 } while(0U) 00977 00978 /** 00979 * @brief Disable the DSI wrapper. 00980 * @param __HANDLE__ DSI handle 00981 * @retval None. 00982 */ 00983 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ 00984 __IO uint32_t tmpreg = 0x00U; \ 00985 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00986 /* Delay after an DSI warpper disabling*/ \ 00987 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00988 UNUSED(tmpreg); \ 00989 } while(0U) 00990 00991 /** 00992 * @brief Enables the DSI PLL. 00993 * @param __HANDLE__ DSI handle 00994 * @retval None. 00995 */ 00996 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ 00997 __IO uint32_t tmpreg = 0x00U; \ 00998 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 00999 /* Delay after an DSI PLL enabling */ \ 01000 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01001 UNUSED(tmpreg); \ 01002 } while(0U) 01003 01004 /** 01005 * @brief Disables the DSI PLL. 01006 * @param __HANDLE__ DSI handle 01007 * @retval None. 01008 */ 01009 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ 01010 __IO uint32_t tmpreg = 0x00U; \ 01011 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01012 /* Delay after an DSI PLL disabling */ \ 01013 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01014 UNUSED(tmpreg); \ 01015 } while(0U) 01016 01017 /** 01018 * @brief Enables the DSI regulator. 01019 * @param __HANDLE__ DSI handle 01020 * @retval None. 01021 */ 01022 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ 01023 __IO uint32_t tmpreg = 0x00U; \ 01024 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01025 /* Delay after an DSI regulator enabling */ \ 01026 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01027 UNUSED(tmpreg); \ 01028 } while(0U) 01029 01030 /** 01031 * @brief Disables the DSI regulator. 01032 * @param __HANDLE__ DSI handle 01033 * @retval None. 01034 */ 01035 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ 01036 __IO uint32_t tmpreg = 0x00U; \ 01037 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01038 /* Delay after an DSI regulator disabling */ \ 01039 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01040 UNUSED(tmpreg); \ 01041 } while(0U) 01042 01043 /** 01044 * @brief Get the DSI pending flags. 01045 * @param __HANDLE__ DSI handle. 01046 * @param __FLAG__ Get the specified flag. 01047 * This parameter can be any combination of the following values: 01048 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 01049 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 01050 * @arg DSI_FLAG_BUSY : Busy Flag 01051 * @arg DSI_FLAG_PLLLS: PLL Lock Status 01052 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 01053 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 01054 * @arg DSI_FLAG_RRS : Regulator Ready Flag 01055 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 01056 * @retval The state of FLAG (SET or RESET). 01057 */ 01058 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) 01059 01060 /** 01061 * @brief Clears the DSI pending flags. 01062 * @param __HANDLE__ DSI handle. 01063 * @param __FLAG__ specifies the flag to clear. 01064 * This parameter can be any combination of the following values: 01065 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 01066 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 01067 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 01068 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 01069 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 01070 * @retval None 01071 */ 01072 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) 01073 01074 /** 01075 * @brief Enables the specified DSI interrupts. 01076 * @param __HANDLE__ DSI handle. 01077 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. 01078 * This parameter can be any combination of the following values: 01079 * @arg DSI_IT_TE : Tearing Effect Interrupt 01080 * @arg DSI_IT_ER : End of Refresh Interrupt 01081 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01082 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01083 * @arg DSI_IT_RR : Regulator Ready Interrupt 01084 * @retval None 01085 */ 01086 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) 01087 01088 /** 01089 * @brief Disables the specified DSI interrupts. 01090 * @param __HANDLE__ DSI handle 01091 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. 01092 * This parameter can be any combination of the following values: 01093 * @arg DSI_IT_TE : Tearing Effect Interrupt 01094 * @arg DSI_IT_ER : End of Refresh Interrupt 01095 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01096 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01097 * @arg DSI_IT_RR : Regulator Ready Interrupt 01098 * @retval None 01099 */ 01100 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) 01101 01102 /** 01103 * @brief Checks whether the specified DSI interrupt source is enabled or not. 01104 * @param __HANDLE__ DSI handle 01105 * @param __INTERRUPT__ specifies the DSI interrupt source to check. 01106 * This parameter can be one of the following values: 01107 * @arg DSI_IT_TE : Tearing Effect Interrupt 01108 * @arg DSI_IT_ER : End of Refresh Interrupt 01109 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01110 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01111 * @arg DSI_IT_RR : Regulator Ready Interrupt 01112 * @retval The state of INTERRUPT (SET or RESET). 01113 */ 01114 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) 01115 01116 /** 01117 * @} 01118 */ 01119 01120 /* Exported functions --------------------------------------------------------*/ 01121 /** @defgroup DSI_Exported_Functions DSI Exported Functions 01122 * @{ 01123 */ 01124 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); 01125 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); 01126 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); 01127 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); 01128 01129 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); 01130 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); 01131 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); 01132 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); 01133 01134 /* Callbacks Register/UnRegister functions ***********************************/ 01135 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 01136 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, 01137 pDSI_CallbackTypeDef pCallback); 01138 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); 01139 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 01140 01141 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); 01142 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); 01143 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); 01144 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); 01145 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); 01146 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); 01147 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); 01148 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); 01149 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); 01150 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); 01151 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); 01152 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); 01153 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 01154 uint32_t ChannelID, 01155 uint32_t Mode, 01156 uint32_t Param1, 01157 uint32_t Param2); 01158 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 01159 uint32_t ChannelID, 01160 uint32_t Mode, 01161 uint32_t NbParams, 01162 uint32_t Param1, 01163 uint8_t *ParametersTable); 01164 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 01165 uint32_t ChannelNbr, 01166 uint8_t *Array, 01167 uint32_t Size, 01168 uint32_t Mode, 01169 uint32_t DCSCmd, 01170 uint8_t *ParametersTable); 01171 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); 01172 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); 01173 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); 01174 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); 01175 01176 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); 01177 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); 01178 01179 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, 01180 uint32_t Value); 01181 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); 01182 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); 01183 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, 01184 FunctionalState State); 01185 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, 01186 uint32_t Value); 01187 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); 01188 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); 01189 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); 01190 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); 01191 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); 01192 01193 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); 01194 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); 01195 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); 01196 /** 01197 * @} 01198 */ 01199 01200 /* Private types -------------------------------------------------------------*/ 01201 /** @defgroup DSI_Private_Types DSI Private Types 01202 * @{ 01203 */ 01204 01205 /** 01206 * @} 01207 */ 01208 01209 /* Private defines -----------------------------------------------------------*/ 01210 /** @defgroup DSI_Private_Defines DSI Private Defines 01211 * @{ 01212 */ 01213 01214 /** 01215 * @} 01216 */ 01217 01218 /* Private variables ---------------------------------------------------------*/ 01219 /** @defgroup DSI_Private_Variables DSI Private Variables 01220 * @{ 01221 */ 01222 01223 /** 01224 * @} 01225 */ 01226 01227 /* Private constants ---------------------------------------------------------*/ 01228 /** @defgroup DSI_Private_Constants DSI Private Constants 01229 * @{ 01230 */ 01231 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ 01232 /** 01233 * @} 01234 */ 01235 01236 /* Private macros ------------------------------------------------------------*/ 01237 /** @defgroup DSI_Private_Macros DSI Private Macros 01238 * @{ 01239 */ 01240 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) 01241 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ 01242 ((IDF) == DSI_PLL_IN_DIV2) || \ 01243 ((IDF) == DSI_PLL_IN_DIV3) || \ 01244 ((IDF) == DSI_PLL_IN_DIV4) || \ 01245 ((IDF) == DSI_PLL_IN_DIV5) || \ 01246 ((IDF) == DSI_PLL_IN_DIV6) || \ 01247 ((IDF) == DSI_PLL_IN_DIV7)) 01248 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ 01249 ((ODF) == DSI_PLL_OUT_DIV2) || \ 01250 ((ODF) == DSI_PLL_OUT_DIV4) || \ 01251 ((ODF) == DSI_PLL_OUT_DIV8)) 01252 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) 01253 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) 01254 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) 01255 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) 01256 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) 01257 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) 01258 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) 01259 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) 01260 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ 01261 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ 01262 ((VideoModeType) == DSI_VID_MODE_BURST)) 01263 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) 01264 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) 01265 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) 01266 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) 01267 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) 01268 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) 01269 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) 01270 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) 01271 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) 01272 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) 01273 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) 01274 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) 01275 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) 01276 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) 01277 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) 01278 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) 01279 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) 01280 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) 01281 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) 01282 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) 01283 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) 01284 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) 01285 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) 01286 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) 01287 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) 01288 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) 01289 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) 01290 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) 01291 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ 01292 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ 01293 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ 01294 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ 01295 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) 01296 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ 01297 ((MODE) == DSI_GEN_LONG_PKT_WRITE)) 01298 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ 01299 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ 01300 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ 01301 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) 01302 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) 01303 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) 01304 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) 01305 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) 01306 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ 01307 ((Timing) == DSI_TLPX_CLK ) || \ 01308 ((Timing) == DSI_THS_EXIT ) || \ 01309 ((Timing) == DSI_TLPX_DATA ) || \ 01310 ((Timing) == DSI_THS_ZERO ) || \ 01311 ((Timing) == DSI_THS_TRAIL ) || \ 01312 ((Timing) == DSI_THS_PREPARE ) || \ 01313 ((Timing) == DSI_TCLK_ZERO ) || \ 01314 ((Timing) == DSI_TCLK_PREPARE)) 01315 01316 /** 01317 * @} 01318 */ 01319 01320 /* Private functions prototypes ----------------------------------------------*/ 01321 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes 01322 * @{ 01323 */ 01324 01325 /** 01326 * @} 01327 */ 01328 01329 /* Private functions ---------------------------------------------------------*/ 01330 /** @defgroup DSI_Private_Functions DSI Private Functions 01331 * @{ 01332 */ 01333 01334 /** 01335 * @} 01336 */ 01337 01338 /** 01339 * @} 01340 */ 01341 01342 /** 01343 * @} 01344 */ 01345 #endif /* DSI */ 01346 01347 #ifdef __cplusplus 01348 } 01349 #endif 01350 01351 #endif /* STM32F4xx_HAL_DSI_H */ 01352 01353 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1