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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_fmpsmbus.h 00004 * @author MCD Application Team 00005 * @brief Header file of FMPSMBUS HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F4xx_HAL_FMPSMBUS_H 00022 #define STM32F4xx_HAL_FMPSMBUS_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 #if defined(FMPI2C_CR1_PE) 00029 /* Includes ------------------------------------------------------------------*/ 00030 #include "stm32f4xx_hal_def.h" 00031 00032 /** @addtogroup STM32F4xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @addtogroup FMPSMBUS 00037 * @{ 00038 */ 00039 00040 /* Exported types ------------------------------------------------------------*/ 00041 /** @defgroup FMPSMBUS_Exported_Types FMPSMBUS Exported Types 00042 * @{ 00043 */ 00044 00045 /** @defgroup FMPSMBUS_Configuration_Structure_definition FMPSMBUS Configuration Structure definition 00046 * @brief FMPSMBUS Configuration Structure definition 00047 * @{ 00048 */ 00049 typedef struct 00050 { 00051 uint32_t Timing; /*!< Specifies the FMPSMBUS_TIMINGR_register value. 00052 This parameter calculated by referring to FMPSMBUS initialization section 00053 in Reference manual */ 00054 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 00055 This parameter can be a value of @ref FMPSMBUS_Analog_Filter */ 00056 00057 uint32_t OwnAddress1; /*!< Specifies the first device own address. 00058 This parameter can be a 7-bit or 10-bit address. */ 00059 00060 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 00061 This parameter can be a value of @ref FMPSMBUS_addressing_mode */ 00062 00063 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 00064 This parameter can be a value of @ref FMPSMBUS_dual_addressing_mode */ 00065 00066 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 00067 This parameter can be a 7-bit address. */ 00068 00069 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address 00070 if dual addressing mode is selected 00071 This parameter can be a value of @ref FMPSMBUS_own_address2_masks. */ 00072 00073 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 00074 This parameter can be a value of @ref FMPSMBUS_general_call_addressing_mode. */ 00075 00076 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 00077 This parameter can be a value of @ref FMPSMBUS_nostretch_mode */ 00078 00079 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 00080 This parameter can be a value of @ref FMPSMBUS_packet_error_check_mode */ 00081 00082 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 00083 This parameter can be a value of @ref FMPSMBUS_peripheral_mode */ 00084 00085 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits FMPSMBUS_TIMEOUT_register value. 00086 (Enable bits and different timeout values) 00087 This parameter calculated by referring to FMPSMBUS initialization section 00088 in Reference manual */ 00089 } FMPSMBUS_InitTypeDef; 00090 /** 00091 * @} 00092 */ 00093 00094 /** @defgroup HAL_state_definition HAL state definition 00095 * @brief HAL State definition 00096 * @{ 00097 */ 00098 #define HAL_FMPSMBUS_STATE_RESET (0x00000000U) /*!< FMPSMBUS not yet initialized or disabled */ 00099 #define HAL_FMPSMBUS_STATE_READY (0x00000001U) /*!< FMPSMBUS initialized and ready for use */ 00100 #define HAL_FMPSMBUS_STATE_BUSY (0x00000002U) /*!< FMPSMBUS internal process is ongoing */ 00101 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 00102 #define HAL_FMPSMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 00103 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 00104 #define HAL_FMPSMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 00105 #define HAL_FMPSMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 00106 #define HAL_FMPSMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 00107 #define HAL_FMPSMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 00108 /** 00109 * @} 00110 */ 00111 00112 /** @defgroup FMPSMBUS_Error_Code_definition FMPSMBUS Error Code definition 00113 * @brief FMPSMBUS Error Code definition 00114 * @{ 00115 */ 00116 #define HAL_FMPSMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 00117 #define HAL_FMPSMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 00118 #define HAL_FMPSMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 00119 #define HAL_FMPSMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 00120 #define HAL_FMPSMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 00121 #define HAL_FMPSMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 00122 #define HAL_FMPSMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 00123 #define HAL_FMPSMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 00124 #define HAL_FMPSMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 00125 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 00126 #define HAL_FMPSMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 00127 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 00128 #define HAL_FMPSMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 00129 /** 00130 * @} 00131 */ 00132 00133 /** @defgroup FMPSMBUS_handle_Structure_definition FMPSMBUS handle Structure definition 00134 * @brief FMPSMBUS handle Structure definition 00135 * @{ 00136 */ 00137 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 00138 typedef struct __FMPSMBUS_HandleTypeDef 00139 #else 00140 typedef struct 00141 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 00142 { 00143 FMPI2C_TypeDef *Instance; /*!< FMPSMBUS registers base address */ 00144 00145 FMPSMBUS_InitTypeDef Init; /*!< FMPSMBUS communication parameters */ 00146 00147 uint8_t *pBuffPtr; /*!< Pointer to FMPSMBUS transfer buffer */ 00148 00149 uint16_t XferSize; /*!< FMPSMBUS transfer size */ 00150 00151 __IO uint16_t XferCount; /*!< FMPSMBUS transfer counter */ 00152 00153 __IO uint32_t XferOptions; /*!< FMPSMBUS transfer options */ 00154 00155 __IO uint32_t PreviousState; /*!< FMPSMBUS communication Previous state */ 00156 00157 HAL_LockTypeDef Lock; /*!< FMPSMBUS locking object */ 00158 00159 __IO uint32_t State; /*!< FMPSMBUS communication state */ 00160 00161 __IO uint32_t ErrorCode; /*!< FMPSMBUS Error code */ 00162 00163 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 00164 void (* MasterTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 00165 /*!< FMPSMBUS Master Tx Transfer completed callback */ 00166 void (* MasterRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 00167 /*!< FMPSMBUS Master Rx Transfer completed callback */ 00168 void (* SlaveTxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 00169 /*!< FMPSMBUS Slave Tx Transfer completed callback */ 00170 void (* SlaveRxCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 00171 /*!< FMPSMBUS Slave Rx Transfer completed callback */ 00172 void (* ListenCpltCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 00173 /*!< FMPSMBUS Listen Complete callback */ 00174 void (* ErrorCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 00175 /*!< FMPSMBUS Error callback */ 00176 00177 void (* AddrCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 00178 /*!< FMPSMBUS Slave Address Match callback */ 00179 00180 void (* MspInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 00181 /*!< FMPSMBUS Msp Init callback */ 00182 void (* MspDeInitCallback)(struct __FMPSMBUS_HandleTypeDef *hfmpsmbus); 00183 /*!< FMPSMBUS Msp DeInit callback */ 00184 00185 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 00186 } FMPSMBUS_HandleTypeDef; 00187 00188 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 00189 /** 00190 * @brief HAL FMPSMBUS Callback ID enumeration definition 00191 */ 00192 typedef enum 00193 { 00194 HAL_FMPSMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< FMPSMBUS Master Tx Transfer completed callback ID */ 00195 HAL_FMPSMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< FMPSMBUS Master Rx Transfer completed callback ID */ 00196 HAL_FMPSMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< FMPSMBUS Slave Tx Transfer completed callback ID */ 00197 HAL_FMPSMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< FMPSMBUS Slave Rx Transfer completed callback ID */ 00198 HAL_FMPSMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< FMPSMBUS Listen Complete callback ID */ 00199 HAL_FMPSMBUS_ERROR_CB_ID = 0x05U, /*!< FMPSMBUS Error callback ID */ 00200 00201 HAL_FMPSMBUS_MSPINIT_CB_ID = 0x06U, /*!< FMPSMBUS Msp Init callback ID */ 00202 HAL_FMPSMBUS_MSPDEINIT_CB_ID = 0x07U /*!< FMPSMBUS Msp DeInit callback ID */ 00203 00204 } HAL_FMPSMBUS_CallbackIDTypeDef; 00205 00206 /** 00207 * @brief HAL FMPSMBUS Callback pointer definition 00208 */ 00209 typedef void (*pFMPSMBUS_CallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00210 /*!< pointer to an FMPSMBUS callback function */ 00211 typedef void (*pFMPSMBUS_AddrCallbackTypeDef)(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, 00212 uint16_t AddrMatchCode); 00213 /*!< pointer to an FMPSMBUS Address Match callback function */ 00214 00215 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 00216 /** 00217 * @} 00218 */ 00219 00220 /** 00221 * @} 00222 */ 00223 /* Exported constants --------------------------------------------------------*/ 00224 00225 /** @defgroup FMPSMBUS_Exported_Constants FMPSMBUS Exported Constants 00226 * @{ 00227 */ 00228 00229 /** @defgroup FMPSMBUS_Analog_Filter FMPSMBUS Analog Filter 00230 * @{ 00231 */ 00232 #define FMPSMBUS_ANALOGFILTER_ENABLE (0x00000000U) 00233 #define FMPSMBUS_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF 00234 /** 00235 * @} 00236 */ 00237 00238 /** @defgroup FMPSMBUS_addressing_mode FMPSMBUS addressing mode 00239 * @{ 00240 */ 00241 #define FMPSMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 00242 #define FMPSMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 00243 /** 00244 * @} 00245 */ 00246 00247 /** @defgroup FMPSMBUS_dual_addressing_mode FMPSMBUS dual addressing mode 00248 * @{ 00249 */ 00250 00251 #define FMPSMBUS_DUALADDRESS_DISABLE (0x00000000U) 00252 #define FMPSMBUS_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup FMPSMBUS_own_address2_masks FMPSMBUS ownaddress2 masks 00258 * @{ 00259 */ 00260 00261 #define FMPSMBUS_OA2_NOMASK ((uint8_t)0x00U) 00262 #define FMPSMBUS_OA2_MASK01 ((uint8_t)0x01U) 00263 #define FMPSMBUS_OA2_MASK02 ((uint8_t)0x02U) 00264 #define FMPSMBUS_OA2_MASK03 ((uint8_t)0x03U) 00265 #define FMPSMBUS_OA2_MASK04 ((uint8_t)0x04U) 00266 #define FMPSMBUS_OA2_MASK05 ((uint8_t)0x05U) 00267 #define FMPSMBUS_OA2_MASK06 ((uint8_t)0x06U) 00268 #define FMPSMBUS_OA2_MASK07 ((uint8_t)0x07U) 00269 /** 00270 * @} 00271 */ 00272 00273 00274 /** @defgroup FMPSMBUS_general_call_addressing_mode FMPSMBUS general call addressing mode 00275 * @{ 00276 */ 00277 #define FMPSMBUS_GENERALCALL_DISABLE (0x00000000U) 00278 #define FMPSMBUS_GENERALCALL_ENABLE FMPI2C_CR1_GCEN 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup FMPSMBUS_nostretch_mode FMPSMBUS nostretch mode 00284 * @{ 00285 */ 00286 #define FMPSMBUS_NOSTRETCH_DISABLE (0x00000000U) 00287 #define FMPSMBUS_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH 00288 /** 00289 * @} 00290 */ 00291 00292 /** @defgroup FMPSMBUS_packet_error_check_mode FMPSMBUS packet error check mode 00293 * @{ 00294 */ 00295 #define FMPSMBUS_PEC_DISABLE (0x00000000U) 00296 #define FMPSMBUS_PEC_ENABLE FMPI2C_CR1_PECEN 00297 /** 00298 * @} 00299 */ 00300 00301 /** @defgroup FMPSMBUS_peripheral_mode FMPSMBUS peripheral mode 00302 * @{ 00303 */ 00304 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST FMPI2C_CR1_SMBHEN 00305 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE (0x00000000U) 00306 #define FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP FMPI2C_CR1_SMBDEN 00307 /** 00308 * @} 00309 */ 00310 00311 /** @defgroup FMPSMBUS_ReloadEndMode_definition FMPSMBUS ReloadEndMode definition 00312 * @{ 00313 */ 00314 00315 #define FMPSMBUS_SOFTEND_MODE (0x00000000U) 00316 #define FMPSMBUS_RELOAD_MODE FMPI2C_CR2_RELOAD 00317 #define FMPSMBUS_AUTOEND_MODE FMPI2C_CR2_AUTOEND 00318 #define FMPSMBUS_SENDPEC_MODE FMPI2C_CR2_PECBYTE 00319 /** 00320 * @} 00321 */ 00322 00323 /** @defgroup FMPSMBUS_StartStopMode_definition FMPSMBUS StartStopMode definition 00324 * @{ 00325 */ 00326 00327 #define FMPSMBUS_NO_STARTSTOP (0x00000000U) 00328 #define FMPSMBUS_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP) 00329 #define FMPSMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN) 00330 #define FMPSMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START) 00331 /** 00332 * @} 00333 */ 00334 00335 /** @defgroup FMPSMBUS_XferOptions_definition FMPSMBUS XferOptions definition 00336 * @{ 00337 */ 00338 00339 /* List of XferOptions in usage of : 00340 * 1- Restart condition when direction change 00341 * 2- No Restart condition in other use cases 00342 */ 00343 #define FMPSMBUS_FIRST_FRAME FMPSMBUS_SOFTEND_MODE 00344 #define FMPSMBUS_NEXT_FRAME ((uint32_t)(FMPSMBUS_RELOAD_MODE | FMPSMBUS_SOFTEND_MODE)) 00345 #define FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 00346 #define FMPSMBUS_LAST_FRAME_NO_PEC FMPSMBUS_AUTOEND_MODE 00347 #define FMPSMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_SOFTEND_MODE | FMPSMBUS_SENDPEC_MODE)) 00348 #define FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 00349 #define FMPSMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) 00350 00351 /* List of XferOptions in usage of : 00352 * 1- Restart condition in all use cases (direction change or not) 00353 */ 00354 #define FMPSMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 00355 #define FMPSMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 00356 #define FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 00357 #define FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 00358 /** 00359 * @} 00360 */ 00361 00362 /** @defgroup FMPSMBUS_Interrupt_configuration_definition FMPSMBUS Interrupt configuration definition 00363 * @brief FMPSMBUS Interrupt definition 00364 * Elements values convention: 0xXXXXXXXX 00365 * - XXXXXXXX : Interrupt control mask 00366 * @{ 00367 */ 00368 #define FMPSMBUS_IT_ERRI FMPI2C_CR1_ERRIE 00369 #define FMPSMBUS_IT_TCI FMPI2C_CR1_TCIE 00370 #define FMPSMBUS_IT_STOPI FMPI2C_CR1_STOPIE 00371 #define FMPSMBUS_IT_NACKI FMPI2C_CR1_NACKIE 00372 #define FMPSMBUS_IT_ADDRI FMPI2C_CR1_ADDRIE 00373 #define FMPSMBUS_IT_RXI FMPI2C_CR1_RXIE 00374 #define FMPSMBUS_IT_TXI FMPI2C_CR1_TXIE 00375 #define FMPSMBUS_IT_TX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_STOPI | \ 00376 FMPSMBUS_IT_NACKI | FMPSMBUS_IT_TXI) 00377 #define FMPSMBUS_IT_RX (FMPSMBUS_IT_ERRI | FMPSMBUS_IT_TCI | FMPSMBUS_IT_NACKI | \ 00378 FMPSMBUS_IT_RXI) 00379 #define FMPSMBUS_IT_ALERT (FMPSMBUS_IT_ERRI) 00380 #define FMPSMBUS_IT_ADDR (FMPSMBUS_IT_ADDRI | FMPSMBUS_IT_STOPI | FMPSMBUS_IT_NACKI) 00381 /** 00382 * @} 00383 */ 00384 00385 /** @defgroup FMPSMBUS_Flag_definition FMPSMBUS Flag definition 00386 * @brief Flag definition 00387 * Elements values convention: 0xXXXXYYYY 00388 * - XXXXXXXX : Flag mask 00389 * @{ 00390 */ 00391 00392 #define FMPSMBUS_FLAG_TXE FMPI2C_ISR_TXE 00393 #define FMPSMBUS_FLAG_TXIS FMPI2C_ISR_TXIS 00394 #define FMPSMBUS_FLAG_RXNE FMPI2C_ISR_RXNE 00395 #define FMPSMBUS_FLAG_ADDR FMPI2C_ISR_ADDR 00396 #define FMPSMBUS_FLAG_AF FMPI2C_ISR_NACKF 00397 #define FMPSMBUS_FLAG_STOPF FMPI2C_ISR_STOPF 00398 #define FMPSMBUS_FLAG_TC FMPI2C_ISR_TC 00399 #define FMPSMBUS_FLAG_TCR FMPI2C_ISR_TCR 00400 #define FMPSMBUS_FLAG_BERR FMPI2C_ISR_BERR 00401 #define FMPSMBUS_FLAG_ARLO FMPI2C_ISR_ARLO 00402 #define FMPSMBUS_FLAG_OVR FMPI2C_ISR_OVR 00403 #define FMPSMBUS_FLAG_PECERR FMPI2C_ISR_PECERR 00404 #define FMPSMBUS_FLAG_TIMEOUT FMPI2C_ISR_TIMEOUT 00405 #define FMPSMBUS_FLAG_ALERT FMPI2C_ISR_ALERT 00406 #define FMPSMBUS_FLAG_BUSY FMPI2C_ISR_BUSY 00407 #define FMPSMBUS_FLAG_DIR FMPI2C_ISR_DIR 00408 /** 00409 * @} 00410 */ 00411 00412 /** 00413 * @} 00414 */ 00415 00416 /* Exported macros ------------------------------------------------------------*/ 00417 /** @defgroup FMPSMBUS_Exported_Macros FMPSMBUS Exported Macros 00418 * @{ 00419 */ 00420 00421 /** @brief Reset FMPSMBUS handle state. 00422 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00423 * @retval None 00424 */ 00425 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 00426 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00427 (__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET; \ 00428 (__HANDLE__)->MspInitCallback = NULL; \ 00429 (__HANDLE__)->MspDeInitCallback = NULL; \ 00430 } while(0) 00431 #else 00432 #define __HAL_FMPSMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FMPSMBUS_STATE_RESET) 00433 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 00434 00435 /** @brief Enable the specified FMPSMBUS interrupts. 00436 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00437 * @param __INTERRUPT__ specifies the interrupt source to enable. 00438 * This parameter can be one of the following values: 00439 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 00440 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 00441 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 00442 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 00443 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 00444 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 00445 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 00446 * 00447 * @retval None 00448 */ 00449 #define __HAL_FMPSMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 00450 00451 /** @brief Disable the specified FMPSMBUS interrupts. 00452 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00453 * @param __INTERRUPT__ specifies the interrupt source to disable. 00454 * This parameter can be one of the following values: 00455 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 00456 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 00457 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 00458 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 00459 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 00460 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 00461 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 00462 * 00463 * @retval None 00464 */ 00465 #define __HAL_FMPSMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 00466 00467 /** @brief Check whether the specified FMPSMBUS interrupt source is enabled or not. 00468 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00469 * @param __INTERRUPT__ specifies the FMPSMBUS interrupt source to check. 00470 * This parameter can be one of the following values: 00471 * @arg @ref FMPSMBUS_IT_ERRI Errors interrupt enable 00472 * @arg @ref FMPSMBUS_IT_TCI Transfer complete interrupt enable 00473 * @arg @ref FMPSMBUS_IT_STOPI STOP detection interrupt enable 00474 * @arg @ref FMPSMBUS_IT_NACKI NACK received interrupt enable 00475 * @arg @ref FMPSMBUS_IT_ADDRI Address match interrupt enable 00476 * @arg @ref FMPSMBUS_IT_RXI RX interrupt enable 00477 * @arg @ref FMPSMBUS_IT_TXI TX interrupt enable 00478 * 00479 * @retval The new state of __IT__ (SET or RESET). 00480 */ 00481 #define __HAL_FMPSMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 00482 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00483 00484 /** @brief Check whether the specified FMPSMBUS flag is set or not. 00485 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00486 * @param __FLAG__ specifies the flag to check. 00487 * This parameter can be one of the following values: 00488 * @arg @ref FMPSMBUS_FLAG_TXE Transmit data register empty 00489 * @arg @ref FMPSMBUS_FLAG_TXIS Transmit interrupt status 00490 * @arg @ref FMPSMBUS_FLAG_RXNE Receive data register not empty 00491 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 00492 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 00493 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 00494 * @arg @ref FMPSMBUS_FLAG_TC Transfer complete (master mode) 00495 * @arg @ref FMPSMBUS_FLAG_TCR Transfer complete reload 00496 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 00497 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 00498 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 00499 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 00500 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 00501 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 00502 * @arg @ref FMPSMBUS_FLAG_BUSY Bus busy 00503 * @arg @ref FMPSMBUS_FLAG_DIR Transfer direction (slave mode) 00504 * 00505 * @retval The new state of __FLAG__ (SET or RESET). 00506 */ 00507 #define FMPSMBUS_FLAG_MASK (0x0001FFFFU) 00508 #define __HAL_FMPSMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ 00509 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ 00510 ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 00511 00512 /** @brief Clear the FMPSMBUS pending flags which are cleared by writing 1 in a specific bit. 00513 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00514 * @param __FLAG__ specifies the flag to clear. 00515 * This parameter can be any combination of the following values: 00516 * @arg @ref FMPSMBUS_FLAG_ADDR Address matched (slave mode) 00517 * @arg @ref FMPSMBUS_FLAG_AF NACK received flag 00518 * @arg @ref FMPSMBUS_FLAG_STOPF STOP detection flag 00519 * @arg @ref FMPSMBUS_FLAG_BERR Bus error 00520 * @arg @ref FMPSMBUS_FLAG_ARLO Arbitration lost 00521 * @arg @ref FMPSMBUS_FLAG_OVR Overrun/Underrun 00522 * @arg @ref FMPSMBUS_FLAG_PECERR PEC error in reception 00523 * @arg @ref FMPSMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 00524 * @arg @ref FMPSMBUS_FLAG_ALERT SMBus alert 00525 * 00526 * @retval None 00527 */ 00528 #define __HAL_FMPSMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 00529 00530 /** @brief Enable the specified FMPSMBUS peripheral. 00531 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00532 * @retval None 00533 */ 00534 #define __HAL_FMPSMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 00535 00536 /** @brief Disable the specified FMPSMBUS peripheral. 00537 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00538 * @retval None 00539 */ 00540 #define __HAL_FMPSMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE)) 00541 00542 /** @brief Generate a Non-Acknowledge FMPSMBUS peripheral in Slave mode. 00543 * @param __HANDLE__ specifies the FMPSMBUS Handle. 00544 * @retval None 00545 */ 00546 #define __HAL_FMPSMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK)) 00547 00548 /** 00549 * @} 00550 */ 00551 00552 00553 /* Private constants ---------------------------------------------------------*/ 00554 00555 /* Private macros ------------------------------------------------------------*/ 00556 /** @defgroup FMPSMBUS_Private_Macro FMPSMBUS Private Macros 00557 * @{ 00558 */ 00559 00560 #define IS_FMPSMBUS_ANALOG_FILTER(FILTER) (((FILTER) == FMPSMBUS_ANALOGFILTER_ENABLE) || \ 00561 ((FILTER) == FMPSMBUS_ANALOGFILTER_DISABLE)) 00562 00563 #define IS_FMPSMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 00564 00565 #define IS_FMPSMBUS_ADDRESSING_MODE(MODE) (((MODE) == FMPSMBUS_ADDRESSINGMODE_7BIT) || \ 00566 ((MODE) == FMPSMBUS_ADDRESSINGMODE_10BIT)) 00567 00568 #define IS_FMPSMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPSMBUS_DUALADDRESS_DISABLE) || \ 00569 ((ADDRESS) == FMPSMBUS_DUALADDRESS_ENABLE)) 00570 00571 #define IS_FMPSMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPSMBUS_OA2_NOMASK) || \ 00572 ((MASK) == FMPSMBUS_OA2_MASK01) || \ 00573 ((MASK) == FMPSMBUS_OA2_MASK02) || \ 00574 ((MASK) == FMPSMBUS_OA2_MASK03) || \ 00575 ((MASK) == FMPSMBUS_OA2_MASK04) || \ 00576 ((MASK) == FMPSMBUS_OA2_MASK05) || \ 00577 ((MASK) == FMPSMBUS_OA2_MASK06) || \ 00578 ((MASK) == FMPSMBUS_OA2_MASK07)) 00579 00580 #define IS_FMPSMBUS_GENERAL_CALL(CALL) (((CALL) == FMPSMBUS_GENERALCALL_DISABLE) || \ 00581 ((CALL) == FMPSMBUS_GENERALCALL_ENABLE)) 00582 00583 #define IS_FMPSMBUS_NO_STRETCH(STRETCH) (((STRETCH) == FMPSMBUS_NOSTRETCH_DISABLE) || \ 00584 ((STRETCH) == FMPSMBUS_NOSTRETCH_ENABLE)) 00585 00586 #define IS_FMPSMBUS_PEC(PEC) (((PEC) == FMPSMBUS_PEC_DISABLE) || \ 00587 ((PEC) == FMPSMBUS_PEC_ENABLE)) 00588 00589 #define IS_FMPSMBUS_PERIPHERAL_MODE(MODE) (((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_HOST) || \ 00590 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE) || \ 00591 ((MODE) == FMPSMBUS_PERIPHERAL_MODE_FMPSMBUS_SLAVE_ARP)) 00592 00593 #define IS_FMPSMBUS_TRANSFER_MODE(MODE) (((MODE) == FMPSMBUS_RELOAD_MODE) || \ 00594 ((MODE) == FMPSMBUS_AUTOEND_MODE) || \ 00595 ((MODE) == FMPSMBUS_SOFTEND_MODE) || \ 00596 ((MODE) == FMPSMBUS_SENDPEC_MODE) || \ 00597 ((MODE) == (FMPSMBUS_RELOAD_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 00598 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE)) || \ 00599 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_RELOAD_MODE)) || \ 00600 ((MODE) == (FMPSMBUS_AUTOEND_MODE | FMPSMBUS_SENDPEC_MODE | \ 00601 FMPSMBUS_RELOAD_MODE ))) 00602 00603 00604 #define IS_FMPSMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_GENERATE_STOP) || \ 00605 ((REQUEST) == FMPSMBUS_GENERATE_START_READ) || \ 00606 ((REQUEST) == FMPSMBUS_GENERATE_START_WRITE) || \ 00607 ((REQUEST) == FMPSMBUS_NO_STARTSTOP)) 00608 00609 00610 #define IS_FMPSMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 00611 ((REQUEST) == FMPSMBUS_FIRST_FRAME) || \ 00612 ((REQUEST) == FMPSMBUS_NEXT_FRAME) || \ 00613 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 00614 ((REQUEST) == FMPSMBUS_LAST_FRAME_NO_PEC) || \ 00615 ((REQUEST) == FMPSMBUS_FIRST_FRAME_WITH_PEC) || \ 00616 ((REQUEST) == FMPSMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 00617 ((REQUEST) == FMPSMBUS_LAST_FRAME_WITH_PEC)) 00618 00619 #define IS_FMPSMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == FMPSMBUS_OTHER_FRAME_NO_PEC) || \ 00620 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 00621 ((REQUEST) == FMPSMBUS_OTHER_FRAME_WITH_PEC) || \ 00622 ((REQUEST) == FMPSMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 00623 00624 #define FMPSMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ 00625 (uint32_t)~((uint32_t)(FMPI2C_CR1_SMBHEN | FMPI2C_CR1_SMBDEN | \ 00626 FMPI2C_CR1_PECEN))) 00627 #define FMPSMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ 00628 (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | \ 00629 FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | \ 00630 FMPI2C_CR2_RD_WRN))) 00631 00632 #define FMPSMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPSMBUS_ADDRESSINGMODE_7BIT) ? \ 00633 (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | \ 00634 (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & \ 00635 (~FMPI2C_CR2_RD_WRN)) : \ 00636 (uint32_t)((((uint32_t)(__ADDRESS__) & \ 00637 (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | \ 00638 (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN))) 00639 00640 #define FMPSMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_ADDCODE) >> 17U) 00641 #define FMPSMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & FMPI2C_ISR_DIR) >> 16U) 00642 #define FMPSMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_AUTOEND) 00643 #define FMPSMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & FMPI2C_CR2_PECBYTE) 00644 #define FMPSMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & FMPI2C_CR1_ALERTEN) 00645 00646 #define FMPSMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & FMPSMBUS_FLAG_MASK)) == \ 00647 ((__FLAG__) & FMPSMBUS_FLAG_MASK)) ? SET : RESET) 00648 #define FMPSMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 00649 00650 #define IS_FMPSMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 00651 #define IS_FMPSMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 00652 00653 /** 00654 * @} 00655 */ 00656 00657 /* Include FMPSMBUS HAL Extended module */ 00658 #include "stm32f4xx_hal_fmpsmbus_ex.h" 00659 00660 /* Exported functions --------------------------------------------------------*/ 00661 /** @addtogroup FMPSMBUS_Exported_Functions FMPSMBUS Exported Functions 00662 * @{ 00663 */ 00664 00665 /** @addtogroup FMPSMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 00666 * @{ 00667 */ 00668 00669 /* Initialization and de-initialization functions ****************************/ 00670 HAL_StatusTypeDef HAL_FMPSMBUS_Init(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00671 HAL_StatusTypeDef HAL_FMPSMBUS_DeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00672 void HAL_FMPSMBUS_MspInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00673 void HAL_FMPSMBUS_MspDeInit(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00674 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigAnalogFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t AnalogFilter); 00675 HAL_StatusTypeDef HAL_FMPSMBUS_ConfigDigitalFilter(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint32_t DigitalFilter); 00676 00677 /* Callbacks Register/UnRegister functions ***********************************/ 00678 #if (USE_HAL_FMPSMBUS_REGISTER_CALLBACKS == 1) 00679 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 00680 HAL_FMPSMBUS_CallbackIDTypeDef CallbackID, 00681 pFMPSMBUS_CallbackTypeDef pCallback); 00682 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 00683 HAL_FMPSMBUS_CallbackIDTypeDef CallbackID); 00684 00685 HAL_StatusTypeDef HAL_FMPSMBUS_RegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, 00686 pFMPSMBUS_AddrCallbackTypeDef pCallback); 00687 HAL_StatusTypeDef HAL_FMPSMBUS_UnRegisterAddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00688 #endif /* USE_HAL_FMPSMBUS_REGISTER_CALLBACKS */ 00689 /** 00690 * @} 00691 */ 00692 00693 /** @addtogroup FMPSMBUS_Exported_Functions_Group2 Input and Output operation functions 00694 * @{ 00695 */ 00696 00697 /* IO operation functions *****************************************************/ 00698 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 00699 * @{ 00700 */ 00701 /******* Blocking mode: Polling */ 00702 HAL_StatusTypeDef HAL_FMPSMBUS_IsDeviceReady(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, uint32_t Trials, 00703 uint32_t Timeout); 00704 /** 00705 * @} 00706 */ 00707 00708 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 00709 * @{ 00710 */ 00711 /******* Non-Blocking mode: Interrupt */ 00712 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, 00713 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00714 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress, 00715 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00716 HAL_StatusTypeDef HAL_FMPSMBUS_Master_Abort_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint16_t DevAddress); 00717 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Transmit_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, 00718 uint32_t XferOptions); 00719 HAL_StatusTypeDef HAL_FMPSMBUS_Slave_Receive_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t *pData, uint16_t Size, 00720 uint32_t XferOptions); 00721 00722 HAL_StatusTypeDef HAL_FMPSMBUS_EnableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00723 HAL_StatusTypeDef HAL_FMPSMBUS_DisableAlert_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00724 HAL_StatusTypeDef HAL_FMPSMBUS_EnableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00725 HAL_StatusTypeDef HAL_FMPSMBUS_DisableListen_IT(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00726 /** 00727 * @} 00728 */ 00729 00730 /** @addtogroup FMPSMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 00731 * @{ 00732 */ 00733 /******* FMPSMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 00734 void HAL_FMPSMBUS_EV_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00735 void HAL_FMPSMBUS_ER_IRQHandler(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00736 void HAL_FMPSMBUS_MasterTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00737 void HAL_FMPSMBUS_MasterRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00738 void HAL_FMPSMBUS_SlaveTxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00739 void HAL_FMPSMBUS_SlaveRxCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00740 void HAL_FMPSMBUS_AddrCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 00741 void HAL_FMPSMBUS_ListenCpltCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00742 void HAL_FMPSMBUS_ErrorCallback(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00743 00744 /** 00745 * @} 00746 */ 00747 00748 /** @addtogroup FMPSMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 00749 * @{ 00750 */ 00751 00752 /* Peripheral State and Errors functions **************************************************/ 00753 uint32_t HAL_FMPSMBUS_GetState(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00754 uint32_t HAL_FMPSMBUS_GetError(FMPSMBUS_HandleTypeDef *hfmpsmbus); 00755 00756 /** 00757 * @} 00758 */ 00759 00760 /** 00761 * @} 00762 */ 00763 00764 /* Private Functions ---------------------------------------------------------*/ 00765 /** @defgroup FMPSMBUS_Private_Functions FMPSMBUS Private Functions 00766 * @{ 00767 */ 00768 /* Private functions are defined in stm32f4xx_hal_fmpsmbus.c file */ 00769 /** 00770 * @} 00771 */ 00772 00773 /** 00774 * @} 00775 */ 00776 00777 /** 00778 * @} 00779 */ 00780 00781 /** 00782 * @} 00783 */ 00784 00785 #endif /* FMPI2C_CR1_PE */ 00786 #ifdef __cplusplus 00787 } 00788 #endif 00789 00790 00791 #endif /* STM32F4xx_HAL_FMPSMBUS_H */ 00792 00793 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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