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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_i2c.c 00004 * @author MCD Application Team 00005 * @brief I2C HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Inter Integrated Circuit (I2C) peripheral: 00008 * + Initialization and de-initialization functions 00009 * + IO operation functions 00010 * + Peripheral State, Mode and Error functions 00011 * 00012 @verbatim 00013 ============================================================================== 00014 ##### How to use this driver ##### 00015 ============================================================================== 00016 [..] 00017 The I2C HAL driver can be used as follows: 00018 00019 (#) Declare a I2C_HandleTypeDef handle structure, for example: 00020 I2C_HandleTypeDef hi2c; 00021 00022 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: 00023 (##) Enable the I2Cx interface clock 00024 (##) I2C pins configuration 00025 (+++) Enable the clock for the I2C GPIOs 00026 (+++) Configure I2C pins as alternate function open-drain 00027 (##) NVIC configuration if you need to use interrupt process 00028 (+++) Configure the I2Cx interrupt priority 00029 (+++) Enable the NVIC I2C IRQ Channel 00030 (##) DMA Configuration if you need to use DMA process 00031 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream 00032 (+++) Enable the DMAx interface clock using 00033 (+++) Configure the DMA handle parameters 00034 (+++) Configure the DMA Tx or Rx stream 00035 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle 00036 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on 00037 the DMA Tx or Rx stream 00038 00039 (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, 00040 Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. 00041 00042 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware 00043 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API. 00044 00045 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() 00046 00047 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : 00048 00049 *** Polling mode IO operation *** 00050 ================================= 00051 [..] 00052 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() 00053 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() 00054 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() 00055 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() 00056 00057 *** Polling mode IO MEM operation *** 00058 ===================================== 00059 [..] 00060 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() 00061 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() 00062 00063 00064 *** Interrupt mode IO operation *** 00065 =================================== 00066 [..] 00067 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() 00068 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can 00069 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() 00070 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() 00071 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can 00072 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() 00073 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() 00074 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can 00075 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() 00076 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() 00077 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can 00078 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() 00079 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 00080 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 00081 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() 00082 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can 00083 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() 00084 00085 *** Interrupt mode or DMA mode IO sequential operation *** 00086 ========================================================== 00087 [..] 00088 (@) These interfaces allow to manage a sequential transfer with a repeated start condition 00089 when a direction change during transfer 00090 [..] 00091 (+) A specific option field manage the different steps of a sequential transfer 00092 (+) Option field values are defined through I2C_XferOptions_definition and are listed below: 00093 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode 00094 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address 00095 and data to transfer without a final stop condition 00096 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address 00097 and data to transfer without a final stop condition, an then permit a call the same master sequential interface 00098 several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() 00099 or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) 00100 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address 00101 and with new data to transfer if the direction change or manage only the new data to transfer 00102 if no direction change and without a final stop condition in both cases 00103 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address 00104 and with new data to transfer if the direction change or manage only the new data to transfer 00105 if no direction change and with a final stop condition in both cases 00106 (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential 00107 interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). 00108 Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) 00109 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) 00110 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) 00111 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). 00112 Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit 00113 without stopping the communication and so generate a restart condition. 00114 (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential 00115 interface. 00116 Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) 00117 or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) 00118 or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) 00119 or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). 00120 Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. 00121 00122 (+) Different sequential I2C interfaces are listed below: 00123 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT() 00124 or using HAL_I2C_Master_Seq_Transmit_DMA() 00125 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can 00126 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() 00127 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT() 00128 or using HAL_I2C_Master_Seq_Receive_DMA() 00129 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can 00130 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() 00131 (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() 00132 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can 00133 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() 00134 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() 00135 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can 00136 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). 00137 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can 00138 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() 00139 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT() 00140 or using HAL_I2C_Slave_Seq_Transmit_DMA() 00141 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can 00142 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() 00143 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT() 00144 or using HAL_I2C_Slave_Seq_Receive_DMA() 00145 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can 00146 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() 00147 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 00148 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 00149 00150 *** Interrupt mode IO MEM operation *** 00151 ======================================= 00152 [..] 00153 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using 00154 HAL_I2C_Mem_Write_IT() 00155 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can 00156 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() 00157 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using 00158 HAL_I2C_Mem_Read_IT() 00159 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can 00160 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() 00161 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 00162 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 00163 00164 *** DMA mode IO operation *** 00165 ============================== 00166 [..] 00167 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using 00168 HAL_I2C_Master_Transmit_DMA() 00169 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can 00170 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() 00171 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using 00172 HAL_I2C_Master_Receive_DMA() 00173 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can 00174 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() 00175 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using 00176 HAL_I2C_Slave_Transmit_DMA() 00177 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can 00178 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() 00179 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using 00180 HAL_I2C_Slave_Receive_DMA() 00181 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can 00182 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() 00183 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 00184 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 00185 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() 00186 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can 00187 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() 00188 00189 *** DMA mode IO MEM operation *** 00190 ================================= 00191 [..] 00192 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using 00193 HAL_I2C_Mem_Write_DMA() 00194 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can 00195 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() 00196 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using 00197 HAL_I2C_Mem_Read_DMA() 00198 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can 00199 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() 00200 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can 00201 add his own code by customization of function pointer HAL_I2C_ErrorCallback() 00202 00203 00204 *** I2C HAL driver macros list *** 00205 ================================== 00206 [..] 00207 Below the list of most used macros in I2C HAL driver. 00208 00209 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral 00210 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral 00211 (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not 00212 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag 00213 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt 00214 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt 00215 00216 *** Callback registration *** 00217 ============================================= 00218 [..] 00219 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 00220 allows the user to configure dynamically the driver callbacks. 00221 Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() 00222 to register an interrupt callback. 00223 [..] 00224 Function HAL_I2C_RegisterCallback() allows to register following callbacks: 00225 (+) MasterTxCpltCallback : callback for Master transmission end of transfer. 00226 (+) MasterRxCpltCallback : callback for Master reception end of transfer. 00227 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. 00228 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. 00229 (+) ListenCpltCallback : callback for end of listen mode. 00230 (+) MemTxCpltCallback : callback for Memory transmission end of transfer. 00231 (+) MemRxCpltCallback : callback for Memory reception end of transfer. 00232 (+) ErrorCallback : callback for error detection. 00233 (+) AbortCpltCallback : callback for abort completion process. 00234 (+) MspInitCallback : callback for Msp Init. 00235 (+) MspDeInitCallback : callback for Msp DeInit. 00236 This function takes as parameters the HAL peripheral handle, the Callback ID 00237 and a pointer to the user callback function. 00238 [..] 00239 For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). 00240 [..] 00241 Use function HAL_I2C_UnRegisterCallback to reset a callback to the default 00242 weak function. 00243 HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, 00244 and the Callback ID. 00245 This function allows to reset following callbacks: 00246 (+) MasterTxCpltCallback : callback for Master transmission end of transfer. 00247 (+) MasterRxCpltCallback : callback for Master reception end of transfer. 00248 (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. 00249 (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. 00250 (+) ListenCpltCallback : callback for end of listen mode. 00251 (+) MemTxCpltCallback : callback for Memory transmission end of transfer. 00252 (+) MemRxCpltCallback : callback for Memory reception end of transfer. 00253 (+) ErrorCallback : callback for error detection. 00254 (+) AbortCpltCallback : callback for abort completion process. 00255 (+) MspInitCallback : callback for Msp Init. 00256 (+) MspDeInitCallback : callback for Msp DeInit. 00257 [..] 00258 For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). 00259 [..] 00260 By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET 00261 all callbacks are set to the corresponding weak functions: 00262 examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). 00263 Exception done for MspInit and MspDeInit functions that are 00264 reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when 00265 these callbacks are null (not registered beforehand). 00266 If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() 00267 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. 00268 [..] 00269 Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. 00270 Exception done MspInit/MspDeInit functions that can be registered/unregistered 00271 in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, 00272 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. 00273 Then, the user first registers the MspInit/MspDeInit user callbacks 00274 using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() 00275 or HAL_I2C_Init() function. 00276 [..] 00277 When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or 00278 not defined, the callback registration feature is not available and all callbacks 00279 are set to the corresponding weak functions. 00280 00281 00282 00283 [..] 00284 (@) You can refer to the I2C HAL driver header file for more useful macros 00285 00286 @endverbatim 00287 ****************************************************************************** 00288 * @attention 00289 * 00290 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00291 * All rights reserved.</center></h2> 00292 * 00293 * This software component is licensed by ST under BSD 3-Clause license, 00294 * the "License"; You may not use this file except in compliance with the 00295 * License. You may obtain a copy of the License at: 00296 * opensource.org/licenses/BSD-3-Clause 00297 * 00298 ****************************************************************************** 00299 */ 00300 00301 /* Includes ------------------------------------------------------------------*/ 00302 #include "stm32f4xx_hal.h" 00303 00304 /** @addtogroup STM32F4xx_HAL_Driver 00305 * @{ 00306 */ 00307 00308 /** @defgroup I2C I2C 00309 * @brief I2C HAL module driver 00310 * @{ 00311 */ 00312 00313 #ifdef HAL_I2C_MODULE_ENABLED 00314 00315 /* Private typedef -----------------------------------------------------------*/ 00316 /* Private define ------------------------------------------------------------*/ 00317 /** @addtogroup I2C_Private_Define 00318 * @{ 00319 */ 00320 #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ 00321 #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ 00322 #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ 00323 #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ 00324 00325 /* Private define for @ref PreviousState usage */ 00326 #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ 00327 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ 00328 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ 00329 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ 00330 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ 00331 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ 00332 00333 /** 00334 * @} 00335 */ 00336 00337 /* Private macro -------------------------------------------------------------*/ 00338 /* Private variables ---------------------------------------------------------*/ 00339 /* Private function prototypes -----------------------------------------------*/ 00340 00341 /** @defgroup I2C_Private_Functions I2C Private Functions 00342 * @{ 00343 */ 00344 /* Private functions to handle DMA transfer */ 00345 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); 00346 static void I2C_DMAError(DMA_HandleTypeDef *hdma); 00347 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); 00348 00349 static void I2C_ITError(I2C_HandleTypeDef *hi2c); 00350 00351 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); 00352 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); 00353 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); 00354 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); 00355 00356 /* Private functions to handle flags during polling transfer */ 00357 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); 00358 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); 00359 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); 00360 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); 00361 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); 00362 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); 00363 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); 00364 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); 00365 00366 /* Private functions for I2C transfer IRQ handler */ 00367 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); 00368 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); 00369 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); 00370 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); 00371 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); 00372 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); 00373 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); 00374 00375 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); 00376 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); 00377 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); 00378 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); 00379 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); 00380 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); 00381 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); 00382 00383 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); 00384 00385 /* Private function to Convert Specific options */ 00386 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); 00387 /** 00388 * @} 00389 */ 00390 00391 /* Exported functions --------------------------------------------------------*/ 00392 00393 /** @defgroup I2C_Exported_Functions I2C Exported Functions 00394 * @{ 00395 */ 00396 00397 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions 00398 * @brief Initialization and Configuration functions 00399 * 00400 @verbatim 00401 =============================================================================== 00402 ##### Initialization and de-initialization functions ##### 00403 =============================================================================== 00404 [..] This subsection provides a set of functions allowing to initialize and 00405 deinitialize the I2Cx peripheral: 00406 00407 (+) User must Implement HAL_I2C_MspInit() function in which he configures 00408 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). 00409 00410 (+) Call the function HAL_I2C_Init() to configure the selected device with 00411 the selected configuration: 00412 (++) Communication Speed 00413 (++) Duty cycle 00414 (++) Addressing mode 00415 (++) Own Address 1 00416 (++) Dual Addressing mode 00417 (++) Own Address 2 00418 (++) General call mode 00419 (++) Nostretch mode 00420 00421 (+) Call the function HAL_I2C_DeInit() to restore the default configuration 00422 of the selected I2Cx peripheral. 00423 00424 @endverbatim 00425 * @{ 00426 */ 00427 00428 /** 00429 * @brief Initializes the I2C according to the specified parameters 00430 * in the I2C_InitTypeDef and initialize the associated handle. 00431 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 00432 * the configuration information for the specified I2C. 00433 * @retval HAL status 00434 */ 00435 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) 00436 { 00437 uint32_t freqrange; 00438 uint32_t pclk1; 00439 00440 /* Check the I2C handle allocation */ 00441 if (hi2c == NULL) 00442 { 00443 return HAL_ERROR; 00444 } 00445 00446 /* Check the parameters */ 00447 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 00448 assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); 00449 assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); 00450 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); 00451 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); 00452 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); 00453 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); 00454 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); 00455 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); 00456 00457 if (hi2c->State == HAL_I2C_STATE_RESET) 00458 { 00459 /* Allocate lock resource and initialize it */ 00460 hi2c->Lock = HAL_UNLOCKED; 00461 00462 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 00463 /* Init the I2C Callback settings */ 00464 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ 00465 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ 00466 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ 00467 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ 00468 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ 00469 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ 00470 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ 00471 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ 00472 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ 00473 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ 00474 00475 if (hi2c->MspInitCallback == NULL) 00476 { 00477 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ 00478 } 00479 00480 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 00481 hi2c->MspInitCallback(hi2c); 00482 #else 00483 /* Init the low level hardware : GPIO, CLOCK, NVIC */ 00484 HAL_I2C_MspInit(hi2c); 00485 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 00486 } 00487 00488 hi2c->State = HAL_I2C_STATE_BUSY; 00489 00490 /* Disable the selected I2C peripheral */ 00491 __HAL_I2C_DISABLE(hi2c); 00492 00493 /*Reset I2C*/ 00494 hi2c->Instance->CR1 |= I2C_CR1_SWRST; 00495 hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; 00496 00497 /* Get PCLK1 frequency */ 00498 pclk1 = HAL_RCC_GetPCLK1Freq(); 00499 00500 /* Check the minimum allowed PCLK1 frequency */ 00501 if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) 00502 { 00503 return HAL_ERROR; 00504 } 00505 00506 /* Calculate frequency range */ 00507 freqrange = I2C_FREQRANGE(pclk1); 00508 00509 /*---------------------------- I2Cx CR2 Configuration ----------------------*/ 00510 /* Configure I2Cx: Frequency range */ 00511 MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); 00512 00513 /*---------------------------- I2Cx TRISE Configuration --------------------*/ 00514 /* Configure I2Cx: Rise Time */ 00515 MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); 00516 00517 /*---------------------------- I2Cx CCR Configuration ----------------------*/ 00518 /* Configure I2Cx: Speed */ 00519 MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); 00520 00521 /*---------------------------- I2Cx CR1 Configuration ----------------------*/ 00522 /* Configure I2Cx: Generalcall and NoStretch mode */ 00523 MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); 00524 00525 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ 00526 /* Configure I2Cx: Own Address1 and addressing mode */ 00527 MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); 00528 00529 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ 00530 /* Configure I2Cx: Dual mode and Own Address2 */ 00531 MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); 00532 00533 /* Enable the selected I2C peripheral */ 00534 __HAL_I2C_ENABLE(hi2c); 00535 00536 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 00537 hi2c->State = HAL_I2C_STATE_READY; 00538 hi2c->PreviousState = I2C_STATE_NONE; 00539 hi2c->Mode = HAL_I2C_MODE_NONE; 00540 00541 return HAL_OK; 00542 } 00543 00544 /** 00545 * @brief DeInitialize the I2C peripheral. 00546 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 00547 * the configuration information for the specified I2C. 00548 * @retval HAL status 00549 */ 00550 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) 00551 { 00552 /* Check the I2C handle allocation */ 00553 if (hi2c == NULL) 00554 { 00555 return HAL_ERROR; 00556 } 00557 00558 /* Check the parameters */ 00559 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 00560 00561 hi2c->State = HAL_I2C_STATE_BUSY; 00562 00563 /* Disable the I2C Peripheral Clock */ 00564 __HAL_I2C_DISABLE(hi2c); 00565 00566 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 00567 if (hi2c->MspDeInitCallback == NULL) 00568 { 00569 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ 00570 } 00571 00572 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 00573 hi2c->MspDeInitCallback(hi2c); 00574 #else 00575 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ 00576 HAL_I2C_MspDeInit(hi2c); 00577 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 00578 00579 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 00580 hi2c->State = HAL_I2C_STATE_RESET; 00581 hi2c->PreviousState = I2C_STATE_NONE; 00582 hi2c->Mode = HAL_I2C_MODE_NONE; 00583 00584 /* Release Lock */ 00585 __HAL_UNLOCK(hi2c); 00586 00587 return HAL_OK; 00588 } 00589 00590 /** 00591 * @brief Initialize the I2C MSP. 00592 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 00593 * the configuration information for the specified I2C. 00594 * @retval None 00595 */ 00596 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) 00597 { 00598 /* Prevent unused argument(s) compilation warning */ 00599 UNUSED(hi2c); 00600 00601 /* NOTE : This function should not be modified, when the callback is needed, 00602 the HAL_I2C_MspInit could be implemented in the user file 00603 */ 00604 } 00605 00606 /** 00607 * @brief DeInitialize the I2C MSP. 00608 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 00609 * the configuration information for the specified I2C. 00610 * @retval None 00611 */ 00612 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) 00613 { 00614 /* Prevent unused argument(s) compilation warning */ 00615 UNUSED(hi2c); 00616 00617 /* NOTE : This function should not be modified, when the callback is needed, 00618 the HAL_I2C_MspDeInit could be implemented in the user file 00619 */ 00620 } 00621 00622 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 00623 /** 00624 * @brief Register a User I2C Callback 00625 * To be used instead of the weak predefined callback 00626 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 00627 * the configuration information for the specified I2C. 00628 * @param CallbackID ID of the callback to be registered 00629 * This parameter can be one of the following values: 00630 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID 00631 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID 00632 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID 00633 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID 00634 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID 00635 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID 00636 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID 00637 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID 00638 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID 00639 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID 00640 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID 00641 * @param pCallback pointer to the Callback function 00642 * @retval HAL status 00643 */ 00644 HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) 00645 { 00646 HAL_StatusTypeDef status = HAL_OK; 00647 00648 if (pCallback == NULL) 00649 { 00650 /* Update the error code */ 00651 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00652 00653 return HAL_ERROR; 00654 } 00655 /* Process locked */ 00656 __HAL_LOCK(hi2c); 00657 00658 if (HAL_I2C_STATE_READY == hi2c->State) 00659 { 00660 switch (CallbackID) 00661 { 00662 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : 00663 hi2c->MasterTxCpltCallback = pCallback; 00664 break; 00665 00666 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : 00667 hi2c->MasterRxCpltCallback = pCallback; 00668 break; 00669 00670 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : 00671 hi2c->SlaveTxCpltCallback = pCallback; 00672 break; 00673 00674 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : 00675 hi2c->SlaveRxCpltCallback = pCallback; 00676 break; 00677 00678 case HAL_I2C_LISTEN_COMPLETE_CB_ID : 00679 hi2c->ListenCpltCallback = pCallback; 00680 break; 00681 00682 case HAL_I2C_MEM_TX_COMPLETE_CB_ID : 00683 hi2c->MemTxCpltCallback = pCallback; 00684 break; 00685 00686 case HAL_I2C_MEM_RX_COMPLETE_CB_ID : 00687 hi2c->MemRxCpltCallback = pCallback; 00688 break; 00689 00690 case HAL_I2C_ERROR_CB_ID : 00691 hi2c->ErrorCallback = pCallback; 00692 break; 00693 00694 case HAL_I2C_ABORT_CB_ID : 00695 hi2c->AbortCpltCallback = pCallback; 00696 break; 00697 00698 case HAL_I2C_MSPINIT_CB_ID : 00699 hi2c->MspInitCallback = pCallback; 00700 break; 00701 00702 case HAL_I2C_MSPDEINIT_CB_ID : 00703 hi2c->MspDeInitCallback = pCallback; 00704 break; 00705 00706 default : 00707 /* Update the error code */ 00708 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00709 00710 /* Return error status */ 00711 status = HAL_ERROR; 00712 break; 00713 } 00714 } 00715 else if (HAL_I2C_STATE_RESET == hi2c->State) 00716 { 00717 switch (CallbackID) 00718 { 00719 case HAL_I2C_MSPINIT_CB_ID : 00720 hi2c->MspInitCallback = pCallback; 00721 break; 00722 00723 case HAL_I2C_MSPDEINIT_CB_ID : 00724 hi2c->MspDeInitCallback = pCallback; 00725 break; 00726 00727 default : 00728 /* Update the error code */ 00729 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00730 00731 /* Return error status */ 00732 status = HAL_ERROR; 00733 break; 00734 } 00735 } 00736 else 00737 { 00738 /* Update the error code */ 00739 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00740 00741 /* Return error status */ 00742 status = HAL_ERROR; 00743 } 00744 00745 /* Release Lock */ 00746 __HAL_UNLOCK(hi2c); 00747 return status; 00748 } 00749 00750 /** 00751 * @brief Unregister an I2C Callback 00752 * I2C callback is redirected to the weak predefined callback 00753 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 00754 * the configuration information for the specified I2C. 00755 * @param CallbackID ID of the callback to be unregistered 00756 * This parameter can be one of the following values: 00757 * This parameter can be one of the following values: 00758 * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID 00759 * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID 00760 * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID 00761 * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID 00762 * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID 00763 * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID 00764 * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID 00765 * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID 00766 * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID 00767 * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID 00768 * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID 00769 * @retval HAL status 00770 */ 00771 HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) 00772 { 00773 HAL_StatusTypeDef status = HAL_OK; 00774 00775 /* Process locked */ 00776 __HAL_LOCK(hi2c); 00777 00778 if (HAL_I2C_STATE_READY == hi2c->State) 00779 { 00780 switch (CallbackID) 00781 { 00782 case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : 00783 hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ 00784 break; 00785 00786 case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : 00787 hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ 00788 break; 00789 00790 case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : 00791 hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ 00792 break; 00793 00794 case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : 00795 hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ 00796 break; 00797 00798 case HAL_I2C_LISTEN_COMPLETE_CB_ID : 00799 hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ 00800 break; 00801 00802 case HAL_I2C_MEM_TX_COMPLETE_CB_ID : 00803 hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ 00804 break; 00805 00806 case HAL_I2C_MEM_RX_COMPLETE_CB_ID : 00807 hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ 00808 break; 00809 00810 case HAL_I2C_ERROR_CB_ID : 00811 hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ 00812 break; 00813 00814 case HAL_I2C_ABORT_CB_ID : 00815 hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ 00816 break; 00817 00818 case HAL_I2C_MSPINIT_CB_ID : 00819 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ 00820 break; 00821 00822 case HAL_I2C_MSPDEINIT_CB_ID : 00823 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ 00824 break; 00825 00826 default : 00827 /* Update the error code */ 00828 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00829 00830 /* Return error status */ 00831 status = HAL_ERROR; 00832 break; 00833 } 00834 } 00835 else if (HAL_I2C_STATE_RESET == hi2c->State) 00836 { 00837 switch (CallbackID) 00838 { 00839 case HAL_I2C_MSPINIT_CB_ID : 00840 hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ 00841 break; 00842 00843 case HAL_I2C_MSPDEINIT_CB_ID : 00844 hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ 00845 break; 00846 00847 default : 00848 /* Update the error code */ 00849 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00850 00851 /* Return error status */ 00852 status = HAL_ERROR; 00853 break; 00854 } 00855 } 00856 else 00857 { 00858 /* Update the error code */ 00859 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00860 00861 /* Return error status */ 00862 status = HAL_ERROR; 00863 } 00864 00865 /* Release Lock */ 00866 __HAL_UNLOCK(hi2c); 00867 return status; 00868 } 00869 00870 /** 00871 * @brief Register the Slave Address Match I2C Callback 00872 * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback 00873 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 00874 * the configuration information for the specified I2C. 00875 * @param pCallback pointer to the Address Match Callback function 00876 * @retval HAL status 00877 */ 00878 HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) 00879 { 00880 HAL_StatusTypeDef status = HAL_OK; 00881 00882 if (pCallback == NULL) 00883 { 00884 /* Update the error code */ 00885 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00886 00887 return HAL_ERROR; 00888 } 00889 /* Process locked */ 00890 __HAL_LOCK(hi2c); 00891 00892 if (HAL_I2C_STATE_READY == hi2c->State) 00893 { 00894 hi2c->AddrCallback = pCallback; 00895 } 00896 else 00897 { 00898 /* Update the error code */ 00899 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00900 00901 /* Return error status */ 00902 status = HAL_ERROR; 00903 } 00904 00905 /* Release Lock */ 00906 __HAL_UNLOCK(hi2c); 00907 return status; 00908 } 00909 00910 /** 00911 * @brief UnRegister the Slave Address Match I2C Callback 00912 * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback 00913 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 00914 * the configuration information for the specified I2C. 00915 * @retval HAL status 00916 */ 00917 HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) 00918 { 00919 HAL_StatusTypeDef status = HAL_OK; 00920 00921 /* Process locked */ 00922 __HAL_LOCK(hi2c); 00923 00924 if (HAL_I2C_STATE_READY == hi2c->State) 00925 { 00926 hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ 00927 } 00928 else 00929 { 00930 /* Update the error code */ 00931 hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; 00932 00933 /* Return error status */ 00934 status = HAL_ERROR; 00935 } 00936 00937 /* Release Lock */ 00938 __HAL_UNLOCK(hi2c); 00939 return status; 00940 } 00941 00942 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 00943 00944 /** 00945 * @} 00946 */ 00947 00948 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions 00949 * @brief Data transfers functions 00950 * 00951 @verbatim 00952 =============================================================================== 00953 ##### IO operation functions ##### 00954 =============================================================================== 00955 [..] 00956 This subsection provides a set of functions allowing to manage the I2C data 00957 transfers. 00958 00959 (#) There are two modes of transfer: 00960 (++) Blocking mode : The communication is performed in the polling mode. 00961 The status of all data processing is returned by the same function 00962 after finishing transfer. 00963 (++) No-Blocking mode : The communication is performed using Interrupts 00964 or DMA. These functions return the status of the transfer startup. 00965 The end of the data processing will be indicated through the 00966 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when 00967 using DMA mode. 00968 00969 (#) Blocking mode functions are : 00970 (++) HAL_I2C_Master_Transmit() 00971 (++) HAL_I2C_Master_Receive() 00972 (++) HAL_I2C_Slave_Transmit() 00973 (++) HAL_I2C_Slave_Receive() 00974 (++) HAL_I2C_Mem_Write() 00975 (++) HAL_I2C_Mem_Read() 00976 (++) HAL_I2C_IsDeviceReady() 00977 00978 (#) No-Blocking mode functions with Interrupt are : 00979 (++) HAL_I2C_Master_Transmit_IT() 00980 (++) HAL_I2C_Master_Receive_IT() 00981 (++) HAL_I2C_Slave_Transmit_IT() 00982 (++) HAL_I2C_Slave_Receive_IT() 00983 (++) HAL_I2C_Mem_Write_IT() 00984 (++) HAL_I2C_Mem_Read_IT() 00985 (++) HAL_I2C_Master_Seq_Transmit_IT() 00986 (++) HAL_I2C_Master_Seq_Receive_IT() 00987 (++) HAL_I2C_Slave_Seq_Transmit_IT() 00988 (++) HAL_I2C_Slave_Seq_Receive_IT() 00989 (++) HAL_I2C_EnableListen_IT() 00990 (++) HAL_I2C_DisableListen_IT() 00991 (++) HAL_I2C_Master_Abort_IT() 00992 00993 (#) No-Blocking mode functions with DMA are : 00994 (++) HAL_I2C_Master_Transmit_DMA() 00995 (++) HAL_I2C_Master_Receive_DMA() 00996 (++) HAL_I2C_Slave_Transmit_DMA() 00997 (++) HAL_I2C_Slave_Receive_DMA() 00998 (++) HAL_I2C_Mem_Write_DMA() 00999 (++) HAL_I2C_Mem_Read_DMA() 01000 (++) HAL_I2C_Master_Seq_Transmit_DMA() 01001 (++) HAL_I2C_Master_Seq_Receive_DMA() 01002 (++) HAL_I2C_Slave_Seq_Transmit_DMA() 01003 (++) HAL_I2C_Slave_Seq_Receive_DMA() 01004 01005 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: 01006 (++) HAL_I2C_MasterTxCpltCallback() 01007 (++) HAL_I2C_MasterRxCpltCallback() 01008 (++) HAL_I2C_SlaveTxCpltCallback() 01009 (++) HAL_I2C_SlaveRxCpltCallback() 01010 (++) HAL_I2C_MemTxCpltCallback() 01011 (++) HAL_I2C_MemRxCpltCallback() 01012 (++) HAL_I2C_AddrCallback() 01013 (++) HAL_I2C_ListenCpltCallback() 01014 (++) HAL_I2C_ErrorCallback() 01015 (++) HAL_I2C_AbortCpltCallback() 01016 01017 @endverbatim 01018 * @{ 01019 */ 01020 01021 /** 01022 * @brief Transmits in master mode an amount of data in blocking mode. 01023 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01024 * the configuration information for the specified I2C. 01025 * @param DevAddress Target device address: The device 7 bits address value 01026 * in datasheet must be shifted to the left before calling the interface 01027 * @param pData Pointer to data buffer 01028 * @param Size Amount of data to be sent 01029 * @param Timeout Timeout duration 01030 * @retval HAL status 01031 */ 01032 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) 01033 { 01034 /* Init tickstart for timeout management*/ 01035 uint32_t tickstart = HAL_GetTick(); 01036 01037 if (hi2c->State == HAL_I2C_STATE_READY) 01038 { 01039 /* Wait until BUSY flag is reset */ 01040 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 01041 { 01042 return HAL_BUSY; 01043 } 01044 01045 /* Process Locked */ 01046 __HAL_LOCK(hi2c); 01047 01048 /* Check if the I2C is already enabled */ 01049 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01050 { 01051 /* Enable I2C peripheral */ 01052 __HAL_I2C_ENABLE(hi2c); 01053 } 01054 01055 /* Disable Pos */ 01056 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01057 01058 hi2c->State = HAL_I2C_STATE_BUSY_TX; 01059 hi2c->Mode = HAL_I2C_MODE_MASTER; 01060 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01061 01062 /* Prepare transfer parameters */ 01063 hi2c->pBuffPtr = pData; 01064 hi2c->XferCount = Size; 01065 hi2c->XferSize = hi2c->XferCount; 01066 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01067 01068 /* Send Slave Address */ 01069 if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) 01070 { 01071 return HAL_ERROR; 01072 } 01073 01074 /* Clear ADDR flag */ 01075 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 01076 01077 while (hi2c->XferSize > 0U) 01078 { 01079 /* Wait until TXE flag is set */ 01080 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 01081 { 01082 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 01083 { 01084 /* Generate Stop */ 01085 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 01086 } 01087 return HAL_ERROR; 01088 } 01089 01090 /* Write data to DR */ 01091 hi2c->Instance->DR = *hi2c->pBuffPtr; 01092 01093 /* Increment Buffer pointer */ 01094 hi2c->pBuffPtr++; 01095 01096 /* Update counter */ 01097 hi2c->XferCount--; 01098 hi2c->XferSize--; 01099 01100 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 01101 { 01102 /* Write data to DR */ 01103 hi2c->Instance->DR = *hi2c->pBuffPtr; 01104 01105 /* Increment Buffer pointer */ 01106 hi2c->pBuffPtr++; 01107 01108 /* Update counter */ 01109 hi2c->XferCount--; 01110 hi2c->XferSize--; 01111 } 01112 01113 /* Wait until BTF flag is set */ 01114 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 01115 { 01116 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 01117 { 01118 /* Generate Stop */ 01119 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 01120 } 01121 return HAL_ERROR; 01122 } 01123 } 01124 01125 /* Generate Stop */ 01126 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 01127 01128 hi2c->State = HAL_I2C_STATE_READY; 01129 hi2c->Mode = HAL_I2C_MODE_NONE; 01130 01131 /* Process Unlocked */ 01132 __HAL_UNLOCK(hi2c); 01133 01134 return HAL_OK; 01135 } 01136 else 01137 { 01138 return HAL_BUSY; 01139 } 01140 } 01141 01142 /** 01143 * @brief Receives in master mode an amount of data in blocking mode. 01144 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01145 * the configuration information for the specified I2C. 01146 * @param DevAddress Target device address: The device 7 bits address value 01147 * in datasheet must be shifted to the left before calling the interface 01148 * @param pData Pointer to data buffer 01149 * @param Size Amount of data to be sent 01150 * @param Timeout Timeout duration 01151 * @retval HAL status 01152 */ 01153 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) 01154 { 01155 /* Init tickstart for timeout management*/ 01156 uint32_t tickstart = HAL_GetTick(); 01157 01158 if (hi2c->State == HAL_I2C_STATE_READY) 01159 { 01160 /* Wait until BUSY flag is reset */ 01161 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 01162 { 01163 return HAL_BUSY; 01164 } 01165 01166 /* Process Locked */ 01167 __HAL_LOCK(hi2c); 01168 01169 /* Check if the I2C is already enabled */ 01170 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01171 { 01172 /* Enable I2C peripheral */ 01173 __HAL_I2C_ENABLE(hi2c); 01174 } 01175 01176 /* Disable Pos */ 01177 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01178 01179 hi2c->State = HAL_I2C_STATE_BUSY_RX; 01180 hi2c->Mode = HAL_I2C_MODE_MASTER; 01181 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01182 01183 /* Prepare transfer parameters */ 01184 hi2c->pBuffPtr = pData; 01185 hi2c->XferCount = Size; 01186 hi2c->XferSize = hi2c->XferCount; 01187 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01188 01189 /* Send Slave Address */ 01190 if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) 01191 { 01192 return HAL_ERROR; 01193 } 01194 01195 if (hi2c->XferSize == 0U) 01196 { 01197 /* Clear ADDR flag */ 01198 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 01199 01200 /* Generate Stop */ 01201 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 01202 } 01203 else if (hi2c->XferSize == 1U) 01204 { 01205 /* Disable Acknowledge */ 01206 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01207 01208 /* Clear ADDR flag */ 01209 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 01210 01211 /* Generate Stop */ 01212 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 01213 } 01214 else if (hi2c->XferSize == 2U) 01215 { 01216 /* Disable Acknowledge */ 01217 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01218 01219 /* Enable Pos */ 01220 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01221 01222 /* Clear ADDR flag */ 01223 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 01224 } 01225 else 01226 { 01227 /* Enable Acknowledge */ 01228 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01229 01230 /* Clear ADDR flag */ 01231 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 01232 } 01233 01234 while (hi2c->XferSize > 0U) 01235 { 01236 if (hi2c->XferSize <= 3U) 01237 { 01238 /* One byte */ 01239 if (hi2c->XferSize == 1U) 01240 { 01241 /* Wait until RXNE flag is set */ 01242 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 01243 { 01244 return HAL_ERROR; 01245 } 01246 01247 /* Read data from DR */ 01248 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01249 01250 /* Increment Buffer pointer */ 01251 hi2c->pBuffPtr++; 01252 01253 /* Update counter */ 01254 hi2c->XferSize--; 01255 hi2c->XferCount--; 01256 } 01257 /* Two bytes */ 01258 else if (hi2c->XferSize == 2U) 01259 { 01260 /* Wait until BTF flag is set */ 01261 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 01262 { 01263 return HAL_ERROR; 01264 } 01265 01266 /* Generate Stop */ 01267 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 01268 01269 /* Read data from DR */ 01270 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01271 01272 /* Increment Buffer pointer */ 01273 hi2c->pBuffPtr++; 01274 01275 /* Update counter */ 01276 hi2c->XferSize--; 01277 hi2c->XferCount--; 01278 01279 /* Read data from DR */ 01280 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01281 01282 /* Increment Buffer pointer */ 01283 hi2c->pBuffPtr++; 01284 01285 /* Update counter */ 01286 hi2c->XferSize--; 01287 hi2c->XferCount--; 01288 } 01289 /* 3 Last bytes */ 01290 else 01291 { 01292 /* Wait until BTF flag is set */ 01293 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 01294 { 01295 return HAL_ERROR; 01296 } 01297 01298 /* Disable Acknowledge */ 01299 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01300 01301 /* Read data from DR */ 01302 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01303 01304 /* Increment Buffer pointer */ 01305 hi2c->pBuffPtr++; 01306 01307 /* Update counter */ 01308 hi2c->XferSize--; 01309 hi2c->XferCount--; 01310 01311 /* Wait until BTF flag is set */ 01312 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 01313 { 01314 return HAL_ERROR; 01315 } 01316 01317 /* Generate Stop */ 01318 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 01319 01320 /* Read data from DR */ 01321 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01322 01323 /* Increment Buffer pointer */ 01324 hi2c->pBuffPtr++; 01325 01326 /* Update counter */ 01327 hi2c->XferSize--; 01328 hi2c->XferCount--; 01329 01330 /* Read data from DR */ 01331 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01332 01333 /* Increment Buffer pointer */ 01334 hi2c->pBuffPtr++; 01335 01336 /* Update counter */ 01337 hi2c->XferSize--; 01338 hi2c->XferCount--; 01339 } 01340 } 01341 else 01342 { 01343 /* Wait until RXNE flag is set */ 01344 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 01345 { 01346 return HAL_ERROR; 01347 } 01348 01349 /* Read data from DR */ 01350 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01351 01352 /* Increment Buffer pointer */ 01353 hi2c->pBuffPtr++; 01354 01355 /* Update counter */ 01356 hi2c->XferSize--; 01357 hi2c->XferCount--; 01358 01359 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 01360 { 01361 /* Read data from DR */ 01362 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01363 01364 /* Increment Buffer pointer */ 01365 hi2c->pBuffPtr++; 01366 01367 /* Update counter */ 01368 hi2c->XferSize--; 01369 hi2c->XferCount--; 01370 } 01371 } 01372 } 01373 01374 hi2c->State = HAL_I2C_STATE_READY; 01375 hi2c->Mode = HAL_I2C_MODE_NONE; 01376 01377 /* Process Unlocked */ 01378 __HAL_UNLOCK(hi2c); 01379 01380 return HAL_OK; 01381 } 01382 else 01383 { 01384 return HAL_BUSY; 01385 } 01386 } 01387 01388 /** 01389 * @brief Transmits in slave mode an amount of data in blocking mode. 01390 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01391 * the configuration information for the specified I2C. 01392 * @param pData Pointer to data buffer 01393 * @param Size Amount of data to be sent 01394 * @param Timeout Timeout duration 01395 * @retval HAL status 01396 */ 01397 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) 01398 { 01399 /* Init tickstart for timeout management*/ 01400 uint32_t tickstart = HAL_GetTick(); 01401 01402 if (hi2c->State == HAL_I2C_STATE_READY) 01403 { 01404 if ((pData == NULL) || (Size == 0U)) 01405 { 01406 return HAL_ERROR; 01407 } 01408 01409 /* Process Locked */ 01410 __HAL_LOCK(hi2c); 01411 01412 /* Check if the I2C is already enabled */ 01413 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01414 { 01415 /* Enable I2C peripheral */ 01416 __HAL_I2C_ENABLE(hi2c); 01417 } 01418 01419 /* Disable Pos */ 01420 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01421 01422 hi2c->State = HAL_I2C_STATE_BUSY_TX; 01423 hi2c->Mode = HAL_I2C_MODE_SLAVE; 01424 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01425 01426 /* Prepare transfer parameters */ 01427 hi2c->pBuffPtr = pData; 01428 hi2c->XferCount = Size; 01429 hi2c->XferSize = hi2c->XferCount; 01430 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01431 01432 /* Enable Address Acknowledge */ 01433 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01434 01435 /* Wait until ADDR flag is set */ 01436 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) 01437 { 01438 return HAL_ERROR; 01439 } 01440 01441 /* Clear ADDR flag */ 01442 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 01443 01444 /* If 10bit addressing mode is selected */ 01445 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) 01446 { 01447 /* Wait until ADDR flag is set */ 01448 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) 01449 { 01450 return HAL_ERROR; 01451 } 01452 01453 /* Clear ADDR flag */ 01454 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 01455 } 01456 01457 while (hi2c->XferSize > 0U) 01458 { 01459 /* Wait until TXE flag is set */ 01460 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 01461 { 01462 /* Disable Address Acknowledge */ 01463 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01464 01465 return HAL_ERROR; 01466 } 01467 01468 /* Write data to DR */ 01469 hi2c->Instance->DR = *hi2c->pBuffPtr; 01470 01471 /* Increment Buffer pointer */ 01472 hi2c->pBuffPtr++; 01473 01474 /* Update counter */ 01475 hi2c->XferCount--; 01476 hi2c->XferSize--; 01477 01478 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 01479 { 01480 /* Write data to DR */ 01481 hi2c->Instance->DR = *hi2c->pBuffPtr; 01482 01483 /* Increment Buffer pointer */ 01484 hi2c->pBuffPtr++; 01485 01486 /* Update counter */ 01487 hi2c->XferCount--; 01488 hi2c->XferSize--; 01489 } 01490 } 01491 01492 /* Wait until AF flag is set */ 01493 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) 01494 { 01495 return HAL_ERROR; 01496 } 01497 01498 /* Clear AF flag */ 01499 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 01500 01501 /* Disable Address Acknowledge */ 01502 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01503 01504 hi2c->State = HAL_I2C_STATE_READY; 01505 hi2c->Mode = HAL_I2C_MODE_NONE; 01506 01507 /* Process Unlocked */ 01508 __HAL_UNLOCK(hi2c); 01509 01510 return HAL_OK; 01511 } 01512 else 01513 { 01514 return HAL_BUSY; 01515 } 01516 } 01517 01518 /** 01519 * @brief Receive in slave mode an amount of data in blocking mode 01520 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01521 * the configuration information for the specified I2C. 01522 * @param pData Pointer to data buffer 01523 * @param Size Amount of data to be sent 01524 * @param Timeout Timeout duration 01525 * @retval HAL status 01526 */ 01527 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) 01528 { 01529 /* Init tickstart for timeout management*/ 01530 uint32_t tickstart = HAL_GetTick(); 01531 01532 if (hi2c->State == HAL_I2C_STATE_READY) 01533 { 01534 if ((pData == NULL) || (Size == (uint16_t)0)) 01535 { 01536 return HAL_ERROR; 01537 } 01538 01539 /* Process Locked */ 01540 __HAL_LOCK(hi2c); 01541 01542 /* Check if the I2C is already enabled */ 01543 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01544 { 01545 /* Enable I2C peripheral */ 01546 __HAL_I2C_ENABLE(hi2c); 01547 } 01548 01549 /* Disable Pos */ 01550 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01551 01552 hi2c->State = HAL_I2C_STATE_BUSY_RX; 01553 hi2c->Mode = HAL_I2C_MODE_SLAVE; 01554 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01555 01556 /* Prepare transfer parameters */ 01557 hi2c->pBuffPtr = pData; 01558 hi2c->XferCount = Size; 01559 hi2c->XferSize = hi2c->XferCount; 01560 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01561 01562 /* Enable Address Acknowledge */ 01563 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01564 01565 /* Wait until ADDR flag is set */ 01566 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) 01567 { 01568 return HAL_ERROR; 01569 } 01570 01571 /* Clear ADDR flag */ 01572 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 01573 01574 while (hi2c->XferSize > 0U) 01575 { 01576 /* Wait until RXNE flag is set */ 01577 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 01578 { 01579 /* Disable Address Acknowledge */ 01580 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01581 01582 return HAL_ERROR; 01583 } 01584 01585 /* Read data from DR */ 01586 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01587 01588 /* Increment Buffer pointer */ 01589 hi2c->pBuffPtr++; 01590 01591 /* Update counter */ 01592 hi2c->XferSize--; 01593 hi2c->XferCount--; 01594 01595 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 01596 { 01597 /* Read data from DR */ 01598 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 01599 01600 /* Increment Buffer pointer */ 01601 hi2c->pBuffPtr++; 01602 01603 /* Update counter */ 01604 hi2c->XferSize--; 01605 hi2c->XferCount--; 01606 } 01607 } 01608 01609 /* Wait until STOP flag is set */ 01610 if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 01611 { 01612 /* Disable Address Acknowledge */ 01613 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01614 01615 return HAL_ERROR; 01616 } 01617 01618 /* Clear STOP flag */ 01619 __HAL_I2C_CLEAR_STOPFLAG(hi2c); 01620 01621 /* Disable Address Acknowledge */ 01622 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01623 01624 hi2c->State = HAL_I2C_STATE_READY; 01625 hi2c->Mode = HAL_I2C_MODE_NONE; 01626 01627 /* Process Unlocked */ 01628 __HAL_UNLOCK(hi2c); 01629 01630 return HAL_OK; 01631 } 01632 else 01633 { 01634 return HAL_BUSY; 01635 } 01636 } 01637 01638 /** 01639 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt 01640 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01641 * the configuration information for the specified I2C. 01642 * @param DevAddress Target device address: The device 7 bits address value 01643 * in datasheet must be shifted to the left before calling the interface 01644 * @param pData Pointer to data buffer 01645 * @param Size Amount of data to be sent 01646 * @retval HAL status 01647 */ 01648 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) 01649 { 01650 __IO uint32_t count = 0U; 01651 01652 if (hi2c->State == HAL_I2C_STATE_READY) 01653 { 01654 /* Wait until BUSY flag is reset */ 01655 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 01656 do 01657 { 01658 count--; 01659 if (count == 0U) 01660 { 01661 hi2c->PreviousState = I2C_STATE_NONE; 01662 hi2c->State = HAL_I2C_STATE_READY; 01663 hi2c->Mode = HAL_I2C_MODE_NONE; 01664 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 01665 01666 /* Process Unlocked */ 01667 __HAL_UNLOCK(hi2c); 01668 01669 return HAL_ERROR; 01670 } 01671 } 01672 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 01673 01674 /* Process Locked */ 01675 __HAL_LOCK(hi2c); 01676 01677 /* Check if the I2C is already enabled */ 01678 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01679 { 01680 /* Enable I2C peripheral */ 01681 __HAL_I2C_ENABLE(hi2c); 01682 } 01683 01684 /* Disable Pos */ 01685 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01686 01687 hi2c->State = HAL_I2C_STATE_BUSY_TX; 01688 hi2c->Mode = HAL_I2C_MODE_MASTER; 01689 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01690 01691 /* Prepare transfer parameters */ 01692 hi2c->pBuffPtr = pData; 01693 hi2c->XferCount = Size; 01694 hi2c->XferSize = hi2c->XferCount; 01695 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01696 hi2c->Devaddress = DevAddress; 01697 01698 /* Process Unlocked */ 01699 __HAL_UNLOCK(hi2c); 01700 01701 /* Note : The I2C interrupts must be enabled after unlocking current process 01702 to avoid the risk of I2C interrupt handle execution before current 01703 process unlock */ 01704 /* Enable EVT, BUF and ERR interrupt */ 01705 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 01706 01707 /* Generate Start */ 01708 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 01709 01710 return HAL_OK; 01711 } 01712 else 01713 { 01714 return HAL_BUSY; 01715 } 01716 } 01717 01718 /** 01719 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt 01720 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01721 * the configuration information for the specified I2C. 01722 * @param DevAddress Target device address: The device 7 bits address value 01723 * in datasheet must be shifted to the left before calling the interface 01724 * @param pData Pointer to data buffer 01725 * @param Size Amount of data to be sent 01726 * @retval HAL status 01727 */ 01728 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) 01729 { 01730 __IO uint32_t count = 0U; 01731 01732 if (hi2c->State == HAL_I2C_STATE_READY) 01733 { 01734 /* Wait until BUSY flag is reset */ 01735 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 01736 do 01737 { 01738 count--; 01739 if (count == 0U) 01740 { 01741 hi2c->PreviousState = I2C_STATE_NONE; 01742 hi2c->State = HAL_I2C_STATE_READY; 01743 hi2c->Mode = HAL_I2C_MODE_NONE; 01744 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 01745 01746 /* Process Unlocked */ 01747 __HAL_UNLOCK(hi2c); 01748 01749 return HAL_ERROR; 01750 } 01751 } 01752 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 01753 01754 /* Process Locked */ 01755 __HAL_LOCK(hi2c); 01756 01757 /* Check if the I2C is already enabled */ 01758 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01759 { 01760 /* Enable I2C peripheral */ 01761 __HAL_I2C_ENABLE(hi2c); 01762 } 01763 01764 /* Disable Pos */ 01765 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01766 01767 hi2c->State = HAL_I2C_STATE_BUSY_RX; 01768 hi2c->Mode = HAL_I2C_MODE_MASTER; 01769 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01770 01771 /* Prepare transfer parameters */ 01772 hi2c->pBuffPtr = pData; 01773 hi2c->XferCount = Size; 01774 hi2c->XferSize = hi2c->XferCount; 01775 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01776 hi2c->Devaddress = DevAddress; 01777 01778 01779 /* Process Unlocked */ 01780 __HAL_UNLOCK(hi2c); 01781 01782 /* Note : The I2C interrupts must be enabled after unlocking current process 01783 to avoid the risk of I2C interrupt handle execution before current 01784 process unlock */ 01785 01786 /* Enable EVT, BUF and ERR interrupt */ 01787 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 01788 01789 /* Enable Acknowledge */ 01790 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01791 01792 /* Generate Start */ 01793 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 01794 01795 return HAL_OK; 01796 } 01797 else 01798 { 01799 return HAL_BUSY; 01800 } 01801 } 01802 01803 /** 01804 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt 01805 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01806 * the configuration information for the specified I2C. 01807 * @param pData Pointer to data buffer 01808 * @param Size Amount of data to be sent 01809 * @retval HAL status 01810 */ 01811 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) 01812 { 01813 01814 if (hi2c->State == HAL_I2C_STATE_READY) 01815 { 01816 if ((pData == NULL) || (Size == 0U)) 01817 { 01818 return HAL_ERROR; 01819 } 01820 01821 /* Process Locked */ 01822 __HAL_LOCK(hi2c); 01823 01824 /* Check if the I2C is already enabled */ 01825 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01826 { 01827 /* Enable I2C peripheral */ 01828 __HAL_I2C_ENABLE(hi2c); 01829 } 01830 01831 /* Disable Pos */ 01832 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01833 01834 hi2c->State = HAL_I2C_STATE_BUSY_TX; 01835 hi2c->Mode = HAL_I2C_MODE_SLAVE; 01836 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01837 01838 /* Prepare transfer parameters */ 01839 hi2c->pBuffPtr = pData; 01840 hi2c->XferCount = Size; 01841 hi2c->XferSize = hi2c->XferCount; 01842 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01843 01844 /* Enable Address Acknowledge */ 01845 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01846 01847 /* Process Unlocked */ 01848 __HAL_UNLOCK(hi2c); 01849 01850 /* Note : The I2C interrupts must be enabled after unlocking current process 01851 to avoid the risk of I2C interrupt handle execution before current 01852 process unlock */ 01853 01854 /* Enable EVT, BUF and ERR interrupt */ 01855 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 01856 01857 return HAL_OK; 01858 } 01859 else 01860 { 01861 return HAL_BUSY; 01862 } 01863 } 01864 01865 /** 01866 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt 01867 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01868 * the configuration information for the specified I2C. 01869 * @param pData Pointer to data buffer 01870 * @param Size Amount of data to be sent 01871 * @retval HAL status 01872 */ 01873 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) 01874 { 01875 01876 if (hi2c->State == HAL_I2C_STATE_READY) 01877 { 01878 if ((pData == NULL) || (Size == 0U)) 01879 { 01880 return HAL_ERROR; 01881 } 01882 01883 /* Process Locked */ 01884 __HAL_LOCK(hi2c); 01885 01886 /* Check if the I2C is already enabled */ 01887 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01888 { 01889 /* Enable I2C peripheral */ 01890 __HAL_I2C_ENABLE(hi2c); 01891 } 01892 01893 /* Disable Pos */ 01894 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01895 01896 hi2c->State = HAL_I2C_STATE_BUSY_RX; 01897 hi2c->Mode = HAL_I2C_MODE_SLAVE; 01898 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01899 01900 /* Prepare transfer parameters */ 01901 hi2c->pBuffPtr = pData; 01902 hi2c->XferCount = Size; 01903 hi2c->XferSize = hi2c->XferCount; 01904 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01905 01906 /* Enable Address Acknowledge */ 01907 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 01908 01909 /* Process Unlocked */ 01910 __HAL_UNLOCK(hi2c); 01911 01912 /* Note : The I2C interrupts must be enabled after unlocking current process 01913 to avoid the risk of I2C interrupt handle execution before current 01914 process unlock */ 01915 01916 /* Enable EVT, BUF and ERR interrupt */ 01917 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 01918 01919 return HAL_OK; 01920 } 01921 else 01922 { 01923 return HAL_BUSY; 01924 } 01925 } 01926 01927 /** 01928 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA 01929 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 01930 * the configuration information for the specified I2C. 01931 * @param DevAddress Target device address: The device 7 bits address value 01932 * in datasheet must be shifted to the left before calling the interface 01933 * @param pData Pointer to data buffer 01934 * @param Size Amount of data to be sent 01935 * @retval HAL status 01936 */ 01937 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) 01938 { 01939 __IO uint32_t count = 0U; 01940 HAL_StatusTypeDef dmaxferstatus; 01941 01942 if (hi2c->State == HAL_I2C_STATE_READY) 01943 { 01944 /* Wait until BUSY flag is reset */ 01945 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 01946 do 01947 { 01948 count--; 01949 if (count == 0U) 01950 { 01951 hi2c->PreviousState = I2C_STATE_NONE; 01952 hi2c->State = HAL_I2C_STATE_READY; 01953 hi2c->Mode = HAL_I2C_MODE_NONE; 01954 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 01955 01956 /* Process Unlocked */ 01957 __HAL_UNLOCK(hi2c); 01958 01959 return HAL_ERROR; 01960 } 01961 } 01962 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 01963 01964 /* Process Locked */ 01965 __HAL_LOCK(hi2c); 01966 01967 /* Check if the I2C is already enabled */ 01968 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 01969 { 01970 /* Enable I2C peripheral */ 01971 __HAL_I2C_ENABLE(hi2c); 01972 } 01973 01974 /* Disable Pos */ 01975 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 01976 01977 hi2c->State = HAL_I2C_STATE_BUSY_TX; 01978 hi2c->Mode = HAL_I2C_MODE_MASTER; 01979 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 01980 01981 /* Prepare transfer parameters */ 01982 hi2c->pBuffPtr = pData; 01983 hi2c->XferCount = Size; 01984 hi2c->XferSize = hi2c->XferCount; 01985 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 01986 hi2c->Devaddress = DevAddress; 01987 01988 if (hi2c->XferSize > 0U) 01989 { 01990 if (hi2c->hdmatx != NULL) 01991 { 01992 /* Set the I2C DMA transfer complete callback */ 01993 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 01994 01995 /* Set the DMA error callback */ 01996 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 01997 01998 /* Set the unused DMA callbacks to NULL */ 01999 hi2c->hdmatx->XferHalfCpltCallback = NULL; 02000 hi2c->hdmatx->XferM1CpltCallback = NULL; 02001 hi2c->hdmatx->XferM1HalfCpltCallback = NULL; 02002 hi2c->hdmatx->XferAbortCallback = NULL; 02003 02004 /* Enable the DMA stream */ 02005 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 02006 } 02007 else 02008 { 02009 /* Update I2C state */ 02010 hi2c->State = HAL_I2C_STATE_READY; 02011 hi2c->Mode = HAL_I2C_MODE_NONE; 02012 02013 /* Update I2C error code */ 02014 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 02015 02016 /* Process Unlocked */ 02017 __HAL_UNLOCK(hi2c); 02018 02019 return HAL_ERROR; 02020 } 02021 02022 if (dmaxferstatus == HAL_OK) 02023 { 02024 /* Process Unlocked */ 02025 __HAL_UNLOCK(hi2c); 02026 02027 /* Note : The I2C interrupts must be enabled after unlocking current process 02028 to avoid the risk of I2C interrupt handle execution before current 02029 process unlock */ 02030 02031 /* Enable EVT and ERR interrupt */ 02032 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 02033 02034 /* Enable DMA Request */ 02035 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 02036 02037 /* Enable Acknowledge */ 02038 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02039 02040 /* Generate Start */ 02041 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 02042 } 02043 else 02044 { 02045 /* Update I2C state */ 02046 hi2c->State = HAL_I2C_STATE_READY; 02047 hi2c->Mode = HAL_I2C_MODE_NONE; 02048 02049 /* Update I2C error code */ 02050 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 02051 02052 /* Process Unlocked */ 02053 __HAL_UNLOCK(hi2c); 02054 02055 return HAL_ERROR; 02056 } 02057 } 02058 else 02059 { 02060 /* Enable Acknowledge */ 02061 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02062 02063 /* Generate Start */ 02064 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 02065 02066 /* Process Unlocked */ 02067 __HAL_UNLOCK(hi2c); 02068 02069 /* Note : The I2C interrupts must be enabled after unlocking current process 02070 to avoid the risk of I2C interrupt handle execution before current 02071 process unlock */ 02072 02073 /* Enable EVT, BUF and ERR interrupt */ 02074 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 02075 } 02076 02077 return HAL_OK; 02078 } 02079 else 02080 { 02081 return HAL_BUSY; 02082 } 02083 } 02084 02085 /** 02086 * @brief Receive in master mode an amount of data in non-blocking mode with DMA 02087 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 02088 * the configuration information for the specified I2C. 02089 * @param DevAddress Target device address: The device 7 bits address value 02090 * in datasheet must be shifted to the left before calling the interface 02091 * @param pData Pointer to data buffer 02092 * @param Size Amount of data to be sent 02093 * @retval HAL status 02094 */ 02095 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) 02096 { 02097 __IO uint32_t count = 0U; 02098 HAL_StatusTypeDef dmaxferstatus; 02099 02100 if (hi2c->State == HAL_I2C_STATE_READY) 02101 { 02102 /* Wait until BUSY flag is reset */ 02103 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 02104 do 02105 { 02106 count--; 02107 if (count == 0U) 02108 { 02109 hi2c->PreviousState = I2C_STATE_NONE; 02110 hi2c->State = HAL_I2C_STATE_READY; 02111 hi2c->Mode = HAL_I2C_MODE_NONE; 02112 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 02113 02114 /* Process Unlocked */ 02115 __HAL_UNLOCK(hi2c); 02116 02117 return HAL_ERROR; 02118 } 02119 } 02120 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 02121 02122 /* Process Locked */ 02123 __HAL_LOCK(hi2c); 02124 02125 /* Check if the I2C is already enabled */ 02126 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 02127 { 02128 /* Enable I2C peripheral */ 02129 __HAL_I2C_ENABLE(hi2c); 02130 } 02131 02132 /* Disable Pos */ 02133 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 02134 02135 hi2c->State = HAL_I2C_STATE_BUSY_RX; 02136 hi2c->Mode = HAL_I2C_MODE_MASTER; 02137 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 02138 02139 /* Prepare transfer parameters */ 02140 hi2c->pBuffPtr = pData; 02141 hi2c->XferCount = Size; 02142 hi2c->XferSize = hi2c->XferCount; 02143 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 02144 hi2c->Devaddress = DevAddress; 02145 02146 if (hi2c->XferSize > 0U) 02147 { 02148 if (hi2c->hdmarx != NULL) 02149 { 02150 /* Set the I2C DMA transfer complete callback */ 02151 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 02152 02153 /* Set the DMA error callback */ 02154 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 02155 02156 /* Set the unused DMA callbacks to NULL */ 02157 hi2c->hdmarx->XferHalfCpltCallback = NULL; 02158 hi2c->hdmarx->XferM1CpltCallback = NULL; 02159 hi2c->hdmarx->XferM1HalfCpltCallback = NULL; 02160 hi2c->hdmarx->XferAbortCallback = NULL; 02161 02162 /* Enable the DMA stream */ 02163 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 02164 } 02165 else 02166 { 02167 /* Update I2C state */ 02168 hi2c->State = HAL_I2C_STATE_READY; 02169 hi2c->Mode = HAL_I2C_MODE_NONE; 02170 02171 /* Update I2C error code */ 02172 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 02173 02174 /* Process Unlocked */ 02175 __HAL_UNLOCK(hi2c); 02176 02177 return HAL_ERROR; 02178 } 02179 02180 if (dmaxferstatus == HAL_OK) 02181 { 02182 /* Enable Acknowledge */ 02183 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02184 02185 /* Generate Start */ 02186 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 02187 02188 /* Process Unlocked */ 02189 __HAL_UNLOCK(hi2c); 02190 02191 /* Note : The I2C interrupts must be enabled after unlocking current process 02192 to avoid the risk of I2C interrupt handle execution before current 02193 process unlock */ 02194 02195 /* Enable EVT and ERR interrupt */ 02196 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 02197 02198 /* Enable DMA Request */ 02199 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 02200 } 02201 else 02202 { 02203 /* Update I2C state */ 02204 hi2c->State = HAL_I2C_STATE_READY; 02205 hi2c->Mode = HAL_I2C_MODE_NONE; 02206 02207 /* Update I2C error code */ 02208 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 02209 02210 /* Process Unlocked */ 02211 __HAL_UNLOCK(hi2c); 02212 02213 return HAL_ERROR; 02214 } 02215 } 02216 else 02217 { 02218 /* Process Unlocked */ 02219 __HAL_UNLOCK(hi2c); 02220 02221 /* Note : The I2C interrupts must be enabled after unlocking current process 02222 to avoid the risk of I2C interrupt handle execution before current 02223 process unlock */ 02224 02225 /* Enable EVT, BUF and ERR interrupt */ 02226 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 02227 02228 /* Enable Acknowledge */ 02229 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02230 02231 /* Generate Start */ 02232 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 02233 } 02234 02235 return HAL_OK; 02236 } 02237 else 02238 { 02239 return HAL_BUSY; 02240 } 02241 } 02242 02243 /** 02244 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA 02245 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 02246 * the configuration information for the specified I2C. 02247 * @param pData Pointer to data buffer 02248 * @param Size Amount of data to be sent 02249 * @retval HAL status 02250 */ 02251 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) 02252 { 02253 HAL_StatusTypeDef dmaxferstatus; 02254 02255 if (hi2c->State == HAL_I2C_STATE_READY) 02256 { 02257 if ((pData == NULL) || (Size == 0U)) 02258 { 02259 return HAL_ERROR; 02260 } 02261 02262 /* Process Locked */ 02263 __HAL_LOCK(hi2c); 02264 02265 /* Check if the I2C is already enabled */ 02266 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 02267 { 02268 /* Enable I2C peripheral */ 02269 __HAL_I2C_ENABLE(hi2c); 02270 } 02271 02272 /* Disable Pos */ 02273 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 02274 02275 hi2c->State = HAL_I2C_STATE_BUSY_TX; 02276 hi2c->Mode = HAL_I2C_MODE_SLAVE; 02277 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 02278 02279 /* Prepare transfer parameters */ 02280 hi2c->pBuffPtr = pData; 02281 hi2c->XferCount = Size; 02282 hi2c->XferSize = hi2c->XferCount; 02283 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 02284 02285 if (hi2c->hdmatx != NULL) 02286 { 02287 /* Set the I2C DMA transfer complete callback */ 02288 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 02289 02290 /* Set the DMA error callback */ 02291 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 02292 02293 /* Set the unused DMA callbacks to NULL */ 02294 hi2c->hdmatx->XferHalfCpltCallback = NULL; 02295 hi2c->hdmatx->XferM1CpltCallback = NULL; 02296 hi2c->hdmatx->XferM1HalfCpltCallback = NULL; 02297 hi2c->hdmatx->XferAbortCallback = NULL; 02298 02299 /* Enable the DMA stream */ 02300 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 02301 } 02302 else 02303 { 02304 /* Update I2C state */ 02305 hi2c->State = HAL_I2C_STATE_LISTEN; 02306 hi2c->Mode = HAL_I2C_MODE_NONE; 02307 02308 /* Update I2C error code */ 02309 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 02310 02311 /* Process Unlocked */ 02312 __HAL_UNLOCK(hi2c); 02313 02314 return HAL_ERROR; 02315 } 02316 02317 if (dmaxferstatus == HAL_OK) 02318 { 02319 /* Enable Address Acknowledge */ 02320 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02321 02322 /* Process Unlocked */ 02323 __HAL_UNLOCK(hi2c); 02324 02325 /* Note : The I2C interrupts must be enabled after unlocking current process 02326 to avoid the risk of I2C interrupt handle execution before current 02327 process unlock */ 02328 /* Enable EVT and ERR interrupt */ 02329 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 02330 02331 /* Enable DMA Request */ 02332 hi2c->Instance->CR2 |= I2C_CR2_DMAEN; 02333 02334 return HAL_OK; 02335 } 02336 else 02337 { 02338 /* Update I2C state */ 02339 hi2c->State = HAL_I2C_STATE_READY; 02340 hi2c->Mode = HAL_I2C_MODE_NONE; 02341 02342 /* Update I2C error code */ 02343 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 02344 02345 /* Process Unlocked */ 02346 __HAL_UNLOCK(hi2c); 02347 02348 return HAL_ERROR; 02349 } 02350 } 02351 else 02352 { 02353 return HAL_BUSY; 02354 } 02355 } 02356 02357 /** 02358 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA 02359 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 02360 * the configuration information for the specified I2C. 02361 * @param pData Pointer to data buffer 02362 * @param Size Amount of data to be sent 02363 * @retval HAL status 02364 */ 02365 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) 02366 { 02367 HAL_StatusTypeDef dmaxferstatus; 02368 02369 if (hi2c->State == HAL_I2C_STATE_READY) 02370 { 02371 if ((pData == NULL) || (Size == 0U)) 02372 { 02373 return HAL_ERROR; 02374 } 02375 02376 /* Process Locked */ 02377 __HAL_LOCK(hi2c); 02378 02379 /* Check if the I2C is already enabled */ 02380 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 02381 { 02382 /* Enable I2C peripheral */ 02383 __HAL_I2C_ENABLE(hi2c); 02384 } 02385 02386 /* Disable Pos */ 02387 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 02388 02389 hi2c->State = HAL_I2C_STATE_BUSY_RX; 02390 hi2c->Mode = HAL_I2C_MODE_SLAVE; 02391 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 02392 02393 /* Prepare transfer parameters */ 02394 hi2c->pBuffPtr = pData; 02395 hi2c->XferCount = Size; 02396 hi2c->XferSize = hi2c->XferCount; 02397 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 02398 02399 if (hi2c->hdmarx != NULL) 02400 { 02401 /* Set the I2C DMA transfer complete callback */ 02402 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 02403 02404 /* Set the DMA error callback */ 02405 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 02406 02407 /* Set the unused DMA callbacks to NULL */ 02408 hi2c->hdmarx->XferHalfCpltCallback = NULL; 02409 hi2c->hdmarx->XferM1CpltCallback = NULL; 02410 hi2c->hdmarx->XferM1HalfCpltCallback = NULL; 02411 hi2c->hdmarx->XferAbortCallback = NULL; 02412 02413 /* Enable the DMA stream */ 02414 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 02415 } 02416 else 02417 { 02418 /* Update I2C state */ 02419 hi2c->State = HAL_I2C_STATE_LISTEN; 02420 hi2c->Mode = HAL_I2C_MODE_NONE; 02421 02422 /* Update I2C error code */ 02423 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 02424 02425 /* Process Unlocked */ 02426 __HAL_UNLOCK(hi2c); 02427 02428 return HAL_ERROR; 02429 } 02430 02431 if (dmaxferstatus == HAL_OK) 02432 { 02433 /* Enable Address Acknowledge */ 02434 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02435 02436 /* Process Unlocked */ 02437 __HAL_UNLOCK(hi2c); 02438 02439 /* Note : The I2C interrupts must be enabled after unlocking current process 02440 to avoid the risk of I2C interrupt handle execution before current 02441 process unlock */ 02442 /* Enable EVT and ERR interrupt */ 02443 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 02444 02445 /* Enable DMA Request */ 02446 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 02447 02448 return HAL_OK; 02449 } 02450 else 02451 { 02452 /* Update I2C state */ 02453 hi2c->State = HAL_I2C_STATE_READY; 02454 hi2c->Mode = HAL_I2C_MODE_NONE; 02455 02456 /* Update I2C error code */ 02457 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 02458 02459 /* Process Unlocked */ 02460 __HAL_UNLOCK(hi2c); 02461 02462 return HAL_ERROR; 02463 } 02464 } 02465 else 02466 { 02467 return HAL_BUSY; 02468 } 02469 } 02470 02471 /** 02472 * @brief Write an amount of data in blocking mode to a specific memory address 02473 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 02474 * the configuration information for the specified I2C. 02475 * @param DevAddress Target device address: The device 7 bits address value 02476 * in datasheet must be shifted to the left before calling the interface 02477 * @param MemAddress Internal memory address 02478 * @param MemAddSize Size of internal memory address 02479 * @param pData Pointer to data buffer 02480 * @param Size Amount of data to be sent 02481 * @param Timeout Timeout duration 02482 * @retval HAL status 02483 */ 02484 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) 02485 { 02486 /* Init tickstart for timeout management*/ 02487 uint32_t tickstart = HAL_GetTick(); 02488 02489 /* Check the parameters */ 02490 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 02491 02492 if (hi2c->State == HAL_I2C_STATE_READY) 02493 { 02494 /* Wait until BUSY flag is reset */ 02495 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 02496 { 02497 return HAL_BUSY; 02498 } 02499 02500 /* Process Locked */ 02501 __HAL_LOCK(hi2c); 02502 02503 /* Check if the I2C is already enabled */ 02504 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 02505 { 02506 /* Enable I2C peripheral */ 02507 __HAL_I2C_ENABLE(hi2c); 02508 } 02509 02510 /* Disable Pos */ 02511 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 02512 02513 hi2c->State = HAL_I2C_STATE_BUSY_TX; 02514 hi2c->Mode = HAL_I2C_MODE_MEM; 02515 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 02516 02517 /* Prepare transfer parameters */ 02518 hi2c->pBuffPtr = pData; 02519 hi2c->XferCount = Size; 02520 hi2c->XferSize = hi2c->XferCount; 02521 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 02522 02523 /* Send Slave Address and Memory Address */ 02524 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 02525 { 02526 return HAL_ERROR; 02527 } 02528 02529 while (hi2c->XferSize > 0U) 02530 { 02531 /* Wait until TXE flag is set */ 02532 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 02533 { 02534 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 02535 { 02536 /* Generate Stop */ 02537 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 02538 } 02539 return HAL_ERROR; 02540 } 02541 02542 /* Write data to DR */ 02543 hi2c->Instance->DR = *hi2c->pBuffPtr; 02544 02545 /* Increment Buffer pointer */ 02546 hi2c->pBuffPtr++; 02547 02548 /* Update counter */ 02549 hi2c->XferSize--; 02550 hi2c->XferCount--; 02551 02552 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) 02553 { 02554 /* Write data to DR */ 02555 hi2c->Instance->DR = *hi2c->pBuffPtr; 02556 02557 /* Increment Buffer pointer */ 02558 hi2c->pBuffPtr++; 02559 02560 /* Update counter */ 02561 hi2c->XferSize--; 02562 hi2c->XferCount--; 02563 } 02564 } 02565 02566 /* Wait until BTF flag is set */ 02567 if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 02568 { 02569 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 02570 { 02571 /* Generate Stop */ 02572 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 02573 } 02574 return HAL_ERROR; 02575 } 02576 02577 /* Generate Stop */ 02578 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 02579 02580 hi2c->State = HAL_I2C_STATE_READY; 02581 hi2c->Mode = HAL_I2C_MODE_NONE; 02582 02583 /* Process Unlocked */ 02584 __HAL_UNLOCK(hi2c); 02585 02586 return HAL_OK; 02587 } 02588 else 02589 { 02590 return HAL_BUSY; 02591 } 02592 } 02593 02594 /** 02595 * @brief Read an amount of data in blocking mode from a specific memory address 02596 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 02597 * the configuration information for the specified I2C. 02598 * @param DevAddress Target device address: The device 7 bits address value 02599 * in datasheet must be shifted to the left before calling the interface 02600 * @param MemAddress Internal memory address 02601 * @param MemAddSize Size of internal memory address 02602 * @param pData Pointer to data buffer 02603 * @param Size Amount of data to be sent 02604 * @param Timeout Timeout duration 02605 * @retval HAL status 02606 */ 02607 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) 02608 { 02609 /* Init tickstart for timeout management*/ 02610 uint32_t tickstart = HAL_GetTick(); 02611 02612 /* Check the parameters */ 02613 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 02614 02615 if (hi2c->State == HAL_I2C_STATE_READY) 02616 { 02617 /* Wait until BUSY flag is reset */ 02618 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 02619 { 02620 return HAL_BUSY; 02621 } 02622 02623 /* Process Locked */ 02624 __HAL_LOCK(hi2c); 02625 02626 /* Check if the I2C is already enabled */ 02627 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 02628 { 02629 /* Enable I2C peripheral */ 02630 __HAL_I2C_ENABLE(hi2c); 02631 } 02632 02633 /* Disable Pos */ 02634 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 02635 02636 hi2c->State = HAL_I2C_STATE_BUSY_RX; 02637 hi2c->Mode = HAL_I2C_MODE_MEM; 02638 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 02639 02640 /* Prepare transfer parameters */ 02641 hi2c->pBuffPtr = pData; 02642 hi2c->XferCount = Size; 02643 hi2c->XferSize = hi2c->XferCount; 02644 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 02645 02646 /* Send Slave Address and Memory Address */ 02647 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) 02648 { 02649 return HAL_ERROR; 02650 } 02651 02652 if (hi2c->XferSize == 0U) 02653 { 02654 /* Clear ADDR flag */ 02655 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 02656 02657 /* Generate Stop */ 02658 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 02659 } 02660 else if (hi2c->XferSize == 1U) 02661 { 02662 /* Disable Acknowledge */ 02663 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02664 02665 /* Clear ADDR flag */ 02666 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 02667 02668 /* Generate Stop */ 02669 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 02670 } 02671 else if (hi2c->XferSize == 2U) 02672 { 02673 /* Disable Acknowledge */ 02674 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02675 02676 /* Enable Pos */ 02677 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 02678 02679 /* Clear ADDR flag */ 02680 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 02681 } 02682 else 02683 { 02684 /* Clear ADDR flag */ 02685 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 02686 } 02687 02688 while (hi2c->XferSize > 0U) 02689 { 02690 if (hi2c->XferSize <= 3U) 02691 { 02692 /* One byte */ 02693 if (hi2c->XferSize == 1U) 02694 { 02695 /* Wait until RXNE flag is set */ 02696 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 02697 { 02698 return HAL_ERROR; 02699 } 02700 02701 /* Read data from DR */ 02702 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 02703 02704 /* Increment Buffer pointer */ 02705 hi2c->pBuffPtr++; 02706 02707 /* Update counter */ 02708 hi2c->XferSize--; 02709 hi2c->XferCount--; 02710 } 02711 /* Two bytes */ 02712 else if (hi2c->XferSize == 2U) 02713 { 02714 /* Wait until BTF flag is set */ 02715 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 02716 { 02717 return HAL_ERROR; 02718 } 02719 02720 /* Generate Stop */ 02721 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 02722 02723 /* Read data from DR */ 02724 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 02725 02726 /* Increment Buffer pointer */ 02727 hi2c->pBuffPtr++; 02728 02729 /* Update counter */ 02730 hi2c->XferSize--; 02731 hi2c->XferCount--; 02732 02733 /* Read data from DR */ 02734 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 02735 02736 /* Increment Buffer pointer */ 02737 hi2c->pBuffPtr++; 02738 02739 /* Update counter */ 02740 hi2c->XferSize--; 02741 hi2c->XferCount--; 02742 } 02743 /* 3 Last bytes */ 02744 else 02745 { 02746 /* Wait until BTF flag is set */ 02747 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 02748 { 02749 return HAL_ERROR; 02750 } 02751 02752 /* Disable Acknowledge */ 02753 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 02754 02755 /* Read data from DR */ 02756 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 02757 02758 /* Increment Buffer pointer */ 02759 hi2c->pBuffPtr++; 02760 02761 /* Update counter */ 02762 hi2c->XferSize--; 02763 hi2c->XferCount--; 02764 02765 /* Wait until BTF flag is set */ 02766 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) 02767 { 02768 return HAL_ERROR; 02769 } 02770 02771 /* Generate Stop */ 02772 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 02773 02774 /* Read data from DR */ 02775 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 02776 02777 /* Increment Buffer pointer */ 02778 hi2c->pBuffPtr++; 02779 02780 /* Update counter */ 02781 hi2c->XferSize--; 02782 hi2c->XferCount--; 02783 02784 /* Read data from DR */ 02785 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 02786 02787 /* Increment Buffer pointer */ 02788 hi2c->pBuffPtr++; 02789 02790 /* Update counter */ 02791 hi2c->XferSize--; 02792 hi2c->XferCount--; 02793 } 02794 } 02795 else 02796 { 02797 /* Wait until RXNE flag is set */ 02798 if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) 02799 { 02800 return HAL_ERROR; 02801 } 02802 02803 /* Read data from DR */ 02804 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 02805 02806 /* Increment Buffer pointer */ 02807 hi2c->pBuffPtr++; 02808 02809 /* Update counter */ 02810 hi2c->XferSize--; 02811 hi2c->XferCount--; 02812 02813 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 02814 { 02815 /* Read data from DR */ 02816 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 02817 02818 /* Increment Buffer pointer */ 02819 hi2c->pBuffPtr++; 02820 02821 /* Update counter */ 02822 hi2c->XferSize--; 02823 hi2c->XferCount--; 02824 } 02825 } 02826 } 02827 02828 hi2c->State = HAL_I2C_STATE_READY; 02829 hi2c->Mode = HAL_I2C_MODE_NONE; 02830 02831 /* Process Unlocked */ 02832 __HAL_UNLOCK(hi2c); 02833 02834 return HAL_OK; 02835 } 02836 else 02837 { 02838 return HAL_BUSY; 02839 } 02840 } 02841 02842 /** 02843 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address 02844 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 02845 * the configuration information for the specified I2C. 02846 * @param DevAddress Target device address: The device 7 bits address value 02847 * in datasheet must be shifted to the left before calling the interface 02848 * @param MemAddress Internal memory address 02849 * @param MemAddSize Size of internal memory address 02850 * @param pData Pointer to data buffer 02851 * @param Size Amount of data to be sent 02852 * @retval HAL status 02853 */ 02854 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) 02855 { 02856 __IO uint32_t count = 0U; 02857 02858 /* Check the parameters */ 02859 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 02860 02861 if (hi2c->State == HAL_I2C_STATE_READY) 02862 { 02863 /* Wait until BUSY flag is reset */ 02864 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 02865 do 02866 { 02867 count--; 02868 if (count == 0U) 02869 { 02870 hi2c->PreviousState = I2C_STATE_NONE; 02871 hi2c->State = HAL_I2C_STATE_READY; 02872 hi2c->Mode = HAL_I2C_MODE_NONE; 02873 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 02874 02875 /* Process Unlocked */ 02876 __HAL_UNLOCK(hi2c); 02877 02878 return HAL_ERROR; 02879 } 02880 } 02881 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 02882 02883 /* Process Locked */ 02884 __HAL_LOCK(hi2c); 02885 02886 /* Check if the I2C is already enabled */ 02887 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 02888 { 02889 /* Enable I2C peripheral */ 02890 __HAL_I2C_ENABLE(hi2c); 02891 } 02892 02893 /* Disable Pos */ 02894 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 02895 02896 hi2c->State = HAL_I2C_STATE_BUSY_TX; 02897 hi2c->Mode = HAL_I2C_MODE_MEM; 02898 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 02899 02900 /* Prepare transfer parameters */ 02901 hi2c->pBuffPtr = pData; 02902 hi2c->XferCount = Size; 02903 hi2c->XferSize = hi2c->XferCount; 02904 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 02905 hi2c->Devaddress = DevAddress; 02906 hi2c->Memaddress = MemAddress; 02907 hi2c->MemaddSize = MemAddSize; 02908 hi2c->EventCount = 0U; 02909 02910 /* Generate Start */ 02911 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 02912 02913 /* Process Unlocked */ 02914 __HAL_UNLOCK(hi2c); 02915 02916 /* Note : The I2C interrupts must be enabled after unlocking current process 02917 to avoid the risk of I2C interrupt handle execution before current 02918 process unlock */ 02919 02920 /* Enable EVT, BUF and ERR interrupt */ 02921 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 02922 02923 return HAL_OK; 02924 } 02925 else 02926 { 02927 return HAL_BUSY; 02928 } 02929 } 02930 02931 /** 02932 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address 02933 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 02934 * the configuration information for the specified I2C. 02935 * @param DevAddress Target device address 02936 * @param MemAddress Internal memory address 02937 * @param MemAddSize Size of internal memory address 02938 * @param pData Pointer to data buffer 02939 * @param Size Amount of data to be sent 02940 * @retval HAL status 02941 */ 02942 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) 02943 { 02944 __IO uint32_t count = 0U; 02945 02946 /* Check the parameters */ 02947 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 02948 02949 if (hi2c->State == HAL_I2C_STATE_READY) 02950 { 02951 /* Wait until BUSY flag is reset */ 02952 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 02953 do 02954 { 02955 count--; 02956 if (count == 0U) 02957 { 02958 hi2c->PreviousState = I2C_STATE_NONE; 02959 hi2c->State = HAL_I2C_STATE_READY; 02960 hi2c->Mode = HAL_I2C_MODE_NONE; 02961 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 02962 02963 /* Process Unlocked */ 02964 __HAL_UNLOCK(hi2c); 02965 02966 return HAL_ERROR; 02967 } 02968 } 02969 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 02970 02971 /* Process Locked */ 02972 __HAL_LOCK(hi2c); 02973 02974 /* Check if the I2C is already enabled */ 02975 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 02976 { 02977 /* Enable I2C peripheral */ 02978 __HAL_I2C_ENABLE(hi2c); 02979 } 02980 02981 /* Disable Pos */ 02982 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 02983 02984 hi2c->State = HAL_I2C_STATE_BUSY_RX; 02985 hi2c->Mode = HAL_I2C_MODE_MEM; 02986 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 02987 02988 /* Prepare transfer parameters */ 02989 hi2c->pBuffPtr = pData; 02990 hi2c->XferCount = Size; 02991 hi2c->XferSize = hi2c->XferCount; 02992 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 02993 hi2c->Devaddress = DevAddress; 02994 hi2c->Memaddress = MemAddress; 02995 hi2c->MemaddSize = MemAddSize; 02996 hi2c->EventCount = 0U; 02997 02998 /* Enable Acknowledge */ 02999 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03000 03001 /* Generate Start */ 03002 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 03003 03004 /* Process Unlocked */ 03005 __HAL_UNLOCK(hi2c); 03006 03007 if (hi2c->XferSize > 0U) 03008 { 03009 /* Note : The I2C interrupts must be enabled after unlocking current process 03010 to avoid the risk of I2C interrupt handle execution before current 03011 process unlock */ 03012 03013 /* Enable EVT, BUF and ERR interrupt */ 03014 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 03015 } 03016 return HAL_OK; 03017 } 03018 else 03019 { 03020 return HAL_BUSY; 03021 } 03022 } 03023 03024 /** 03025 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address 03026 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 03027 * the configuration information for the specified I2C. 03028 * @param DevAddress Target device address: The device 7 bits address value 03029 * in datasheet must be shifted to the left before calling the interface 03030 * @param MemAddress Internal memory address 03031 * @param MemAddSize Size of internal memory address 03032 * @param pData Pointer to data buffer 03033 * @param Size Amount of data to be sent 03034 * @retval HAL status 03035 */ 03036 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) 03037 { 03038 __IO uint32_t count = 0U; 03039 HAL_StatusTypeDef dmaxferstatus; 03040 03041 /* Init tickstart for timeout management*/ 03042 uint32_t tickstart = HAL_GetTick(); 03043 03044 /* Check the parameters */ 03045 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 03046 03047 if (hi2c->State == HAL_I2C_STATE_READY) 03048 { 03049 /* Wait until BUSY flag is reset */ 03050 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 03051 do 03052 { 03053 count--; 03054 if (count == 0U) 03055 { 03056 hi2c->PreviousState = I2C_STATE_NONE; 03057 hi2c->State = HAL_I2C_STATE_READY; 03058 hi2c->Mode = HAL_I2C_MODE_NONE; 03059 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 03060 03061 /* Process Unlocked */ 03062 __HAL_UNLOCK(hi2c); 03063 03064 return HAL_ERROR; 03065 } 03066 } 03067 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 03068 03069 /* Process Locked */ 03070 __HAL_LOCK(hi2c); 03071 03072 /* Check if the I2C is already enabled */ 03073 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 03074 { 03075 /* Enable I2C peripheral */ 03076 __HAL_I2C_ENABLE(hi2c); 03077 } 03078 03079 /* Disable Pos */ 03080 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 03081 03082 hi2c->State = HAL_I2C_STATE_BUSY_TX; 03083 hi2c->Mode = HAL_I2C_MODE_MEM; 03084 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 03085 03086 /* Prepare transfer parameters */ 03087 hi2c->pBuffPtr = pData; 03088 hi2c->XferCount = Size; 03089 hi2c->XferSize = hi2c->XferCount; 03090 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 03091 hi2c->Devaddress = DevAddress; 03092 hi2c->Memaddress = MemAddress; 03093 hi2c->MemaddSize = MemAddSize; 03094 hi2c->EventCount = 0U; 03095 03096 if (hi2c->XferSize > 0U) 03097 { 03098 if (hi2c->hdmatx != NULL) 03099 { 03100 /* Set the I2C DMA transfer complete callback */ 03101 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 03102 03103 /* Set the DMA error callback */ 03104 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 03105 03106 /* Set the unused DMA callbacks to NULL */ 03107 hi2c->hdmatx->XferHalfCpltCallback = NULL; 03108 hi2c->hdmatx->XferM1CpltCallback = NULL; 03109 hi2c->hdmatx->XferM1HalfCpltCallback = NULL; 03110 hi2c->hdmatx->XferAbortCallback = NULL; 03111 03112 /* Enable the DMA stream */ 03113 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 03114 } 03115 else 03116 { 03117 /* Update I2C state */ 03118 hi2c->State = HAL_I2C_STATE_READY; 03119 hi2c->Mode = HAL_I2C_MODE_NONE; 03120 03121 /* Update I2C error code */ 03122 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 03123 03124 /* Process Unlocked */ 03125 __HAL_UNLOCK(hi2c); 03126 03127 return HAL_ERROR; 03128 } 03129 03130 if (dmaxferstatus == HAL_OK) 03131 { 03132 /* Send Slave Address and Memory Address */ 03133 if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) 03134 { 03135 /* Abort the ongoing DMA */ 03136 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); 03137 03138 /* Prevent unused argument(s) compilation and MISRA warning */ 03139 UNUSED(dmaxferstatus); 03140 03141 /* Set the unused I2C DMA transfer complete callback to NULL */ 03142 hi2c->hdmatx->XferCpltCallback = NULL; 03143 03144 /* Disable Acknowledge */ 03145 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03146 03147 hi2c->XferSize = 0U; 03148 hi2c->XferCount = 0U; 03149 03150 /* Disable I2C peripheral to prevent dummy data in buffer */ 03151 __HAL_I2C_DISABLE(hi2c); 03152 03153 return HAL_ERROR; 03154 } 03155 03156 /* Clear ADDR flag */ 03157 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 03158 03159 /* Process Unlocked */ 03160 __HAL_UNLOCK(hi2c); 03161 03162 /* Note : The I2C interrupts must be enabled after unlocking current process 03163 to avoid the risk of I2C interrupt handle execution before current 03164 process unlock */ 03165 /* Enable ERR interrupt */ 03166 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); 03167 03168 /* Enable DMA Request */ 03169 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 03170 03171 return HAL_OK; 03172 } 03173 else 03174 { 03175 /* Update I2C state */ 03176 hi2c->State = HAL_I2C_STATE_READY; 03177 hi2c->Mode = HAL_I2C_MODE_NONE; 03178 03179 /* Update I2C error code */ 03180 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 03181 03182 /* Process Unlocked */ 03183 __HAL_UNLOCK(hi2c); 03184 03185 return HAL_ERROR; 03186 } 03187 } 03188 else 03189 { 03190 /* Update I2C state */ 03191 hi2c->State = HAL_I2C_STATE_READY; 03192 hi2c->Mode = HAL_I2C_MODE_NONE; 03193 03194 /* Update I2C error code */ 03195 hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; 03196 03197 /* Process Unlocked */ 03198 __HAL_UNLOCK(hi2c); 03199 03200 return HAL_ERROR; 03201 } 03202 } 03203 else 03204 { 03205 return HAL_BUSY; 03206 } 03207 } 03208 03209 /** 03210 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. 03211 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 03212 * the configuration information for the specified I2C. 03213 * @param DevAddress Target device address: The device 7 bits address value 03214 * in datasheet must be shifted to the left before calling the interface 03215 * @param MemAddress Internal memory address 03216 * @param MemAddSize Size of internal memory address 03217 * @param pData Pointer to data buffer 03218 * @param Size Amount of data to be read 03219 * @retval HAL status 03220 */ 03221 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) 03222 { 03223 /* Init tickstart for timeout management*/ 03224 uint32_t tickstart = HAL_GetTick(); 03225 __IO uint32_t count = 0U; 03226 HAL_StatusTypeDef dmaxferstatus; 03227 03228 /* Check the parameters */ 03229 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); 03230 03231 if (hi2c->State == HAL_I2C_STATE_READY) 03232 { 03233 /* Wait until BUSY flag is reset */ 03234 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 03235 do 03236 { 03237 count--; 03238 if (count == 0U) 03239 { 03240 hi2c->PreviousState = I2C_STATE_NONE; 03241 hi2c->State = HAL_I2C_STATE_READY; 03242 hi2c->Mode = HAL_I2C_MODE_NONE; 03243 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 03244 03245 /* Process Unlocked */ 03246 __HAL_UNLOCK(hi2c); 03247 03248 return HAL_ERROR; 03249 } 03250 } 03251 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 03252 03253 /* Process Locked */ 03254 __HAL_LOCK(hi2c); 03255 03256 /* Check if the I2C is already enabled */ 03257 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 03258 { 03259 /* Enable I2C peripheral */ 03260 __HAL_I2C_ENABLE(hi2c); 03261 } 03262 03263 /* Disable Pos */ 03264 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 03265 03266 hi2c->State = HAL_I2C_STATE_BUSY_RX; 03267 hi2c->Mode = HAL_I2C_MODE_MEM; 03268 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 03269 03270 /* Prepare transfer parameters */ 03271 hi2c->pBuffPtr = pData; 03272 hi2c->XferCount = Size; 03273 hi2c->XferSize = hi2c->XferCount; 03274 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 03275 hi2c->Devaddress = DevAddress; 03276 hi2c->Memaddress = MemAddress; 03277 hi2c->MemaddSize = MemAddSize; 03278 hi2c->EventCount = 0U; 03279 03280 if (hi2c->XferSize > 0U) 03281 { 03282 if (hi2c->hdmarx != NULL) 03283 { 03284 /* Set the I2C DMA transfer complete callback */ 03285 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 03286 03287 /* Set the DMA error callback */ 03288 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 03289 03290 /* Set the unused DMA callbacks to NULL */ 03291 hi2c->hdmarx->XferHalfCpltCallback = NULL; 03292 hi2c->hdmarx->XferM1CpltCallback = NULL; 03293 hi2c->hdmarx->XferM1HalfCpltCallback = NULL; 03294 hi2c->hdmarx->XferAbortCallback = NULL; 03295 03296 /* Enable the DMA stream */ 03297 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 03298 } 03299 else 03300 { 03301 /* Update I2C state */ 03302 hi2c->State = HAL_I2C_STATE_READY; 03303 hi2c->Mode = HAL_I2C_MODE_NONE; 03304 03305 /* Update I2C error code */ 03306 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 03307 03308 /* Process Unlocked */ 03309 __HAL_UNLOCK(hi2c); 03310 03311 return HAL_ERROR; 03312 } 03313 03314 if (dmaxferstatus == HAL_OK) 03315 { 03316 /* Send Slave Address and Memory Address */ 03317 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) 03318 { 03319 /* Abort the ongoing DMA */ 03320 dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); 03321 03322 /* Prevent unused argument(s) compilation and MISRA warning */ 03323 UNUSED(dmaxferstatus); 03324 03325 /* Set the unused I2C DMA transfer complete callback to NULL */ 03326 hi2c->hdmarx->XferCpltCallback = NULL; 03327 03328 /* Disable Acknowledge */ 03329 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03330 03331 hi2c->XferSize = 0U; 03332 hi2c->XferCount = 0U; 03333 03334 /* Disable I2C peripheral to prevent dummy data in buffer */ 03335 __HAL_I2C_DISABLE(hi2c); 03336 03337 return HAL_ERROR; 03338 } 03339 03340 if (hi2c->XferSize == 1U) 03341 { 03342 /* Disable Acknowledge */ 03343 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03344 } 03345 else 03346 { 03347 /* Enable Last DMA bit */ 03348 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 03349 } 03350 03351 /* Clear ADDR flag */ 03352 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 03353 03354 /* Process Unlocked */ 03355 __HAL_UNLOCK(hi2c); 03356 03357 /* Note : The I2C interrupts must be enabled after unlocking current process 03358 to avoid the risk of I2C interrupt handle execution before current 03359 process unlock */ 03360 /* Enable ERR interrupt */ 03361 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); 03362 03363 /* Enable DMA Request */ 03364 hi2c->Instance->CR2 |= I2C_CR2_DMAEN; 03365 } 03366 else 03367 { 03368 /* Update I2C state */ 03369 hi2c->State = HAL_I2C_STATE_READY; 03370 hi2c->Mode = HAL_I2C_MODE_NONE; 03371 03372 /* Update I2C error code */ 03373 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 03374 03375 /* Process Unlocked */ 03376 __HAL_UNLOCK(hi2c); 03377 03378 return HAL_ERROR; 03379 } 03380 } 03381 else 03382 { 03383 /* Send Slave Address and Memory Address */ 03384 if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) 03385 { 03386 return HAL_ERROR; 03387 } 03388 03389 /* Clear ADDR flag */ 03390 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 03391 03392 /* Generate Stop */ 03393 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 03394 03395 hi2c->State = HAL_I2C_STATE_READY; 03396 03397 /* Process Unlocked */ 03398 __HAL_UNLOCK(hi2c); 03399 } 03400 03401 return HAL_OK; 03402 } 03403 else 03404 { 03405 return HAL_BUSY; 03406 } 03407 } 03408 03409 /** 03410 * @brief Checks if target device is ready for communication. 03411 * @note This function is used with Memory devices 03412 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 03413 * the configuration information for the specified I2C. 03414 * @param DevAddress Target device address: The device 7 bits address value 03415 * in datasheet must be shifted to the left before calling the interface 03416 * @param Trials Number of trials 03417 * @param Timeout Timeout duration 03418 * @retval HAL status 03419 */ 03420 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) 03421 { 03422 /* Get tick */ 03423 uint32_t tickstart = HAL_GetTick(); 03424 uint32_t I2C_Trials = 1U; 03425 FlagStatus tmp1; 03426 FlagStatus tmp2; 03427 03428 if (hi2c->State == HAL_I2C_STATE_READY) 03429 { 03430 /* Wait until BUSY flag is reset */ 03431 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 03432 { 03433 return HAL_BUSY; 03434 } 03435 03436 /* Process Locked */ 03437 __HAL_LOCK(hi2c); 03438 03439 /* Check if the I2C is already enabled */ 03440 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 03441 { 03442 /* Enable I2C peripheral */ 03443 __HAL_I2C_ENABLE(hi2c); 03444 } 03445 03446 /* Disable Pos */ 03447 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 03448 03449 hi2c->State = HAL_I2C_STATE_BUSY; 03450 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 03451 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 03452 03453 do 03454 { 03455 /* Generate Start */ 03456 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 03457 03458 /* Wait until SB flag is set */ 03459 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) 03460 { 03461 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 03462 { 03463 hi2c->ErrorCode = HAL_I2C_WRONG_START; 03464 } 03465 return HAL_TIMEOUT; 03466 } 03467 03468 /* Send slave address */ 03469 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 03470 03471 /* Wait until ADDR or AF flag are set */ 03472 /* Get tick */ 03473 tickstart = HAL_GetTick(); 03474 03475 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); 03476 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); 03477 while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) 03478 { 03479 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 03480 { 03481 hi2c->State = HAL_I2C_STATE_TIMEOUT; 03482 } 03483 tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); 03484 tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); 03485 } 03486 03487 hi2c->State = HAL_I2C_STATE_READY; 03488 03489 /* Check if the ADDR flag has been set */ 03490 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) 03491 { 03492 /* Generate Stop */ 03493 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 03494 03495 /* Clear ADDR Flag */ 03496 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 03497 03498 /* Wait until BUSY flag is reset */ 03499 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 03500 { 03501 return HAL_ERROR; 03502 } 03503 03504 hi2c->State = HAL_I2C_STATE_READY; 03505 03506 /* Process Unlocked */ 03507 __HAL_UNLOCK(hi2c); 03508 03509 return HAL_OK; 03510 } 03511 else 03512 { 03513 /* Generate Stop */ 03514 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 03515 03516 /* Clear AF Flag */ 03517 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 03518 03519 /* Wait until BUSY flag is reset */ 03520 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) 03521 { 03522 return HAL_ERROR; 03523 } 03524 } 03525 03526 /* Increment Trials */ 03527 I2C_Trials++; 03528 } 03529 while (I2C_Trials < Trials); 03530 03531 hi2c->State = HAL_I2C_STATE_READY; 03532 03533 /* Process Unlocked */ 03534 __HAL_UNLOCK(hi2c); 03535 03536 return HAL_ERROR; 03537 } 03538 else 03539 { 03540 return HAL_BUSY; 03541 } 03542 } 03543 03544 /** 03545 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. 03546 * @note This interface allow to manage repeated start condition when a direction change during transfer 03547 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 03548 * the configuration information for the specified I2C. 03549 * @param DevAddress Target device address: The device 7 bits address value 03550 * in datasheet must be shifted to the left before calling the interface 03551 * @param pData Pointer to data buffer 03552 * @param Size Amount of data to be sent 03553 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 03554 * @retval HAL status 03555 */ 03556 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 03557 { 03558 __IO uint32_t Prev_State = 0x00U; 03559 __IO uint32_t count = 0x00U; 03560 03561 /* Check the parameters */ 03562 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 03563 03564 if (hi2c->State == HAL_I2C_STATE_READY) 03565 { 03566 /* Check Busy Flag only if FIRST call of Master interface */ 03567 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) 03568 { 03569 /* Wait until BUSY flag is reset */ 03570 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 03571 do 03572 { 03573 count--; 03574 if (count == 0U) 03575 { 03576 hi2c->PreviousState = I2C_STATE_NONE; 03577 hi2c->State = HAL_I2C_STATE_READY; 03578 hi2c->Mode = HAL_I2C_MODE_NONE; 03579 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 03580 03581 /* Process Unlocked */ 03582 __HAL_UNLOCK(hi2c); 03583 03584 return HAL_ERROR; 03585 } 03586 } 03587 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 03588 } 03589 03590 /* Process Locked */ 03591 __HAL_LOCK(hi2c); 03592 03593 /* Check if the I2C is already enabled */ 03594 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 03595 { 03596 /* Enable I2C peripheral */ 03597 __HAL_I2C_ENABLE(hi2c); 03598 } 03599 03600 /* Disable Pos */ 03601 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 03602 03603 hi2c->State = HAL_I2C_STATE_BUSY_TX; 03604 hi2c->Mode = HAL_I2C_MODE_MASTER; 03605 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 03606 03607 /* Prepare transfer parameters */ 03608 hi2c->pBuffPtr = pData; 03609 hi2c->XferCount = Size; 03610 hi2c->XferSize = hi2c->XferCount; 03611 hi2c->XferOptions = XferOptions; 03612 hi2c->Devaddress = DevAddress; 03613 03614 Prev_State = hi2c->PreviousState; 03615 03616 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 03617 /* Mean Previous state is same as current state */ 03618 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 03619 { 03620 /* Generate Start */ 03621 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 03622 } 03623 03624 /* Process Unlocked */ 03625 __HAL_UNLOCK(hi2c); 03626 03627 /* Note : The I2C interrupts must be enabled after unlocking current process 03628 to avoid the risk of I2C interrupt handle execution before current 03629 process unlock */ 03630 03631 /* Enable EVT, BUF and ERR interrupt */ 03632 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 03633 03634 return HAL_OK; 03635 } 03636 else 03637 { 03638 return HAL_BUSY; 03639 } 03640 } 03641 03642 /** 03643 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. 03644 * @note This interface allow to manage repeated start condition when a direction change during transfer 03645 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 03646 * the configuration information for the specified I2C. 03647 * @param DevAddress Target device address: The device 7 bits address value 03648 * in datasheet must be shifted to the left before calling the interface 03649 * @param pData Pointer to data buffer 03650 * @param Size Amount of data to be sent 03651 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 03652 * @retval HAL status 03653 */ 03654 HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 03655 { 03656 __IO uint32_t Prev_State = 0x00U; 03657 __IO uint32_t count = 0x00U; 03658 HAL_StatusTypeDef dmaxferstatus; 03659 03660 /* Check the parameters */ 03661 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 03662 03663 if (hi2c->State == HAL_I2C_STATE_READY) 03664 { 03665 /* Check Busy Flag only if FIRST call of Master interface */ 03666 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) 03667 { 03668 /* Wait until BUSY flag is reset */ 03669 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 03670 do 03671 { 03672 count--; 03673 if (count == 0U) 03674 { 03675 hi2c->PreviousState = I2C_STATE_NONE; 03676 hi2c->State = HAL_I2C_STATE_READY; 03677 hi2c->Mode = HAL_I2C_MODE_NONE; 03678 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 03679 03680 /* Process Unlocked */ 03681 __HAL_UNLOCK(hi2c); 03682 03683 return HAL_ERROR; 03684 } 03685 } 03686 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 03687 } 03688 03689 /* Process Locked */ 03690 __HAL_LOCK(hi2c); 03691 03692 /* Check if the I2C is already enabled */ 03693 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 03694 { 03695 /* Enable I2C peripheral */ 03696 __HAL_I2C_ENABLE(hi2c); 03697 } 03698 03699 /* Disable Pos */ 03700 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 03701 03702 hi2c->State = HAL_I2C_STATE_BUSY_TX; 03703 hi2c->Mode = HAL_I2C_MODE_MASTER; 03704 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 03705 03706 /* Prepare transfer parameters */ 03707 hi2c->pBuffPtr = pData; 03708 hi2c->XferCount = Size; 03709 hi2c->XferSize = hi2c->XferCount; 03710 hi2c->XferOptions = XferOptions; 03711 hi2c->Devaddress = DevAddress; 03712 03713 Prev_State = hi2c->PreviousState; 03714 03715 if (hi2c->XferSize > 0U) 03716 { 03717 if (hi2c->hdmatx != NULL) 03718 { 03719 /* Set the I2C DMA transfer complete callback */ 03720 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 03721 03722 /* Set the DMA error callback */ 03723 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 03724 03725 /* Set the unused DMA callbacks to NULL */ 03726 hi2c->hdmatx->XferHalfCpltCallback = NULL; 03727 hi2c->hdmatx->XferAbortCallback = NULL; 03728 03729 /* Enable the DMA stream */ 03730 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 03731 } 03732 else 03733 { 03734 /* Update I2C state */ 03735 hi2c->State = HAL_I2C_STATE_READY; 03736 hi2c->Mode = HAL_I2C_MODE_NONE; 03737 03738 /* Update I2C error code */ 03739 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 03740 03741 /* Process Unlocked */ 03742 __HAL_UNLOCK(hi2c); 03743 03744 return HAL_ERROR; 03745 } 03746 03747 if (dmaxferstatus == HAL_OK) 03748 { 03749 /* Enable Acknowledge */ 03750 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03751 03752 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 03753 /* Mean Previous state is same as current state */ 03754 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 03755 { 03756 /* Generate Start */ 03757 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 03758 } 03759 03760 /* Process Unlocked */ 03761 __HAL_UNLOCK(hi2c); 03762 03763 /* Note : The I2C interrupts must be enabled after unlocking current process 03764 to avoid the risk of I2C interrupt handle execution before current 03765 process unlock */ 03766 03767 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ 03768 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ 03769 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) 03770 { 03771 /* Enable DMA Request */ 03772 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 03773 } 03774 03775 /* Enable EVT and ERR interrupt */ 03776 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 03777 } 03778 else 03779 { 03780 /* Update I2C state */ 03781 hi2c->State = HAL_I2C_STATE_READY; 03782 hi2c->Mode = HAL_I2C_MODE_NONE; 03783 03784 /* Update I2C error code */ 03785 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 03786 03787 /* Process Unlocked */ 03788 __HAL_UNLOCK(hi2c); 03789 03790 return HAL_ERROR; 03791 } 03792 } 03793 else 03794 { 03795 /* Enable Acknowledge */ 03796 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03797 03798 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 03799 /* Mean Previous state is same as current state */ 03800 if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 03801 { 03802 /* Generate Start */ 03803 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 03804 } 03805 03806 /* Process Unlocked */ 03807 __HAL_UNLOCK(hi2c); 03808 03809 /* Note : The I2C interrupts must be enabled after unlocking current process 03810 to avoid the risk of I2C interrupt handle execution before current 03811 process unlock */ 03812 03813 /* Enable EVT, BUF and ERR interrupt */ 03814 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 03815 } 03816 03817 return HAL_OK; 03818 } 03819 else 03820 { 03821 return HAL_BUSY; 03822 } 03823 } 03824 03825 /** 03826 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt 03827 * @note This interface allow to manage repeated start condition when a direction change during transfer 03828 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 03829 * the configuration information for the specified I2C. 03830 * @param DevAddress Target device address: The device 7 bits address value 03831 * in datasheet must be shifted to the left before calling the interface 03832 * @param pData Pointer to data buffer 03833 * @param Size Amount of data to be sent 03834 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 03835 * @retval HAL status 03836 */ 03837 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 03838 { 03839 __IO uint32_t Prev_State = 0x00U; 03840 __IO uint32_t count = 0U; 03841 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 03842 03843 /* Check the parameters */ 03844 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 03845 03846 if (hi2c->State == HAL_I2C_STATE_READY) 03847 { 03848 /* Check Busy Flag only if FIRST call of Master interface */ 03849 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) 03850 { 03851 /* Wait until BUSY flag is reset */ 03852 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 03853 do 03854 { 03855 count--; 03856 if (count == 0U) 03857 { 03858 hi2c->PreviousState = I2C_STATE_NONE; 03859 hi2c->State = HAL_I2C_STATE_READY; 03860 hi2c->Mode = HAL_I2C_MODE_NONE; 03861 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 03862 03863 /* Process Unlocked */ 03864 __HAL_UNLOCK(hi2c); 03865 03866 return HAL_ERROR; 03867 } 03868 } 03869 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 03870 } 03871 03872 /* Process Locked */ 03873 __HAL_LOCK(hi2c); 03874 03875 /* Check if the I2C is already enabled */ 03876 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 03877 { 03878 /* Enable I2C peripheral */ 03879 __HAL_I2C_ENABLE(hi2c); 03880 } 03881 03882 /* Disable Pos */ 03883 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 03884 03885 hi2c->State = HAL_I2C_STATE_BUSY_RX; 03886 hi2c->Mode = HAL_I2C_MODE_MASTER; 03887 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 03888 03889 /* Prepare transfer parameters */ 03890 hi2c->pBuffPtr = pData; 03891 hi2c->XferCount = Size; 03892 hi2c->XferSize = hi2c->XferCount; 03893 hi2c->XferOptions = XferOptions; 03894 hi2c->Devaddress = DevAddress; 03895 03896 Prev_State = hi2c->PreviousState; 03897 03898 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) 03899 { 03900 if (Prev_State == I2C_STATE_MASTER_BUSY_RX) 03901 { 03902 /* Disable Acknowledge */ 03903 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03904 03905 /* Enable Pos */ 03906 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 03907 03908 /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ 03909 enableIT &= ~I2C_IT_BUF; 03910 } 03911 else 03912 { 03913 /* Enable Acknowledge */ 03914 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03915 } 03916 } 03917 else 03918 { 03919 /* Enable Acknowledge */ 03920 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 03921 } 03922 03923 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 03924 /* Mean Previous state is same as current state */ 03925 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 03926 { 03927 /* Generate Start */ 03928 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 03929 } 03930 03931 /* Process Unlocked */ 03932 __HAL_UNLOCK(hi2c); 03933 03934 /* Note : The I2C interrupts must be enabled after unlocking current process 03935 to avoid the risk of I2C interrupt handle execution before current 03936 process unlock */ 03937 03938 /* Enable interrupts */ 03939 __HAL_I2C_ENABLE_IT(hi2c, enableIT); 03940 03941 return HAL_OK; 03942 } 03943 else 03944 { 03945 return HAL_BUSY; 03946 } 03947 } 03948 03949 /** 03950 * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA 03951 * @note This interface allow to manage repeated start condition when a direction change during transfer 03952 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 03953 * the configuration information for the specified I2C. 03954 * @param DevAddress Target device address: The device 7 bits address value 03955 * in datasheet must be shifted to the left before calling the interface 03956 * @param pData Pointer to data buffer 03957 * @param Size Amount of data to be sent 03958 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 03959 * @retval HAL status 03960 */ 03961 HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 03962 { 03963 __IO uint32_t Prev_State = 0x00U; 03964 __IO uint32_t count = 0U; 03965 uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 03966 HAL_StatusTypeDef dmaxferstatus; 03967 03968 /* Check the parameters */ 03969 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 03970 03971 if (hi2c->State == HAL_I2C_STATE_READY) 03972 { 03973 /* Check Busy Flag only if FIRST call of Master interface */ 03974 if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) 03975 { 03976 /* Wait until BUSY flag is reset */ 03977 count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); 03978 do 03979 { 03980 count--; 03981 if (count == 0U) 03982 { 03983 hi2c->PreviousState = I2C_STATE_NONE; 03984 hi2c->State = HAL_I2C_STATE_READY; 03985 hi2c->Mode = HAL_I2C_MODE_NONE; 03986 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 03987 03988 /* Process Unlocked */ 03989 __HAL_UNLOCK(hi2c); 03990 03991 return HAL_ERROR; 03992 } 03993 } 03994 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); 03995 } 03996 03997 /* Process Locked */ 03998 __HAL_LOCK(hi2c); 03999 04000 /* Check if the I2C is already enabled */ 04001 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 04002 { 04003 /* Enable I2C peripheral */ 04004 __HAL_I2C_ENABLE(hi2c); 04005 } 04006 04007 /* Disable Pos */ 04008 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 04009 04010 /* Clear Last DMA bit */ 04011 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 04012 04013 hi2c->State = HAL_I2C_STATE_BUSY_RX; 04014 hi2c->Mode = HAL_I2C_MODE_MASTER; 04015 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 04016 04017 /* Prepare transfer parameters */ 04018 hi2c->pBuffPtr = pData; 04019 hi2c->XferCount = Size; 04020 hi2c->XferSize = hi2c->XferCount; 04021 hi2c->XferOptions = XferOptions; 04022 hi2c->Devaddress = DevAddress; 04023 04024 Prev_State = hi2c->PreviousState; 04025 04026 if (hi2c->XferSize > 0U) 04027 { 04028 if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) 04029 { 04030 if (Prev_State == I2C_STATE_MASTER_BUSY_RX) 04031 { 04032 /* Disable Acknowledge */ 04033 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04034 04035 /* Enable Pos */ 04036 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 04037 04038 /* Enable Last DMA bit */ 04039 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 04040 } 04041 else 04042 { 04043 /* Enable Acknowledge */ 04044 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04045 } 04046 } 04047 else 04048 { 04049 /* Enable Acknowledge */ 04050 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04051 04052 if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) 04053 { 04054 /* Enable Last DMA bit */ 04055 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 04056 } 04057 } 04058 if (hi2c->hdmarx != NULL) 04059 { 04060 /* Set the I2C DMA transfer complete callback */ 04061 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 04062 04063 /* Set the DMA error callback */ 04064 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 04065 04066 /* Set the unused DMA callbacks to NULL */ 04067 hi2c->hdmarx->XferHalfCpltCallback = NULL; 04068 hi2c->hdmarx->XferAbortCallback = NULL; 04069 04070 /* Enable the DMA stream */ 04071 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 04072 } 04073 else 04074 { 04075 /* Update I2C state */ 04076 hi2c->State = HAL_I2C_STATE_READY; 04077 hi2c->Mode = HAL_I2C_MODE_NONE; 04078 04079 /* Update I2C error code */ 04080 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 04081 04082 /* Process Unlocked */ 04083 __HAL_UNLOCK(hi2c); 04084 04085 return HAL_ERROR; 04086 } 04087 if (dmaxferstatus == HAL_OK) 04088 { 04089 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 04090 /* Mean Previous state is same as current state */ 04091 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 04092 { 04093 /* Generate Start */ 04094 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 04095 04096 /* Update interrupt for only EVT and ERR */ 04097 enableIT = (I2C_IT_EVT | I2C_IT_ERR); 04098 } 04099 else 04100 { 04101 /* Update interrupt for only ERR */ 04102 enableIT = I2C_IT_ERR; 04103 } 04104 04105 /* Process Unlocked */ 04106 __HAL_UNLOCK(hi2c); 04107 04108 /* Note : The I2C interrupts must be enabled after unlocking current process 04109 to avoid the risk of I2C interrupt handle execution before current 04110 process unlock */ 04111 04112 /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ 04113 /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ 04114 if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) 04115 { 04116 /* Enable DMA Request */ 04117 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 04118 } 04119 04120 /* Enable EVT and ERR interrupt */ 04121 __HAL_I2C_ENABLE_IT(hi2c, enableIT); 04122 } 04123 else 04124 { 04125 /* Update I2C state */ 04126 hi2c->State = HAL_I2C_STATE_READY; 04127 hi2c->Mode = HAL_I2C_MODE_NONE; 04128 04129 /* Update I2C error code */ 04130 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 04131 04132 /* Process Unlocked */ 04133 __HAL_UNLOCK(hi2c); 04134 04135 return HAL_ERROR; 04136 } 04137 } 04138 else 04139 { 04140 /* Enable Acknowledge */ 04141 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04142 04143 /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ 04144 /* Mean Previous state is same as current state */ 04145 if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) 04146 { 04147 /* Generate Start */ 04148 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 04149 } 04150 04151 /* Process Unlocked */ 04152 __HAL_UNLOCK(hi2c); 04153 04154 /* Note : The I2C interrupts must be enabled after unlocking current process 04155 to avoid the risk of I2C interrupt handle execution before current 04156 process unlock */ 04157 04158 /* Enable interrupts */ 04159 __HAL_I2C_ENABLE_IT(hi2c, enableIT); 04160 } 04161 return HAL_OK; 04162 } 04163 else 04164 { 04165 return HAL_BUSY; 04166 } 04167 } 04168 04169 /** 04170 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt 04171 * @note This interface allow to manage repeated start condition when a direction change during transfer 04172 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04173 * the configuration information for the specified I2C. 04174 * @param pData Pointer to data buffer 04175 * @param Size Amount of data to be sent 04176 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 04177 * @retval HAL status 04178 */ 04179 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 04180 { 04181 /* Check the parameters */ 04182 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 04183 04184 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 04185 { 04186 if ((pData == NULL) || (Size == 0U)) 04187 { 04188 return HAL_ERROR; 04189 } 04190 04191 /* Process Locked */ 04192 __HAL_LOCK(hi2c); 04193 04194 /* Check if the I2C is already enabled */ 04195 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 04196 { 04197 /* Enable I2C peripheral */ 04198 __HAL_I2C_ENABLE(hi2c); 04199 } 04200 04201 /* Disable Pos */ 04202 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 04203 04204 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; 04205 hi2c->Mode = HAL_I2C_MODE_SLAVE; 04206 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 04207 04208 /* Prepare transfer parameters */ 04209 hi2c->pBuffPtr = pData; 04210 hi2c->XferCount = Size; 04211 hi2c->XferSize = hi2c->XferCount; 04212 hi2c->XferOptions = XferOptions; 04213 04214 /* Clear ADDR flag */ 04215 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 04216 04217 /* Process Unlocked */ 04218 __HAL_UNLOCK(hi2c); 04219 04220 /* Note : The I2C interrupts must be enabled after unlocking current process 04221 to avoid the risk of I2C interrupt handle execution before current 04222 process unlock */ 04223 04224 /* Enable EVT, BUF and ERR interrupt */ 04225 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 04226 04227 return HAL_OK; 04228 } 04229 else 04230 { 04231 return HAL_BUSY; 04232 } 04233 } 04234 04235 /** 04236 * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA 04237 * @note This interface allow to manage repeated start condition when a direction change during transfer 04238 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04239 * the configuration information for the specified I2C. 04240 * @param pData Pointer to data buffer 04241 * @param Size Amount of data to be sent 04242 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 04243 * @retval HAL status 04244 */ 04245 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 04246 { 04247 HAL_StatusTypeDef dmaxferstatus; 04248 04249 /* Check the parameters */ 04250 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 04251 04252 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 04253 { 04254 if ((pData == NULL) || (Size == 0U)) 04255 { 04256 return HAL_ERROR; 04257 } 04258 04259 /* Process Locked */ 04260 __HAL_LOCK(hi2c); 04261 04262 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ 04263 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 04264 04265 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ 04266 /* and then toggle the HAL slave RX state to TX state */ 04267 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 04268 { 04269 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 04270 { 04271 /* Abort DMA Xfer if any */ 04272 if (hi2c->hdmarx != NULL) 04273 { 04274 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 04275 04276 /* Set the I2C DMA Abort callback : 04277 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 04278 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 04279 04280 /* Abort DMA RX */ 04281 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 04282 { 04283 /* Call Directly XferAbortCallback function in case of error */ 04284 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 04285 } 04286 } 04287 } 04288 } 04289 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 04290 { 04291 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 04292 { 04293 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 04294 04295 /* Abort DMA Xfer if any */ 04296 if (hi2c->hdmatx != NULL) 04297 { 04298 /* Set the I2C DMA Abort callback : 04299 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 04300 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 04301 04302 /* Abort DMA TX */ 04303 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 04304 { 04305 /* Call Directly XferAbortCallback function in case of error */ 04306 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 04307 } 04308 } 04309 } 04310 } 04311 else 04312 { 04313 /* Nothing to do */ 04314 } 04315 04316 /* Check if the I2C is already enabled */ 04317 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 04318 { 04319 /* Enable I2C peripheral */ 04320 __HAL_I2C_ENABLE(hi2c); 04321 } 04322 04323 /* Disable Pos */ 04324 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 04325 04326 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; 04327 hi2c->Mode = HAL_I2C_MODE_SLAVE; 04328 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 04329 04330 /* Prepare transfer parameters */ 04331 hi2c->pBuffPtr = pData; 04332 hi2c->XferCount = Size; 04333 hi2c->XferSize = hi2c->XferCount; 04334 hi2c->XferOptions = XferOptions; 04335 04336 if (hi2c->hdmatx != NULL) 04337 { 04338 /* Set the I2C DMA transfer complete callback */ 04339 hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; 04340 04341 /* Set the DMA error callback */ 04342 hi2c->hdmatx->XferErrorCallback = I2C_DMAError; 04343 04344 /* Set the unused DMA callbacks to NULL */ 04345 hi2c->hdmatx->XferHalfCpltCallback = NULL; 04346 hi2c->hdmatx->XferAbortCallback = NULL; 04347 04348 /* Enable the DMA stream */ 04349 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); 04350 } 04351 else 04352 { 04353 /* Update I2C state */ 04354 hi2c->State = HAL_I2C_STATE_LISTEN; 04355 hi2c->Mode = HAL_I2C_MODE_NONE; 04356 04357 /* Update I2C error code */ 04358 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 04359 04360 /* Process Unlocked */ 04361 __HAL_UNLOCK(hi2c); 04362 04363 return HAL_ERROR; 04364 } 04365 04366 if (dmaxferstatus == HAL_OK) 04367 { 04368 /* Enable Address Acknowledge */ 04369 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04370 04371 /* Clear ADDR flag */ 04372 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 04373 04374 /* Process Unlocked */ 04375 __HAL_UNLOCK(hi2c); 04376 04377 /* Note : The I2C interrupts must be enabled after unlocking current process 04378 to avoid the risk of I2C interrupt handle execution before current 04379 process unlock */ 04380 /* Enable EVT and ERR interrupt */ 04381 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 04382 04383 /* Enable DMA Request */ 04384 hi2c->Instance->CR2 |= I2C_CR2_DMAEN; 04385 04386 return HAL_OK; 04387 } 04388 else 04389 { 04390 /* Update I2C state */ 04391 hi2c->State = HAL_I2C_STATE_READY; 04392 hi2c->Mode = HAL_I2C_MODE_NONE; 04393 04394 /* Update I2C error code */ 04395 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 04396 04397 /* Process Unlocked */ 04398 __HAL_UNLOCK(hi2c); 04399 04400 return HAL_ERROR; 04401 } 04402 } 04403 else 04404 { 04405 return HAL_BUSY; 04406 } 04407 } 04408 04409 /** 04410 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt 04411 * @note This interface allow to manage repeated start condition when a direction change during transfer 04412 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04413 * the configuration information for the specified I2C. 04414 * @param pData Pointer to data buffer 04415 * @param Size Amount of data to be sent 04416 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 04417 * @retval HAL status 04418 */ 04419 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 04420 { 04421 /* Check the parameters */ 04422 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 04423 04424 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 04425 { 04426 if ((pData == NULL) || (Size == 0U)) 04427 { 04428 return HAL_ERROR; 04429 } 04430 04431 /* Process Locked */ 04432 __HAL_LOCK(hi2c); 04433 04434 /* Check if the I2C is already enabled */ 04435 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 04436 { 04437 /* Enable I2C peripheral */ 04438 __HAL_I2C_ENABLE(hi2c); 04439 } 04440 04441 /* Disable Pos */ 04442 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 04443 04444 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; 04445 hi2c->Mode = HAL_I2C_MODE_SLAVE; 04446 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 04447 04448 /* Prepare transfer parameters */ 04449 hi2c->pBuffPtr = pData; 04450 hi2c->XferCount = Size; 04451 hi2c->XferSize = hi2c->XferCount; 04452 hi2c->XferOptions = XferOptions; 04453 04454 /* Clear ADDR flag */ 04455 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 04456 04457 /* Process Unlocked */ 04458 __HAL_UNLOCK(hi2c); 04459 04460 /* Note : The I2C interrupts must be enabled after unlocking current process 04461 to avoid the risk of I2C interrupt handle execution before current 04462 process unlock */ 04463 04464 /* Enable EVT, BUF and ERR interrupt */ 04465 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 04466 04467 return HAL_OK; 04468 } 04469 else 04470 { 04471 return HAL_BUSY; 04472 } 04473 } 04474 04475 /** 04476 * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA 04477 * @note This interface allow to manage repeated start condition when a direction change during transfer 04478 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04479 * the configuration information for the specified I2C. 04480 * @param pData Pointer to data buffer 04481 * @param Size Amount of data to be sent 04482 * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition 04483 * @retval HAL status 04484 */ 04485 HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) 04486 { 04487 HAL_StatusTypeDef dmaxferstatus; 04488 04489 /* Check the parameters */ 04490 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); 04491 04492 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 04493 { 04494 if ((pData == NULL) || (Size == 0U)) 04495 { 04496 return HAL_ERROR; 04497 } 04498 04499 /* Process Locked */ 04500 __HAL_LOCK(hi2c); 04501 04502 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ 04503 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 04504 04505 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ 04506 /* and then toggle the HAL slave RX state to TX state */ 04507 if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) 04508 { 04509 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 04510 { 04511 /* Abort DMA Xfer if any */ 04512 if (hi2c->hdmarx != NULL) 04513 { 04514 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 04515 04516 /* Set the I2C DMA Abort callback : 04517 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 04518 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 04519 04520 /* Abort DMA RX */ 04521 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 04522 { 04523 /* Call Directly XferAbortCallback function in case of error */ 04524 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 04525 } 04526 } 04527 } 04528 } 04529 else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) 04530 { 04531 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 04532 { 04533 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 04534 04535 /* Abort DMA Xfer if any */ 04536 if (hi2c->hdmatx != NULL) 04537 { 04538 /* Set the I2C DMA Abort callback : 04539 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 04540 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 04541 04542 /* Abort DMA TX */ 04543 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 04544 { 04545 /* Call Directly XferAbortCallback function in case of error */ 04546 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 04547 } 04548 } 04549 } 04550 } 04551 else 04552 { 04553 /* Nothing to do */ 04554 } 04555 04556 /* Check if the I2C is already enabled */ 04557 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 04558 { 04559 /* Enable I2C peripheral */ 04560 __HAL_I2C_ENABLE(hi2c); 04561 } 04562 04563 /* Disable Pos */ 04564 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 04565 04566 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; 04567 hi2c->Mode = HAL_I2C_MODE_SLAVE; 04568 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 04569 04570 /* Prepare transfer parameters */ 04571 hi2c->pBuffPtr = pData; 04572 hi2c->XferCount = Size; 04573 hi2c->XferSize = hi2c->XferCount; 04574 hi2c->XferOptions = XferOptions; 04575 04576 if (hi2c->hdmarx != NULL) 04577 { 04578 /* Set the I2C DMA transfer complete callback */ 04579 hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; 04580 04581 /* Set the DMA error callback */ 04582 hi2c->hdmarx->XferErrorCallback = I2C_DMAError; 04583 04584 /* Set the unused DMA callbacks to NULL */ 04585 hi2c->hdmarx->XferHalfCpltCallback = NULL; 04586 hi2c->hdmarx->XferAbortCallback = NULL; 04587 04588 /* Enable the DMA stream */ 04589 dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); 04590 } 04591 else 04592 { 04593 /* Update I2C state */ 04594 hi2c->State = HAL_I2C_STATE_LISTEN; 04595 hi2c->Mode = HAL_I2C_MODE_NONE; 04596 04597 /* Update I2C error code */ 04598 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; 04599 04600 /* Process Unlocked */ 04601 __HAL_UNLOCK(hi2c); 04602 04603 return HAL_ERROR; 04604 } 04605 04606 if (dmaxferstatus == HAL_OK) 04607 { 04608 /* Enable Address Acknowledge */ 04609 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04610 04611 /* Clear ADDR flag */ 04612 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 04613 04614 /* Process Unlocked */ 04615 __HAL_UNLOCK(hi2c); 04616 04617 /* Enable DMA Request */ 04618 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 04619 04620 /* Note : The I2C interrupts must be enabled after unlocking current process 04621 to avoid the risk of I2C interrupt handle execution before current 04622 process unlock */ 04623 /* Enable EVT and ERR interrupt */ 04624 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 04625 04626 return HAL_OK; 04627 } 04628 else 04629 { 04630 /* Update I2C state */ 04631 hi2c->State = HAL_I2C_STATE_READY; 04632 hi2c->Mode = HAL_I2C_MODE_NONE; 04633 04634 /* Update I2C error code */ 04635 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 04636 04637 /* Process Unlocked */ 04638 __HAL_UNLOCK(hi2c); 04639 04640 return HAL_ERROR; 04641 } 04642 } 04643 else 04644 { 04645 return HAL_BUSY; 04646 } 04647 } 04648 04649 /** 04650 * @brief Enable the Address listen mode with Interrupt. 04651 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04652 * the configuration information for the specified I2C. 04653 * @retval HAL status 04654 */ 04655 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) 04656 { 04657 if (hi2c->State == HAL_I2C_STATE_READY) 04658 { 04659 hi2c->State = HAL_I2C_STATE_LISTEN; 04660 04661 /* Check if the I2C is already enabled */ 04662 if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) 04663 { 04664 /* Enable I2C peripheral */ 04665 __HAL_I2C_ENABLE(hi2c); 04666 } 04667 04668 /* Enable Address Acknowledge */ 04669 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04670 04671 /* Enable EVT and ERR interrupt */ 04672 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 04673 04674 return HAL_OK; 04675 } 04676 else 04677 { 04678 return HAL_BUSY; 04679 } 04680 } 04681 04682 /** 04683 * @brief Disable the Address listen mode with Interrupt. 04684 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04685 * the configuration information for the specified I2C. 04686 * @retval HAL status 04687 */ 04688 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) 04689 { 04690 /* Declaration of tmp to prevent undefined behavior of volatile usage */ 04691 uint32_t tmp; 04692 04693 /* Disable Address listen mode only if a transfer is not ongoing */ 04694 if (hi2c->State == HAL_I2C_STATE_LISTEN) 04695 { 04696 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; 04697 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); 04698 hi2c->State = HAL_I2C_STATE_READY; 04699 hi2c->Mode = HAL_I2C_MODE_NONE; 04700 04701 /* Disable Address Acknowledge */ 04702 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04703 04704 /* Disable EVT and ERR interrupt */ 04705 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 04706 04707 return HAL_OK; 04708 } 04709 else 04710 { 04711 return HAL_BUSY; 04712 } 04713 } 04714 04715 /** 04716 * @brief Abort a master I2C IT or DMA process communication with Interrupt. 04717 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04718 * the configuration information for the specified I2C. 04719 * @param DevAddress Target device address: The device 7 bits address value 04720 * in datasheet must be shifted to the left before calling the interface 04721 * @retval HAL status 04722 */ 04723 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) 04724 { 04725 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 04726 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 04727 04728 /* Prevent unused argument(s) compilation warning */ 04729 UNUSED(DevAddress); 04730 04731 /* Abort Master transfer during Receive or Transmit process */ 04732 if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) 04733 { 04734 /* Process Locked */ 04735 __HAL_LOCK(hi2c); 04736 04737 hi2c->PreviousState = I2C_STATE_NONE; 04738 hi2c->State = HAL_I2C_STATE_ABORT; 04739 04740 /* Disable Acknowledge */ 04741 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 04742 04743 /* Generate Stop */ 04744 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 04745 04746 hi2c->XferCount = 0U; 04747 04748 /* Disable EVT, BUF and ERR interrupt */ 04749 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 04750 04751 /* Process Unlocked */ 04752 __HAL_UNLOCK(hi2c); 04753 04754 /* Call the corresponding callback to inform upper layer of End of Transfer */ 04755 I2C_ITError(hi2c); 04756 04757 return HAL_OK; 04758 } 04759 else 04760 { 04761 /* Wrong usage of abort function */ 04762 /* This function should be used only in case of abort monitored by master device */ 04763 /* Or periphal is not in busy state, mean there is no active sequence to be abort */ 04764 return HAL_ERROR; 04765 } 04766 } 04767 04768 /** 04769 * @} 04770 */ 04771 04772 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 04773 * @{ 04774 */ 04775 04776 /** 04777 * @brief This function handles I2C event interrupt request. 04778 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04779 * the configuration information for the specified I2C. 04780 * @retval None 04781 */ 04782 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) 04783 { 04784 uint32_t sr1itflags; 04785 uint32_t sr2itflags = 0U; 04786 uint32_t itsources = READ_REG(hi2c->Instance->CR2); 04787 uint32_t CurrentXferOptions = hi2c->XferOptions; 04788 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 04789 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 04790 04791 /* Master or Memory mode selected */ 04792 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) 04793 { 04794 sr2itflags = READ_REG(hi2c->Instance->SR2); 04795 sr1itflags = READ_REG(hi2c->Instance->SR1); 04796 04797 /* Exit IRQ event until Start Bit detected in case of Other frame requested */ 04798 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) 04799 { 04800 return; 04801 } 04802 04803 /* SB Set ----------------------------------------------------------------*/ 04804 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04805 { 04806 /* Convert OTHER_xxx XferOptions if any */ 04807 I2C_ConvertOtherXferOptions(hi2c); 04808 04809 I2C_Master_SB(hi2c); 04810 } 04811 /* ADD10 Set -------------------------------------------------------------*/ 04812 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04813 { 04814 I2C_Master_ADD10(hi2c); 04815 } 04816 /* ADDR Set --------------------------------------------------------------*/ 04817 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04818 { 04819 I2C_Master_ADDR(hi2c); 04820 } 04821 /* I2C in mode Transmitter -----------------------------------------------*/ 04822 else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) 04823 { 04824 /* Do not check buffer and BTF flag if a Xfer DMA is on going */ 04825 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) 04826 { 04827 /* TXE set and BTF reset -----------------------------------------------*/ 04828 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) 04829 { 04830 I2C_MasterTransmit_TXE(hi2c); 04831 } 04832 /* BTF set -------------------------------------------------------------*/ 04833 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04834 { 04835 if (CurrentState == HAL_I2C_STATE_BUSY_TX) 04836 { 04837 I2C_MasterTransmit_BTF(hi2c); 04838 } 04839 else /* HAL_I2C_MODE_MEM */ 04840 { 04841 if (CurrentMode == HAL_I2C_MODE_MEM) 04842 { 04843 I2C_MemoryTransmit_TXE_BTF(hi2c); 04844 } 04845 } 04846 } 04847 else 04848 { 04849 /* Do nothing */ 04850 } 04851 } 04852 } 04853 /* I2C in mode Receiver --------------------------------------------------*/ 04854 else 04855 { 04856 /* Do not check buffer and BTF flag if a Xfer DMA is on going */ 04857 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) 04858 { 04859 /* RXNE set and BTF reset -----------------------------------------------*/ 04860 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) 04861 { 04862 I2C_MasterReceive_RXNE(hi2c); 04863 } 04864 /* BTF set -------------------------------------------------------------*/ 04865 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04866 { 04867 I2C_MasterReceive_BTF(hi2c); 04868 } 04869 else 04870 { 04871 /* Do nothing */ 04872 } 04873 } 04874 } 04875 } 04876 /* Slave mode selected */ 04877 else 04878 { 04879 /* If an error is detected, read only SR1 register to prevent */ 04880 /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ 04881 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 04882 { 04883 sr1itflags = READ_REG(hi2c->Instance->SR1); 04884 } 04885 else 04886 { 04887 sr2itflags = READ_REG(hi2c->Instance->SR2); 04888 sr1itflags = READ_REG(hi2c->Instance->SR1); 04889 } 04890 04891 /* ADDR set --------------------------------------------------------------*/ 04892 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04893 { 04894 /* Now time to read SR2, this will clear ADDR flag automatically */ 04895 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 04896 { 04897 sr2itflags = READ_REG(hi2c->Instance->SR2); 04898 } 04899 I2C_Slave_ADDR(hi2c, sr2itflags); 04900 } 04901 /* STOPF set --------------------------------------------------------------*/ 04902 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04903 { 04904 I2C_Slave_STOPF(hi2c); 04905 } 04906 /* I2C in mode Transmitter -----------------------------------------------*/ 04907 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) 04908 { 04909 /* TXE set and BTF reset -----------------------------------------------*/ 04910 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) 04911 { 04912 I2C_SlaveTransmit_TXE(hi2c); 04913 } 04914 /* BTF set -------------------------------------------------------------*/ 04915 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04916 { 04917 I2C_SlaveTransmit_BTF(hi2c); 04918 } 04919 else 04920 { 04921 /* Do nothing */ 04922 } 04923 } 04924 /* I2C in mode Receiver --------------------------------------------------*/ 04925 else 04926 { 04927 /* RXNE set and BTF reset ----------------------------------------------*/ 04928 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) 04929 { 04930 I2C_SlaveReceive_RXNE(hi2c); 04931 } 04932 /* BTF set -------------------------------------------------------------*/ 04933 else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) 04934 { 04935 I2C_SlaveReceive_BTF(hi2c); 04936 } 04937 else 04938 { 04939 /* Do nothing */ 04940 } 04941 } 04942 } 04943 } 04944 04945 /** 04946 * @brief This function handles I2C error interrupt request. 04947 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 04948 * the configuration information for the specified I2C. 04949 * @retval None 04950 */ 04951 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) 04952 { 04953 HAL_I2C_ModeTypeDef tmp1; 04954 uint32_t tmp2; 04955 HAL_I2C_StateTypeDef tmp3; 04956 uint32_t tmp4; 04957 uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); 04958 uint32_t itsources = READ_REG(hi2c->Instance->CR2); 04959 uint32_t error = HAL_I2C_ERROR_NONE; 04960 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 04961 04962 /* I2C Bus error interrupt occurred ----------------------------------------*/ 04963 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) 04964 { 04965 error |= HAL_I2C_ERROR_BERR; 04966 04967 /* Clear BERR flag */ 04968 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); 04969 } 04970 04971 /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ 04972 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) 04973 { 04974 error |= HAL_I2C_ERROR_ARLO; 04975 04976 /* Clear ARLO flag */ 04977 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); 04978 } 04979 04980 /* I2C Acknowledge failure error interrupt occurred ------------------------*/ 04981 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) 04982 { 04983 tmp1 = CurrentMode; 04984 tmp2 = hi2c->XferCount; 04985 tmp3 = hi2c->State; 04986 tmp4 = hi2c->PreviousState; 04987 if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ 04988 ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ 04989 ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) 04990 { 04991 I2C_Slave_AF(hi2c); 04992 } 04993 else 04994 { 04995 /* Clear AF flag */ 04996 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 04997 04998 error |= HAL_I2C_ERROR_AF; 04999 05000 /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ 05001 if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) 05002 { 05003 /* Generate Stop */ 05004 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 05005 } 05006 } 05007 } 05008 05009 /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ 05010 if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) 05011 { 05012 error |= HAL_I2C_ERROR_OVR; 05013 /* Clear OVR flag */ 05014 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); 05015 } 05016 05017 /* Call the Error Callback in case of Error detected -----------------------*/ 05018 if (error != HAL_I2C_ERROR_NONE) 05019 { 05020 hi2c->ErrorCode |= error; 05021 I2C_ITError(hi2c); 05022 } 05023 } 05024 05025 /** 05026 * @brief Master Tx Transfer completed callback. 05027 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05028 * the configuration information for the specified I2C. 05029 * @retval None 05030 */ 05031 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) 05032 { 05033 /* Prevent unused argument(s) compilation warning */ 05034 UNUSED(hi2c); 05035 05036 /* NOTE : This function should not be modified, when the callback is needed, 05037 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file 05038 */ 05039 } 05040 05041 /** 05042 * @brief Master Rx Transfer completed callback. 05043 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05044 * the configuration information for the specified I2C. 05045 * @retval None 05046 */ 05047 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) 05048 { 05049 /* Prevent unused argument(s) compilation warning */ 05050 UNUSED(hi2c); 05051 05052 /* NOTE : This function should not be modified, when the callback is needed, 05053 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file 05054 */ 05055 } 05056 05057 /** @brief Slave Tx Transfer completed callback. 05058 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05059 * the configuration information for the specified I2C. 05060 * @retval None 05061 */ 05062 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) 05063 { 05064 /* Prevent unused argument(s) compilation warning */ 05065 UNUSED(hi2c); 05066 05067 /* NOTE : This function should not be modified, when the callback is needed, 05068 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file 05069 */ 05070 } 05071 05072 /** 05073 * @brief Slave Rx Transfer completed callback. 05074 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05075 * the configuration information for the specified I2C. 05076 * @retval None 05077 */ 05078 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) 05079 { 05080 /* Prevent unused argument(s) compilation warning */ 05081 UNUSED(hi2c); 05082 05083 /* NOTE : This function should not be modified, when the callback is needed, 05084 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file 05085 */ 05086 } 05087 05088 /** 05089 * @brief Slave Address Match callback. 05090 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05091 * the configuration information for the specified I2C. 05092 * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition 05093 * @param AddrMatchCode Address Match Code 05094 * @retval None 05095 */ 05096 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) 05097 { 05098 /* Prevent unused argument(s) compilation warning */ 05099 UNUSED(hi2c); 05100 UNUSED(TransferDirection); 05101 UNUSED(AddrMatchCode); 05102 05103 /* NOTE : This function should not be modified, when the callback is needed, 05104 the HAL_I2C_AddrCallback() could be implemented in the user file 05105 */ 05106 } 05107 05108 /** 05109 * @brief Listen Complete callback. 05110 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05111 * the configuration information for the specified I2C. 05112 * @retval None 05113 */ 05114 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) 05115 { 05116 /* Prevent unused argument(s) compilation warning */ 05117 UNUSED(hi2c); 05118 05119 /* NOTE : This function should not be modified, when the callback is needed, 05120 the HAL_I2C_ListenCpltCallback() could be implemented in the user file 05121 */ 05122 } 05123 05124 /** 05125 * @brief Memory Tx Transfer completed callback. 05126 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05127 * the configuration information for the specified I2C. 05128 * @retval None 05129 */ 05130 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) 05131 { 05132 /* Prevent unused argument(s) compilation warning */ 05133 UNUSED(hi2c); 05134 05135 /* NOTE : This function should not be modified, when the callback is needed, 05136 the HAL_I2C_MemTxCpltCallback could be implemented in the user file 05137 */ 05138 } 05139 05140 /** 05141 * @brief Memory Rx Transfer completed callback. 05142 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05143 * the configuration information for the specified I2C. 05144 * @retval None 05145 */ 05146 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) 05147 { 05148 /* Prevent unused argument(s) compilation warning */ 05149 UNUSED(hi2c); 05150 05151 /* NOTE : This function should not be modified, when the callback is needed, 05152 the HAL_I2C_MemRxCpltCallback could be implemented in the user file 05153 */ 05154 } 05155 05156 /** 05157 * @brief I2C error callback. 05158 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05159 * the configuration information for the specified I2C. 05160 * @retval None 05161 */ 05162 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) 05163 { 05164 /* Prevent unused argument(s) compilation warning */ 05165 UNUSED(hi2c); 05166 05167 /* NOTE : This function should not be modified, when the callback is needed, 05168 the HAL_I2C_ErrorCallback could be implemented in the user file 05169 */ 05170 } 05171 05172 /** 05173 * @brief I2C abort callback. 05174 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05175 * the configuration information for the specified I2C. 05176 * @retval None 05177 */ 05178 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) 05179 { 05180 /* Prevent unused argument(s) compilation warning */ 05181 UNUSED(hi2c); 05182 05183 /* NOTE : This function should not be modified, when the callback is needed, 05184 the HAL_I2C_AbortCpltCallback could be implemented in the user file 05185 */ 05186 } 05187 05188 /** 05189 * @} 05190 */ 05191 05192 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions 05193 * @brief Peripheral State, Mode and Error functions 05194 * 05195 @verbatim 05196 =============================================================================== 05197 ##### Peripheral State, Mode and Error functions ##### 05198 =============================================================================== 05199 [..] 05200 This subsection permit to get in run-time the status of the peripheral 05201 and the data flow. 05202 05203 @endverbatim 05204 * @{ 05205 */ 05206 05207 /** 05208 * @brief Return the I2C handle state. 05209 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05210 * the configuration information for the specified I2C. 05211 * @retval HAL state 05212 */ 05213 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) 05214 { 05215 /* Return I2C handle state */ 05216 return hi2c->State; 05217 } 05218 05219 /** 05220 * @brief Returns the I2C Master, Slave, Memory or no mode. 05221 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05222 * the configuration information for I2C module 05223 * @retval HAL mode 05224 */ 05225 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) 05226 { 05227 return hi2c->Mode; 05228 } 05229 05230 /** 05231 * @brief Return the I2C error code. 05232 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05233 * the configuration information for the specified I2C. 05234 * @retval I2C Error Code 05235 */ 05236 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) 05237 { 05238 return hi2c->ErrorCode; 05239 } 05240 05241 /** 05242 * @} 05243 */ 05244 05245 /** 05246 * @} 05247 */ 05248 05249 /** @addtogroup I2C_Private_Functions 05250 * @{ 05251 */ 05252 05253 /** 05254 * @brief Handle TXE flag for Master 05255 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05256 * the configuration information for I2C module 05257 * @retval None 05258 */ 05259 static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) 05260 { 05261 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 05262 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 05263 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 05264 uint32_t CurrentXferOptions = hi2c->XferOptions; 05265 05266 if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) 05267 { 05268 /* Call TxCpltCallback() directly if no stop mode is set */ 05269 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) 05270 { 05271 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 05272 05273 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 05274 hi2c->Mode = HAL_I2C_MODE_NONE; 05275 hi2c->State = HAL_I2C_STATE_READY; 05276 05277 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05278 hi2c->MasterTxCpltCallback(hi2c); 05279 #else 05280 HAL_I2C_MasterTxCpltCallback(hi2c); 05281 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05282 } 05283 else /* Generate Stop condition then Call TxCpltCallback() */ 05284 { 05285 /* Disable EVT, BUF and ERR interrupt */ 05286 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 05287 05288 /* Generate Stop */ 05289 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 05290 05291 hi2c->PreviousState = I2C_STATE_NONE; 05292 hi2c->State = HAL_I2C_STATE_READY; 05293 05294 if (hi2c->Mode == HAL_I2C_MODE_MEM) 05295 { 05296 hi2c->Mode = HAL_I2C_MODE_NONE; 05297 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05298 hi2c->MemTxCpltCallback(hi2c); 05299 #else 05300 HAL_I2C_MemTxCpltCallback(hi2c); 05301 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05302 } 05303 else 05304 { 05305 hi2c->Mode = HAL_I2C_MODE_NONE; 05306 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05307 hi2c->MasterTxCpltCallback(hi2c); 05308 #else 05309 HAL_I2C_MasterTxCpltCallback(hi2c); 05310 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05311 } 05312 } 05313 } 05314 else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ 05315 ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) 05316 { 05317 if (hi2c->XferCount == 0U) 05318 { 05319 /* Disable BUF interrupt */ 05320 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 05321 } 05322 else 05323 { 05324 if (hi2c->Mode == HAL_I2C_MODE_MEM) 05325 { 05326 I2C_MemoryTransmit_TXE_BTF(hi2c); 05327 } 05328 else 05329 { 05330 /* Write data to DR */ 05331 hi2c->Instance->DR = *hi2c->pBuffPtr; 05332 05333 /* Increment Buffer pointer */ 05334 hi2c->pBuffPtr++; 05335 05336 /* Update counter */ 05337 hi2c->XferCount--; 05338 } 05339 } 05340 } 05341 else 05342 { 05343 /* Do nothing */ 05344 } 05345 } 05346 05347 /** 05348 * @brief Handle BTF flag for Master transmitter 05349 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05350 * the configuration information for I2C module 05351 * @retval None 05352 */ 05353 static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) 05354 { 05355 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 05356 uint32_t CurrentXferOptions = hi2c->XferOptions; 05357 05358 if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 05359 { 05360 if (hi2c->XferCount != 0U) 05361 { 05362 /* Write data to DR */ 05363 hi2c->Instance->DR = *hi2c->pBuffPtr; 05364 05365 /* Increment Buffer pointer */ 05366 hi2c->pBuffPtr++; 05367 05368 /* Update counter */ 05369 hi2c->XferCount--; 05370 } 05371 else 05372 { 05373 /* Call TxCpltCallback() directly if no stop mode is set */ 05374 if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) 05375 { 05376 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 05377 05378 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; 05379 hi2c->Mode = HAL_I2C_MODE_NONE; 05380 hi2c->State = HAL_I2C_STATE_READY; 05381 05382 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05383 hi2c->MasterTxCpltCallback(hi2c); 05384 #else 05385 HAL_I2C_MasterTxCpltCallback(hi2c); 05386 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05387 } 05388 else /* Generate Stop condition then Call TxCpltCallback() */ 05389 { 05390 /* Disable EVT, BUF and ERR interrupt */ 05391 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 05392 05393 /* Generate Stop */ 05394 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 05395 05396 hi2c->PreviousState = I2C_STATE_NONE; 05397 hi2c->State = HAL_I2C_STATE_READY; 05398 if (hi2c->Mode == HAL_I2C_MODE_MEM) 05399 { 05400 hi2c->Mode = HAL_I2C_MODE_NONE; 05401 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05402 hi2c->MemTxCpltCallback(hi2c); 05403 #else 05404 HAL_I2C_MemTxCpltCallback(hi2c); 05405 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05406 } 05407 else 05408 { 05409 hi2c->Mode = HAL_I2C_MODE_NONE; 05410 05411 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05412 hi2c->MasterTxCpltCallback(hi2c); 05413 #else 05414 HAL_I2C_MasterTxCpltCallback(hi2c); 05415 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05416 } 05417 } 05418 } 05419 } 05420 else 05421 { 05422 /* Do nothing */ 05423 } 05424 } 05425 05426 /** 05427 * @brief Handle TXE and BTF flag for Memory transmitter 05428 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05429 * the configuration information for I2C module 05430 * @retval None 05431 */ 05432 static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) 05433 { 05434 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 05435 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 05436 05437 if (hi2c->EventCount == 0U) 05438 { 05439 /* If Memory address size is 8Bit */ 05440 if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) 05441 { 05442 /* Send Memory Address */ 05443 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); 05444 05445 hi2c->EventCount += 2U; 05446 } 05447 /* If Memory address size is 16Bit */ 05448 else 05449 { 05450 /* Send MSB of Memory Address */ 05451 hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); 05452 05453 hi2c->EventCount++; 05454 } 05455 } 05456 else if (hi2c->EventCount == 1U) 05457 { 05458 /* Send LSB of Memory Address */ 05459 hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); 05460 05461 hi2c->EventCount++; 05462 } 05463 else if (hi2c->EventCount == 2U) 05464 { 05465 if (CurrentState == HAL_I2C_STATE_BUSY_RX) 05466 { 05467 /* Generate Restart */ 05468 hi2c->Instance->CR1 |= I2C_CR1_START; 05469 05470 hi2c->EventCount++; 05471 } 05472 else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) 05473 { 05474 /* Write data to DR */ 05475 hi2c->Instance->DR = *hi2c->pBuffPtr; 05476 05477 /* Increment Buffer pointer */ 05478 hi2c->pBuffPtr++; 05479 05480 /* Update counter */ 05481 hi2c->XferCount--; 05482 } 05483 else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) 05484 { 05485 /* Generate Stop condition then Call TxCpltCallback() */ 05486 /* Disable EVT, BUF and ERR interrupt */ 05487 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 05488 05489 /* Generate Stop */ 05490 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 05491 05492 hi2c->PreviousState = I2C_STATE_NONE; 05493 hi2c->State = HAL_I2C_STATE_READY; 05494 hi2c->Mode = HAL_I2C_MODE_NONE; 05495 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05496 hi2c->MemTxCpltCallback(hi2c); 05497 #else 05498 HAL_I2C_MemTxCpltCallback(hi2c); 05499 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05500 } 05501 else 05502 { 05503 /* Do nothing */ 05504 } 05505 } 05506 else 05507 { 05508 /* Do nothing */ 05509 } 05510 } 05511 05512 /** 05513 * @brief Handle RXNE flag for Master 05514 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05515 * the configuration information for I2C module 05516 * @retval None 05517 */ 05518 static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) 05519 { 05520 if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 05521 { 05522 uint32_t tmp; 05523 05524 tmp = hi2c->XferCount; 05525 if (tmp > 3U) 05526 { 05527 /* Read data from DR */ 05528 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 05529 05530 /* Increment Buffer pointer */ 05531 hi2c->pBuffPtr++; 05532 05533 /* Update counter */ 05534 hi2c->XferCount--; 05535 05536 if (hi2c->XferCount == (uint16_t)3) 05537 { 05538 /* Disable BUF interrupt, this help to treat correctly the last 4 bytes 05539 on BTF subroutine */ 05540 /* Disable BUF interrupt */ 05541 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 05542 } 05543 } 05544 else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) 05545 { 05546 if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) 05547 { 05548 /* Disable Acknowledge */ 05549 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05550 05551 /* Disable EVT, BUF and ERR interrupt */ 05552 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 05553 05554 /* Read data from DR */ 05555 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 05556 05557 /* Increment Buffer pointer */ 05558 hi2c->pBuffPtr++; 05559 05560 /* Update counter */ 05561 hi2c->XferCount--; 05562 05563 hi2c->State = HAL_I2C_STATE_READY; 05564 05565 if (hi2c->Mode == HAL_I2C_MODE_MEM) 05566 { 05567 hi2c->Mode = HAL_I2C_MODE_NONE; 05568 hi2c->PreviousState = I2C_STATE_NONE; 05569 05570 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05571 hi2c->MemRxCpltCallback(hi2c); 05572 #else 05573 HAL_I2C_MemRxCpltCallback(hi2c); 05574 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05575 } 05576 else 05577 { 05578 hi2c->Mode = HAL_I2C_MODE_NONE; 05579 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 05580 05581 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05582 hi2c->MasterRxCpltCallback(hi2c); 05583 #else 05584 HAL_I2C_MasterRxCpltCallback(hi2c); 05585 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05586 } 05587 } 05588 else 05589 { 05590 /* Disable EVT, BUF and ERR interrupt */ 05591 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 05592 05593 /* Read data from DR */ 05594 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 05595 05596 /* Increment Buffer pointer */ 05597 hi2c->pBuffPtr++; 05598 05599 /* Update counter */ 05600 hi2c->XferCount--; 05601 05602 hi2c->State = HAL_I2C_STATE_READY; 05603 hi2c->Mode = HAL_I2C_MODE_NONE; 05604 05605 /* Call user error callback */ 05606 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05607 hi2c->ErrorCallback(hi2c); 05608 #else 05609 HAL_I2C_ErrorCallback(hi2c); 05610 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05611 } 05612 } 05613 else 05614 { 05615 /* Do nothing */ 05616 } 05617 } 05618 } 05619 05620 /** 05621 * @brief Handle BTF flag for Master receiver 05622 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05623 * the configuration information for I2C module 05624 * @retval None 05625 */ 05626 static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) 05627 { 05628 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 05629 uint32_t CurrentXferOptions = hi2c->XferOptions; 05630 05631 if (hi2c->XferCount == 4U) 05632 { 05633 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes 05634 on BTF subroutine if there is a reception delay between N-1 and N byte */ 05635 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 05636 05637 /* Read data from DR */ 05638 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 05639 05640 /* Increment Buffer pointer */ 05641 hi2c->pBuffPtr++; 05642 05643 /* Update counter */ 05644 hi2c->XferCount--; 05645 } 05646 else if (hi2c->XferCount == 3U) 05647 { 05648 /* Disable BUF interrupt, this help to treat correctly the last 2 bytes 05649 on BTF subroutine if there is a reception delay between N-1 and N byte */ 05650 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 05651 05652 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) 05653 { 05654 /* Disable Acknowledge */ 05655 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05656 } 05657 05658 /* Read data from DR */ 05659 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 05660 05661 /* Increment Buffer pointer */ 05662 hi2c->pBuffPtr++; 05663 05664 /* Update counter */ 05665 hi2c->XferCount--; 05666 } 05667 else if (hi2c->XferCount == 2U) 05668 { 05669 /* Prepare next transfer or stop current transfer */ 05670 if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) 05671 { 05672 /* Disable Acknowledge */ 05673 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05674 } 05675 else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) 05676 { 05677 /* Enable Acknowledge */ 05678 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05679 } 05680 else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP) 05681 { 05682 /* Generate Stop */ 05683 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 05684 } 05685 else 05686 { 05687 /* Do nothing */ 05688 } 05689 05690 /* Read data from DR */ 05691 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 05692 05693 /* Increment Buffer pointer */ 05694 hi2c->pBuffPtr++; 05695 05696 /* Update counter */ 05697 hi2c->XferCount--; 05698 05699 /* Read data from DR */ 05700 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 05701 05702 /* Increment Buffer pointer */ 05703 hi2c->pBuffPtr++; 05704 05705 /* Update counter */ 05706 hi2c->XferCount--; 05707 05708 /* Disable EVT and ERR interrupt */ 05709 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 05710 05711 hi2c->State = HAL_I2C_STATE_READY; 05712 if (hi2c->Mode == HAL_I2C_MODE_MEM) 05713 { 05714 hi2c->Mode = HAL_I2C_MODE_NONE; 05715 hi2c->PreviousState = I2C_STATE_NONE; 05716 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05717 hi2c->MemRxCpltCallback(hi2c); 05718 #else 05719 HAL_I2C_MemRxCpltCallback(hi2c); 05720 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05721 } 05722 else 05723 { 05724 hi2c->Mode = HAL_I2C_MODE_NONE; 05725 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 05726 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 05727 hi2c->MasterRxCpltCallback(hi2c); 05728 #else 05729 HAL_I2C_MasterRxCpltCallback(hi2c); 05730 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 05731 } 05732 } 05733 else 05734 { 05735 /* Read data from DR */ 05736 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 05737 05738 /* Increment Buffer pointer */ 05739 hi2c->pBuffPtr++; 05740 05741 /* Update counter */ 05742 hi2c->XferCount--; 05743 } 05744 } 05745 05746 /** 05747 * @brief Handle SB flag for Master 05748 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05749 * the configuration information for I2C module 05750 * @retval None 05751 */ 05752 static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) 05753 { 05754 if (hi2c->Mode == HAL_I2C_MODE_MEM) 05755 { 05756 if (hi2c->EventCount == 0U) 05757 { 05758 /* Send slave address */ 05759 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); 05760 } 05761 else 05762 { 05763 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); 05764 } 05765 } 05766 else 05767 { 05768 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 05769 { 05770 /* Send slave 7 Bits address */ 05771 if (hi2c->State == HAL_I2C_STATE_BUSY_TX) 05772 { 05773 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); 05774 } 05775 else 05776 { 05777 hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); 05778 } 05779 05780 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) 05781 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) 05782 { 05783 /* Enable DMA Request */ 05784 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 05785 } 05786 } 05787 else 05788 { 05789 if (hi2c->EventCount == 0U) 05790 { 05791 /* Send header of slave address */ 05792 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); 05793 } 05794 else if (hi2c->EventCount == 1U) 05795 { 05796 /* Send header of slave address */ 05797 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); 05798 } 05799 else 05800 { 05801 /* Do nothing */ 05802 } 05803 } 05804 } 05805 } 05806 05807 /** 05808 * @brief Handle ADD10 flag for Master 05809 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05810 * the configuration information for I2C module 05811 * @retval None 05812 */ 05813 static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) 05814 { 05815 /* Send slave address */ 05816 hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); 05817 05818 if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) 05819 || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) 05820 { 05821 /* Enable DMA Request */ 05822 SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 05823 } 05824 } 05825 05826 /** 05827 * @brief Handle ADDR flag for Master 05828 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05829 * the configuration information for I2C module 05830 * @retval None 05831 */ 05832 static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) 05833 { 05834 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 05835 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 05836 uint32_t CurrentXferOptions = hi2c->XferOptions; 05837 uint32_t Prev_State = hi2c->PreviousState; 05838 05839 if (hi2c->State == HAL_I2C_STATE_BUSY_RX) 05840 { 05841 if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) 05842 { 05843 /* Clear ADDR flag */ 05844 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05845 } 05846 else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) 05847 { 05848 /* Clear ADDR flag */ 05849 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05850 05851 /* Generate Restart */ 05852 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 05853 05854 hi2c->EventCount++; 05855 } 05856 else 05857 { 05858 if (hi2c->XferCount == 0U) 05859 { 05860 /* Clear ADDR flag */ 05861 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05862 05863 /* Generate Stop */ 05864 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 05865 } 05866 else if (hi2c->XferCount == 1U) 05867 { 05868 if (CurrentXferOptions == I2C_NO_OPTION_FRAME) 05869 { 05870 /* Disable Acknowledge */ 05871 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05872 05873 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 05874 { 05875 /* Disable Acknowledge */ 05876 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05877 05878 /* Clear ADDR flag */ 05879 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05880 } 05881 else 05882 { 05883 /* Clear ADDR flag */ 05884 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05885 05886 /* Generate Stop */ 05887 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 05888 } 05889 } 05890 /* Prepare next transfer or stop current transfer */ 05891 else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ 05892 && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) 05893 { 05894 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) 05895 { 05896 /* Disable Acknowledge */ 05897 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05898 } 05899 else 05900 { 05901 /* Enable Acknowledge */ 05902 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05903 } 05904 05905 /* Clear ADDR flag */ 05906 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05907 } 05908 else 05909 { 05910 /* Disable Acknowledge */ 05911 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05912 05913 /* Clear ADDR flag */ 05914 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05915 05916 /* Generate Stop */ 05917 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 05918 } 05919 } 05920 else if (hi2c->XferCount == 2U) 05921 { 05922 if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) 05923 { 05924 /* Disable Acknowledge */ 05925 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05926 05927 /* Enable Pos */ 05928 SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); 05929 } 05930 else 05931 { 05932 /* Enable Acknowledge */ 05933 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05934 } 05935 05936 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) 05937 { 05938 /* Enable Last DMA bit */ 05939 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 05940 } 05941 05942 /* Clear ADDR flag */ 05943 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05944 } 05945 else 05946 { 05947 /* Enable Acknowledge */ 05948 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 05949 05950 if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) 05951 { 05952 /* Enable Last DMA bit */ 05953 SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 05954 } 05955 05956 /* Clear ADDR flag */ 05957 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05958 } 05959 05960 /* Reset Event counter */ 05961 hi2c->EventCount = 0U; 05962 } 05963 } 05964 else 05965 { 05966 /* Clear ADDR flag */ 05967 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 05968 } 05969 } 05970 05971 /** 05972 * @brief Handle TXE flag for Slave 05973 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 05974 * the configuration information for I2C module 05975 * @retval None 05976 */ 05977 static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) 05978 { 05979 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 05980 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 05981 05982 if (hi2c->XferCount != 0U) 05983 { 05984 /* Write data to DR */ 05985 hi2c->Instance->DR = *hi2c->pBuffPtr; 05986 05987 /* Increment Buffer pointer */ 05988 hi2c->pBuffPtr++; 05989 05990 /* Update counter */ 05991 hi2c->XferCount--; 05992 05993 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) 05994 { 05995 /* Last Byte is received, disable Interrupt */ 05996 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 05997 05998 /* Set state at HAL_I2C_STATE_LISTEN */ 05999 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 06000 hi2c->State = HAL_I2C_STATE_LISTEN; 06001 06002 /* Call the corresponding callback to inform upper layer of End of Transfer */ 06003 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06004 hi2c->SlaveTxCpltCallback(hi2c); 06005 #else 06006 HAL_I2C_SlaveTxCpltCallback(hi2c); 06007 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06008 } 06009 } 06010 } 06011 06012 /** 06013 * @brief Handle BTF flag for Slave transmitter 06014 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06015 * the configuration information for I2C module 06016 * @retval None 06017 */ 06018 static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) 06019 { 06020 if (hi2c->XferCount != 0U) 06021 { 06022 /* Write data to DR */ 06023 hi2c->Instance->DR = *hi2c->pBuffPtr; 06024 06025 /* Increment Buffer pointer */ 06026 hi2c->pBuffPtr++; 06027 06028 /* Update counter */ 06029 hi2c->XferCount--; 06030 } 06031 } 06032 06033 /** 06034 * @brief Handle RXNE flag for Slave 06035 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06036 * the configuration information for I2C module 06037 * @retval None 06038 */ 06039 static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) 06040 { 06041 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 06042 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 06043 06044 if (hi2c->XferCount != 0U) 06045 { 06046 /* Read data from DR */ 06047 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 06048 06049 /* Increment Buffer pointer */ 06050 hi2c->pBuffPtr++; 06051 06052 /* Update counter */ 06053 hi2c->XferCount--; 06054 06055 if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) 06056 { 06057 /* Last Byte is received, disable Interrupt */ 06058 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); 06059 06060 /* Set state at HAL_I2C_STATE_LISTEN */ 06061 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 06062 hi2c->State = HAL_I2C_STATE_LISTEN; 06063 06064 /* Call the corresponding callback to inform upper layer of End of Transfer */ 06065 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06066 hi2c->SlaveRxCpltCallback(hi2c); 06067 #else 06068 HAL_I2C_SlaveRxCpltCallback(hi2c); 06069 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06070 } 06071 } 06072 } 06073 06074 /** 06075 * @brief Handle BTF flag for Slave receiver 06076 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06077 * the configuration information for I2C module 06078 * @retval None 06079 */ 06080 static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) 06081 { 06082 if (hi2c->XferCount != 0U) 06083 { 06084 /* Read data from DR */ 06085 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 06086 06087 /* Increment Buffer pointer */ 06088 hi2c->pBuffPtr++; 06089 06090 /* Update counter */ 06091 hi2c->XferCount--; 06092 } 06093 } 06094 06095 /** 06096 * @brief Handle ADD flag for Slave 06097 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06098 * the configuration information for I2C module 06099 * @param IT2Flags Interrupt2 flags to handle. 06100 * @retval None 06101 */ 06102 static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) 06103 { 06104 uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; 06105 uint16_t SlaveAddrCode; 06106 06107 if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 06108 { 06109 /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ 06110 __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); 06111 06112 /* Transfer Direction requested by Master */ 06113 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) 06114 { 06115 TransferDirection = I2C_DIRECTION_TRANSMIT; 06116 } 06117 06118 if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) 06119 { 06120 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; 06121 } 06122 else 06123 { 06124 SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; 06125 } 06126 06127 /* Process Unlocked */ 06128 __HAL_UNLOCK(hi2c); 06129 06130 /* Call Slave Addr callback */ 06131 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06132 hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); 06133 #else 06134 HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); 06135 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06136 } 06137 else 06138 { 06139 /* Clear ADDR flag */ 06140 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 06141 06142 /* Process Unlocked */ 06143 __HAL_UNLOCK(hi2c); 06144 } 06145 } 06146 06147 /** 06148 * @brief Handle STOPF flag for Slave 06149 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06150 * the configuration information for I2C module 06151 * @retval None 06152 */ 06153 static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) 06154 { 06155 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 06156 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 06157 06158 /* Disable EVT, BUF and ERR interrupt */ 06159 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 06160 06161 /* Clear STOPF flag */ 06162 __HAL_I2C_CLEAR_STOPFLAG(hi2c); 06163 06164 /* Disable Acknowledge */ 06165 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 06166 06167 /* If a DMA is ongoing, Update handle size context */ 06168 if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 06169 { 06170 if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) 06171 { 06172 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx)); 06173 06174 if (hi2c->XferCount != 0U) 06175 { 06176 /* Set ErrorCode corresponding to a Non-Acknowledge */ 06177 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 06178 } 06179 06180 /* Disable, stop the current DMA */ 06181 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 06182 06183 /* Abort DMA Xfer if any */ 06184 if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) 06185 { 06186 /* Set the I2C DMA Abort callback : 06187 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 06188 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 06189 06190 /* Abort DMA RX */ 06191 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 06192 { 06193 /* Call Directly XferAbortCallback function in case of error */ 06194 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 06195 } 06196 } 06197 } 06198 else 06199 { 06200 hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx)); 06201 06202 if (hi2c->XferCount != 0U) 06203 { 06204 /* Set ErrorCode corresponding to a Non-Acknowledge */ 06205 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 06206 } 06207 06208 /* Disable, stop the current DMA */ 06209 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 06210 06211 /* Abort DMA Xfer if any */ 06212 if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) 06213 { 06214 /* Set the I2C DMA Abort callback : 06215 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 06216 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 06217 06218 /* Abort DMA TX */ 06219 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 06220 { 06221 /* Call Directly XferAbortCallback function in case of error */ 06222 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 06223 } 06224 } 06225 } 06226 } 06227 06228 /* All data are not transferred, so set error code accordingly */ 06229 if (hi2c->XferCount != 0U) 06230 { 06231 /* Store Last receive data if any */ 06232 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) 06233 { 06234 /* Read data from DR */ 06235 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 06236 06237 /* Increment Buffer pointer */ 06238 hi2c->pBuffPtr++; 06239 06240 /* Update counter */ 06241 hi2c->XferCount--; 06242 } 06243 06244 /* Store Last receive data if any */ 06245 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) 06246 { 06247 /* Read data from DR */ 06248 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 06249 06250 /* Increment Buffer pointer */ 06251 hi2c->pBuffPtr++; 06252 06253 /* Update counter */ 06254 hi2c->XferCount--; 06255 } 06256 06257 if (hi2c->XferCount != 0U) 06258 { 06259 /* Set ErrorCode corresponding to a Non-Acknowledge */ 06260 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 06261 } 06262 } 06263 06264 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 06265 { 06266 /* Call the corresponding callback to inform upper layer of End of Transfer */ 06267 I2C_ITError(hi2c); 06268 } 06269 else 06270 { 06271 if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) 06272 { 06273 /* Set state at HAL_I2C_STATE_LISTEN */ 06274 hi2c->PreviousState = I2C_STATE_NONE; 06275 hi2c->State = HAL_I2C_STATE_LISTEN; 06276 06277 /* Call the corresponding callback to inform upper layer of End of Transfer */ 06278 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06279 hi2c->SlaveRxCpltCallback(hi2c); 06280 #else 06281 HAL_I2C_SlaveRxCpltCallback(hi2c); 06282 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06283 } 06284 06285 if (hi2c->State == HAL_I2C_STATE_LISTEN) 06286 { 06287 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 06288 hi2c->PreviousState = I2C_STATE_NONE; 06289 hi2c->State = HAL_I2C_STATE_READY; 06290 hi2c->Mode = HAL_I2C_MODE_NONE; 06291 06292 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ 06293 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06294 hi2c->ListenCpltCallback(hi2c); 06295 #else 06296 HAL_I2C_ListenCpltCallback(hi2c); 06297 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06298 } 06299 else 06300 { 06301 if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) 06302 { 06303 hi2c->PreviousState = I2C_STATE_NONE; 06304 hi2c->State = HAL_I2C_STATE_READY; 06305 hi2c->Mode = HAL_I2C_MODE_NONE; 06306 06307 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06308 hi2c->SlaveRxCpltCallback(hi2c); 06309 #else 06310 HAL_I2C_SlaveRxCpltCallback(hi2c); 06311 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06312 } 06313 } 06314 } 06315 } 06316 06317 /** 06318 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06319 * the configuration information for I2C module 06320 * @retval None 06321 */ 06322 static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) 06323 { 06324 /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ 06325 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 06326 uint32_t CurrentXferOptions = hi2c->XferOptions; 06327 06328 if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ 06329 (CurrentState == HAL_I2C_STATE_LISTEN)) 06330 { 06331 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 06332 06333 /* Disable EVT, BUF and ERR interrupt */ 06334 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 06335 06336 /* Clear AF flag */ 06337 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 06338 06339 /* Disable Acknowledge */ 06340 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 06341 06342 hi2c->PreviousState = I2C_STATE_NONE; 06343 hi2c->State = HAL_I2C_STATE_READY; 06344 hi2c->Mode = HAL_I2C_MODE_NONE; 06345 06346 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ 06347 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06348 hi2c->ListenCpltCallback(hi2c); 06349 #else 06350 HAL_I2C_ListenCpltCallback(hi2c); 06351 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06352 } 06353 else if (CurrentState == HAL_I2C_STATE_BUSY_TX) 06354 { 06355 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 06356 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 06357 hi2c->State = HAL_I2C_STATE_READY; 06358 hi2c->Mode = HAL_I2C_MODE_NONE; 06359 06360 /* Disable EVT, BUF and ERR interrupt */ 06361 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 06362 06363 /* Clear AF flag */ 06364 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 06365 06366 /* Disable Acknowledge */ 06367 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 06368 06369 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06370 hi2c->SlaveTxCpltCallback(hi2c); 06371 #else 06372 HAL_I2C_SlaveTxCpltCallback(hi2c); 06373 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06374 } 06375 else 06376 { 06377 /* Clear AF flag only */ 06378 /* State Listen, but XferOptions == FIRST or NEXT */ 06379 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 06380 } 06381 } 06382 06383 /** 06384 * @brief I2C interrupts error process 06385 * @param hi2c I2C handle. 06386 * @retval None 06387 */ 06388 static void I2C_ITError(I2C_HandleTypeDef *hi2c) 06389 { 06390 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 06391 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 06392 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 06393 uint32_t CurrentError; 06394 06395 if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) 06396 { 06397 /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ 06398 hi2c->Instance->CR1 &= ~I2C_CR1_POS; 06399 } 06400 06401 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 06402 { 06403 /* keep HAL_I2C_STATE_LISTEN */ 06404 hi2c->PreviousState = I2C_STATE_NONE; 06405 hi2c->State = HAL_I2C_STATE_LISTEN; 06406 } 06407 else 06408 { 06409 /* If state is an abort treatment on going, don't change state */ 06410 /* This change will be do later */ 06411 if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) 06412 { 06413 hi2c->State = HAL_I2C_STATE_READY; 06414 hi2c->Mode = HAL_I2C_MODE_NONE; 06415 } 06416 hi2c->PreviousState = I2C_STATE_NONE; 06417 } 06418 06419 /* Abort DMA transfer */ 06420 if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) 06421 { 06422 hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; 06423 06424 if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) 06425 { 06426 /* Set the DMA Abort callback : 06427 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 06428 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; 06429 06430 if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) 06431 { 06432 /* Disable I2C peripheral to prevent dummy data in buffer */ 06433 __HAL_I2C_DISABLE(hi2c); 06434 06435 hi2c->State = HAL_I2C_STATE_READY; 06436 06437 /* Call Directly XferAbortCallback function in case of error */ 06438 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); 06439 } 06440 } 06441 else 06442 { 06443 /* Set the DMA Abort callback : 06444 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ 06445 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; 06446 06447 if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) 06448 { 06449 /* Store Last receive data if any */ 06450 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) 06451 { 06452 /* Read data from DR */ 06453 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 06454 06455 /* Increment Buffer pointer */ 06456 hi2c->pBuffPtr++; 06457 } 06458 06459 /* Disable I2C peripheral to prevent dummy data in buffer */ 06460 __HAL_I2C_DISABLE(hi2c); 06461 06462 hi2c->State = HAL_I2C_STATE_READY; 06463 06464 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ 06465 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); 06466 } 06467 } 06468 } 06469 else if (hi2c->State == HAL_I2C_STATE_ABORT) 06470 { 06471 hi2c->State = HAL_I2C_STATE_READY; 06472 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 06473 06474 /* Store Last receive data if any */ 06475 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) 06476 { 06477 /* Read data from DR */ 06478 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 06479 06480 /* Increment Buffer pointer */ 06481 hi2c->pBuffPtr++; 06482 } 06483 06484 /* Disable I2C peripheral to prevent dummy data in buffer */ 06485 __HAL_I2C_DISABLE(hi2c); 06486 06487 /* Call the corresponding callback to inform upper layer of End of Transfer */ 06488 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06489 hi2c->AbortCpltCallback(hi2c); 06490 #else 06491 HAL_I2C_AbortCpltCallback(hi2c); 06492 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06493 } 06494 else 06495 { 06496 /* Store Last receive data if any */ 06497 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) 06498 { 06499 /* Read data from DR */ 06500 *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; 06501 06502 /* Increment Buffer pointer */ 06503 hi2c->pBuffPtr++; 06504 } 06505 06506 /* Call user error callback */ 06507 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06508 hi2c->ErrorCallback(hi2c); 06509 #else 06510 HAL_I2C_ErrorCallback(hi2c); 06511 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06512 } 06513 06514 /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ 06515 CurrentError = hi2c->ErrorCode; 06516 06517 if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ 06518 ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ 06519 ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ 06520 ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) 06521 { 06522 /* Disable EVT, BUF and ERR interrupt */ 06523 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); 06524 } 06525 06526 /* So may inform upper layer that listen phase is stopped */ 06527 /* during NACK error treatment */ 06528 CurrentState = hi2c->State; 06529 if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) 06530 { 06531 hi2c->XferOptions = I2C_NO_OPTION_FRAME; 06532 hi2c->PreviousState = I2C_STATE_NONE; 06533 hi2c->State = HAL_I2C_STATE_READY; 06534 hi2c->Mode = HAL_I2C_MODE_NONE; 06535 06536 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ 06537 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06538 hi2c->ListenCpltCallback(hi2c); 06539 #else 06540 HAL_I2C_ListenCpltCallback(hi2c); 06541 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06542 } 06543 } 06544 06545 /** 06546 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06547 * the configuration information for I2C module 06548 * @param DevAddress Target device address: The device 7 bits address value 06549 * in datasheet must be shifted to the left before calling the interface 06550 * @param Timeout Timeout duration 06551 * @param Tickstart Tick start value 06552 * @retval HAL status 06553 */ 06554 static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) 06555 { 06556 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 06557 uint32_t CurrentXferOptions = hi2c->XferOptions; 06558 06559 /* Generate Start condition if first transfer */ 06560 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) 06561 { 06562 /* Generate Start */ 06563 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 06564 } 06565 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) 06566 { 06567 /* Generate ReStart */ 06568 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 06569 } 06570 else 06571 { 06572 /* Do nothing */ 06573 } 06574 06575 /* Wait until SB flag is set */ 06576 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 06577 { 06578 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 06579 { 06580 hi2c->ErrorCode = HAL_I2C_WRONG_START; 06581 } 06582 return HAL_TIMEOUT; 06583 } 06584 06585 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 06586 { 06587 /* Send slave address */ 06588 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 06589 } 06590 else 06591 { 06592 /* Send header of slave address */ 06593 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); 06594 06595 /* Wait until ADD10 flag is set */ 06596 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) 06597 { 06598 return HAL_ERROR; 06599 } 06600 06601 /* Send slave address */ 06602 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); 06603 } 06604 06605 /* Wait until ADDR flag is set */ 06606 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 06607 { 06608 return HAL_ERROR; 06609 } 06610 06611 return HAL_OK; 06612 } 06613 06614 /** 06615 * @brief Master sends target device address for read request. 06616 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06617 * the configuration information for I2C module 06618 * @param DevAddress Target device address: The device 7 bits address value 06619 * in datasheet must be shifted to the left before calling the interface 06620 * @param Timeout Timeout duration 06621 * @param Tickstart Tick start value 06622 * @retval HAL status 06623 */ 06624 static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) 06625 { 06626 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 06627 uint32_t CurrentXferOptions = hi2c->XferOptions; 06628 06629 /* Enable Acknowledge */ 06630 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 06631 06632 /* Generate Start condition if first transfer */ 06633 if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) 06634 { 06635 /* Generate Start */ 06636 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 06637 } 06638 else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) 06639 { 06640 /* Generate ReStart */ 06641 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 06642 } 06643 else 06644 { 06645 /* Do nothing */ 06646 } 06647 06648 /* Wait until SB flag is set */ 06649 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 06650 { 06651 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 06652 { 06653 hi2c->ErrorCode = HAL_I2C_WRONG_START; 06654 } 06655 return HAL_TIMEOUT; 06656 } 06657 06658 if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) 06659 { 06660 /* Send slave address */ 06661 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); 06662 } 06663 else 06664 { 06665 /* Send header of slave address */ 06666 hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); 06667 06668 /* Wait until ADD10 flag is set */ 06669 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) 06670 { 06671 return HAL_ERROR; 06672 } 06673 06674 /* Send slave address */ 06675 hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); 06676 06677 /* Wait until ADDR flag is set */ 06678 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 06679 { 06680 return HAL_ERROR; 06681 } 06682 06683 /* Clear ADDR flag */ 06684 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 06685 06686 /* Generate Restart */ 06687 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 06688 06689 /* Wait until SB flag is set */ 06690 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 06691 { 06692 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 06693 { 06694 hi2c->ErrorCode = HAL_I2C_WRONG_START; 06695 } 06696 return HAL_TIMEOUT; 06697 } 06698 06699 /* Send header of slave address */ 06700 hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); 06701 } 06702 06703 /* Wait until ADDR flag is set */ 06704 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 06705 { 06706 return HAL_ERROR; 06707 } 06708 06709 return HAL_OK; 06710 } 06711 06712 /** 06713 * @brief Master sends target device address followed by internal memory address for write request. 06714 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06715 * the configuration information for I2C module 06716 * @param DevAddress Target device address: The device 7 bits address value 06717 * in datasheet must be shifted to the left before calling the interface 06718 * @param MemAddress Internal memory address 06719 * @param MemAddSize Size of internal memory address 06720 * @param Timeout Timeout duration 06721 * @param Tickstart Tick start value 06722 * @retval HAL status 06723 */ 06724 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) 06725 { 06726 /* Generate Start */ 06727 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 06728 06729 /* Wait until SB flag is set */ 06730 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 06731 { 06732 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 06733 { 06734 hi2c->ErrorCode = HAL_I2C_WRONG_START; 06735 } 06736 return HAL_TIMEOUT; 06737 } 06738 06739 /* Send slave address */ 06740 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 06741 06742 /* Wait until ADDR flag is set */ 06743 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 06744 { 06745 return HAL_ERROR; 06746 } 06747 06748 /* Clear ADDR flag */ 06749 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 06750 06751 /* Wait until TXE flag is set */ 06752 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 06753 { 06754 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 06755 { 06756 /* Generate Stop */ 06757 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 06758 } 06759 return HAL_ERROR; 06760 } 06761 06762 /* If Memory address size is 8Bit */ 06763 if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 06764 { 06765 /* Send Memory Address */ 06766 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); 06767 } 06768 /* If Memory address size is 16Bit */ 06769 else 06770 { 06771 /* Send MSB of Memory Address */ 06772 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); 06773 06774 /* Wait until TXE flag is set */ 06775 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 06776 { 06777 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 06778 { 06779 /* Generate Stop */ 06780 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 06781 } 06782 return HAL_ERROR; 06783 } 06784 06785 /* Send LSB of Memory Address */ 06786 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); 06787 } 06788 06789 return HAL_OK; 06790 } 06791 06792 /** 06793 * @brief Master sends target device address followed by internal memory address for read request. 06794 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 06795 * the configuration information for I2C module 06796 * @param DevAddress Target device address: The device 7 bits address value 06797 * in datasheet must be shifted to the left before calling the interface 06798 * @param MemAddress Internal memory address 06799 * @param MemAddSize Size of internal memory address 06800 * @param Timeout Timeout duration 06801 * @param Tickstart Tick start value 06802 * @retval HAL status 06803 */ 06804 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) 06805 { 06806 /* Enable Acknowledge */ 06807 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 06808 06809 /* Generate Start */ 06810 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 06811 06812 /* Wait until SB flag is set */ 06813 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 06814 { 06815 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 06816 { 06817 hi2c->ErrorCode = HAL_I2C_WRONG_START; 06818 } 06819 return HAL_TIMEOUT; 06820 } 06821 06822 /* Send slave address */ 06823 hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); 06824 06825 /* Wait until ADDR flag is set */ 06826 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 06827 { 06828 return HAL_ERROR; 06829 } 06830 06831 /* Clear ADDR flag */ 06832 __HAL_I2C_CLEAR_ADDRFLAG(hi2c); 06833 06834 /* Wait until TXE flag is set */ 06835 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 06836 { 06837 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 06838 { 06839 /* Generate Stop */ 06840 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 06841 } 06842 return HAL_ERROR; 06843 } 06844 06845 /* If Memory address size is 8Bit */ 06846 if (MemAddSize == I2C_MEMADD_SIZE_8BIT) 06847 { 06848 /* Send Memory Address */ 06849 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); 06850 } 06851 /* If Memory address size is 16Bit */ 06852 else 06853 { 06854 /* Send MSB of Memory Address */ 06855 hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); 06856 06857 /* Wait until TXE flag is set */ 06858 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 06859 { 06860 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 06861 { 06862 /* Generate Stop */ 06863 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 06864 } 06865 return HAL_ERROR; 06866 } 06867 06868 /* Send LSB of Memory Address */ 06869 hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); 06870 } 06871 06872 /* Wait until TXE flag is set */ 06873 if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) 06874 { 06875 if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) 06876 { 06877 /* Generate Stop */ 06878 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 06879 } 06880 return HAL_ERROR; 06881 } 06882 06883 /* Generate Restart */ 06884 SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); 06885 06886 /* Wait until SB flag is set */ 06887 if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) 06888 { 06889 if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) 06890 { 06891 hi2c->ErrorCode = HAL_I2C_WRONG_START; 06892 } 06893 return HAL_TIMEOUT; 06894 } 06895 06896 /* Send slave address */ 06897 hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); 06898 06899 /* Wait until ADDR flag is set */ 06900 if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) 06901 { 06902 return HAL_ERROR; 06903 } 06904 06905 return HAL_OK; 06906 } 06907 06908 /** 06909 * @brief DMA I2C process complete callback. 06910 * @param hdma DMA handle 06911 * @retval None 06912 */ 06913 static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) 06914 { 06915 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ 06916 06917 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 06918 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 06919 HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; 06920 uint32_t CurrentXferOptions = hi2c->XferOptions; 06921 06922 /* Disable EVT and ERR interrupt */ 06923 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 06924 06925 /* Clear Complete callback */ 06926 if (hi2c->hdmatx != NULL) 06927 { 06928 hi2c->hdmatx->XferCpltCallback = NULL; 06929 } 06930 if (hi2c->hdmarx != NULL) 06931 { 06932 hi2c->hdmarx->XferCpltCallback = NULL; 06933 } 06934 06935 if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) 06936 { 06937 /* Disable DMA Request */ 06938 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 06939 06940 hi2c->XferCount = 0U; 06941 06942 if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) 06943 { 06944 /* Set state at HAL_I2C_STATE_LISTEN */ 06945 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; 06946 hi2c->State = HAL_I2C_STATE_LISTEN; 06947 06948 /* Call the corresponding callback to inform upper layer of End of Transfer */ 06949 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06950 hi2c->SlaveTxCpltCallback(hi2c); 06951 #else 06952 HAL_I2C_SlaveTxCpltCallback(hi2c); 06953 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06954 } 06955 else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) 06956 { 06957 /* Set state at HAL_I2C_STATE_LISTEN */ 06958 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; 06959 hi2c->State = HAL_I2C_STATE_LISTEN; 06960 06961 /* Call the corresponding callback to inform upper layer of End of Transfer */ 06962 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 06963 hi2c->SlaveRxCpltCallback(hi2c); 06964 #else 06965 HAL_I2C_SlaveRxCpltCallback(hi2c); 06966 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 06967 } 06968 else 06969 { 06970 /* Do nothing */ 06971 } 06972 06973 /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ 06974 __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 06975 } 06976 /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ 06977 else if (hi2c->Mode != HAL_I2C_MODE_NONE) 06978 { 06979 if (hi2c->XferCount == (uint16_t)1) 06980 { 06981 /* Disable Acknowledge */ 06982 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 06983 } 06984 06985 /* Disable EVT and ERR interrupt */ 06986 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); 06987 06988 /* Prepare next transfer or stop current transfer */ 06989 if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) 06990 { 06991 /* Generate Stop */ 06992 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 06993 } 06994 06995 /* Disable Last DMA */ 06996 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); 06997 06998 /* Disable DMA Request */ 06999 CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); 07000 07001 hi2c->XferCount = 0U; 07002 07003 /* Check if Errors has been detected during transfer */ 07004 if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) 07005 { 07006 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 07007 hi2c->ErrorCallback(hi2c); 07008 #else 07009 HAL_I2C_ErrorCallback(hi2c); 07010 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 07011 } 07012 else 07013 { 07014 hi2c->State = HAL_I2C_STATE_READY; 07015 07016 if (hi2c->Mode == HAL_I2C_MODE_MEM) 07017 { 07018 hi2c->Mode = HAL_I2C_MODE_NONE; 07019 hi2c->PreviousState = I2C_STATE_NONE; 07020 07021 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 07022 hi2c->MemRxCpltCallback(hi2c); 07023 #else 07024 HAL_I2C_MemRxCpltCallback(hi2c); 07025 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 07026 } 07027 else 07028 { 07029 hi2c->Mode = HAL_I2C_MODE_NONE; 07030 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; 07031 07032 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 07033 hi2c->MasterRxCpltCallback(hi2c); 07034 #else 07035 HAL_I2C_MasterRxCpltCallback(hi2c); 07036 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 07037 } 07038 } 07039 } 07040 else 07041 { 07042 /* Do nothing */ 07043 } 07044 } 07045 07046 /** 07047 * @brief DMA I2C communication error callback. 07048 * @param hdma DMA handle 07049 * @retval None 07050 */ 07051 static void I2C_DMAError(DMA_HandleTypeDef *hdma) 07052 { 07053 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ 07054 07055 /* Clear Complete callback */ 07056 if (hi2c->hdmatx != NULL) 07057 { 07058 hi2c->hdmatx->XferCpltCallback = NULL; 07059 } 07060 if (hi2c->hdmarx != NULL) 07061 { 07062 hi2c->hdmarx->XferCpltCallback = NULL; 07063 } 07064 07065 /* Ignore DMA FIFO error */ 07066 if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE) 07067 { 07068 /* Disable Acknowledge */ 07069 hi2c->Instance->CR1 &= ~I2C_CR1_ACK; 07070 07071 hi2c->XferCount = 0U; 07072 07073 hi2c->State = HAL_I2C_STATE_READY; 07074 hi2c->Mode = HAL_I2C_MODE_NONE; 07075 07076 hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; 07077 07078 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 07079 hi2c->ErrorCallback(hi2c); 07080 #else 07081 HAL_I2C_ErrorCallback(hi2c); 07082 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 07083 } 07084 } 07085 07086 /** 07087 * @brief DMA I2C communication abort callback 07088 * (To be called at end of DMA Abort procedure). 07089 * @param hdma DMA handle. 07090 * @retval None 07091 */ 07092 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) 07093 { 07094 __IO uint32_t count = 0U; 07095 I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ 07096 07097 /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ 07098 HAL_I2C_StateTypeDef CurrentState = hi2c->State; 07099 07100 /* During abort treatment, check that there is no pending STOP request */ 07101 /* Wait until STOP flag is reset */ 07102 count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); 07103 do 07104 { 07105 if (count == 0U) 07106 { 07107 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 07108 break; 07109 } 07110 count--; 07111 } 07112 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); 07113 07114 /* Clear Complete callback */ 07115 if (hi2c->hdmatx != NULL) 07116 { 07117 hi2c->hdmatx->XferCpltCallback = NULL; 07118 } 07119 if (hi2c->hdmarx != NULL) 07120 { 07121 hi2c->hdmarx->XferCpltCallback = NULL; 07122 } 07123 07124 /* Disable Acknowledge */ 07125 CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 07126 07127 hi2c->XferCount = 0U; 07128 07129 /* Reset XferAbortCallback */ 07130 if (hi2c->hdmatx != NULL) 07131 { 07132 hi2c->hdmatx->XferAbortCallback = NULL; 07133 } 07134 if (hi2c->hdmarx != NULL) 07135 { 07136 hi2c->hdmarx->XferAbortCallback = NULL; 07137 } 07138 07139 /* Disable I2C peripheral to prevent dummy data in buffer */ 07140 __HAL_I2C_DISABLE(hi2c); 07141 07142 /* Check if come from abort from user */ 07143 if (hi2c->State == HAL_I2C_STATE_ABORT) 07144 { 07145 hi2c->State = HAL_I2C_STATE_READY; 07146 hi2c->Mode = HAL_I2C_MODE_NONE; 07147 hi2c->ErrorCode = HAL_I2C_ERROR_NONE; 07148 07149 /* Call the corresponding callback to inform upper layer of End of Transfer */ 07150 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 07151 hi2c->AbortCpltCallback(hi2c); 07152 #else 07153 HAL_I2C_AbortCpltCallback(hi2c); 07154 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 07155 } 07156 else 07157 { 07158 if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) 07159 { 07160 /* Renable I2C peripheral */ 07161 __HAL_I2C_ENABLE(hi2c); 07162 07163 /* Enable Acknowledge */ 07164 SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); 07165 07166 /* keep HAL_I2C_STATE_LISTEN */ 07167 hi2c->PreviousState = I2C_STATE_NONE; 07168 hi2c->State = HAL_I2C_STATE_LISTEN; 07169 } 07170 else 07171 { 07172 hi2c->State = HAL_I2C_STATE_READY; 07173 hi2c->Mode = HAL_I2C_MODE_NONE; 07174 } 07175 07176 /* Call the corresponding callback to inform upper layer of End of Transfer */ 07177 #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) 07178 hi2c->ErrorCallback(hi2c); 07179 #else 07180 HAL_I2C_ErrorCallback(hi2c); 07181 #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ 07182 } 07183 } 07184 07185 /** 07186 * @brief This function handles I2C Communication Timeout. 07187 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 07188 * the configuration information for I2C module 07189 * @param Flag specifies the I2C flag to check. 07190 * @param Status The new Flag status (SET or RESET). 07191 * @param Timeout Timeout duration 07192 * @param Tickstart Tick start value 07193 * @retval HAL status 07194 */ 07195 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) 07196 { 07197 /* Wait until flag is set */ 07198 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) 07199 { 07200 /* Check for the Timeout */ 07201 if (Timeout != HAL_MAX_DELAY) 07202 { 07203 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 07204 { 07205 hi2c->PreviousState = I2C_STATE_NONE; 07206 hi2c->State = HAL_I2C_STATE_READY; 07207 hi2c->Mode = HAL_I2C_MODE_NONE; 07208 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 07209 07210 /* Process Unlocked */ 07211 __HAL_UNLOCK(hi2c); 07212 07213 return HAL_ERROR; 07214 } 07215 } 07216 } 07217 return HAL_OK; 07218 } 07219 07220 /** 07221 * @brief This function handles I2C Communication Timeout for Master addressing phase. 07222 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 07223 * the configuration information for I2C module 07224 * @param Flag specifies the I2C flag to check. 07225 * @param Timeout Timeout duration 07226 * @param Tickstart Tick start value 07227 * @retval HAL status 07228 */ 07229 static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) 07230 { 07231 while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) 07232 { 07233 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 07234 { 07235 /* Generate Stop */ 07236 SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); 07237 07238 /* Clear AF Flag */ 07239 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 07240 07241 hi2c->PreviousState = I2C_STATE_NONE; 07242 hi2c->State = HAL_I2C_STATE_READY; 07243 hi2c->Mode = HAL_I2C_MODE_NONE; 07244 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 07245 07246 /* Process Unlocked */ 07247 __HAL_UNLOCK(hi2c); 07248 07249 return HAL_ERROR; 07250 } 07251 07252 /* Check for the Timeout */ 07253 if (Timeout != HAL_MAX_DELAY) 07254 { 07255 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 07256 { 07257 hi2c->PreviousState = I2C_STATE_NONE; 07258 hi2c->State = HAL_I2C_STATE_READY; 07259 hi2c->Mode = HAL_I2C_MODE_NONE; 07260 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 07261 07262 /* Process Unlocked */ 07263 __HAL_UNLOCK(hi2c); 07264 07265 return HAL_ERROR; 07266 } 07267 } 07268 } 07269 return HAL_OK; 07270 } 07271 07272 /** 07273 * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. 07274 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 07275 * the configuration information for the specified I2C. 07276 * @param Timeout Timeout duration 07277 * @param Tickstart Tick start value 07278 * @retval HAL status 07279 */ 07280 static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) 07281 { 07282 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) 07283 { 07284 /* Check if a NACK is detected */ 07285 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) 07286 { 07287 return HAL_ERROR; 07288 } 07289 07290 /* Check for the Timeout */ 07291 if (Timeout != HAL_MAX_DELAY) 07292 { 07293 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 07294 { 07295 hi2c->PreviousState = I2C_STATE_NONE; 07296 hi2c->State = HAL_I2C_STATE_READY; 07297 hi2c->Mode = HAL_I2C_MODE_NONE; 07298 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 07299 07300 /* Process Unlocked */ 07301 __HAL_UNLOCK(hi2c); 07302 07303 return HAL_ERROR; 07304 } 07305 } 07306 } 07307 return HAL_OK; 07308 } 07309 07310 /** 07311 * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. 07312 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 07313 * the configuration information for the specified I2C. 07314 * @param Timeout Timeout duration 07315 * @param Tickstart Tick start value 07316 * @retval HAL status 07317 */ 07318 static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) 07319 { 07320 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) 07321 { 07322 /* Check if a NACK is detected */ 07323 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) 07324 { 07325 return HAL_ERROR; 07326 } 07327 07328 /* Check for the Timeout */ 07329 if (Timeout != HAL_MAX_DELAY) 07330 { 07331 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 07332 { 07333 hi2c->PreviousState = I2C_STATE_NONE; 07334 hi2c->State = HAL_I2C_STATE_READY; 07335 hi2c->Mode = HAL_I2C_MODE_NONE; 07336 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 07337 07338 /* Process Unlocked */ 07339 __HAL_UNLOCK(hi2c); 07340 07341 return HAL_ERROR; 07342 } 07343 } 07344 } 07345 return HAL_OK; 07346 } 07347 07348 /** 07349 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. 07350 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 07351 * the configuration information for the specified I2C. 07352 * @param Timeout Timeout duration 07353 * @param Tickstart Tick start value 07354 * @retval HAL status 07355 */ 07356 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) 07357 { 07358 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) 07359 { 07360 /* Check if a NACK is detected */ 07361 if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) 07362 { 07363 return HAL_ERROR; 07364 } 07365 07366 /* Check for the Timeout */ 07367 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 07368 { 07369 hi2c->PreviousState = I2C_STATE_NONE; 07370 hi2c->State = HAL_I2C_STATE_READY; 07371 hi2c->Mode = HAL_I2C_MODE_NONE; 07372 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 07373 07374 /* Process Unlocked */ 07375 __HAL_UNLOCK(hi2c); 07376 07377 return HAL_ERROR; 07378 } 07379 } 07380 return HAL_OK; 07381 } 07382 07383 /** 07384 * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. 07385 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 07386 * the configuration information for the specified I2C. 07387 * @retval HAL status 07388 */ 07389 static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) 07390 { 07391 __IO uint32_t count = 0U; 07392 07393 /* Wait until STOP flag is reset */ 07394 count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); 07395 do 07396 { 07397 count--; 07398 if (count == 0U) 07399 { 07400 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 07401 07402 return HAL_ERROR; 07403 } 07404 } 07405 while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); 07406 07407 return HAL_OK; 07408 } 07409 07410 /** 07411 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. 07412 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 07413 * the configuration information for the specified I2C. 07414 * @param Timeout Timeout duration 07415 * @param Tickstart Tick start value 07416 * @retval HAL status 07417 */ 07418 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) 07419 { 07420 07421 while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) 07422 { 07423 /* Check if a STOPF is detected */ 07424 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) 07425 { 07426 /* Clear STOP Flag */ 07427 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); 07428 07429 hi2c->PreviousState = I2C_STATE_NONE; 07430 hi2c->State = HAL_I2C_STATE_READY; 07431 hi2c->Mode = HAL_I2C_MODE_NONE; 07432 hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; 07433 07434 /* Process Unlocked */ 07435 __HAL_UNLOCK(hi2c); 07436 07437 return HAL_ERROR; 07438 } 07439 07440 /* Check for the Timeout */ 07441 if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 07442 { 07443 hi2c->PreviousState = I2C_STATE_NONE; 07444 hi2c->State = HAL_I2C_STATE_READY; 07445 hi2c->Mode = HAL_I2C_MODE_NONE; 07446 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; 07447 07448 /* Process Unlocked */ 07449 __HAL_UNLOCK(hi2c); 07450 07451 return HAL_ERROR; 07452 } 07453 } 07454 return HAL_OK; 07455 } 07456 07457 /** 07458 * @brief This function handles Acknowledge failed detection during an I2C Communication. 07459 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 07460 * the configuration information for the specified I2C. 07461 * @retval HAL status 07462 */ 07463 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) 07464 { 07465 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) 07466 { 07467 /* Clear NACKF Flag */ 07468 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); 07469 07470 hi2c->PreviousState = I2C_STATE_NONE; 07471 hi2c->State = HAL_I2C_STATE_READY; 07472 hi2c->Mode = HAL_I2C_MODE_NONE; 07473 hi2c->ErrorCode |= HAL_I2C_ERROR_AF; 07474 07475 /* Process Unlocked */ 07476 __HAL_UNLOCK(hi2c); 07477 07478 return HAL_ERROR; 07479 } 07480 return HAL_OK; 07481 } 07482 07483 /** 07484 * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. 07485 * @param hi2c I2C handle. 07486 * @retval None 07487 */ 07488 static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) 07489 { 07490 /* if user set XferOptions to I2C_OTHER_FRAME */ 07491 /* it request implicitly to generate a restart condition */ 07492 /* set XferOptions to I2C_FIRST_FRAME */ 07493 if (hi2c->XferOptions == I2C_OTHER_FRAME) 07494 { 07495 hi2c->XferOptions = I2C_FIRST_FRAME; 07496 } 07497 /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ 07498 /* it request implicitly to generate a restart condition */ 07499 /* then generate a stop condition at the end of transfer */ 07500 /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ 07501 else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) 07502 { 07503 hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; 07504 } 07505 else 07506 { 07507 /* Nothing to do */ 07508 } 07509 } 07510 07511 /** 07512 * @} 07513 */ 07514 07515 #endif /* HAL_I2C_MODULE_ENABLED */ 07516 /** 07517 * @} 07518 */ 07519 07520 /** 07521 * @} 07522 */ 07523 07524 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1