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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_i2s.h 00004 * @author MCD Application Team 00005 * @brief Header file of I2S HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2016 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F4xx_HAL_I2S_H 00022 #define STM32F4xx_HAL_I2S_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx_hal_def.h" 00030 00031 /** @addtogroup STM32F4xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup I2S 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 /** @defgroup I2S_Exported_Types I2S Exported Types 00041 * @{ 00042 */ 00043 00044 /** 00045 * @brief I2S Init structure definition 00046 */ 00047 typedef struct 00048 { 00049 uint32_t Mode; /*!< Specifies the I2S operating mode. 00050 This parameter can be a value of @ref I2S_Mode */ 00051 00052 uint32_t Standard; /*!< Specifies the standard used for the I2S communication. 00053 This parameter can be a value of @ref I2S_Standard */ 00054 00055 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. 00056 This parameter can be a value of @ref I2S_Data_Format */ 00057 00058 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 00059 This parameter can be a value of @ref I2S_MCLK_Output */ 00060 00061 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 00062 This parameter can be a value of @ref I2S_Audio_Frequency */ 00063 00064 uint32_t CPOL; /*!< Specifies the idle state of the I2S clock. 00065 This parameter can be a value of @ref I2S_Clock_Polarity */ 00066 00067 uint32_t ClockSource; /*!< Specifies the I2S Clock Source. 00068 This parameter can be a value of @ref I2S_Clock_Source */ 00069 uint32_t FullDuplexMode; /*!< Specifies the I2S FullDuplex mode. 00070 This parameter can be a value of @ref I2S_FullDuplex_Mode */ 00071 } I2S_InitTypeDef; 00072 00073 /** 00074 * @brief HAL State structures definition 00075 */ 00076 typedef enum 00077 { 00078 HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */ 00079 HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */ 00080 HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */ 00081 HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ 00082 HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ 00083 HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ 00084 HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */ 00085 HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */ 00086 } HAL_I2S_StateTypeDef; 00087 00088 /** 00089 * @brief I2S handle Structure definition 00090 */ 00091 typedef struct __I2S_HandleTypeDef 00092 { 00093 SPI_TypeDef *Instance; /*!< I2S registers base address */ 00094 00095 I2S_InitTypeDef Init; /*!< I2S communication parameters */ 00096 00097 uint16_t *pTxBuffPtr; /*!< Pointer to I2S Tx transfer buffer */ 00098 00099 __IO uint16_t TxXferSize; /*!< I2S Tx transfer size */ 00100 00101 __IO uint16_t TxXferCount; /*!< I2S Tx transfer Counter */ 00102 00103 uint16_t *pRxBuffPtr; /*!< Pointer to I2S Rx transfer buffer */ 00104 00105 __IO uint16_t RxXferSize; /*!< I2S Rx transfer size */ 00106 00107 __IO uint16_t RxXferCount; /*!< I2S Rx transfer counter 00108 (This field is initialized at the 00109 same value as transfer size at the 00110 beginning of the transfer and 00111 decremented when a sample is received 00112 NbSamplesReceived = RxBufferSize-RxBufferCount) */ 00113 void (*IrqHandlerISR)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S function pointer on IrqHandler */ 00114 00115 DMA_HandleTypeDef *hdmatx; /*!< I2S Tx DMA handle parameters */ 00116 00117 DMA_HandleTypeDef *hdmarx; /*!< I2S Rx DMA handle parameters */ 00118 00119 __IO HAL_LockTypeDef Lock; /*!< I2S locking object */ 00120 00121 __IO HAL_I2S_StateTypeDef State; /*!< I2S communication state */ 00122 00123 __IO uint32_t ErrorCode; /*!< I2S Error code 00124 This parameter can be a value of @ref I2S_Error */ 00125 00126 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 00127 void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Completed callback */ 00128 void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Completed callback */ 00129 void (* TxRxCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Completed callback */ 00130 void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Tx Half Completed callback */ 00131 void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Rx Half Completed callback */ 00132 void (* TxRxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S TxRx Half Completed callback */ 00133 void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Error callback */ 00134 void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp Init callback */ 00135 void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s); /*!< I2S Msp DeInit callback */ 00136 00137 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 00138 } I2S_HandleTypeDef; 00139 00140 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 00141 /** 00142 * @brief HAL I2S Callback ID enumeration definition 00143 */ 00144 typedef enum 00145 { 00146 HAL_I2S_TX_COMPLETE_CB_ID = 0x00U, /*!< I2S Tx Completed callback ID */ 00147 HAL_I2S_RX_COMPLETE_CB_ID = 0x01U, /*!< I2S Rx Completed callback ID */ 00148 HAL_I2S_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< I2S TxRx Completed callback ID */ 00149 HAL_I2S_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< I2S Tx Half Completed callback ID */ 00150 HAL_I2S_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< I2S Rx Half Completed callback ID */ 00151 HAL_I2S_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< I2S TxRx Half Completed callback ID */ 00152 HAL_I2S_ERROR_CB_ID = 0x06U, /*!< I2S Error callback ID */ 00153 HAL_I2S_MSPINIT_CB_ID = 0x07U, /*!< I2S Msp Init callback ID */ 00154 HAL_I2S_MSPDEINIT_CB_ID = 0x08U /*!< I2S Msp DeInit callback ID */ 00155 00156 } HAL_I2S_CallbackIDTypeDef; 00157 00158 /** 00159 * @brief HAL I2S Callback pointer definition 00160 */ 00161 typedef void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */ 00162 00163 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 00164 /** 00165 * @} 00166 */ 00167 00168 /* Exported constants --------------------------------------------------------*/ 00169 /** @defgroup I2S_Exported_Constants I2S Exported Constants 00170 * @{ 00171 */ 00172 /** @defgroup I2S_Error I2S Error 00173 * @{ 00174 */ 00175 #define HAL_I2S_ERROR_NONE (0x00000000U) /*!< No error */ 00176 #define HAL_I2S_ERROR_TIMEOUT (0x00000001U) /*!< Timeout error */ 00177 #define HAL_I2S_ERROR_OVR (0x00000002U) /*!< OVR error */ 00178 #define HAL_I2S_ERROR_UDR (0x00000004U) /*!< UDR error */ 00179 #define HAL_I2S_ERROR_DMA (0x00000008U) /*!< DMA transfer error */ 00180 #define HAL_I2S_ERROR_PRESCALER (0x00000010U) /*!< Prescaler Calculation error */ 00181 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 00182 #define HAL_I2S_ERROR_INVALID_CALLBACK (0x00000020U) /*!< Invalid Callback error */ 00183 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 00184 #define HAL_I2S_ERROR_BUSY_LINE_RX (0x00000040U) /*!< Busy Rx Line error */ 00185 /** 00186 * @} 00187 */ 00188 00189 /** @defgroup I2S_Mode I2S Mode 00190 * @{ 00191 */ 00192 #define I2S_MODE_SLAVE_TX (0x00000000U) 00193 #define I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) 00194 #define I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) 00195 #define I2S_MODE_MASTER_RX ((SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)) 00196 /** 00197 * @} 00198 */ 00199 00200 /** @defgroup I2S_Standard I2S Standard 00201 * @{ 00202 */ 00203 #define I2S_STANDARD_PHILIPS (0x00000000U) 00204 #define I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) 00205 #define I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) 00206 #define I2S_STANDARD_PCM_SHORT ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)) 00207 #define I2S_STANDARD_PCM_LONG ((SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)) 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup I2S_Data_Format I2S Data Format 00213 * @{ 00214 */ 00215 #define I2S_DATAFORMAT_16B (0x00000000U) 00216 #define I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) 00217 #define I2S_DATAFORMAT_24B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) 00218 #define I2S_DATAFORMAT_32B ((SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) 00219 /** 00220 * @} 00221 */ 00222 00223 /** @defgroup I2S_MCLK_Output I2S MCLK Output 00224 * @{ 00225 */ 00226 #define I2S_MCLKOUTPUT_ENABLE (SPI_I2SPR_MCKOE) 00227 #define I2S_MCLKOUTPUT_DISABLE (0x00000000U) 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup I2S_Audio_Frequency I2S Audio Frequency 00233 * @{ 00234 */ 00235 #define I2S_AUDIOFREQ_192K (192000U) 00236 #define I2S_AUDIOFREQ_96K (96000U) 00237 #define I2S_AUDIOFREQ_48K (48000U) 00238 #define I2S_AUDIOFREQ_44K (44100U) 00239 #define I2S_AUDIOFREQ_32K (32000U) 00240 #define I2S_AUDIOFREQ_22K (22050U) 00241 #define I2S_AUDIOFREQ_16K (16000U) 00242 #define I2S_AUDIOFREQ_11K (11025U) 00243 #define I2S_AUDIOFREQ_8K (8000U) 00244 #define I2S_AUDIOFREQ_DEFAULT (2U) 00245 /** 00246 * @} 00247 */ 00248 00249 /** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode 00250 * @{ 00251 */ 00252 #define I2S_FULLDUPLEXMODE_DISABLE (0x00000000U) 00253 #define I2S_FULLDUPLEXMODE_ENABLE (0x00000001U) 00254 /** 00255 * @} 00256 */ 00257 00258 /** @defgroup I2S_Clock_Polarity I2S Clock Polarity 00259 * @{ 00260 */ 00261 #define I2S_CPOL_LOW (0x00000000U) 00262 #define I2S_CPOL_HIGH (SPI_I2SCFGR_CKPOL) 00263 /** 00264 * @} 00265 */ 00266 00267 /** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition 00268 * @{ 00269 */ 00270 #define I2S_IT_TXE SPI_CR2_TXEIE 00271 #define I2S_IT_RXNE SPI_CR2_RXNEIE 00272 #define I2S_IT_ERR SPI_CR2_ERRIE 00273 /** 00274 * @} 00275 */ 00276 00277 /** @defgroup I2S_Flags_Definition I2S Flags Definition 00278 * @{ 00279 */ 00280 #define I2S_FLAG_TXE SPI_SR_TXE 00281 #define I2S_FLAG_RXNE SPI_SR_RXNE 00282 00283 #define I2S_FLAG_UDR SPI_SR_UDR 00284 #define I2S_FLAG_OVR SPI_SR_OVR 00285 #define I2S_FLAG_FRE SPI_SR_FRE 00286 00287 #define I2S_FLAG_CHSIDE SPI_SR_CHSIDE 00288 #define I2S_FLAG_BSY SPI_SR_BSY 00289 00290 #define I2S_FLAG_MASK (SPI_SR_RXNE\ 00291 | SPI_SR_TXE | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_CHSIDE | SPI_SR_BSY) 00292 /** 00293 * @} 00294 */ 00295 00296 /** @defgroup I2S_Clock_Source I2S Clock Source Definition 00297 * @{ 00298 */ 00299 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx) 00300 #define I2S_CLOCK_PLL (0x00000000U) 00301 #define I2S_CLOCK_EXTERNAL (0x00000001U) 00302 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 00303 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 00304 00305 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00306 #define I2S_CLOCK_PLL (0x00000000U) 00307 #define I2S_CLOCK_EXTERNAL (0x00000001U) 00308 #define I2S_CLOCK_PLLR (0x00000002U) 00309 #define I2S_CLOCK_PLLSRC (0x00000003U) 00310 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00311 00312 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00313 #define I2S_CLOCK_PLLSRC (0x00000000U) 00314 #define I2S_CLOCK_EXTERNAL (0x00000001U) 00315 #define I2S_CLOCK_PLLR (0x00000002U) 00316 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00317 /** 00318 * @} 00319 */ 00320 00321 /** 00322 * @} 00323 */ 00324 00325 /* Exported macros -----------------------------------------------------------*/ 00326 /** @defgroup I2S_Exported_macros I2S Exported Macros 00327 * @{ 00328 */ 00329 00330 /** @brief Reset I2S handle state 00331 * @param __HANDLE__ specifies the I2S Handle. 00332 * @retval None 00333 */ 00334 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 00335 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00336 (__HANDLE__)->State = HAL_I2S_STATE_RESET; \ 00337 (__HANDLE__)->MspInitCallback = NULL; \ 00338 (__HANDLE__)->MspDeInitCallback = NULL; \ 00339 } while(0) 00340 #else 00341 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) 00342 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 00343 00344 /** @brief Enable the specified SPI peripheral (in I2S mode). 00345 * @param __HANDLE__ specifies the I2S Handle. 00346 * @retval None 00347 */ 00348 #define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) 00349 00350 /** @brief Disable the specified SPI peripheral (in I2S mode). 00351 * @param __HANDLE__ specifies the I2S Handle. 00352 * @retval None 00353 */ 00354 #define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) 00355 00356 /** @brief Enable the specified I2S interrupts. 00357 * @param __HANDLE__ specifies the I2S Handle. 00358 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 00359 * This parameter can be one of the following values: 00360 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 00361 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 00362 * @arg I2S_IT_ERR: Error interrupt enable 00363 * @retval None 00364 */ 00365 #define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) 00366 00367 /** @brief Disable the specified I2S interrupts. 00368 * @param __HANDLE__ specifies the I2S Handle. 00369 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 00370 * This parameter can be one of the following values: 00371 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 00372 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 00373 * @arg I2S_IT_ERR: Error interrupt enable 00374 * @retval None 00375 */ 00376 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) 00377 00378 /** @brief Checks if the specified I2S interrupt source is enabled or disabled. 00379 * @param __HANDLE__ specifies the I2S Handle. 00380 * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. 00381 * @param __INTERRUPT__ specifies the I2S interrupt source to check. 00382 * This parameter can be one of the following values: 00383 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 00384 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 00385 * @arg I2S_IT_ERR: Error interrupt enable 00386 * @retval The new state of __IT__ (TRUE or FALSE). 00387 */ 00388 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\ 00389 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00390 00391 /** @brief Checks whether the specified I2S flag is set or not. 00392 * @param __HANDLE__ specifies the I2S Handle. 00393 * @param __FLAG__ specifies the flag to check. 00394 * This parameter can be one of the following values: 00395 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag 00396 * @arg I2S_FLAG_TXE: Transmit buffer empty flag 00397 * @arg I2S_FLAG_UDR: Underrun flag 00398 * @arg I2S_FLAG_OVR: Overrun flag 00399 * @arg I2S_FLAG_FRE: Frame error flag 00400 * @arg I2S_FLAG_CHSIDE: Channel Side flag 00401 * @arg I2S_FLAG_BSY: Busy flag 00402 * @retval The new state of __FLAG__ (TRUE or FALSE). 00403 */ 00404 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 00405 00406 /** @brief Clears the I2S OVR pending flag. 00407 * @param __HANDLE__ specifies the I2S Handle. 00408 * @retval None 00409 */ 00410 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \ 00411 __IO uint32_t tmpreg_ovr = 0x00U; \ 00412 tmpreg_ovr = (__HANDLE__)->Instance->DR; \ 00413 tmpreg_ovr = (__HANDLE__)->Instance->SR; \ 00414 UNUSED(tmpreg_ovr); \ 00415 }while(0U) 00416 /** @brief Clears the I2S UDR pending flag. 00417 * @param __HANDLE__ specifies the I2S Handle. 00418 * @retval None 00419 */ 00420 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\ 00421 __IO uint32_t tmpreg_udr = 0x00U;\ 00422 tmpreg_udr = ((__HANDLE__)->Instance->SR);\ 00423 UNUSED(tmpreg_udr); \ 00424 }while(0U) 00425 /** @brief Flush the I2S DR Register. 00426 * @param __HANDLE__ specifies the I2S Handle. 00427 * @retval None 00428 */ 00429 #define __HAL_I2S_FLUSH_RX_DR(__HANDLE__) do{\ 00430 __IO uint32_t tmpreg_dr = 0x00U;\ 00431 tmpreg_dr = ((__HANDLE__)->Instance->DR);\ 00432 UNUSED(tmpreg_dr); \ 00433 }while(0U) 00434 /** 00435 * @} 00436 */ 00437 00438 /* Include I2S Extension module */ 00439 #include "stm32f4xx_hal_i2s_ex.h" 00440 00441 /* Exported functions --------------------------------------------------------*/ 00442 /** @addtogroup I2S_Exported_Functions 00443 * @{ 00444 */ 00445 00446 /** @addtogroup I2S_Exported_Functions_Group1 00447 * @{ 00448 */ 00449 /* Initialization/de-initialization functions ********************************/ 00450 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); 00451 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s); 00452 void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); 00453 void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); 00454 00455 /* Callbacks Register/UnRegister functions ***********************************/ 00456 #if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U) 00457 HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, 00458 pI2S_CallbackTypeDef pCallback); 00459 HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID); 00460 #endif /* USE_HAL_I2S_REGISTER_CALLBACKS */ 00461 /** 00462 * @} 00463 */ 00464 00465 /** @addtogroup I2S_Exported_Functions_Group2 00466 * @{ 00467 */ 00468 /* I/O operation functions ***************************************************/ 00469 /* Blocking mode: Polling */ 00470 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); 00471 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); 00472 00473 /* Non-Blocking mode: Interrupt */ 00474 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 00475 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 00476 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s); 00477 00478 /* Non-Blocking mode: DMA */ 00479 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 00480 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size); 00481 00482 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); 00483 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); 00484 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); 00485 00486 /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ 00487 void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); 00488 void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); 00489 void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); 00490 void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); 00491 void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); 00492 /** 00493 * @} 00494 */ 00495 00496 /** @addtogroup I2S_Exported_Functions_Group3 00497 * @{ 00498 */ 00499 /* Peripheral Control and State functions ************************************/ 00500 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); 00501 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); 00502 /** 00503 * @} 00504 */ 00505 00506 /** 00507 * @} 00508 */ 00509 00510 /* Private types -------------------------------------------------------------*/ 00511 /* Private variables ---------------------------------------------------------*/ 00512 /* Private constants ---------------------------------------------------------*/ 00513 /* Private macros ------------------------------------------------------------*/ 00514 /** @defgroup I2S_Private_Macros I2S Private Macros 00515 * @{ 00516 */ 00517 00518 /** @brief Check whether the specified SPI flag is set or not. 00519 * @param __SR__ copy of I2S SR register. 00520 * @param __FLAG__ specifies the flag to check. 00521 * This parameter can be one of the following values: 00522 * @arg I2S_FLAG_RXNE: Receive buffer not empty flag 00523 * @arg I2S_FLAG_TXE: Transmit buffer empty flag 00524 * @arg I2S_FLAG_UDR: Underrun error flag 00525 * @arg I2S_FLAG_OVR: Overrun flag 00526 * @arg I2S_FLAG_CHSIDE: Channel side flag 00527 * @arg I2S_FLAG_BSY: Busy flag 00528 * @retval SET or RESET. 00529 */ 00530 #define I2S_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__)\ 00531 & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET) 00532 00533 /** @brief Check whether the specified SPI Interrupt is set or not. 00534 * @param __CR2__ copy of I2S CR2 register. 00535 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 00536 * This parameter can be one of the following values: 00537 * @arg I2S_IT_TXE: Tx buffer empty interrupt enable 00538 * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable 00539 * @arg I2S_IT_ERR: Error interrupt enable 00540 * @retval SET or RESET. 00541 */ 00542 #define I2S_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__)\ 00543 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00544 00545 /** @brief Checks if I2S Mode parameter is in allowed range. 00546 * @param __MODE__ specifies the I2S Mode. 00547 * This parameter can be a value of @ref I2S_Mode 00548 * @retval None 00549 */ 00550 #define IS_I2S_MODE(__MODE__) (((__MODE__) == I2S_MODE_SLAVE_TX) || \ 00551 ((__MODE__) == I2S_MODE_SLAVE_RX) || \ 00552 ((__MODE__) == I2S_MODE_MASTER_TX) || \ 00553 ((__MODE__) == I2S_MODE_MASTER_RX)) 00554 00555 #define IS_I2S_STANDARD(__STANDARD__) (((__STANDARD__) == I2S_STANDARD_PHILIPS) || \ 00556 ((__STANDARD__) == I2S_STANDARD_MSB) || \ 00557 ((__STANDARD__) == I2S_STANDARD_LSB) || \ 00558 ((__STANDARD__) == I2S_STANDARD_PCM_SHORT) || \ 00559 ((__STANDARD__) == I2S_STANDARD_PCM_LONG)) 00560 00561 #define IS_I2S_DATA_FORMAT(__FORMAT__) (((__FORMAT__) == I2S_DATAFORMAT_16B) || \ 00562 ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED) || \ 00563 ((__FORMAT__) == I2S_DATAFORMAT_24B) || \ 00564 ((__FORMAT__) == I2S_DATAFORMAT_32B)) 00565 00566 #define IS_I2S_MCLK_OUTPUT(__OUTPUT__) (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE) || \ 00567 ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE)) 00568 00569 #define IS_I2S_AUDIO_FREQ(__FREQ__) ((((__FREQ__) >= I2S_AUDIOFREQ_8K) && \ 00570 ((__FREQ__) <= I2S_AUDIOFREQ_192K)) || \ 00571 ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT)) 00572 00573 #define IS_I2S_FULLDUPLEX_MODE(MODE) (((MODE) == I2S_FULLDUPLEXMODE_DISABLE) || \ 00574 ((MODE) == I2S_FULLDUPLEXMODE_ENABLE)) 00575 00576 /** @brief Checks if I2S Serial clock steady state parameter is in allowed range. 00577 * @param __CPOL__ specifies the I2S serial clock steady state. 00578 * This parameter can be a value of @ref I2S_Clock_Polarity 00579 * @retval None 00580 */ 00581 #define IS_I2S_CPOL(__CPOL__) (((__CPOL__) == I2S_CPOL_LOW) || \ 00582 ((__CPOL__) == I2S_CPOL_HIGH)) 00583 00584 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F469xx) || defined(STM32F479xx) 00585 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ 00586 ((CLOCK) == I2S_CLOCK_PLL)) 00587 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || 00588 STM32F401xC || STM32F401xE || STM32F411xE || STM32F469xx || STM32F479xx */ 00589 00590 #if defined(STM32F446xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined (STM32F413xx) || defined(STM32F423xx) 00591 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ 00592 ((CLOCK) == I2S_CLOCK_PLL) ||\ 00593 ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ 00594 ((CLOCK) == I2S_CLOCK_PLLR)) 00595 #endif /* STM32F446xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */ 00596 00597 #if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) 00598 #define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) ||\ 00599 ((CLOCK) == I2S_CLOCK_PLLSRC) ||\ 00600 ((CLOCK) == I2S_CLOCK_PLLR)) 00601 #endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */ 00602 /** 00603 * @} 00604 */ 00605 00606 /** 00607 * @} 00608 */ 00609 00610 /** 00611 * @} 00612 */ 00613 00614 #ifdef __cplusplus 00615 } 00616 #endif 00617 00618 #endif /* STM32F4xx_HAL_I2S_H */ 00619 00620 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1