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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_nand.h 00004 * @author MCD Application Team 00005 * @brief Header file of NAND HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F4xx_HAL_NAND_H 00022 #define STM32F4xx_HAL_NAND_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 #if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3) 00029 00030 /* Includes ------------------------------------------------------------------*/ 00031 #if defined(FSMC_Bank2_3) 00032 #include "stm32f4xx_ll_fsmc.h" 00033 #else 00034 #include "stm32f4xx_ll_fmc.h" 00035 #endif /* FSMC_Bank2_3 */ 00036 00037 /** @addtogroup STM32F4xx_HAL_Driver 00038 * @{ 00039 */ 00040 00041 /** @addtogroup NAND 00042 * @{ 00043 */ 00044 00045 /* Exported typedef ----------------------------------------------------------*/ 00046 /* Exported types ------------------------------------------------------------*/ 00047 /** @defgroup NAND_Exported_Types NAND Exported Types 00048 * @{ 00049 */ 00050 00051 /** 00052 * @brief HAL NAND State structures definition 00053 */ 00054 typedef enum 00055 { 00056 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 00057 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 00058 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 00059 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 00060 } HAL_NAND_StateTypeDef; 00061 00062 /** 00063 * @brief NAND Memory electronic signature Structure definition 00064 */ 00065 typedef struct 00066 { 00067 /*<! NAND memory electronic signature maker and device IDs */ 00068 00069 uint8_t Maker_Id; 00070 00071 uint8_t Device_Id; 00072 00073 uint8_t Third_Id; 00074 00075 uint8_t Fourth_Id; 00076 } NAND_IDTypeDef; 00077 00078 /** 00079 * @brief NAND Memory address Structure definition 00080 */ 00081 typedef struct 00082 { 00083 uint16_t Page; /*!< NAND memory Page address */ 00084 00085 uint16_t Plane; /*!< NAND memory Zone address */ 00086 00087 uint16_t Block; /*!< NAND memory Block address */ 00088 00089 } NAND_AddressTypeDef; 00090 00091 /** 00092 * @brief NAND Memory info Structure definition 00093 */ 00094 typedef struct 00095 { 00096 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 00097 for 8 bits addressing or words for 16 bits addressing */ 00098 00099 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 00100 for 8 bits addressing or words for 16 bits addressing */ 00101 00102 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 00103 00104 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 00105 00106 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 00107 00108 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 00109 00110 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 00111 parameter is mandatory for some NAND parts after the read 00112 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 00113 Example: Toshiba THTH58BYG3S0HBAI6. 00114 This parameter could be ENABLE or DISABLE 00115 Please check the Read Mode sequnece in the NAND device datasheet */ 00116 } NAND_DeviceConfigTypeDef; 00117 00118 /** 00119 * @brief NAND handle Structure definition 00120 */ 00121 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00122 typedef struct __NAND_HandleTypeDef 00123 #else 00124 typedef struct 00125 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00126 { 00127 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 00128 00129 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 00130 00131 HAL_LockTypeDef Lock; /*!< NAND locking object */ 00132 00133 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 00134 00135 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ 00136 00137 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00138 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ 00139 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ 00140 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ 00141 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00142 } NAND_HandleTypeDef; 00143 00144 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00145 /** 00146 * @brief HAL NAND Callback ID enumeration definition 00147 */ 00148 typedef enum 00149 { 00150 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ 00151 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ 00152 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ 00153 } HAL_NAND_CallbackIDTypeDef; 00154 00155 /** 00156 * @brief HAL NAND Callback pointer definition 00157 */ 00158 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); 00159 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00160 00161 /** 00162 * @} 00163 */ 00164 00165 /* Exported constants --------------------------------------------------------*/ 00166 /* Exported macro ------------------------------------------------------------*/ 00167 /** @defgroup NAND_Exported_Macros NAND Exported Macros 00168 * @{ 00169 */ 00170 00171 /** @brief Reset NAND handle state 00172 * @param __HANDLE__ specifies the NAND handle. 00173 * @retval None 00174 */ 00175 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00176 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ 00177 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ 00178 (__HANDLE__)->MspInitCallback = NULL; \ 00179 (__HANDLE__)->MspDeInitCallback = NULL; \ 00180 } while(0) 00181 #else 00182 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 00183 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00184 00185 /** 00186 * @} 00187 */ 00188 00189 /* Exported functions --------------------------------------------------------*/ 00190 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 00191 * @{ 00192 */ 00193 00194 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 00195 * @{ 00196 */ 00197 00198 /* Initialization/de-initialization functions ********************************/ 00199 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, 00200 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 00201 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 00202 00203 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 00204 00205 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 00206 00207 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 00208 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 00209 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 00210 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 00211 00212 /** 00213 * @} 00214 */ 00215 00216 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 00217 * @{ 00218 */ 00219 00220 /* IO operation functions ****************************************************/ 00221 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 00222 00223 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 00224 uint32_t NumPageToRead); 00225 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 00226 uint32_t NumPageToWrite); 00227 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00228 uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 00229 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00230 uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 00231 00232 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 00233 uint32_t NumPageToRead); 00234 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 00235 uint32_t NumPageToWrite); 00236 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00237 uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 00238 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00239 uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 00240 00241 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00242 00243 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00244 00245 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00246 /* NAND callback registering/unregistering */ 00247 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, 00248 pNAND_CallbackTypeDef pCallback); 00249 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); 00250 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00251 00252 /** 00253 * @} 00254 */ 00255 00256 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 00257 * @{ 00258 */ 00259 00260 /* NAND Control functions ****************************************************/ 00261 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 00262 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 00263 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 00264 00265 /** 00266 * @} 00267 */ 00268 00269 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 00270 * @{ 00271 */ 00272 /* NAND State functions *******************************************************/ 00273 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); 00274 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); 00275 /** 00276 * @} 00277 */ 00278 00279 /** 00280 * @} 00281 */ 00282 00283 /* Private types -------------------------------------------------------------*/ 00284 /* Private variables ---------------------------------------------------------*/ 00285 /* Private constants ---------------------------------------------------------*/ 00286 /** @defgroup NAND_Private_Constants NAND Private Constants 00287 * @{ 00288 */ 00289 #if defined(FMC_Bank2_3) 00290 #define NAND_DEVICE1 0x70000000UL 00291 #define NAND_DEVICE2 0x80000000UL 00292 #else 00293 #define NAND_DEVICE 0x80000000UL 00294 #endif 00295 #define NAND_WRITE_TIMEOUT 0x01000000UL 00296 00297 #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ 00298 #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ 00299 00300 #define NAND_CMD_AREA_A ((uint8_t)0x00) 00301 #define NAND_CMD_AREA_B ((uint8_t)0x01) 00302 #define NAND_CMD_AREA_C ((uint8_t)0x50) 00303 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) 00304 00305 #define NAND_CMD_WRITE0 ((uint8_t)0x80) 00306 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) 00307 #define NAND_CMD_ERASE0 ((uint8_t)0x60) 00308 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) 00309 #define NAND_CMD_READID ((uint8_t)0x90) 00310 #define NAND_CMD_STATUS ((uint8_t)0x70) 00311 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) 00312 #define NAND_CMD_RESET ((uint8_t)0xFF) 00313 00314 /* NAND memory status */ 00315 #define NAND_VALID_ADDRESS 0x00000100UL 00316 #define NAND_INVALID_ADDRESS 0x00000200UL 00317 #define NAND_TIMEOUT_ERROR 0x00000400UL 00318 #define NAND_BUSY 0x00000000UL 00319 #define NAND_ERROR 0x00000001UL 00320 #define NAND_READY 0x00000040UL 00321 /** 00322 * @} 00323 */ 00324 00325 /* Private macros ------------------------------------------------------------*/ 00326 /** @defgroup NAND_Private_Macros NAND Private Macros 00327 * @{ 00328 */ 00329 00330 /** 00331 * @brief NAND memory address computation. 00332 * @param __ADDRESS__ NAND memory address. 00333 * @param __HANDLE__ NAND handle. 00334 * @retval NAND Raw address value 00335 */ 00336 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ 00337 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * \ 00338 ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) 00339 00340 /** 00341 * @brief NAND memory Column address computation. 00342 * @param __HANDLE__ NAND handle. 00343 * @retval NAND Raw address value 00344 */ 00345 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 00346 00347 /** 00348 * @brief NAND memory address cycling. 00349 * @param __ADDRESS__ NAND memory address. 00350 * @retval NAND address cycling value. 00351 */ 00352 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 00353 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 00354 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 00355 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 00356 00357 /** 00358 * @brief NAND memory Columns cycling. 00359 * @param __ADDRESS__ NAND memory address. 00360 * @retval NAND Column address cycling value. 00361 */ 00362 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ 00363 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 00364 00365 /** 00366 * @} 00367 */ 00368 00369 /** 00370 * @} 00371 */ 00372 00373 /** 00374 * @} 00375 */ 00376 00377 /** 00378 * @} 00379 */ 00380 00381 #endif /* FMC_Bank3) || defined(FMC_Bank2_3) || defined(FSMC_Bank2_3 */ 00382 00383 #ifdef __cplusplus 00384 } 00385 #endif 00386 00387 #endif /* STM32F4xx_HAL_NAND_H */ 00388 00389 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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