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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_nor.h 00004 * @author MCD Application Team 00005 * @brief Header file of NOR HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F4xx_HAL_NOR_H 00022 #define STM32F4xx_HAL_NOR_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 #if defined(FMC_Bank1) || defined(FSMC_Bank1) 00029 00030 /* Includes ------------------------------------------------------------------*/ 00031 #if defined(FSMC_Bank1) 00032 #include "stm32f4xx_ll_fsmc.h" 00033 #else 00034 #include "stm32f4xx_ll_fmc.h" 00035 #endif /* FMC_Bank1 */ 00036 00037 /** @addtogroup STM32F4xx_HAL_Driver 00038 * @{ 00039 */ 00040 00041 /** @addtogroup NOR 00042 * @{ 00043 */ 00044 00045 /* Exported typedef ----------------------------------------------------------*/ 00046 /** @defgroup NOR_Exported_Types NOR Exported Types 00047 * @{ 00048 */ 00049 00050 /** 00051 * @brief HAL SRAM State structures definition 00052 */ 00053 typedef enum 00054 { 00055 HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */ 00056 HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */ 00057 HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */ 00058 HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */ 00059 HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */ 00060 } HAL_NOR_StateTypeDef; 00061 00062 /** 00063 * @brief FMC NOR Status typedef 00064 */ 00065 typedef enum 00066 { 00067 HAL_NOR_STATUS_SUCCESS = 0U, 00068 HAL_NOR_STATUS_ONGOING, 00069 HAL_NOR_STATUS_ERROR, 00070 HAL_NOR_STATUS_TIMEOUT 00071 } HAL_NOR_StatusTypeDef; 00072 00073 /** 00074 * @brief FMC NOR ID typedef 00075 */ 00076 typedef struct 00077 { 00078 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */ 00079 00080 uint16_t Device_Code1; 00081 00082 uint16_t Device_Code2; 00083 00084 uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory. 00085 These codes can be accessed by performing read operations with specific 00086 control signals and addresses set.They can also be accessed by issuing 00087 an Auto Select command */ 00088 } NOR_IDTypeDef; 00089 00090 /** 00091 * @brief FMC NOR CFI typedef 00092 */ 00093 typedef struct 00094 { 00095 /*!< Defines the information stored in the memory's Common flash interface 00096 which contains a description of various electrical and timing parameters, 00097 density information and functions supported by the memory */ 00098 00099 uint16_t CFI_1; 00100 00101 uint16_t CFI_2; 00102 00103 uint16_t CFI_3; 00104 00105 uint16_t CFI_4; 00106 } NOR_CFITypeDef; 00107 00108 /** 00109 * @brief NOR handle Structure definition 00110 */ 00111 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) 00112 typedef struct __NOR_HandleTypeDef 00113 #else 00114 typedef struct 00115 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ 00116 00117 { 00118 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ 00119 00120 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ 00121 00122 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */ 00123 00124 HAL_LockTypeDef Lock; /*!< NOR locking object */ 00125 00126 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */ 00127 00128 uint32_t CommandSet; /*!< NOR algorithm command set and control */ 00129 00130 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) 00131 void (* MspInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp Init callback */ 00132 void (* MspDeInitCallback)(struct __NOR_HandleTypeDef *hnor); /*!< NOR Msp DeInit callback */ 00133 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ 00134 } NOR_HandleTypeDef; 00135 00136 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) 00137 /** 00138 * @brief HAL NOR Callback ID enumeration definition 00139 */ 00140 typedef enum 00141 { 00142 HAL_NOR_MSP_INIT_CB_ID = 0x00U, /*!< NOR MspInit Callback ID */ 00143 HAL_NOR_MSP_DEINIT_CB_ID = 0x01U /*!< NOR MspDeInit Callback ID */ 00144 } HAL_NOR_CallbackIDTypeDef; 00145 00146 /** 00147 * @brief HAL NOR Callback pointer definition 00148 */ 00149 typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor); 00150 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ 00151 /** 00152 * @} 00153 */ 00154 00155 /* Exported constants --------------------------------------------------------*/ 00156 /* Exported macro ------------------------------------------------------------*/ 00157 /** @defgroup NOR_Exported_Macros NOR Exported Macros 00158 * @{ 00159 */ 00160 /** @brief Reset NOR handle state 00161 * @param __HANDLE__ specifies the NOR handle. 00162 * @retval None 00163 */ 00164 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) 00165 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) do { \ 00166 (__HANDLE__)->State = HAL_NOR_STATE_RESET; \ 00167 (__HANDLE__)->MspInitCallback = NULL; \ 00168 (__HANDLE__)->MspDeInitCallback = NULL; \ 00169 } while(0) 00170 #else 00171 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET) 00172 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ 00173 /** 00174 * @} 00175 */ 00176 00177 /* Exported functions --------------------------------------------------------*/ 00178 /** @addtogroup NOR_Exported_Functions NOR Exported Functions 00179 * @{ 00180 */ 00181 00182 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions 00183 * @{ 00184 */ 00185 00186 /* Initialization/de-initialization functions ********************************/ 00187 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, 00188 FMC_NORSRAM_TimingTypeDef *ExtTiming); 00189 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor); 00190 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor); 00191 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor); 00192 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout); 00193 /** 00194 * @} 00195 */ 00196 00197 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions 00198 * @{ 00199 */ 00200 00201 /* I/O operation functions ***************************************************/ 00202 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID); 00203 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor); 00204 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); 00205 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData); 00206 00207 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, 00208 uint32_t uwBufferSize); 00209 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, 00210 uint32_t uwBufferSize); 00211 00212 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address); 00213 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address); 00214 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI); 00215 00216 #if (USE_HAL_NOR_REGISTER_CALLBACKS == 1) 00217 /* NOR callback registering/unregistering */ 00218 HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, 00219 pNOR_CallbackTypeDef pCallback); 00220 HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId); 00221 #endif /* USE_HAL_NOR_REGISTER_CALLBACKS */ 00222 /** 00223 * @} 00224 */ 00225 00226 /** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions 00227 * @{ 00228 */ 00229 00230 /* NOR Control functions *****************************************************/ 00231 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor); 00232 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor); 00233 /** 00234 * @} 00235 */ 00236 00237 /** @addtogroup NOR_Exported_Functions_Group4 NOR State functions 00238 * @{ 00239 */ 00240 00241 /* NOR State functions ********************************************************/ 00242 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor); 00243 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout); 00244 /** 00245 * @} 00246 */ 00247 00248 /** 00249 * @} 00250 */ 00251 00252 /* Private types -------------------------------------------------------------*/ 00253 /* Private variables ---------------------------------------------------------*/ 00254 /* Private constants ---------------------------------------------------------*/ 00255 /** @defgroup NOR_Private_Constants NOR Private Constants 00256 * @{ 00257 */ 00258 /* NOR device IDs addresses */ 00259 #define MC_ADDRESS ((uint16_t)0x0000) 00260 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001) 00261 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E) 00262 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F) 00263 00264 /* NOR CFI IDs addresses */ 00265 #define CFI1_ADDRESS ((uint16_t)0x0061) 00266 #define CFI2_ADDRESS ((uint16_t)0x0062) 00267 #define CFI3_ADDRESS ((uint16_t)0x0063) 00268 #define CFI4_ADDRESS ((uint16_t)0x0064) 00269 00270 /* NOR operation wait timeout */ 00271 #define NOR_TMEOUT ((uint16_t)0xFFFF) 00272 00273 /* NOR memory data width */ 00274 #define NOR_MEMORY_8B ((uint8_t)0x00) 00275 #define NOR_MEMORY_16B ((uint8_t)0x01) 00276 00277 /* NOR memory device read/write start address */ 00278 #define NOR_MEMORY_ADRESS1 (0x60000000U) 00279 #define NOR_MEMORY_ADRESS2 (0x64000000U) 00280 #define NOR_MEMORY_ADRESS3 (0x68000000U) 00281 #define NOR_MEMORY_ADRESS4 (0x6C000000U) 00282 /** 00283 * @} 00284 */ 00285 00286 /* Private macros ------------------------------------------------------------*/ 00287 /** @defgroup NOR_Private_Macros NOR Private Macros 00288 * @{ 00289 */ 00290 /** 00291 * @brief NOR memory address shifting. 00292 * @param __NOR_ADDRESS NOR base address 00293 * @param __NOR_MEMORY_WIDTH_ NOR memory width 00294 * @param __ADDRESS__ NOR memory address 00295 * @retval NOR shifted address value 00296 */ 00297 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \ 00298 ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \ 00299 ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))): \ 00300 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))) 00301 00302 /** 00303 * @brief NOR memory write data to specified address. 00304 * @param __ADDRESS__ NOR memory address 00305 * @param __DATA__ Data to write 00306 * @retval None 00307 */ 00308 #define NOR_WRITE(__ADDRESS__, __DATA__) do{ \ 00309 (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \ 00310 __DSB(); \ 00311 } while(0) 00312 00313 /** 00314 * @} 00315 */ 00316 00317 /** 00318 * @} 00319 */ 00320 00321 /** 00322 * @} 00323 */ 00324 00325 #endif /* FMC_Bank1) || defined(FSMC_Bank1 */ 00326 00327 #ifdef __cplusplus 00328 } 00329 #endif 00330 00331 #endif /* STM32F4xx_HAL_NOR_H */ 00332 00333 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1