STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_pwr.c 00004 * @author MCD Application Team 00005 * @brief PWR HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Power Controller (PWR) peripheral: 00008 * + Initialization and de-initialization functions 00009 * + Peripheral Control functions 00010 * 00011 ****************************************************************************** 00012 * @attention 00013 * 00014 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00015 * All rights reserved.</center></h2> 00016 * 00017 * This software component is licensed by ST under BSD 3-Clause license, 00018 * the "License"; You may not use this file except in compliance with the 00019 * License. You may obtain a copy of the License at: 00020 * opensource.org/licenses/BSD-3-Clause 00021 * 00022 ****************************************************************************** 00023 */ 00024 00025 /* Includes ------------------------------------------------------------------*/ 00026 #include "stm32f4xx_hal.h" 00027 00028 /** @addtogroup STM32F4xx_HAL_Driver 00029 * @{ 00030 */ 00031 00032 /** @defgroup PWR PWR 00033 * @brief PWR HAL module driver 00034 * @{ 00035 */ 00036 00037 #ifdef HAL_PWR_MODULE_ENABLED 00038 00039 /* Private typedef -----------------------------------------------------------*/ 00040 /* Private define ------------------------------------------------------------*/ 00041 /** @addtogroup PWR_Private_Constants 00042 * @{ 00043 */ 00044 00045 /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask 00046 * @{ 00047 */ 00048 #define PVD_MODE_IT 0x00010000U 00049 #define PVD_MODE_EVT 0x00020000U 00050 #define PVD_RISING_EDGE 0x00000001U 00051 #define PVD_FALLING_EDGE 0x00000002U 00052 /** 00053 * @} 00054 */ 00055 00056 /** 00057 * @} 00058 */ 00059 /* Private macro -------------------------------------------------------------*/ 00060 /* Private variables ---------------------------------------------------------*/ 00061 /* Private function prototypes -----------------------------------------------*/ 00062 /* Private functions ---------------------------------------------------------*/ 00063 00064 /** @defgroup PWR_Exported_Functions PWR Exported Functions 00065 * @{ 00066 */ 00067 00068 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 00069 * @brief Initialization and de-initialization functions 00070 * 00071 @verbatim 00072 =============================================================================== 00073 ##### Initialization and de-initialization functions ##### 00074 =============================================================================== 00075 [..] 00076 After reset, the backup domain (RTC registers, RTC backup data 00077 registers and backup SRAM) is protected against possible unwanted 00078 write accesses. 00079 To enable access to the RTC Domain and RTC registers, proceed as follows: 00080 (+) Enable the Power Controller (PWR) APB1 interface clock using the 00081 __HAL_RCC_PWR_CLK_ENABLE() macro. 00082 (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. 00083 00084 @endverbatim 00085 * @{ 00086 */ 00087 00088 /** 00089 * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. 00090 * @retval None 00091 */ 00092 void HAL_PWR_DeInit(void) 00093 { 00094 __HAL_RCC_PWR_FORCE_RESET(); 00095 __HAL_RCC_PWR_RELEASE_RESET(); 00096 } 00097 00098 /** 00099 * @brief Enables access to the backup domain (RTC registers, RTC 00100 * backup data registers and backup SRAM). 00101 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 00102 * Backup Domain Access should be kept enabled. 00103 * @note The following sequence is required to bypass the delay between 00104 * DBP bit programming and the effective enabling of the backup domain. 00105 * Please check the Errata Sheet for more details under "Possible delay 00106 * in backup domain protection disabling/enabling after programming the 00107 * DBP bit" section. 00108 * @retval None 00109 */ 00110 void HAL_PWR_EnableBkUpAccess(void) 00111 { 00112 __IO uint32_t dummyread; 00113 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 00114 dummyread = PWR->CR; 00115 UNUSED(dummyread); 00116 } 00117 00118 /** 00119 * @brief Disables access to the backup domain (RTC registers, RTC 00120 * backup data registers and backup SRAM). 00121 * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 00122 * Backup Domain Access should be kept enabled. 00123 * @note The following sequence is required to bypass the delay between 00124 * DBP bit programming and the effective disabling of the backup domain. 00125 * Please check the Errata Sheet for more details under "Possible delay 00126 * in backup domain protection disabling/enabling after programming the 00127 * DBP bit" section. 00128 * @retval None 00129 */ 00130 void HAL_PWR_DisableBkUpAccess(void) 00131 { 00132 __IO uint32_t dummyread; 00133 *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; 00134 dummyread = PWR->CR; 00135 UNUSED(dummyread); 00136 } 00137 00138 /** 00139 * @} 00140 */ 00141 00142 /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 00143 * @brief Low Power modes configuration functions 00144 * 00145 @verbatim 00146 00147 =============================================================================== 00148 ##### Peripheral Control functions ##### 00149 =============================================================================== 00150 00151 *** PVD configuration *** 00152 ========================= 00153 [..] 00154 (+) The PVD is used to monitor the VDD power supply by comparing it to a 00155 threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 00156 (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 00157 than the PVD threshold. This event is internally connected to the EXTI 00158 line16 and can generate an interrupt if enabled. This is done through 00159 __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. 00160 (+) The PVD is stopped in Standby mode. 00161 00162 *** Wake-up pin configuration *** 00163 ================================ 00164 [..] 00165 (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 00166 forced in input pull-down configuration and is active on rising edges. 00167 (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. 00168 (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 00169 (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01 00170 00171 *** Low Power modes configuration *** 00172 ===================================== 00173 [..] 00174 The devices feature 3 low-power modes: 00175 (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. 00176 (+) Stop mode: all clocks are stopped, regulator running, regulator 00177 in low power mode 00178 (+) Standby mode: 1.2V domain powered off. 00179 00180 *** Sleep mode *** 00181 ================== 00182 [..] 00183 (+) Entry: 00184 The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI) 00185 functions with 00186 (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 00187 (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 00188 00189 -@@- The Regulator parameter is not used for the STM32F4 family 00190 and is kept as parameter just to maintain compatibility with the 00191 lower power families (STM32L). 00192 (+) Exit: 00193 Any peripheral interrupt acknowledged by the nested vectored interrupt 00194 controller (NVIC) can wake up the device from Sleep mode. 00195 00196 *** Stop mode *** 00197 ================= 00198 [..] 00199 In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, 00200 and the HSE RC oscillators are disabled. Internal SRAM and register contents 00201 are preserved. 00202 The voltage regulator can be configured either in normal or low-power mode. 00203 To minimize the consumption In Stop mode, FLASH can be powered off before 00204 entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. 00205 It can be switched on again by software after exiting the Stop mode using 00206 the HAL_PWREx_DisableFlashPowerDown() function. 00207 00208 (+) Entry: 00209 The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON) 00210 function with: 00211 (++) Main regulator ON. 00212 (++) Low Power regulator ON. 00213 (+) Exit: 00214 Any EXTI Line (Internal or External) configured in Interrupt/Event mode. 00215 00216 *** Standby mode *** 00217 ==================== 00218 [..] 00219 (+) 00220 The Standby mode allows to achieve the lowest power consumption. It is based 00221 on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 00222 The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 00223 the HSE oscillator are also switched off. SRAM and register contents are lost 00224 except for the RTC registers, RTC backup registers, backup SRAM and Standby 00225 circuitry. 00226 00227 The voltage regulator is OFF. 00228 00229 (++) Entry: 00230 (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. 00231 (++) Exit: 00232 (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, 00233 tamper event, time-stamp event, external reset in NRST pin, IWDG reset. 00234 00235 *** Auto-wake-up (AWU) from low-power mode *** 00236 ============================================= 00237 [..] 00238 00239 (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 00240 Wake-up event, a tamper event or a time-stamp event, without depending on 00241 an external interrupt (Auto-wake-up mode). 00242 00243 (+) RTC auto-wake-up (AWU) from the Stop and Standby modes 00244 00245 (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to 00246 configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. 00247 00248 (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 00249 is necessary to configure the RTC to detect the tamper or time stamp event using the 00250 HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. 00251 00252 (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to 00253 configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTimer_IT() function. 00254 00255 @endverbatim 00256 * @{ 00257 */ 00258 00259 /** 00260 * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 00261 * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration 00262 * information for the PVD. 00263 * @note Refer to the electrical characteristics of your device datasheet for 00264 * more details about the voltage threshold corresponding to each 00265 * detection level. 00266 * @retval None 00267 */ 00268 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 00269 { 00270 /* Check the parameters */ 00271 assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 00272 assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 00273 00274 /* Set PLS[7:5] bits according to PVDLevel value */ 00275 MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 00276 00277 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00278 __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 00279 __HAL_PWR_PVD_EXTI_DISABLE_IT(); 00280 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); 00281 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 00282 00283 /* Configure interrupt mode */ 00284 if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 00285 { 00286 __HAL_PWR_PVD_EXTI_ENABLE_IT(); 00287 } 00288 00289 /* Configure event mode */ 00290 if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 00291 { 00292 __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 00293 } 00294 00295 /* Configure the edge */ 00296 if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 00297 { 00298 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 00299 } 00300 00301 if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 00302 { 00303 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 00304 } 00305 } 00306 00307 /** 00308 * @brief Enables the Power Voltage Detector(PVD). 00309 * @retval None 00310 */ 00311 void HAL_PWR_EnablePVD(void) 00312 { 00313 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; 00314 } 00315 00316 /** 00317 * @brief Disables the Power Voltage Detector(PVD). 00318 * @retval None 00319 */ 00320 void HAL_PWR_DisablePVD(void) 00321 { 00322 *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; 00323 } 00324 00325 /** 00326 * @brief Enables the Wake-up PINx functionality. 00327 * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. 00328 * This parameter can be one of the following values: 00329 * @arg PWR_WAKEUP_PIN1 00330 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices 00331 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices 00332 * @retval None 00333 */ 00334 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) 00335 { 00336 /* Check the parameter */ 00337 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 00338 00339 /* Enable the wake up pin */ 00340 SET_BIT(PWR->CSR, WakeUpPinx); 00341 } 00342 00343 /** 00344 * @brief Disables the Wake-up PINx functionality. 00345 * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. 00346 * This parameter can be one of the following values: 00347 * @arg PWR_WAKEUP_PIN1 00348 * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices 00349 * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices 00350 * @retval None 00351 */ 00352 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) 00353 { 00354 /* Check the parameter */ 00355 assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 00356 00357 /* Disable the wake up pin */ 00358 CLEAR_BIT(PWR->CSR, WakeUpPinx); 00359 } 00360 00361 /** 00362 * @brief Enters Sleep mode. 00363 * 00364 * @note In Sleep mode, all I/O pins keep the same state as in Run mode. 00365 * 00366 * @note In Sleep mode, the systick is stopped to avoid exit from this mode with 00367 * systick interrupt when used as time base for Timeout 00368 * 00369 * @param Regulator Specifies the regulator state in SLEEP mode. 00370 * This parameter can be one of the following values: 00371 * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON 00372 * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON 00373 * @note This parameter is not used for the STM32F4 family and is kept as parameter 00374 * just to maintain compatibility with the lower power families. 00375 * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. 00376 * This parameter can be one of the following values: 00377 * @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 00378 * @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 00379 * @retval None 00380 */ 00381 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) 00382 { 00383 /* Check the parameters */ 00384 assert_param(IS_PWR_REGULATOR(Regulator)); 00385 assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); 00386 00387 /* Clear SLEEPDEEP bit of Cortex System Control Register */ 00388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00389 00390 /* Select SLEEP mode entry -------------------------------------------------*/ 00391 if(SLEEPEntry == PWR_SLEEPENTRY_WFI) 00392 { 00393 /* Request Wait For Interrupt */ 00394 __WFI(); 00395 } 00396 else 00397 { 00398 /* Request Wait For Event */ 00399 __SEV(); 00400 __WFE(); 00401 __WFE(); 00402 } 00403 } 00404 00405 /** 00406 * @brief Enters Stop mode. 00407 * @note In Stop mode, all I/O pins keep the same state as in Run mode. 00408 * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 00409 * the HSI RC oscillator is selected as system clock. 00410 * @note When the voltage regulator operates in low power mode, an additional 00411 * startup delay is incurred when waking up from Stop mode. 00412 * By keeping the internal regulator ON during Stop mode, the consumption 00413 * is higher although the startup time is reduced. 00414 * @param Regulator Specifies the regulator state in Stop mode. 00415 * This parameter can be one of the following values: 00416 * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON 00417 * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON 00418 * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. 00419 * This parameter can be one of the following values: 00420 * @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction 00421 * @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction 00422 * @retval None 00423 */ 00424 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) 00425 { 00426 /* Check the parameters */ 00427 assert_param(IS_PWR_REGULATOR(Regulator)); 00428 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 00429 00430 /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator value */ 00431 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); 00432 00433 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00434 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00435 00436 /* Select Stop mode entry --------------------------------------------------*/ 00437 if(STOPEntry == PWR_STOPENTRY_WFI) 00438 { 00439 /* Request Wait For Interrupt */ 00440 __WFI(); 00441 } 00442 else 00443 { 00444 /* Request Wait For Event */ 00445 __SEV(); 00446 __WFE(); 00447 __WFE(); 00448 } 00449 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 00450 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00451 } 00452 00453 /** 00454 * @brief Enters Standby mode. 00455 * @note In Standby mode, all I/O pins are high impedance except for: 00456 * - Reset pad (still available) 00457 * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 00458 * Alarm out, or RTC clock calibration out. 00459 * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. 00460 * - WKUP pin 1 (PA0) if enabled. 00461 * @retval None 00462 */ 00463 void HAL_PWR_EnterSTANDBYMode(void) 00464 { 00465 /* Select Standby mode */ 00466 SET_BIT(PWR->CR, PWR_CR_PDDS); 00467 00468 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00469 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00470 00471 /* This option is used to ensure that store operations are completed */ 00472 #if defined ( __CC_ARM) 00473 __force_stores(); 00474 #endif 00475 /* Request Wait For Interrupt */ 00476 __WFI(); 00477 } 00478 00479 /** 00480 * @brief This function handles the PWR PVD interrupt request. 00481 * @note This API should be called under the PVD_IRQHandler(). 00482 * @retval None 00483 */ 00484 void HAL_PWR_PVD_IRQHandler(void) 00485 { 00486 /* Check PWR Exti flag */ 00487 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 00488 { 00489 /* PWR PVD interrupt user callback */ 00490 HAL_PWR_PVDCallback(); 00491 00492 /* Clear PWR Exti pending bit */ 00493 __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 00494 } 00495 } 00496 00497 /** 00498 * @brief PWR PVD interrupt callback 00499 * @retval None 00500 */ 00501 __weak void HAL_PWR_PVDCallback(void) 00502 { 00503 /* NOTE : This function Should not be modified, when the callback is needed, 00504 the HAL_PWR_PVDCallback could be implemented in the user file 00505 */ 00506 } 00507 00508 /** 00509 * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 00510 * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 00511 * re-enters SLEEP mode when an interruption handling is over. 00512 * Setting this bit is useful when the processor is expected to run only on 00513 * interruptions handling. 00514 * @retval None 00515 */ 00516 void HAL_PWR_EnableSleepOnExit(void) 00517 { 00518 /* Set SLEEPONEXIT bit of Cortex System Control Register */ 00519 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00520 } 00521 00522 /** 00523 * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 00524 * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 00525 * re-enters SLEEP mode when an interruption handling is over. 00526 * @retval None 00527 */ 00528 void HAL_PWR_DisableSleepOnExit(void) 00529 { 00530 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 00531 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00532 } 00533 00534 /** 00535 * @brief Enables CORTEX M4 SEVONPEND bit. 00536 * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 00537 * WFE to wake up when an interrupt moves from inactive to pended. 00538 * @retval None 00539 */ 00540 void HAL_PWR_EnableSEVOnPend(void) 00541 { 00542 /* Set SEVONPEND bit of Cortex System Control Register */ 00543 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00544 } 00545 00546 /** 00547 * @brief Disables CORTEX M4 SEVONPEND bit. 00548 * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 00549 * WFE to wake up when an interrupt moves from inactive to pended. 00550 * @retval None 00551 */ 00552 void HAL_PWR_DisableSEVOnPend(void) 00553 { 00554 /* Clear SEVONPEND bit of Cortex System Control Register */ 00555 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00556 } 00557 00558 /** 00559 * @} 00560 */ 00561 00562 /** 00563 * @} 00564 */ 00565 00566 #endif /* HAL_PWR_MODULE_ENABLED */ 00567 /** 00568 * @} 00569 */ 00570 00571 /** 00572 * @} 00573 */ 00574 00575 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/