STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_sdram.c 00004 * @author MCD Application Team 00005 * @brief SDRAM HAL module driver. 00006 * This file provides a generic firmware to drive SDRAM memories mounted 00007 * as external device. 00008 * 00009 @verbatim 00010 ============================================================================== 00011 ##### How to use this driver ##### 00012 ============================================================================== 00013 [..] 00014 This driver is a generic layered driver which contains a set of APIs used to 00015 control SDRAM memories. It uses the FMC layer functions to interface 00016 with SDRAM devices. 00017 The following sequence should be followed to configure the FMC to interface 00018 with SDRAM memories: 00019 00020 (#) Declare a SDRAM_HandleTypeDef handle structure, for example: 00021 SDRAM_HandleTypeDef hsdram 00022 00023 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed 00024 values of the structure member. 00025 00026 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined 00027 base register instance for NOR or SDRAM device 00028 00029 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: 00030 FMC_SDRAM_TimingTypeDef Timing; 00031 and fill its fields with the allowed values of the structure member. 00032 00033 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function 00034 performs the following sequence: 00035 00036 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() 00037 (##) Control register configuration using the FMC SDRAM interface function 00038 FMC_SDRAM_Init() 00039 (##) Timing register configuration using the FMC SDRAM interface function 00040 FMC_SDRAM_Timing_Init() 00041 (##) Program the SDRAM external device by applying its initialization sequence 00042 according to the device plugged in your hardware. This step is mandatory 00043 for accessing the SDRAM device. 00044 00045 (#) At this stage you can perform read/write accesses from/to the memory connected 00046 to the SDRAM Bank. You can perform either polling or DMA transfer using the 00047 following APIs: 00048 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access 00049 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer 00050 00051 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ 00052 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or 00053 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM 00054 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef 00055 structure. 00056 00057 (#) You can continuously monitor the SDRAM device HAL state by calling the function 00058 HAL_SDRAM_GetState() 00059 00060 *** Callback registration *** 00061 ============================================= 00062 [..] 00063 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 00064 allows the user to configure dynamically the driver callbacks. 00065 00066 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, 00067 it allows to register following callbacks: 00068 (+) MspInitCallback : SDRAM MspInit. 00069 (+) MspDeInitCallback : SDRAM MspDeInit. 00070 This function takes as parameters the HAL peripheral handle, the Callback ID 00071 and a pointer to the user callback function. 00072 00073 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default 00074 weak (surcharged) function. It allows to reset following callbacks: 00075 (+) MspInitCallback : SDRAM MspInit. 00076 (+) MspDeInitCallback : SDRAM MspDeInit. 00077 This function) takes as parameters the HAL peripheral handle and the Callback ID. 00078 00079 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET 00080 all callbacks are reset to the corresponding legacy weak (surcharged) functions. 00081 Exception done for MspInit and MspDeInit callbacks that are respectively 00082 reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init 00083 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). 00084 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit 00085 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) 00086 00087 Callbacks can be registered/unregistered in READY state only. 00088 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered 00089 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used 00090 during the Init/DeInit. 00091 In that case first register the MspInit/MspDeInit user callbacks 00092 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit 00093 or HAL_SDRAM_Init function. 00094 00095 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or 00096 not defined, the callback registering feature is not available 00097 and weak (surcharged) callbacks are used. 00098 00099 @endverbatim 00100 ****************************************************************************** 00101 * @attention 00102 * 00103 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00104 * All rights reserved.</center></h2> 00105 * 00106 * This software component is licensed by ST under BSD 3-Clause license, 00107 * the "License"; You may not use this file except in compliance with the 00108 * License. You may obtain a copy of the License at: 00109 * opensource.org/licenses/BSD-3-Clause 00110 * 00111 ****************************************************************************** 00112 */ 00113 00114 /* Includes ------------------------------------------------------------------*/ 00115 #include "stm32f4xx_hal.h" 00116 00117 #if defined(FMC_Bank5_6) 00118 00119 /** @addtogroup STM32F4xx_HAL_Driver 00120 * @{ 00121 */ 00122 00123 #ifdef HAL_SDRAM_MODULE_ENABLED 00124 00125 /** @defgroup SDRAM SDRAM 00126 * @brief SDRAM driver modules 00127 * @{ 00128 */ 00129 00130 /* Private typedef -----------------------------------------------------------*/ 00131 /* Private define ------------------------------------------------------------*/ 00132 /* Private macro -------------------------------------------------------------*/ 00133 /* Private variables ---------------------------------------------------------*/ 00134 /* Private function prototypes -----------------------------------------------*/ 00135 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma); 00136 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma); 00137 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma); 00138 00139 /* Exported functions --------------------------------------------------------*/ 00140 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions 00141 * @{ 00142 */ 00143 00144 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions 00145 * @brief Initialization and Configuration functions 00146 * 00147 @verbatim 00148 ============================================================================== 00149 ##### SDRAM Initialization and de_initialization functions ##### 00150 ============================================================================== 00151 [..] 00152 This section provides functions allowing to initialize/de-initialize 00153 the SDRAM memory 00154 00155 @endverbatim 00156 * @{ 00157 */ 00158 00159 /** 00160 * @brief Performs the SDRAM device initialization sequence. 00161 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00162 * the configuration information for SDRAM module. 00163 * @param Timing Pointer to SDRAM control timing structure 00164 * @retval HAL status 00165 */ 00166 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) 00167 { 00168 /* Check the SDRAM handle parameter */ 00169 if (hsdram == NULL) 00170 { 00171 return HAL_ERROR; 00172 } 00173 00174 if (hsdram->State == HAL_SDRAM_STATE_RESET) 00175 { 00176 /* Allocate lock resource and initialize it */ 00177 hsdram->Lock = HAL_UNLOCKED; 00178 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00179 if (hsdram->MspInitCallback == NULL) 00180 { 00181 hsdram->MspInitCallback = HAL_SDRAM_MspInit; 00182 } 00183 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; 00184 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; 00185 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; 00186 00187 /* Init the low level hardware */ 00188 hsdram->MspInitCallback(hsdram); 00189 #else 00190 /* Initialize the low level hardware (MSP) */ 00191 HAL_SDRAM_MspInit(hsdram); 00192 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00193 } 00194 00195 /* Initialize the SDRAM controller state */ 00196 hsdram->State = HAL_SDRAM_STATE_BUSY; 00197 00198 /* Initialize SDRAM control Interface */ 00199 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); 00200 00201 /* Initialize SDRAM timing Interface */ 00202 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); 00203 /* Update the SDRAM controller state */ 00204 hsdram->State = HAL_SDRAM_STATE_READY; 00205 00206 return HAL_OK; 00207 } 00208 00209 /** 00210 * @brief Perform the SDRAM device initialization sequence. 00211 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00212 * the configuration information for SDRAM module. 00213 * @retval HAL status 00214 */ 00215 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) 00216 { 00217 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00218 if (hsdram->MspDeInitCallback == NULL) 00219 { 00220 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; 00221 } 00222 00223 /* DeInit the low level hardware */ 00224 hsdram->MspDeInitCallback(hsdram); 00225 #else 00226 /* Initialize the low level hardware (MSP) */ 00227 HAL_SDRAM_MspDeInit(hsdram); 00228 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00229 00230 /* Configure the SDRAM registers with their reset values */ 00231 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); 00232 00233 /* Reset the SDRAM controller state */ 00234 hsdram->State = HAL_SDRAM_STATE_RESET; 00235 00236 /* Release Lock */ 00237 __HAL_UNLOCK(hsdram); 00238 00239 return HAL_OK; 00240 } 00241 00242 /** 00243 * @brief SDRAM MSP Init. 00244 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00245 * the configuration information for SDRAM module. 00246 * @retval None 00247 */ 00248 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) 00249 { 00250 /* Prevent unused argument(s) compilation warning */ 00251 UNUSED(hsdram); 00252 00253 /* NOTE: This function Should not be modified, when the callback is needed, 00254 the HAL_SDRAM_MspInit could be implemented in the user file 00255 */ 00256 } 00257 00258 /** 00259 * @brief SDRAM MSP DeInit. 00260 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00261 * the configuration information for SDRAM module. 00262 * @retval None 00263 */ 00264 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) 00265 { 00266 /* Prevent unused argument(s) compilation warning */ 00267 UNUSED(hsdram); 00268 00269 /* NOTE: This function Should not be modified, when the callback is needed, 00270 the HAL_SDRAM_MspDeInit could be implemented in the user file 00271 */ 00272 } 00273 00274 /** 00275 * @brief This function handles SDRAM refresh error interrupt request. 00276 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00277 * the configuration information for SDRAM module. 00278 * @retval HAL status 00279 */ 00280 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) 00281 { 00282 /* Check SDRAM interrupt Rising edge flag */ 00283 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) 00284 { 00285 /* SDRAM refresh error interrupt callback */ 00286 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00287 hsdram->RefreshErrorCallback(hsdram); 00288 #else 00289 HAL_SDRAM_RefreshErrorCallback(hsdram); 00290 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00291 00292 /* Clear SDRAM refresh error interrupt pending bit */ 00293 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); 00294 } 00295 } 00296 00297 /** 00298 * @brief SDRAM Refresh error callback. 00299 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00300 * the configuration information for SDRAM module. 00301 * @retval None 00302 */ 00303 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) 00304 { 00305 /* Prevent unused argument(s) compilation warning */ 00306 UNUSED(hsdram); 00307 00308 /* NOTE: This function Should not be modified, when the callback is needed, 00309 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file 00310 */ 00311 } 00312 00313 /** 00314 * @brief DMA transfer complete callback. 00315 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00316 * the configuration information for the specified DMA module. 00317 * @retval None 00318 */ 00319 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) 00320 { 00321 /* Prevent unused argument(s) compilation warning */ 00322 UNUSED(hdma); 00323 00324 /* NOTE: This function Should not be modified, when the callback is needed, 00325 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file 00326 */ 00327 } 00328 00329 /** 00330 * @brief DMA transfer complete error callback. 00331 * @param hdma DMA handle 00332 * @retval None 00333 */ 00334 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) 00335 { 00336 /* Prevent unused argument(s) compilation warning */ 00337 UNUSED(hdma); 00338 00339 /* NOTE: This function Should not be modified, when the callback is needed, 00340 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file 00341 */ 00342 } 00343 00344 /** 00345 * @} 00346 */ 00347 00348 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions 00349 * @brief Input Output and memory control functions 00350 * 00351 @verbatim 00352 ============================================================================== 00353 ##### SDRAM Input and Output functions ##### 00354 ============================================================================== 00355 [..] 00356 This section provides functions allowing to use and control the SDRAM memory 00357 00358 @endverbatim 00359 * @{ 00360 */ 00361 00362 /** 00363 * @brief Reads 8-bit data buffer from the SDRAM memory. 00364 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00365 * the configuration information for SDRAM module. 00366 * @param pAddress Pointer to read start address 00367 * @param pDstBuffer Pointer to destination buffer 00368 * @param BufferSize Size of the buffer to read from memory 00369 * @retval HAL status 00370 */ 00371 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, 00372 uint32_t BufferSize) 00373 { 00374 uint32_t size; 00375 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; 00376 uint8_t *pdestbuff = pDstBuffer; 00377 HAL_SDRAM_StateTypeDef state = hsdram->State; 00378 00379 /* Check the SDRAM controller state */ 00380 if (state == HAL_SDRAM_STATE_BUSY) 00381 { 00382 return HAL_BUSY; 00383 } 00384 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00385 { 00386 /* Process Locked */ 00387 __HAL_LOCK(hsdram); 00388 00389 /* Update the SDRAM controller state */ 00390 hsdram->State = HAL_SDRAM_STATE_BUSY; 00391 00392 /* Read data from source */ 00393 for (size = BufferSize; size != 0U; size--) 00394 { 00395 *pdestbuff = *(__IO uint8_t *)pSdramAddress; 00396 pdestbuff++; 00397 pSdramAddress++; 00398 } 00399 00400 /* Update the SDRAM controller state */ 00401 hsdram->State = state; 00402 00403 /* Process Unlocked */ 00404 __HAL_UNLOCK(hsdram); 00405 } 00406 else 00407 { 00408 return HAL_ERROR; 00409 } 00410 00411 return HAL_OK; 00412 } 00413 00414 /** 00415 * @brief Writes 8-bit data buffer to SDRAM memory. 00416 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00417 * the configuration information for SDRAM module. 00418 * @param pAddress Pointer to write start address 00419 * @param pSrcBuffer Pointer to source buffer to write 00420 * @param BufferSize Size of the buffer to write to memory 00421 * @retval HAL status 00422 */ 00423 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, 00424 uint32_t BufferSize) 00425 { 00426 uint32_t size; 00427 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; 00428 uint8_t *psrcbuff = pSrcBuffer; 00429 00430 /* Check the SDRAM controller state */ 00431 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 00432 { 00433 return HAL_BUSY; 00434 } 00435 else if (hsdram->State == HAL_SDRAM_STATE_READY) 00436 { 00437 /* Process Locked */ 00438 __HAL_LOCK(hsdram); 00439 00440 /* Update the SDRAM controller state */ 00441 hsdram->State = HAL_SDRAM_STATE_BUSY; 00442 00443 /* Write data to memory */ 00444 for (size = BufferSize; size != 0U; size--) 00445 { 00446 *(__IO uint8_t *)pSdramAddress = *psrcbuff; 00447 psrcbuff++; 00448 pSdramAddress++; 00449 } 00450 00451 /* Update the SDRAM controller state */ 00452 hsdram->State = HAL_SDRAM_STATE_READY; 00453 00454 /* Process Unlocked */ 00455 __HAL_UNLOCK(hsdram); 00456 } 00457 else 00458 { 00459 return HAL_ERROR; 00460 } 00461 00462 return HAL_OK; 00463 } 00464 00465 /** 00466 * @brief Reads 16-bit data buffer from the SDRAM memory. 00467 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00468 * the configuration information for SDRAM module. 00469 * @param pAddress Pointer to read start address 00470 * @param pDstBuffer Pointer to destination buffer 00471 * @param BufferSize Size of the buffer to read from memory 00472 * @retval HAL status 00473 */ 00474 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, 00475 uint32_t BufferSize) 00476 { 00477 uint32_t size; 00478 __IO uint32_t *pSdramAddress = pAddress; 00479 uint16_t *pdestbuff = pDstBuffer; 00480 HAL_SDRAM_StateTypeDef state = hsdram->State; 00481 00482 /* Check the SDRAM controller state */ 00483 if (state == HAL_SDRAM_STATE_BUSY) 00484 { 00485 return HAL_BUSY; 00486 } 00487 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00488 { 00489 /* Process Locked */ 00490 __HAL_LOCK(hsdram); 00491 00492 /* Update the SDRAM controller state */ 00493 hsdram->State = HAL_SDRAM_STATE_BUSY; 00494 00495 /* Read data from memory */ 00496 for (size = BufferSize; size >= 2U ; size -= 2U) 00497 { 00498 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); 00499 pdestbuff++; 00500 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U); 00501 pdestbuff++; 00502 pSdramAddress++; 00503 } 00504 00505 /* Read last 16-bits if size is not 32-bits multiple */ 00506 if ((BufferSize % 2U) != 0U) 00507 { 00508 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); 00509 } 00510 00511 /* Update the SDRAM controller state */ 00512 hsdram->State = state; 00513 00514 /* Process Unlocked */ 00515 __HAL_UNLOCK(hsdram); 00516 } 00517 else 00518 { 00519 return HAL_ERROR; 00520 } 00521 00522 return HAL_OK; 00523 } 00524 00525 /** 00526 * @brief Writes 16-bit data buffer to SDRAM memory. 00527 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00528 * the configuration information for SDRAM module. 00529 * @param pAddress Pointer to write start address 00530 * @param pSrcBuffer Pointer to source buffer to write 00531 * @param BufferSize Size of the buffer to write to memory 00532 * @retval HAL status 00533 */ 00534 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, 00535 uint32_t BufferSize) 00536 { 00537 uint32_t size; 00538 __IO uint32_t *psdramaddress = pAddress; 00539 uint16_t *psrcbuff = pSrcBuffer; 00540 00541 /* Check the SDRAM controller state */ 00542 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 00543 { 00544 return HAL_BUSY; 00545 } 00546 else if (hsdram->State == HAL_SDRAM_STATE_READY) 00547 { 00548 /* Process Locked */ 00549 __HAL_LOCK(hsdram); 00550 00551 /* Update the SDRAM controller state */ 00552 hsdram->State = HAL_SDRAM_STATE_BUSY; 00553 00554 /* Write data to memory */ 00555 for (size = BufferSize; size >= 2U ; size -= 2U) 00556 { 00557 *psdramaddress = (uint32_t)(*psrcbuff); 00558 psrcbuff++; 00559 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U); 00560 psrcbuff++; 00561 psdramaddress++; 00562 } 00563 00564 /* Write last 16-bits if size is not 32-bits multiple */ 00565 if ((BufferSize % 2U) != 0U) 00566 { 00567 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); 00568 } 00569 00570 /* Update the SDRAM controller state */ 00571 hsdram->State = HAL_SDRAM_STATE_READY; 00572 00573 /* Process Unlocked */ 00574 __HAL_UNLOCK(hsdram); 00575 } 00576 else 00577 { 00578 return HAL_ERROR; 00579 } 00580 00581 return HAL_OK; 00582 } 00583 00584 /** 00585 * @brief Reads 32-bit data buffer from the SDRAM memory. 00586 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00587 * the configuration information for SDRAM module. 00588 * @param pAddress Pointer to read start address 00589 * @param pDstBuffer Pointer to destination buffer 00590 * @param BufferSize Size of the buffer to read from memory 00591 * @retval HAL status 00592 */ 00593 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, 00594 uint32_t BufferSize) 00595 { 00596 uint32_t size; 00597 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; 00598 uint32_t *pdestbuff = pDstBuffer; 00599 HAL_SDRAM_StateTypeDef state = hsdram->State; 00600 00601 /* Check the SDRAM controller state */ 00602 if (state == HAL_SDRAM_STATE_BUSY) 00603 { 00604 return HAL_BUSY; 00605 } 00606 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00607 { 00608 /* Process Locked */ 00609 __HAL_LOCK(hsdram); 00610 00611 /* Update the SDRAM controller state */ 00612 hsdram->State = HAL_SDRAM_STATE_BUSY; 00613 00614 /* Read data from source */ 00615 for (size = BufferSize; size != 0U; size--) 00616 { 00617 *pdestbuff = *(__IO uint32_t *)pSdramAddress; 00618 pdestbuff++; 00619 pSdramAddress++; 00620 } 00621 00622 /* Update the SDRAM controller state */ 00623 hsdram->State = state; 00624 00625 /* Process Unlocked */ 00626 __HAL_UNLOCK(hsdram); 00627 } 00628 else 00629 { 00630 return HAL_ERROR; 00631 } 00632 00633 return HAL_OK; 00634 } 00635 00636 /** 00637 * @brief Writes 32-bit data buffer to SDRAM memory. 00638 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00639 * the configuration information for SDRAM module. 00640 * @param pAddress Pointer to write start address 00641 * @param pSrcBuffer Pointer to source buffer to write 00642 * @param BufferSize Size of the buffer to write to memory 00643 * @retval HAL status 00644 */ 00645 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, 00646 uint32_t BufferSize) 00647 { 00648 uint32_t size; 00649 __IO uint32_t *pSdramAddress = pAddress; 00650 uint32_t *psrcbuff = pSrcBuffer; 00651 00652 /* Check the SDRAM controller state */ 00653 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 00654 { 00655 return HAL_BUSY; 00656 } 00657 else if (hsdram->State == HAL_SDRAM_STATE_READY) 00658 { 00659 /* Process Locked */ 00660 __HAL_LOCK(hsdram); 00661 00662 /* Update the SDRAM controller state */ 00663 hsdram->State = HAL_SDRAM_STATE_BUSY; 00664 00665 /* Write data to memory */ 00666 for (size = BufferSize; size != 0U; size--) 00667 { 00668 *pSdramAddress = *psrcbuff; 00669 psrcbuff++; 00670 pSdramAddress++; 00671 } 00672 00673 /* Update the SDRAM controller state */ 00674 hsdram->State = HAL_SDRAM_STATE_READY; 00675 00676 /* Process Unlocked */ 00677 __HAL_UNLOCK(hsdram); 00678 } 00679 else 00680 { 00681 return HAL_ERROR; 00682 } 00683 00684 return HAL_OK; 00685 } 00686 00687 /** 00688 * @brief Reads a Words data from the SDRAM memory using DMA transfer. 00689 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00690 * the configuration information for SDRAM module. 00691 * @param pAddress Pointer to read start address 00692 * @param pDstBuffer Pointer to destination buffer 00693 * @param BufferSize Size of the buffer to read from memory 00694 * @retval HAL status 00695 */ 00696 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, 00697 uint32_t BufferSize) 00698 { 00699 HAL_StatusTypeDef status; 00700 HAL_SDRAM_StateTypeDef state = hsdram->State; 00701 00702 /* Check the SDRAM controller state */ 00703 if (state == HAL_SDRAM_STATE_BUSY) 00704 { 00705 status = HAL_BUSY; 00706 } 00707 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00708 { 00709 /* Process Locked */ 00710 __HAL_LOCK(hsdram); 00711 00712 /* Update the SDRAM controller state */ 00713 hsdram->State = HAL_SDRAM_STATE_BUSY; 00714 00715 /* Configure DMA user callbacks */ 00716 if (state == HAL_SDRAM_STATE_READY) 00717 { 00718 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; 00719 } 00720 else 00721 { 00722 hsdram->hdma->XferCpltCallback = SDRAM_DMACpltProt; 00723 } 00724 hsdram->hdma->XferErrorCallback = SDRAM_DMAError; 00725 00726 /* Enable the DMA Stream */ 00727 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); 00728 00729 /* Process Unlocked */ 00730 __HAL_UNLOCK(hsdram); 00731 } 00732 else 00733 { 00734 status = HAL_ERROR; 00735 } 00736 00737 return status; 00738 } 00739 00740 /** 00741 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. 00742 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00743 * the configuration information for SDRAM module. 00744 * @param pAddress Pointer to write start address 00745 * @param pSrcBuffer Pointer to source buffer to write 00746 * @param BufferSize Size of the buffer to write to memory 00747 * @retval HAL status 00748 */ 00749 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, 00750 uint32_t BufferSize) 00751 { 00752 HAL_StatusTypeDef status; 00753 00754 /* Check the SDRAM controller state */ 00755 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 00756 { 00757 status = HAL_BUSY; 00758 } 00759 else if (hsdram->State == HAL_SDRAM_STATE_READY) 00760 { 00761 /* Process Locked */ 00762 __HAL_LOCK(hsdram); 00763 00764 /* Update the SDRAM controller state */ 00765 hsdram->State = HAL_SDRAM_STATE_BUSY; 00766 00767 /* Configure DMA user callbacks */ 00768 hsdram->hdma->XferCpltCallback = SDRAM_DMACplt; 00769 hsdram->hdma->XferErrorCallback = SDRAM_DMAError; 00770 00771 /* Enable the DMA Stream */ 00772 status = HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); 00773 00774 /* Process Unlocked */ 00775 __HAL_UNLOCK(hsdram); 00776 } 00777 else 00778 { 00779 status = HAL_ERROR; 00780 } 00781 00782 return status; 00783 } 00784 00785 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00786 /** 00787 * @brief Register a User SDRAM Callback 00788 * To be used instead of the weak (surcharged) predefined callback 00789 * @param hsdram : SDRAM handle 00790 * @param CallbackId : ID of the callback to be registered 00791 * This parameter can be one of the following values: 00792 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID 00793 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID 00794 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID 00795 * @param pCallback : pointer to the Callback function 00796 * @retval status 00797 */ 00798 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, 00799 pSDRAM_CallbackTypeDef pCallback) 00800 { 00801 HAL_StatusTypeDef status = HAL_OK; 00802 HAL_SDRAM_StateTypeDef state; 00803 00804 if (pCallback == NULL) 00805 { 00806 return HAL_ERROR; 00807 } 00808 00809 /* Process locked */ 00810 __HAL_LOCK(hsdram); 00811 00812 state = hsdram->State; 00813 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00814 { 00815 switch (CallbackId) 00816 { 00817 case HAL_SDRAM_MSP_INIT_CB_ID : 00818 hsdram->MspInitCallback = pCallback; 00819 break; 00820 case HAL_SDRAM_MSP_DEINIT_CB_ID : 00821 hsdram->MspDeInitCallback = pCallback; 00822 break; 00823 case HAL_SDRAM_REFRESH_ERR_CB_ID : 00824 hsdram->RefreshErrorCallback = pCallback; 00825 break; 00826 default : 00827 /* update return status */ 00828 status = HAL_ERROR; 00829 break; 00830 } 00831 } 00832 else if (hsdram->State == HAL_SDRAM_STATE_RESET) 00833 { 00834 switch (CallbackId) 00835 { 00836 case HAL_SDRAM_MSP_INIT_CB_ID : 00837 hsdram->MspInitCallback = pCallback; 00838 break; 00839 case HAL_SDRAM_MSP_DEINIT_CB_ID : 00840 hsdram->MspDeInitCallback = pCallback; 00841 break; 00842 default : 00843 /* update return status */ 00844 status = HAL_ERROR; 00845 break; 00846 } 00847 } 00848 else 00849 { 00850 /* update return status */ 00851 status = HAL_ERROR; 00852 } 00853 00854 /* Release Lock */ 00855 __HAL_UNLOCK(hsdram); 00856 return status; 00857 } 00858 00859 /** 00860 * @brief Unregister a User SDRAM Callback 00861 * SDRAM Callback is redirected to the weak (surcharged) predefined callback 00862 * @param hsdram : SDRAM handle 00863 * @param CallbackId : ID of the callback to be unregistered 00864 * This parameter can be one of the following values: 00865 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID 00866 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID 00867 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID 00868 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID 00869 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID 00870 * @retval status 00871 */ 00872 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) 00873 { 00874 HAL_StatusTypeDef status = HAL_OK; 00875 HAL_SDRAM_StateTypeDef state; 00876 00877 /* Process locked */ 00878 __HAL_LOCK(hsdram); 00879 00880 state = hsdram->State; 00881 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00882 { 00883 switch (CallbackId) 00884 { 00885 case HAL_SDRAM_MSP_INIT_CB_ID : 00886 hsdram->MspInitCallback = HAL_SDRAM_MspInit; 00887 break; 00888 case HAL_SDRAM_MSP_DEINIT_CB_ID : 00889 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; 00890 break; 00891 case HAL_SDRAM_REFRESH_ERR_CB_ID : 00892 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; 00893 break; 00894 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : 00895 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; 00896 break; 00897 case HAL_SDRAM_DMA_XFER_ERR_CB_ID : 00898 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; 00899 break; 00900 default : 00901 /* update return status */ 00902 status = HAL_ERROR; 00903 break; 00904 } 00905 } 00906 else if (hsdram->State == HAL_SDRAM_STATE_RESET) 00907 { 00908 switch (CallbackId) 00909 { 00910 case HAL_SDRAM_MSP_INIT_CB_ID : 00911 hsdram->MspInitCallback = HAL_SDRAM_MspInit; 00912 break; 00913 case HAL_SDRAM_MSP_DEINIT_CB_ID : 00914 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; 00915 break; 00916 default : 00917 /* update return status */ 00918 status = HAL_ERROR; 00919 break; 00920 } 00921 } 00922 else 00923 { 00924 /* update return status */ 00925 status = HAL_ERROR; 00926 } 00927 00928 /* Release Lock */ 00929 __HAL_UNLOCK(hsdram); 00930 return status; 00931 } 00932 00933 /** 00934 * @brief Register a User SDRAM Callback for DMA transfers 00935 * To be used instead of the weak (surcharged) predefined callback 00936 * @param hsdram : SDRAM handle 00937 * @param CallbackId : ID of the callback to be registered 00938 * This parameter can be one of the following values: 00939 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID 00940 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID 00941 * @param pCallback : pointer to the Callback function 00942 * @retval status 00943 */ 00944 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, 00945 pSDRAM_DmaCallbackTypeDef pCallback) 00946 { 00947 HAL_StatusTypeDef status = HAL_OK; 00948 HAL_SDRAM_StateTypeDef state; 00949 00950 if (pCallback == NULL) 00951 { 00952 return HAL_ERROR; 00953 } 00954 00955 /* Process locked */ 00956 __HAL_LOCK(hsdram); 00957 00958 state = hsdram->State; 00959 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00960 { 00961 switch (CallbackId) 00962 { 00963 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : 00964 hsdram->DmaXferCpltCallback = pCallback; 00965 break; 00966 case HAL_SDRAM_DMA_XFER_ERR_CB_ID : 00967 hsdram->DmaXferErrorCallback = pCallback; 00968 break; 00969 default : 00970 /* update return status */ 00971 status = HAL_ERROR; 00972 break; 00973 } 00974 } 00975 else 00976 { 00977 /* update return status */ 00978 status = HAL_ERROR; 00979 } 00980 00981 /* Release Lock */ 00982 __HAL_UNLOCK(hsdram); 00983 return status; 00984 } 00985 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00986 00987 /** 00988 * @} 00989 */ 00990 00991 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions 00992 * @brief management functions 00993 * 00994 @verbatim 00995 ============================================================================== 00996 ##### SDRAM Control functions ##### 00997 ============================================================================== 00998 [..] 00999 This subsection provides a set of functions allowing to control dynamically 01000 the SDRAM interface. 01001 01002 @endverbatim 01003 * @{ 01004 */ 01005 01006 /** 01007 * @brief Enables dynamically SDRAM write protection. 01008 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01009 * the configuration information for SDRAM module. 01010 * @retval HAL status 01011 */ 01012 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) 01013 { 01014 /* Check the SDRAM controller state */ 01015 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 01016 { 01017 return HAL_BUSY; 01018 } 01019 else if (hsdram->State == HAL_SDRAM_STATE_READY) 01020 { 01021 /* Update the SDRAM state */ 01022 hsdram->State = HAL_SDRAM_STATE_BUSY; 01023 01024 /* Enable write protection */ 01025 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); 01026 01027 /* Update the SDRAM state */ 01028 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; 01029 } 01030 else 01031 { 01032 return HAL_ERROR; 01033 } 01034 01035 return HAL_OK; 01036 } 01037 01038 /** 01039 * @brief Disables dynamically SDRAM write protection. 01040 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01041 * the configuration information for SDRAM module. 01042 * @retval HAL status 01043 */ 01044 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) 01045 { 01046 HAL_SDRAM_StateTypeDef state = hsdram->State; 01047 01048 /* Check the SDRAM controller state */ 01049 if (state == HAL_SDRAM_STATE_BUSY) 01050 { 01051 return HAL_BUSY; 01052 } 01053 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED) 01054 { 01055 /* Update the SDRAM state */ 01056 hsdram->State = HAL_SDRAM_STATE_BUSY; 01057 01058 /* Disable write protection */ 01059 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); 01060 01061 /* Update the SDRAM state */ 01062 hsdram->State = HAL_SDRAM_STATE_READY; 01063 } 01064 else 01065 { 01066 return HAL_ERROR; 01067 } 01068 01069 return HAL_OK; 01070 } 01071 01072 /** 01073 * @brief Sends Command to the SDRAM bank. 01074 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01075 * the configuration information for SDRAM module. 01076 * @param Command SDRAM command structure 01077 * @param Timeout Timeout duration 01078 * @retval HAL status 01079 */ 01080 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, 01081 uint32_t Timeout) 01082 { 01083 HAL_SDRAM_StateTypeDef state = hsdram->State; 01084 01085 /* Check the SDRAM controller state */ 01086 if (state == HAL_SDRAM_STATE_BUSY) 01087 { 01088 return HAL_BUSY; 01089 } 01090 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) 01091 { 01092 /* Update the SDRAM state */ 01093 hsdram->State = HAL_SDRAM_STATE_BUSY; 01094 01095 /* Send SDRAM command */ 01096 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); 01097 01098 /* Update the SDRAM controller state state */ 01099 if (Command->CommandMode == FMC_SDRAM_CMD_PALL) 01100 { 01101 hsdram->State = HAL_SDRAM_STATE_PRECHARGED; 01102 } 01103 else 01104 { 01105 hsdram->State = HAL_SDRAM_STATE_READY; 01106 } 01107 } 01108 else 01109 { 01110 return HAL_ERROR; 01111 } 01112 01113 return HAL_OK; 01114 } 01115 01116 /** 01117 * @brief Programs the SDRAM Memory Refresh rate. 01118 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01119 * the configuration information for SDRAM module. 01120 * @param RefreshRate The SDRAM refresh rate value 01121 * @retval HAL status 01122 */ 01123 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) 01124 { 01125 /* Check the SDRAM controller state */ 01126 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 01127 { 01128 return HAL_BUSY; 01129 } 01130 else if (hsdram->State == HAL_SDRAM_STATE_READY) 01131 { 01132 /* Update the SDRAM state */ 01133 hsdram->State = HAL_SDRAM_STATE_BUSY; 01134 01135 /* Program the refresh rate */ 01136 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); 01137 01138 /* Update the SDRAM state */ 01139 hsdram->State = HAL_SDRAM_STATE_READY; 01140 } 01141 else 01142 { 01143 return HAL_ERROR; 01144 } 01145 01146 return HAL_OK; 01147 } 01148 01149 /** 01150 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. 01151 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01152 * the configuration information for SDRAM module. 01153 * @param AutoRefreshNumber The SDRAM auto Refresh number 01154 * @retval HAL status 01155 */ 01156 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) 01157 { 01158 /* Check the SDRAM controller state */ 01159 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 01160 { 01161 return HAL_BUSY; 01162 } 01163 else if (hsdram->State == HAL_SDRAM_STATE_READY) 01164 { 01165 /* Update the SDRAM state */ 01166 hsdram->State = HAL_SDRAM_STATE_BUSY; 01167 01168 /* Set the Auto-Refresh number */ 01169 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber); 01170 01171 /* Update the SDRAM state */ 01172 hsdram->State = HAL_SDRAM_STATE_READY; 01173 } 01174 else 01175 { 01176 return HAL_ERROR; 01177 } 01178 01179 return HAL_OK; 01180 } 01181 01182 /** 01183 * @brief Returns the SDRAM memory current mode. 01184 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01185 * the configuration information for SDRAM module. 01186 * @retval The SDRAM memory mode. 01187 */ 01188 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) 01189 { 01190 /* Return the SDRAM memory current mode */ 01191 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); 01192 } 01193 01194 /** 01195 * @} 01196 */ 01197 01198 /** @defgroup SDRAM_Exported_Functions_Group4 State functions 01199 * @brief Peripheral State functions 01200 * 01201 @verbatim 01202 ============================================================================== 01203 ##### SDRAM State functions ##### 01204 ============================================================================== 01205 [..] 01206 This subsection permits to get in run-time the status of the SDRAM controller 01207 and the data flow. 01208 01209 @endverbatim 01210 * @{ 01211 */ 01212 01213 /** 01214 * @brief Returns the SDRAM state. 01215 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01216 * the configuration information for SDRAM module. 01217 * @retval HAL state 01218 */ 01219 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) 01220 { 01221 return hsdram->State; 01222 } 01223 01224 /** 01225 * @} 01226 */ 01227 01228 /** 01229 * @} 01230 */ 01231 01232 /** 01233 * @brief DMA SDRAM process complete callback. 01234 * @param hdma : DMA handle 01235 * @retval None 01236 */ 01237 static void SDRAM_DMACplt(DMA_HandleTypeDef *hdma) 01238 { 01239 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); 01240 01241 /* Disable the DMA channel */ 01242 __HAL_DMA_DISABLE(hdma); 01243 01244 /* Update the SDRAM controller state */ 01245 hsdram->State = HAL_SDRAM_STATE_READY; 01246 01247 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 01248 hsdram->DmaXferCpltCallback(hdma); 01249 #else 01250 HAL_SDRAM_DMA_XferCpltCallback(hdma); 01251 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 01252 } 01253 01254 /** 01255 * @brief DMA SRAM process complete callback. 01256 * @param hdma : DMA handle 01257 * @retval None 01258 */ 01259 static void SDRAM_DMACpltProt(DMA_HandleTypeDef *hdma) 01260 { 01261 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); 01262 01263 /* Disable the DMA channel */ 01264 __HAL_DMA_DISABLE(hdma); 01265 01266 /* Update the SDRAM controller state */ 01267 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; 01268 01269 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 01270 hsdram->DmaXferCpltCallback(hdma); 01271 #else 01272 HAL_SDRAM_DMA_XferCpltCallback(hdma); 01273 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 01274 } 01275 01276 /** 01277 * @brief DMA SDRAM error callback. 01278 * @param hdma : DMA handle 01279 * @retval None 01280 */ 01281 static void SDRAM_DMAError(DMA_HandleTypeDef *hdma) 01282 { 01283 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hdma->Parent); 01284 01285 /* Disable the DMA channel */ 01286 __HAL_DMA_DISABLE(hdma); 01287 01288 /* Update the SDRAM controller state */ 01289 hsdram->State = HAL_SDRAM_STATE_ERROR; 01290 01291 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 01292 hsdram->DmaXferErrorCallback(hdma); 01293 #else 01294 HAL_SDRAM_DMA_XferErrorCallback(hdma); 01295 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 01296 } 01297 01298 /** 01299 * @} 01300 */ 01301 01302 #endif /* HAL_SDRAM_MODULE_ENABLED */ 01303 01304 /** 01305 * @} 01306 */ 01307 01308 #endif /* FMC_Bank5_6 */ 01309 01310 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/