STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_sdram.h 00004 * @author MCD Application Team 00005 * @brief Header file of SDRAM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32F4xx_HAL_SDRAM_H 00022 #define STM32F4xx_HAL_SDRAM_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 #if defined(FMC_Bank5_6) 00029 00030 /* Includes ------------------------------------------------------------------*/ 00031 #include "stm32f4xx_ll_fmc.h" 00032 00033 /** @addtogroup STM32F4xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup SDRAM 00038 * @{ 00039 */ 00040 00041 /* Exported typedef ----------------------------------------------------------*/ 00042 00043 /** @defgroup SDRAM_Exported_Types SDRAM Exported Types 00044 * @{ 00045 */ 00046 00047 /** 00048 * @brief HAL SDRAM State structure definition 00049 */ 00050 typedef enum 00051 { 00052 HAL_SDRAM_STATE_RESET = 0x00U, /*!< SDRAM not yet initialized or disabled */ 00053 HAL_SDRAM_STATE_READY = 0x01U, /*!< SDRAM initialized and ready for use */ 00054 HAL_SDRAM_STATE_BUSY = 0x02U, /*!< SDRAM internal process is ongoing */ 00055 HAL_SDRAM_STATE_ERROR = 0x03U, /*!< SDRAM error state */ 00056 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04U, /*!< SDRAM device write protected */ 00057 HAL_SDRAM_STATE_PRECHARGED = 0x05U /*!< SDRAM device precharged */ 00058 00059 } HAL_SDRAM_StateTypeDef; 00060 00061 /** 00062 * @brief SDRAM handle Structure definition 00063 */ 00064 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00065 typedef struct __SDRAM_HandleTypeDef 00066 #else 00067 typedef struct 00068 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00069 { 00070 FMC_SDRAM_TypeDef *Instance; /*!< Register base address */ 00071 00072 FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */ 00073 00074 __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */ 00075 00076 HAL_LockTypeDef Lock; /*!< SDRAM locking object */ 00077 00078 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ 00079 00080 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00081 void (* MspInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp Init callback */ 00082 void (* MspDeInitCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Msp DeInit callback */ 00083 void (* RefreshErrorCallback)(struct __SDRAM_HandleTypeDef *hsdram); /*!< SDRAM Refresh Error callback */ 00084 void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Complete callback */ 00085 void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma); /*!< SDRAM DMA Xfer Error callback */ 00086 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00087 } SDRAM_HandleTypeDef; 00088 00089 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00090 /** 00091 * @brief HAL SDRAM Callback ID enumeration definition 00092 */ 00093 typedef enum 00094 { 00095 HAL_SDRAM_MSP_INIT_CB_ID = 0x00U, /*!< SDRAM MspInit Callback ID */ 00096 HAL_SDRAM_MSP_DEINIT_CB_ID = 0x01U, /*!< SDRAM MspDeInit Callback ID */ 00097 HAL_SDRAM_REFRESH_ERR_CB_ID = 0x02U, /*!< SDRAM Refresh Error Callback ID */ 00098 HAL_SDRAM_DMA_XFER_CPLT_CB_ID = 0x03U, /*!< SDRAM DMA Xfer Complete Callback ID */ 00099 HAL_SDRAM_DMA_XFER_ERR_CB_ID = 0x04U /*!< SDRAM DMA Xfer Error Callback ID */ 00100 } HAL_SDRAM_CallbackIDTypeDef; 00101 00102 /** 00103 * @brief HAL SDRAM Callback pointer definition 00104 */ 00105 typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram); 00106 typedef void (*pSDRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma); 00107 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00108 /** 00109 * @} 00110 */ 00111 00112 /* Exported constants --------------------------------------------------------*/ 00113 /* Exported macro ------------------------------------------------------------*/ 00114 00115 /** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros 00116 * @{ 00117 */ 00118 00119 /** @brief Reset SDRAM handle state 00120 * @param __HANDLE__ specifies the SDRAM handle. 00121 * @retval None 00122 */ 00123 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00124 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) do { \ 00125 (__HANDLE__)->State = HAL_SDRAM_STATE_RESET; \ 00126 (__HANDLE__)->MspInitCallback = NULL; \ 00127 (__HANDLE__)->MspDeInitCallback = NULL; \ 00128 } while(0) 00129 #else 00130 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET) 00131 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00132 /** 00133 * @} 00134 */ 00135 00136 /* Exported functions --------------------------------------------------------*/ 00137 00138 /** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions 00139 * @{ 00140 */ 00141 00142 /** @addtogroup SDRAM_Exported_Functions_Group1 00143 * @{ 00144 */ 00145 00146 /* Initialization/de-initialization functions *********************************/ 00147 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing); 00148 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram); 00149 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram); 00150 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram); 00151 00152 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram); 00153 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram); 00154 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); 00155 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); 00156 00157 /** 00158 * @} 00159 */ 00160 00161 /** @addtogroup SDRAM_Exported_Functions_Group2 00162 * @{ 00163 */ 00164 /* I/O operation functions ****************************************************/ 00165 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, 00166 uint32_t BufferSize); 00167 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, 00168 uint32_t BufferSize); 00169 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, 00170 uint32_t BufferSize); 00171 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, 00172 uint32_t BufferSize); 00173 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, 00174 uint32_t BufferSize); 00175 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, 00176 uint32_t BufferSize); 00177 00178 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, 00179 uint32_t BufferSize); 00180 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, 00181 uint32_t BufferSize); 00182 00183 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00184 /* SDRAM callback registering/unregistering */ 00185 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, 00186 pSDRAM_CallbackTypeDef pCallback); 00187 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId); 00188 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, 00189 pSDRAM_DmaCallbackTypeDef pCallback); 00190 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00191 00192 /** 00193 * @} 00194 */ 00195 00196 /** @addtogroup SDRAM_Exported_Functions_Group3 00197 * @{ 00198 */ 00199 /* SDRAM Control functions *****************************************************/ 00200 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram); 00201 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram); 00202 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, 00203 uint32_t Timeout); 00204 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate); 00205 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber); 00206 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram); 00207 00208 /** 00209 * @} 00210 */ 00211 00212 /** @addtogroup SDRAM_Exported_Functions_Group4 00213 * @{ 00214 */ 00215 /* SDRAM State functions ********************************************************/ 00216 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram); 00217 /** 00218 * @} 00219 */ 00220 00221 /** 00222 * @} 00223 */ 00224 00225 /** 00226 * @} 00227 */ 00228 00229 /** 00230 * @} 00231 */ 00232 00233 #endif /* FMC_Bank5_6 */ 00234 00235 #ifdef __cplusplus 00236 } 00237 #endif 00238 00239 #endif /* STM32F4xx_HAL_SDRAM_H */ 00240 00241 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/