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STM32F479xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_rcc.h 00004 * @author MCD Application Team 00005 * @brief Header file of RCC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved.</center></h2> 00011 * 00012 * This software component is licensed by ST under BSD 3-Clause license, 00013 * the "License"; You may not use this file except in compliance with the 00014 * License. You may obtain a copy of the License at: 00015 * opensource.org/licenses/BSD-3-Clause 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef __STM32F4xx_LL_RCC_H 00022 #define __STM32F4xx_LL_RCC_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32f4xx.h" 00030 00031 /** @addtogroup STM32F4xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined(RCC) 00036 00037 /** @defgroup RCC_LL RCC 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 /** @defgroup RCC_LL_Private_Variables RCC Private Variables 00044 * @{ 00045 */ 00046 00047 #if defined(RCC_DCKCFGR_PLLSAIDIVR) 00048 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16}; 00049 #endif /* RCC_DCKCFGR_PLLSAIDIVR */ 00050 00051 /** 00052 * @} 00053 */ 00054 /* Private constants ---------------------------------------------------------*/ 00055 /* Private macros ------------------------------------------------------------*/ 00056 #if defined(USE_FULL_LL_DRIVER) 00057 /** @defgroup RCC_LL_Private_Macros RCC Private Macros 00058 * @{ 00059 */ 00060 /** 00061 * @} 00062 */ 00063 #endif /*USE_FULL_LL_DRIVER*/ 00064 /* Exported types ------------------------------------------------------------*/ 00065 #if defined(USE_FULL_LL_DRIVER) 00066 /** @defgroup RCC_LL_Exported_Types RCC Exported Types 00067 * @{ 00068 */ 00069 00070 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure 00071 * @{ 00072 */ 00073 00074 /** 00075 * @brief RCC Clocks Frequency Structure 00076 */ 00077 typedef struct 00078 { 00079 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ 00080 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ 00081 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ 00082 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ 00083 } LL_RCC_ClocksTypeDef; 00084 00085 /** 00086 * @} 00087 */ 00088 00089 /** 00090 * @} 00091 */ 00092 #endif /* USE_FULL_LL_DRIVER */ 00093 00094 /* Exported constants --------------------------------------------------------*/ 00095 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants 00096 * @{ 00097 */ 00098 00099 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation 00100 * @brief Defines used to adapt values of different oscillators 00101 * @note These values could be modified in the user environment according to 00102 * HW set-up. 00103 * @{ 00104 */ 00105 #if !defined (HSE_VALUE) 00106 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */ 00107 #endif /* HSE_VALUE */ 00108 00109 #if !defined (HSI_VALUE) 00110 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ 00111 #endif /* HSI_VALUE */ 00112 00113 #if !defined (LSE_VALUE) 00114 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ 00115 #endif /* LSE_VALUE */ 00116 00117 #if !defined (LSI_VALUE) 00118 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ 00119 #endif /* LSI_VALUE */ 00120 00121 #if !defined (EXTERNAL_CLOCK_VALUE) 00122 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */ 00123 #endif /* EXTERNAL_CLOCK_VALUE */ 00124 /** 00125 * @} 00126 */ 00127 00128 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines 00129 * @brief Flags defines which can be used with LL_RCC_WriteReg function 00130 * @{ 00131 */ 00132 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */ 00133 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */ 00134 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */ 00135 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */ 00136 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */ 00137 #if defined(RCC_PLLI2S_SUPPORT) 00138 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */ 00139 #endif /* RCC_PLLI2S_SUPPORT */ 00140 #if defined(RCC_PLLSAI_SUPPORT) 00141 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */ 00142 #endif /* RCC_PLLSAI_SUPPORT */ 00143 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */ 00144 /** 00145 * @} 00146 */ 00147 00148 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines 00149 * @brief Flags defines which can be used with LL_RCC_ReadReg function 00150 * @{ 00151 */ 00152 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */ 00153 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */ 00154 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */ 00155 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */ 00156 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */ 00157 #if defined(RCC_PLLI2S_SUPPORT) 00158 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */ 00159 #endif /* RCC_PLLI2S_SUPPORT */ 00160 #if defined(RCC_PLLSAI_SUPPORT) 00161 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */ 00162 #endif /* RCC_PLLSAI_SUPPORT */ 00163 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */ 00164 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */ 00165 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ 00166 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */ 00167 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ 00168 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ 00169 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ 00170 #if defined(RCC_CSR_BORRSTF) 00171 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */ 00172 #endif /* RCC_CSR_BORRSTF */ 00173 /** 00174 * @} 00175 */ 00176 00177 /** @defgroup RCC_LL_EC_IT IT Defines 00178 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions 00179 * @{ 00180 */ 00181 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */ 00182 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */ 00183 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */ 00184 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */ 00185 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */ 00186 #if defined(RCC_PLLI2S_SUPPORT) 00187 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */ 00188 #endif /* RCC_PLLI2S_SUPPORT */ 00189 #if defined(RCC_PLLSAI_SUPPORT) 00190 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */ 00191 #endif /* RCC_PLLSAI_SUPPORT */ 00192 /** 00193 * @} 00194 */ 00195 00196 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch 00197 * @{ 00198 */ 00199 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */ 00200 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */ 00201 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */ 00202 #if defined(RCC_CFGR_SW_PLLR) 00203 #define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR /*!< PLLR selection as system clock */ 00204 #endif /* RCC_CFGR_SW_PLLR */ 00205 /** 00206 * @} 00207 */ 00208 00209 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status 00210 * @{ 00211 */ 00212 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ 00213 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ 00214 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ 00215 #if defined(RCC_PLLR_SYSCLK_SUPPORT) 00216 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR /*!< PLLR used as system clock */ 00217 #endif /* RCC_PLLR_SYSCLK_SUPPORT */ 00218 /** 00219 * @} 00220 */ 00221 00222 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler 00223 * @{ 00224 */ 00225 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ 00226 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ 00227 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ 00228 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ 00229 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ 00230 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ 00231 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ 00232 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ 00233 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ 00234 /** 00235 * @} 00236 */ 00237 00238 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) 00239 * @{ 00240 */ 00241 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ 00242 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ 00243 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ 00244 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ 00245 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ 00246 /** 00247 * @} 00248 */ 00249 00250 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) 00251 * @{ 00252 */ 00253 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */ 00254 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */ 00255 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */ 00256 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */ 00257 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */ 00258 /** 00259 * @} 00260 */ 00261 00262 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection 00263 * @{ 00264 */ 00265 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */ 00266 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */ 00267 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */ 00268 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */ 00269 #if defined(RCC_CFGR_MCO2) 00270 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */ 00271 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */ 00272 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */ 00273 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */ 00274 #endif /* RCC_CFGR_MCO2 */ 00275 /** 00276 * @} 00277 */ 00278 00279 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler 00280 * @{ 00281 */ 00282 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */ 00283 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */ 00284 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */ 00285 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */ 00286 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */ 00287 #if defined(RCC_CFGR_MCO2PRE) 00288 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */ 00289 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */ 00290 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */ 00291 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */ 00292 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */ 00293 #endif /* RCC_CFGR_MCO2PRE */ 00294 /** 00295 * @} 00296 */ 00297 00298 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock 00299 * @{ 00300 */ 00301 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */ 00302 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */ 00303 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */ 00304 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */ 00305 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */ 00306 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */ 00307 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */ 00308 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */ 00309 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */ 00310 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */ 00311 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */ 00312 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */ 00313 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */ 00314 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */ 00315 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */ 00316 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */ 00317 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */ 00318 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */ 00319 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */ 00320 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */ 00321 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */ 00322 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */ 00323 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */ 00324 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */ 00325 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */ 00326 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */ 00327 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */ 00328 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */ 00329 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */ 00330 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */ 00331 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */ 00332 /** 00333 * @} 00334 */ 00335 00336 #if defined(USE_FULL_LL_DRIVER) 00337 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency 00338 * @{ 00339 */ 00340 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ 00341 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ 00342 /** 00343 * @} 00344 */ 00345 #endif /* USE_FULL_LL_DRIVER */ 00346 00347 #if defined(FMPI2C1) 00348 /** @defgroup RCC_LL_EC_FMPI2C1_CLKSOURCE Peripheral FMPI2C clock source selection 00349 * @{ 00350 */ 00351 #define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as FMPI2C1 clock source */ 00352 #define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0 /*!< SYSCLK clock used as FMPI2C1 clock source */ 00353 #define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1 /*!< HSI clock used as FMPI2C1 clock source */ 00354 /** 00355 * @} 00356 */ 00357 #endif /* FMPI2C1 */ 00358 00359 #if defined(LPTIM1) 00360 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection 00361 * @{ 00362 */ 00363 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */ 00364 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */ 00365 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */ 00366 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */ 00367 /** 00368 * @} 00369 */ 00370 #endif /* LPTIM1 */ 00371 00372 #if defined(SAI1) 00373 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection 00374 * @{ 00375 */ 00376 #if defined(RCC_DCKCFGR_SAI1SRC) 00377 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */ 00378 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 clock source */ 00379 #define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16)) /*!< PLL clock used as SAI1 clock source */ 00380 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16)) /*!< External pin clock used as SAI1 clock source */ 00381 #endif /* RCC_DCKCFGR_SAI1SRC */ 00382 #if defined(RCC_DCKCFGR_SAI2SRC) 00383 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */ 00384 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16)) /*!< PLLI2S clock used as SAI2 clock source */ 00385 #define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16)) /*!< PLL clock used as SAI2 clock source */ 00386 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16)) /*!< PLL Main clock used as SAI2 clock source */ 00387 #endif /* RCC_DCKCFGR_SAI2SRC */ 00388 #if defined(RCC_DCKCFGR_SAI1ASRC) 00389 #if defined(RCC_SAI1A_PLLSOURCE_SUPPORT) 00390 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block A clock source */ 00391 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< External pin used as SAI1 block A clock source */ 00392 #define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< PLL clock used as SAI1 block A clock source */ 00393 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16)) /*!< PLL Main clock used as SAI1 block A clock source */ 00394 #else 00395 #define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block A clock source */ 00396 #define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block A clock source */ 00397 #define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) /*!< External pin clock used as SAI1 block A clock source */ 00398 #endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */ 00399 #endif /* RCC_DCKCFGR_SAI1ASRC */ 00400 #if defined(RCC_DCKCFGR_SAI1BSRC) 00401 #if defined(RCC_SAI1B_PLLSOURCE_SUPPORT) 00402 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLI2S clock used as SAI1 block B clock source */ 00403 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< External pin used as SAI1 block B clock source */ 00404 #define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< PLL clock used as SAI1 block B clock source */ 00405 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16)) /*!< PLL Main clock used as SAI1 block B clock source */ 00406 #else 00407 #define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) /*!< PLLSAI clock used as SAI1 block B clock source */ 00408 #define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) /*!< PLLI2S clock used as SAI1 block B clock source */ 00409 #define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) /*!< External pin clock used as SAI1 block B clock source */ 00410 #endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */ 00411 #endif /* RCC_DCKCFGR_SAI1BSRC */ 00412 /** 00413 * @} 00414 */ 00415 #endif /* SAI1 */ 00416 00417 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) 00418 /** @defgroup RCC_LL_EC_SDIOx_CLKSOURCE Peripheral SDIO clock source selection 00419 * @{ 00420 */ 00421 #define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U /*!< PLL 48M domain clock used as SDIO clock */ 00422 #if defined(RCC_DCKCFGR_SDIOSEL) 00423 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL /*!< System clock clock used as SDIO clock */ 00424 #else 00425 #define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL /*!< System clock clock used as SDIO clock */ 00426 #endif /* RCC_DCKCFGR_SDIOSEL */ 00427 /** 00428 * @} 00429 */ 00430 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ 00431 00432 #if defined(DSI) 00433 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection 00434 * @{ 00435 */ 00436 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */ 00437 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL /*!< PLL clock used as DSI byte lane clock source */ 00438 /** 00439 * @} 00440 */ 00441 #endif /* DSI */ 00442 00443 #if defined(CEC) 00444 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection 00445 * @{ 00446 */ 00447 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U /*!< HSI oscillator clock divided by 488 used as CEC clock */ 00448 #define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL /*!< LSE oscillator clock used as CEC clock */ 00449 /** 00450 * @} 00451 */ 00452 #endif /* CEC */ 00453 00454 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection 00455 * @{ 00456 */ 00457 #if defined(RCC_CFGR_I2SSRC) 00458 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */ 00459 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */ 00460 #endif /* RCC_CFGR_I2SSRC */ 00461 #if defined(RCC_DCKCFGR_I2SSRC) 00462 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U) /*!< PLL clock used as I2S1 clock source */ 00463 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ 00464 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16)) /*!< PLL Main clock used as I2S1 clock source */ 00465 #endif /* RCC_DCKCFGR_I2SSRC */ 00466 #if defined(RCC_DCKCFGR_I2S1SRC) 00467 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U) /*!< PLLI2S clock used as I2S1 clock source */ 00468 #define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16)) /*!< External pin used as I2S1 clock source */ 00469 #define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16)) /*!< PLL clock used as I2S1 clock source */ 00470 #define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16)) /*!< PLL Main clock used as I2S1 clock source */ 00471 #endif /* RCC_DCKCFGR_I2S1SRC */ 00472 #if defined(RCC_DCKCFGR_I2S2SRC) 00473 #define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U) /*!< PLLI2S clock used as I2S2 clock source */ 00474 #define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16)) /*!< External pin used as I2S2 clock source */ 00475 #define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16)) /*!< PLL clock used as I2S2 clock source */ 00476 #define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16)) /*!< PLL Main clock used as I2S2 clock source */ 00477 #endif /* RCC_DCKCFGR_I2S2SRC */ 00478 /** 00479 * @} 00480 */ 00481 00482 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00483 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection 00484 * @{ 00485 */ 00486 #if defined(RCC_DCKCFGR_CK48MSEL) 00487 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ 00488 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ 00489 #endif /* RCC_DCKCFGR_CK48MSEL */ 00490 #if defined(RCC_DCKCFGR2_CK48MSEL) 00491 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */ 00492 #if defined(RCC_PLLSAI_SUPPORT) 00493 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */ 00494 #endif /* RCC_PLLSAI_SUPPORT */ 00495 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00496 #define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL /*!< PLLI2S oscillator clock used as 48Mhz domain clock */ 00497 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00498 #endif /* RCC_DCKCFGR2_CK48MSEL */ 00499 /** 00500 * @} 00501 */ 00502 00503 #if defined(RNG) 00504 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection 00505 * @{ 00506 */ 00507 #define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as RNG clock source */ 00508 #if defined(RCC_PLLSAI_SUPPORT) 00509 #define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as RNG clock source */ 00510 #endif /* RCC_PLLSAI_SUPPORT */ 00511 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00512 #define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as RNG clock source */ 00513 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00514 /** 00515 * @} 00516 */ 00517 #endif /* RNG */ 00518 00519 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 00520 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection 00521 * @{ 00522 */ 00523 #define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL /*!< PLL clock used as USB clock source */ 00524 #if defined(RCC_PLLSAI_SUPPORT) 00525 #define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI /*!< PLLSAI clock used as USB clock source */ 00526 #endif /* RCC_PLLSAI_SUPPORT */ 00527 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 00528 #define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S /*!< PLLI2S clock used as USB clock source */ 00529 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 00530 /** 00531 * @} 00532 */ 00533 #endif /* USB_OTG_FS || USB_OTG_HS */ 00534 00535 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00536 00537 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) 00538 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection 00539 * @{ 00540 */ 00541 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM1 Audio clock source */ 00542 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16)) /*!< I2S2 clock used as DFSDM1 Audio clock source */ 00543 #if defined(DFSDM2_Channel0) 00544 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U) /*!< I2S1 clock used as DFSDM2 Audio clock source */ 00545 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16)) /*!< I2S2 clock used as DFSDM2 Audio clock source */ 00546 #endif /* DFSDM2_Channel0 */ 00547 /** 00548 * @} 00549 */ 00550 00551 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection 00552 * @{ 00553 */ 00554 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */ 00555 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM1 clock */ 00556 #if defined(DFSDM2_Channel0) 00557 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM2 clock */ 00558 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL /*!< System clock used as DFSDM2 clock */ 00559 #endif /* DFSDM2_Channel0 */ 00560 /** 00561 * @} 00562 */ 00563 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ 00564 00565 #if defined(FMPI2C1) 00566 /** @defgroup RCC_LL_EC_FMPI2C1 Peripheral FMPI2C get clock source 00567 * @{ 00568 */ 00569 #define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL /*!< FMPI2C1 Clock source selection */ 00570 /** 00571 * @} 00572 */ 00573 #endif /* FMPI2C1 */ 00574 00575 #if defined(SPDIFRX) 00576 /** @defgroup RCC_LL_EC_SPDIFRX_CLKSOURCE Peripheral SPDIFRX clock source selection 00577 * @{ 00578 */ 00579 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as SPDIFRX clock source */ 00580 #define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL /*!< PLLI2S clock used as SPDIFRX clock source */ 00581 /** 00582 * @} 00583 */ 00584 #endif /* SPDIFRX */ 00585 00586 #if defined(LPTIM1) 00587 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source 00588 * @{ 00589 */ 00590 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */ 00591 /** 00592 * @} 00593 */ 00594 #endif /* LPTIM1 */ 00595 00596 #if defined(SAI1) 00597 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source 00598 * @{ 00599 */ 00600 #if defined(RCC_DCKCFGR_SAI1ASRC) 00601 #define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC /*!< SAI1 block A Clock source selection */ 00602 #endif /* RCC_DCKCFGR_SAI1ASRC */ 00603 #if defined(RCC_DCKCFGR_SAI1BSRC) 00604 #define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC /*!< SAI1 block B Clock source selection */ 00605 #endif /* RCC_DCKCFGR_SAI1BSRC */ 00606 #if defined(RCC_DCKCFGR_SAI1SRC) 00607 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC /*!< SAI1 Clock source selection */ 00608 #endif /* RCC_DCKCFGR_SAI1SRC */ 00609 #if defined(RCC_DCKCFGR_SAI2SRC) 00610 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC /*!< SAI2 Clock source selection */ 00611 #endif /* RCC_DCKCFGR_SAI2SRC */ 00612 /** 00613 * @} 00614 */ 00615 #endif /* SAI1 */ 00616 00617 #if defined(SDIO) 00618 /** @defgroup RCC_LL_EC_SDIOx Peripheral SDIO get clock source 00619 * @{ 00620 */ 00621 #if defined(RCC_DCKCFGR_SDIOSEL) 00622 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL /*!< SDIO Clock source selection */ 00623 #elif defined(RCC_DCKCFGR2_SDIOSEL) 00624 #define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL /*!< SDIO Clock source selection */ 00625 #else 00626 #define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< SDIO Clock source selection */ 00627 #endif 00628 /** 00629 * @} 00630 */ 00631 #endif /* SDIO */ 00632 00633 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00634 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source 00635 * @{ 00636 */ 00637 #if defined(RCC_DCKCFGR_CK48MSEL) 00638 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL /*!< CK48M Domain clock source selection */ 00639 #endif /* RCC_DCKCFGR_CK48MSEL */ 00640 #if defined(RCC_DCKCFGR2_CK48MSEL) 00641 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */ 00642 #endif /* RCC_DCKCFGR_CK48MSEL */ 00643 /** 00644 * @} 00645 */ 00646 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00647 00648 #if defined(RNG) 00649 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source 00650 * @{ 00651 */ 00652 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00653 #define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< RNG Clock source selection */ 00654 #else 00655 #define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< RNG Clock source selection */ 00656 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00657 /** 00658 * @} 00659 */ 00660 #endif /* RNG */ 00661 00662 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 00663 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source 00664 * @{ 00665 */ 00666 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 00667 #define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE /*!< USB Clock source selection */ 00668 #else 00669 #define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ /*!< USB Clock source selection */ 00670 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 00671 /** 00672 * @} 00673 */ 00674 #endif /* USB_OTG_FS || USB_OTG_HS */ 00675 00676 #if defined(CEC) 00677 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source 00678 * @{ 00679 */ 00680 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */ 00681 /** 00682 * @} 00683 */ 00684 #endif /* CEC */ 00685 00686 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source 00687 * @{ 00688 */ 00689 #if defined(RCC_CFGR_I2SSRC) 00690 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S1 Clock source selection */ 00691 #endif /* RCC_CFGR_I2SSRC */ 00692 #if defined(RCC_DCKCFGR_I2SSRC) 00693 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC /*!< I2S1 Clock source selection */ 00694 #endif /* RCC_DCKCFGR_I2SSRC */ 00695 #if defined(RCC_DCKCFGR_I2S1SRC) 00696 #define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC /*!< I2S1 Clock source selection */ 00697 #endif /* RCC_DCKCFGR_I2S1SRC */ 00698 #if defined(RCC_DCKCFGR_I2S2SRC) 00699 #define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC /*!< I2S2 Clock source selection */ 00700 #endif /* RCC_DCKCFGR_I2S2SRC */ 00701 /** 00702 * @} 00703 */ 00704 00705 #if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0) 00706 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source 00707 * @{ 00708 */ 00709 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL /*!< DFSDM1 Audio Clock source selection */ 00710 #if defined(DFSDM2_Channel0) 00711 #define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL /*!< DFSDM2 Audio Clock source selection */ 00712 #endif /* DFSDM2_Channel0 */ 00713 /** 00714 * @} 00715 */ 00716 00717 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source 00718 * @{ 00719 */ 00720 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM1 Clock source selection */ 00721 #if defined(DFSDM2_Channel0) 00722 #define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL /*!< DFSDM2 Clock source selection */ 00723 #endif /* DFSDM2_Channel0 */ 00724 /** 00725 * @} 00726 */ 00727 #endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */ 00728 00729 #if defined(SPDIFRX) 00730 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source 00731 * @{ 00732 */ 00733 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL /*!< SPDIFRX Clock source selection */ 00734 /** 00735 * @} 00736 */ 00737 #endif /* SPDIFRX */ 00738 00739 #if defined(DSI) 00740 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source 00741 * @{ 00742 */ 00743 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL /*!< DSI Clock source selection */ 00744 /** 00745 * @} 00746 */ 00747 #endif /* DSI */ 00748 00749 #if defined(LTDC) 00750 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source 00751 * @{ 00752 */ 00753 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR /*!< LTDC Clock source selection */ 00754 /** 00755 * @} 00756 */ 00757 #endif /* LTDC */ 00758 00759 00760 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection 00761 * @{ 00762 */ 00763 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ 00764 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ 00765 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ 00766 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */ 00767 /** 00768 * @} 00769 */ 00770 00771 #if defined(RCC_DCKCFGR_TIMPRE) 00772 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection 00773 * @{ 00774 */ 00775 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */ 00776 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE /*!< Timers clock to four time PCLK */ 00777 /** 00778 * @} 00779 */ 00780 #endif /* RCC_DCKCFGR_TIMPRE */ 00781 00782 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source 00783 * @{ 00784 */ 00785 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */ 00786 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ 00787 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) 00788 #define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U) /*!< I2S External pin input clock selected as PLLI2S entry clock source */ 00789 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ 00790 /** 00791 * @} 00792 */ 00793 00794 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor 00795 * @{ 00796 */ 00797 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */ 00798 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */ 00799 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */ 00800 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */ 00801 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */ 00802 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */ 00803 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */ 00804 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */ 00805 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */ 00806 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */ 00807 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */ 00808 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */ 00809 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */ 00810 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */ 00811 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */ 00812 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */ 00813 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */ 00814 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */ 00815 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */ 00816 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */ 00817 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */ 00818 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */ 00819 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */ 00820 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */ 00821 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */ 00822 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */ 00823 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */ 00824 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */ 00825 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */ 00826 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */ 00827 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */ 00828 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */ 00829 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */ 00830 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */ 00831 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */ 00832 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */ 00833 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */ 00834 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */ 00835 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */ 00836 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */ 00837 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */ 00838 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */ 00839 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */ 00840 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */ 00841 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */ 00842 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */ 00843 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */ 00844 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */ 00845 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */ 00846 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */ 00847 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */ 00848 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */ 00849 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */ 00850 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */ 00851 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */ 00852 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */ 00853 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */ 00854 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */ 00855 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */ 00856 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */ 00857 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */ 00858 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */ 00859 /** 00860 * @} 00861 */ 00862 00863 #if defined(RCC_PLLCFGR_PLLR) 00864 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR) 00865 * @{ 00866 */ 00867 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */ 00868 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */ 00869 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */ 00870 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */ 00871 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */ 00872 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */ 00873 /** 00874 * @} 00875 */ 00876 #endif /* RCC_PLLCFGR_PLLR */ 00877 00878 #if defined(RCC_DCKCFGR_PLLDIVR) 00879 /** @defgroup RCC_LL_EC_PLLDIVR PLLDIVR division factor (PLLDIVR) 00880 * @{ 00881 */ 00882 #define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 1 */ 00883 #define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 2 */ 00884 #define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 3 */ 00885 #define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 4 */ 00886 #define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 5 */ 00887 #define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 6 */ 00888 #define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 7 */ 00889 #define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 8 */ 00890 #define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 9 */ 00891 #define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 10 */ 00892 #define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 11 */ 00893 #define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 12 */ 00894 #define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 13 */ 00895 #define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 14 */ 00896 #define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 15 */ 00897 #define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4) /*!< PLL division factor for PLLDIVR output by 16 */ 00898 #define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 17 */ 00899 #define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 18 */ 00900 #define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 19 */ 00901 #define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 20 */ 00902 #define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 21 */ 00903 #define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 22 */ 00904 #define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 23 */ 00905 #define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3) /*!< PLL division factor for PLLDIVR output by 24 */ 00906 #define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 25 */ 00907 #define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 26 */ 00908 #define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 27 */ 00909 #define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2) /*!< PLL division factor for PLLDIVR output by 28 */ 00910 #define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 29 */ 00911 #define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1) /*!< PLL division factor for PLLDIVR output by 30 */ 00912 #define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0) /*!< PLL division factor for PLLDIVR output by 31 */ 00913 /** 00914 * @} 00915 */ 00916 #endif /* RCC_DCKCFGR_PLLDIVR */ 00917 00918 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP) 00919 * @{ 00920 */ 00921 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */ 00922 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */ 00923 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */ 00924 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */ 00925 /** 00926 * @} 00927 */ 00928 00929 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ) 00930 * @{ 00931 */ 00932 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */ 00933 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */ 00934 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */ 00935 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */ 00936 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */ 00937 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */ 00938 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */ 00939 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */ 00940 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */ 00941 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */ 00942 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */ 00943 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */ 00944 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */ 00945 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */ 00946 /** 00947 * @} 00948 */ 00949 00950 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection 00951 * @{ 00952 */ 00953 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */ 00954 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */ 00955 /** 00956 * @} 00957 */ 00958 00959 #if defined(RCC_PLLI2S_SUPPORT) 00960 /** @defgroup RCC_LL_EC_PLLI2SM PLLI2SM division factor (PLLI2SM) 00961 * @{ 00962 */ 00963 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 00964 #define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 2 */ 00965 #define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 3 */ 00966 #define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 4 */ 00967 #define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 5 */ 00968 #define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 6 */ 00969 #define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 7 */ 00970 #define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 8 */ 00971 #define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 9 */ 00972 #define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 10 */ 00973 #define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 11 */ 00974 #define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 12 */ 00975 #define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 13 */ 00976 #define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 14 */ 00977 #define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 15 */ 00978 #define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 16 */ 00979 #define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 17 */ 00980 #define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 18 */ 00981 #define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 19 */ 00982 #define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 20 */ 00983 #define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 21 */ 00984 #define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 22 */ 00985 #define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 23 */ 00986 #define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 24 */ 00987 #define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 25 */ 00988 #define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 26 */ 00989 #define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 27 */ 00990 #define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 28 */ 00991 #define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 29 */ 00992 #define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 30 */ 00993 #define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 31 */ 00994 #define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5) /*!< PLLI2S division factor for PLLI2SM output by 32 */ 00995 #define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 33 */ 00996 #define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 34 */ 00997 #define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 35 */ 00998 #define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 36 */ 00999 #define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 37 */ 01000 #define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 38 */ 01001 #define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 39 */ 01002 #define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 40 */ 01003 #define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 41 */ 01004 #define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 42 */ 01005 #define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 43 */ 01006 #define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 44 */ 01007 #define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 45 */ 01008 #define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 46 */ 01009 #define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 47 */ 01010 #define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4) /*!< PLLI2S division factor for PLLI2SM output by 48 */ 01011 #define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 49 */ 01012 #define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 50 */ 01013 #define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 51 */ 01014 #define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 52 */ 01015 #define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 53 */ 01016 #define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 54 */ 01017 #define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 55 */ 01018 #define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3) /*!< PLLI2S division factor for PLLI2SM output by 56 */ 01019 #define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 57 */ 01020 #define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 58 */ 01021 #define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 59 */ 01022 #define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2) /*!< PLLI2S division factor for PLLI2SM output by 60 */ 01023 #define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 61 */ 01024 #define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1) /*!< PLLI2S division factor for PLLI2SM output by 62 */ 01025 #define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0) /*!< PLLI2S division factor for PLLI2SM output by 63 */ 01026 #else 01027 #define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLI2S division factor for PLLI2SM output by 2 */ 01028 #define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLI2S division factor for PLLI2SM output by 3 */ 01029 #define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLI2S division factor for PLLI2SM output by 4 */ 01030 #define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLI2S division factor for PLLI2SM output by 5 */ 01031 #define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLI2S division factor for PLLI2SM output by 6 */ 01032 #define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLI2S division factor for PLLI2SM output by 7 */ 01033 #define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLI2S division factor for PLLI2SM output by 8 */ 01034 #define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLI2S division factor for PLLI2SM output by 9 */ 01035 #define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLI2S division factor for PLLI2SM output by 10 */ 01036 #define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLI2S division factor for PLLI2SM output by 11 */ 01037 #define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLI2S division factor for PLLI2SM output by 12 */ 01038 #define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLI2S division factor for PLLI2SM output by 13 */ 01039 #define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLI2S division factor for PLLI2SM output by 14 */ 01040 #define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLI2S division factor for PLLI2SM output by 15 */ 01041 #define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLI2S division factor for PLLI2SM output by 16 */ 01042 #define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLI2S division factor for PLLI2SM output by 17 */ 01043 #define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLI2S division factor for PLLI2SM output by 18 */ 01044 #define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLI2S division factor for PLLI2SM output by 19 */ 01045 #define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLI2S division factor for PLLI2SM output by 20 */ 01046 #define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLI2S division factor for PLLI2SM output by 21 */ 01047 #define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLI2S division factor for PLLI2SM output by 22 */ 01048 #define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLI2S division factor for PLLI2SM output by 23 */ 01049 #define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLI2S division factor for PLLI2SM output by 24 */ 01050 #define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLI2S division factor for PLLI2SM output by 25 */ 01051 #define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLI2S division factor for PLLI2SM output by 26 */ 01052 #define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLI2S division factor for PLLI2SM output by 27 */ 01053 #define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLI2S division factor for PLLI2SM output by 28 */ 01054 #define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLI2S division factor for PLLI2SM output by 29 */ 01055 #define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLI2S division factor for PLLI2SM output by 30 */ 01056 #define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLI2S division factor for PLLI2SM output by 31 */ 01057 #define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLI2S division factor for PLLI2SM output by 32 */ 01058 #define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLI2S division factor for PLLI2SM output by 33 */ 01059 #define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLI2S division factor for PLLI2SM output by 34 */ 01060 #define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLI2S division factor for PLLI2SM output by 35 */ 01061 #define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLI2S division factor for PLLI2SM output by 36 */ 01062 #define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLI2S division factor for PLLI2SM output by 37 */ 01063 #define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLI2S division factor for PLLI2SM output by 38 */ 01064 #define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLI2S division factor for PLLI2SM output by 39 */ 01065 #define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLI2S division factor for PLLI2SM output by 40 */ 01066 #define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLI2S division factor for PLLI2SM output by 41 */ 01067 #define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLI2S division factor for PLLI2SM output by 42 */ 01068 #define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLI2S division factor for PLLI2SM output by 43 */ 01069 #define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLI2S division factor for PLLI2SM output by 44 */ 01070 #define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLI2S division factor for PLLI2SM output by 45 */ 01071 #define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLI2S division factor for PLLI2SM output by 46 */ 01072 #define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLI2S division factor for PLLI2SM output by 47 */ 01073 #define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLI2S division factor for PLLI2SM output by 48 */ 01074 #define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLI2S division factor for PLLI2SM output by 49 */ 01075 #define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLI2S division factor for PLLI2SM output by 50 */ 01076 #define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLI2S division factor for PLLI2SM output by 51 */ 01077 #define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLI2S division factor for PLLI2SM output by 52 */ 01078 #define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLI2S division factor for PLLI2SM output by 53 */ 01079 #define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLI2S division factor for PLLI2SM output by 54 */ 01080 #define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLI2S division factor for PLLI2SM output by 55 */ 01081 #define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLI2S division factor for PLLI2SM output by 56 */ 01082 #define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLI2S division factor for PLLI2SM output by 57 */ 01083 #define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLI2S division factor for PLLI2SM output by 58 */ 01084 #define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLI2S division factor for PLLI2SM output by 59 */ 01085 #define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLI2S division factor for PLLI2SM output by 60 */ 01086 #define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLI2S division factor for PLLI2SM output by 61 */ 01087 #define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLI2S division factor for PLLI2SM output by 62 */ 01088 #define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLI2S division factor for PLLI2SM output by 63 */ 01089 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 01090 /** 01091 * @} 01092 */ 01093 01094 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) 01095 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ) 01096 * @{ 01097 */ 01098 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */ 01099 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */ 01100 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */ 01101 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */ 01102 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */ 01103 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */ 01104 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */ 01105 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */ 01106 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */ 01107 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */ 01108 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */ 01109 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */ 01110 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */ 01111 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */ 01112 /** 01113 * @} 01114 */ 01115 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */ 01116 01117 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 01118 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ) 01119 * @{ 01120 */ 01121 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */ 01122 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */ 01123 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */ 01124 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */ 01125 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */ 01126 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */ 01127 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */ 01128 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */ 01129 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */ 01130 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */ 01131 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */ 01132 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */ 01133 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */ 01134 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */ 01135 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */ 01136 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */ 01137 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */ 01138 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */ 01139 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */ 01140 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */ 01141 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */ 01142 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */ 01143 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */ 01144 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */ 01145 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */ 01146 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */ 01147 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */ 01148 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */ 01149 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */ 01150 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */ 01151 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */ 01152 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */ 01153 /** 01154 * @} 01155 */ 01156 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 01157 01158 #if defined(RCC_DCKCFGR_PLLI2SDIVR) 01159 /** @defgroup RCC_LL_EC_PLLI2SDIVR PLLI2SDIVR division factor (PLLI2SDIVR) 01160 * @{ 01161 */ 01162 #define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 1 */ 01163 #define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 2 */ 01164 #define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 3 */ 01165 #define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 4 */ 01166 #define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 5 */ 01167 #define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 6 */ 01168 #define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 7 */ 01169 #define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 8 */ 01170 #define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 9 */ 01171 #define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 10 */ 01172 #define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 11 */ 01173 #define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 12 */ 01174 #define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 13 */ 01175 #define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 14 */ 01176 #define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 15 */ 01177 #define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4) /*!< PLLI2S division factor for PLLI2SDIVR output by 16 */ 01178 #define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 17 */ 01179 #define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 18 */ 01180 #define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 19 */ 01181 #define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 20 */ 01182 #define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 21 */ 01183 #define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 22 */ 01184 #define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 23 */ 01185 #define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3) /*!< PLLI2S division factor for PLLI2SDIVR output by 24 */ 01186 #define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 25 */ 01187 #define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 26 */ 01188 #define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 27 */ 01189 #define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2) /*!< PLLI2S division factor for PLLI2SDIVR output by 28 */ 01190 #define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 29 */ 01191 #define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1) /*!< PLLI2S division factor for PLLI2SDIVR output by 30 */ 01192 #define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0) /*!< PLLI2S division factor for PLLI2SDIVR output by 31 */ 01193 /** 01194 * @} 01195 */ 01196 #endif /* RCC_DCKCFGR_PLLI2SDIVR */ 01197 01198 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR) 01199 * @{ 01200 */ 01201 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */ 01202 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */ 01203 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */ 01204 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */ 01205 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */ 01206 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */ 01207 /** 01208 * @} 01209 */ 01210 01211 #if defined(RCC_PLLI2SCFGR_PLLI2SP) 01212 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP) 01213 * @{ 01214 */ 01215 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */ 01216 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */ 01217 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */ 01218 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */ 01219 /** 01220 * @} 01221 */ 01222 #endif /* RCC_PLLI2SCFGR_PLLI2SP */ 01223 #endif /* RCC_PLLI2S_SUPPORT */ 01224 01225 #if defined(RCC_PLLSAI_SUPPORT) 01226 /** @defgroup RCC_LL_EC_PLLSAIM PLLSAIM division factor (PLLSAIM or PLLM) 01227 * @{ 01228 */ 01229 #if defined(RCC_PLLSAICFGR_PLLSAIM) 01230 #define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 2 */ 01231 #define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 3 */ 01232 #define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 4 */ 01233 #define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 5 */ 01234 #define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 6 */ 01235 #define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 7 */ 01236 #define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 8 */ 01237 #define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 9 */ 01238 #define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 10 */ 01239 #define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 11 */ 01240 #define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 12 */ 01241 #define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 13 */ 01242 #define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 14 */ 01243 #define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 15 */ 01244 #define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 16 */ 01245 #define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 17 */ 01246 #define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 18 */ 01247 #define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 19 */ 01248 #define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 20 */ 01249 #define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 21 */ 01250 #define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 22 */ 01251 #define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 23 */ 01252 #define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 24 */ 01253 #define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 25 */ 01254 #define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 26 */ 01255 #define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 27 */ 01256 #define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 28 */ 01257 #define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 29 */ 01258 #define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 30 */ 01259 #define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 31 */ 01260 #define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5) /*!< PLLSAI division factor for PLLSAIM output by 32 */ 01261 #define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 33 */ 01262 #define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 34 */ 01263 #define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 35 */ 01264 #define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 36 */ 01265 #define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 37 */ 01266 #define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 38 */ 01267 #define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 39 */ 01268 #define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 40 */ 01269 #define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 41 */ 01270 #define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 42 */ 01271 #define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 43 */ 01272 #define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 44 */ 01273 #define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 45 */ 01274 #define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 46 */ 01275 #define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 47 */ 01276 #define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4) /*!< PLLSAI division factor for PLLSAIM output by 48 */ 01277 #define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 49 */ 01278 #define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 50 */ 01279 #define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 51 */ 01280 #define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 52 */ 01281 #define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 53 */ 01282 #define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 54 */ 01283 #define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 55 */ 01284 #define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3) /*!< PLLSAI division factor for PLLSAIM output by 56 */ 01285 #define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 57 */ 01286 #define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 58 */ 01287 #define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 59 */ 01288 #define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2) /*!< PLLSAI division factor for PLLSAIM output by 60 */ 01289 #define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 61 */ 01290 #define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1) /*!< PLLSAI division factor for PLLSAIM output by 62 */ 01291 #define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0) /*!< PLLSAI division factor for PLLSAIM output by 63 */ 01292 #else 01293 #define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 /*!< PLLSAI division factor for PLLSAIM output by 2 */ 01294 #define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 /*!< PLLSAI division factor for PLLSAIM output by 3 */ 01295 #define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 /*!< PLLSAI division factor for PLLSAIM output by 4 */ 01296 #define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 /*!< PLLSAI division factor for PLLSAIM output by 5 */ 01297 #define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 /*!< PLLSAI division factor for PLLSAIM output by 6 */ 01298 #define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 /*!< PLLSAI division factor for PLLSAIM output by 7 */ 01299 #define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 /*!< PLLSAI division factor for PLLSAIM output by 8 */ 01300 #define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 /*!< PLLSAI division factor for PLLSAIM output by 9 */ 01301 #define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 /*!< PLLSAI division factor for PLLSAIM output by 10 */ 01302 #define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 /*!< PLLSAI division factor for PLLSAIM output by 11 */ 01303 #define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 /*!< PLLSAI division factor for PLLSAIM output by 12 */ 01304 #define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 /*!< PLLSAI division factor for PLLSAIM output by 13 */ 01305 #define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 /*!< PLLSAI division factor for PLLSAIM output by 14 */ 01306 #define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 /*!< PLLSAI division factor for PLLSAIM output by 15 */ 01307 #define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 /*!< PLLSAI division factor for PLLSAIM output by 16 */ 01308 #define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 /*!< PLLSAI division factor for PLLSAIM output by 17 */ 01309 #define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 /*!< PLLSAI division factor for PLLSAIM output by 18 */ 01310 #define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 /*!< PLLSAI division factor for PLLSAIM output by 19 */ 01311 #define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 /*!< PLLSAI division factor for PLLSAIM output by 20 */ 01312 #define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 /*!< PLLSAI division factor for PLLSAIM output by 21 */ 01313 #define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 /*!< PLLSAI division factor for PLLSAIM output by 22 */ 01314 #define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 /*!< PLLSAI division factor for PLLSAIM output by 23 */ 01315 #define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 /*!< PLLSAI division factor for PLLSAIM output by 24 */ 01316 #define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 /*!< PLLSAI division factor for PLLSAIM output by 25 */ 01317 #define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 /*!< PLLSAI division factor for PLLSAIM output by 26 */ 01318 #define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 /*!< PLLSAI division factor for PLLSAIM output by 27 */ 01319 #define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 /*!< PLLSAI division factor for PLLSAIM output by 28 */ 01320 #define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 /*!< PLLSAI division factor for PLLSAIM output by 29 */ 01321 #define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 /*!< PLLSAI division factor for PLLSAIM output by 30 */ 01322 #define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 /*!< PLLSAI division factor for PLLSAIM output by 31 */ 01323 #define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 /*!< PLLSAI division factor for PLLSAIM output by 32 */ 01324 #define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 /*!< PLLSAI division factor for PLLSAIM output by 33 */ 01325 #define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 /*!< PLLSAI division factor for PLLSAIM output by 34 */ 01326 #define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 /*!< PLLSAI division factor for PLLSAIM output by 35 */ 01327 #define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 /*!< PLLSAI division factor for PLLSAIM output by 36 */ 01328 #define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 /*!< PLLSAI division factor for PLLSAIM output by 37 */ 01329 #define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 /*!< PLLSAI division factor for PLLSAIM output by 38 */ 01330 #define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 /*!< PLLSAI division factor for PLLSAIM output by 39 */ 01331 #define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 /*!< PLLSAI division factor for PLLSAIM output by 40 */ 01332 #define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 /*!< PLLSAI division factor for PLLSAIM output by 41 */ 01333 #define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 /*!< PLLSAI division factor for PLLSAIM output by 42 */ 01334 #define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 /*!< PLLSAI division factor for PLLSAIM output by 43 */ 01335 #define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 /*!< PLLSAI division factor for PLLSAIM output by 44 */ 01336 #define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 /*!< PLLSAI division factor for PLLSAIM output by 45 */ 01337 #define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 /*!< PLLSAI division factor for PLLSAIM output by 46 */ 01338 #define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 /*!< PLLSAI division factor for PLLSAIM output by 47 */ 01339 #define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 /*!< PLLSAI division factor for PLLSAIM output by 48 */ 01340 #define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 /*!< PLLSAI division factor for PLLSAIM output by 49 */ 01341 #define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 /*!< PLLSAI division factor for PLLSAIM output by 50 */ 01342 #define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 /*!< PLLSAI division factor for PLLSAIM output by 51 */ 01343 #define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 /*!< PLLSAI division factor for PLLSAIM output by 52 */ 01344 #define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 /*!< PLLSAI division factor for PLLSAIM output by 53 */ 01345 #define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 /*!< PLLSAI division factor for PLLSAIM output by 54 */ 01346 #define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 /*!< PLLSAI division factor for PLLSAIM output by 55 */ 01347 #define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 /*!< PLLSAI division factor for PLLSAIM output by 56 */ 01348 #define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 /*!< PLLSAI division factor for PLLSAIM output by 57 */ 01349 #define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 /*!< PLLSAI division factor for PLLSAIM output by 58 */ 01350 #define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 /*!< PLLSAI division factor for PLLSAIM output by 59 */ 01351 #define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 /*!< PLLSAI division factor for PLLSAIM output by 60 */ 01352 #define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 /*!< PLLSAI division factor for PLLSAIM output by 61 */ 01353 #define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 /*!< PLLSAI division factor for PLLSAIM output by 62 */ 01354 #define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 /*!< PLLSAI division factor for PLLSAIM output by 63 */ 01355 #endif /* RCC_PLLSAICFGR_PLLSAIM */ 01356 /** 01357 * @} 01358 */ 01359 01360 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ) 01361 * @{ 01362 */ 01363 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */ 01364 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */ 01365 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */ 01366 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */ 01367 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */ 01368 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */ 01369 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */ 01370 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */ 01371 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */ 01372 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */ 01373 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */ 01374 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */ 01375 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */ 01376 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */ 01377 /** 01378 * @} 01379 */ 01380 01381 #if defined(RCC_DCKCFGR_PLLSAIDIVQ) 01382 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ) 01383 * @{ 01384 */ 01385 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */ 01386 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */ 01387 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */ 01388 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */ 01389 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */ 01390 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */ 01391 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */ 01392 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */ 01393 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */ 01394 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */ 01395 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */ 01396 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */ 01397 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */ 01398 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */ 01399 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */ 01400 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */ 01401 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */ 01402 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */ 01403 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */ 01404 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */ 01405 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */ 01406 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */ 01407 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */ 01408 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */ 01409 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */ 01410 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */ 01411 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */ 01412 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */ 01413 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */ 01414 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */ 01415 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */ 01416 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */ 01417 /** 01418 * @} 01419 */ 01420 #endif /* RCC_DCKCFGR_PLLSAIDIVQ */ 01421 01422 #if defined(RCC_PLLSAICFGR_PLLSAIR) 01423 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR) 01424 * @{ 01425 */ 01426 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */ 01427 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */ 01428 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */ 01429 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */ 01430 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */ 01431 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */ 01432 /** 01433 * @} 01434 */ 01435 #endif /* RCC_PLLSAICFGR_PLLSAIR */ 01436 01437 #if defined(RCC_DCKCFGR_PLLSAIDIVR) 01438 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR) 01439 * @{ 01440 */ 01441 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */ 01442 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */ 01443 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */ 01444 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */ 01445 /** 01446 * @} 01447 */ 01448 #endif /* RCC_DCKCFGR_PLLSAIDIVR */ 01449 01450 #if defined(RCC_PLLSAICFGR_PLLSAIP) 01451 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP) 01452 * @{ 01453 */ 01454 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */ 01455 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */ 01456 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */ 01457 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */ 01458 /** 01459 * @} 01460 */ 01461 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 01462 #endif /* RCC_PLLSAI_SUPPORT */ 01463 /** 01464 * @} 01465 */ 01466 01467 /* Exported macro ------------------------------------------------------------*/ 01468 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros 01469 * @{ 01470 */ 01471 01472 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros 01473 * @{ 01474 */ 01475 01476 /** 01477 * @brief Write a value in RCC register 01478 * @param __REG__ Register to be written 01479 * @param __VALUE__ Value to be written in the register 01480 * @retval None 01481 */ 01482 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) 01483 01484 /** 01485 * @brief Read a value in RCC register 01486 * @param __REG__ Register to be read 01487 * @retval Register value 01488 */ 01489 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) 01490 /** 01491 * @} 01492 */ 01493 01494 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies 01495 * @{ 01496 */ 01497 01498 /** 01499 * @brief Helper macro to calculate the PLLCLK frequency on system domain 01500 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01501 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ()); 01502 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01503 * @param __PLLM__ This parameter can be one of the following values: 01504 * @arg @ref LL_RCC_PLLM_DIV_2 01505 * @arg @ref LL_RCC_PLLM_DIV_3 01506 * @arg @ref LL_RCC_PLLM_DIV_4 01507 * @arg @ref LL_RCC_PLLM_DIV_5 01508 * @arg @ref LL_RCC_PLLM_DIV_6 01509 * @arg @ref LL_RCC_PLLM_DIV_7 01510 * @arg @ref LL_RCC_PLLM_DIV_8 01511 * @arg @ref LL_RCC_PLLM_DIV_9 01512 * @arg @ref LL_RCC_PLLM_DIV_10 01513 * @arg @ref LL_RCC_PLLM_DIV_11 01514 * @arg @ref LL_RCC_PLLM_DIV_12 01515 * @arg @ref LL_RCC_PLLM_DIV_13 01516 * @arg @ref LL_RCC_PLLM_DIV_14 01517 * @arg @ref LL_RCC_PLLM_DIV_15 01518 * @arg @ref LL_RCC_PLLM_DIV_16 01519 * @arg @ref LL_RCC_PLLM_DIV_17 01520 * @arg @ref LL_RCC_PLLM_DIV_18 01521 * @arg @ref LL_RCC_PLLM_DIV_19 01522 * @arg @ref LL_RCC_PLLM_DIV_20 01523 * @arg @ref LL_RCC_PLLM_DIV_21 01524 * @arg @ref LL_RCC_PLLM_DIV_22 01525 * @arg @ref LL_RCC_PLLM_DIV_23 01526 * @arg @ref LL_RCC_PLLM_DIV_24 01527 * @arg @ref LL_RCC_PLLM_DIV_25 01528 * @arg @ref LL_RCC_PLLM_DIV_26 01529 * @arg @ref LL_RCC_PLLM_DIV_27 01530 * @arg @ref LL_RCC_PLLM_DIV_28 01531 * @arg @ref LL_RCC_PLLM_DIV_29 01532 * @arg @ref LL_RCC_PLLM_DIV_30 01533 * @arg @ref LL_RCC_PLLM_DIV_31 01534 * @arg @ref LL_RCC_PLLM_DIV_32 01535 * @arg @ref LL_RCC_PLLM_DIV_33 01536 * @arg @ref LL_RCC_PLLM_DIV_34 01537 * @arg @ref LL_RCC_PLLM_DIV_35 01538 * @arg @ref LL_RCC_PLLM_DIV_36 01539 * @arg @ref LL_RCC_PLLM_DIV_37 01540 * @arg @ref LL_RCC_PLLM_DIV_38 01541 * @arg @ref LL_RCC_PLLM_DIV_39 01542 * @arg @ref LL_RCC_PLLM_DIV_40 01543 * @arg @ref LL_RCC_PLLM_DIV_41 01544 * @arg @ref LL_RCC_PLLM_DIV_42 01545 * @arg @ref LL_RCC_PLLM_DIV_43 01546 * @arg @ref LL_RCC_PLLM_DIV_44 01547 * @arg @ref LL_RCC_PLLM_DIV_45 01548 * @arg @ref LL_RCC_PLLM_DIV_46 01549 * @arg @ref LL_RCC_PLLM_DIV_47 01550 * @arg @ref LL_RCC_PLLM_DIV_48 01551 * @arg @ref LL_RCC_PLLM_DIV_49 01552 * @arg @ref LL_RCC_PLLM_DIV_50 01553 * @arg @ref LL_RCC_PLLM_DIV_51 01554 * @arg @ref LL_RCC_PLLM_DIV_52 01555 * @arg @ref LL_RCC_PLLM_DIV_53 01556 * @arg @ref LL_RCC_PLLM_DIV_54 01557 * @arg @ref LL_RCC_PLLM_DIV_55 01558 * @arg @ref LL_RCC_PLLM_DIV_56 01559 * @arg @ref LL_RCC_PLLM_DIV_57 01560 * @arg @ref LL_RCC_PLLM_DIV_58 01561 * @arg @ref LL_RCC_PLLM_DIV_59 01562 * @arg @ref LL_RCC_PLLM_DIV_60 01563 * @arg @ref LL_RCC_PLLM_DIV_61 01564 * @arg @ref LL_RCC_PLLM_DIV_62 01565 * @arg @ref LL_RCC_PLLM_DIV_63 01566 * @param __PLLN__ Between 50/192(*) and 432 01567 * 01568 * (*) value not defined in all devices. 01569 * @param __PLLP__ This parameter can be one of the following values: 01570 * @arg @ref LL_RCC_PLLP_DIV_2 01571 * @arg @ref LL_RCC_PLLP_DIV_4 01572 * @arg @ref LL_RCC_PLLP_DIV_6 01573 * @arg @ref LL_RCC_PLLP_DIV_8 01574 * @retval PLL clock frequency (in Hz) 01575 */ 01576 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01577 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U)) 01578 01579 #if defined(RCC_PLLR_SYSCLK_SUPPORT) 01580 /** 01581 * @brief Helper macro to calculate the PLLRCLK frequency on system domain 01582 * @note ex: @ref __LL_RCC_CALC_PLLRCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01583 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01584 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01585 * @param __PLLM__ This parameter can be one of the following values: 01586 * @arg @ref LL_RCC_PLLM_DIV_2 01587 * @arg @ref LL_RCC_PLLM_DIV_3 01588 * @arg @ref LL_RCC_PLLM_DIV_4 01589 * @arg @ref LL_RCC_PLLM_DIV_5 01590 * @arg @ref LL_RCC_PLLM_DIV_6 01591 * @arg @ref LL_RCC_PLLM_DIV_7 01592 * @arg @ref LL_RCC_PLLM_DIV_8 01593 * @arg @ref LL_RCC_PLLM_DIV_9 01594 * @arg @ref LL_RCC_PLLM_DIV_10 01595 * @arg @ref LL_RCC_PLLM_DIV_11 01596 * @arg @ref LL_RCC_PLLM_DIV_12 01597 * @arg @ref LL_RCC_PLLM_DIV_13 01598 * @arg @ref LL_RCC_PLLM_DIV_14 01599 * @arg @ref LL_RCC_PLLM_DIV_15 01600 * @arg @ref LL_RCC_PLLM_DIV_16 01601 * @arg @ref LL_RCC_PLLM_DIV_17 01602 * @arg @ref LL_RCC_PLLM_DIV_18 01603 * @arg @ref LL_RCC_PLLM_DIV_19 01604 * @arg @ref LL_RCC_PLLM_DIV_20 01605 * @arg @ref LL_RCC_PLLM_DIV_21 01606 * @arg @ref LL_RCC_PLLM_DIV_22 01607 * @arg @ref LL_RCC_PLLM_DIV_23 01608 * @arg @ref LL_RCC_PLLM_DIV_24 01609 * @arg @ref LL_RCC_PLLM_DIV_25 01610 * @arg @ref LL_RCC_PLLM_DIV_26 01611 * @arg @ref LL_RCC_PLLM_DIV_27 01612 * @arg @ref LL_RCC_PLLM_DIV_28 01613 * @arg @ref LL_RCC_PLLM_DIV_29 01614 * @arg @ref LL_RCC_PLLM_DIV_30 01615 * @arg @ref LL_RCC_PLLM_DIV_31 01616 * @arg @ref LL_RCC_PLLM_DIV_32 01617 * @arg @ref LL_RCC_PLLM_DIV_33 01618 * @arg @ref LL_RCC_PLLM_DIV_34 01619 * @arg @ref LL_RCC_PLLM_DIV_35 01620 * @arg @ref LL_RCC_PLLM_DIV_36 01621 * @arg @ref LL_RCC_PLLM_DIV_37 01622 * @arg @ref LL_RCC_PLLM_DIV_38 01623 * @arg @ref LL_RCC_PLLM_DIV_39 01624 * @arg @ref LL_RCC_PLLM_DIV_40 01625 * @arg @ref LL_RCC_PLLM_DIV_41 01626 * @arg @ref LL_RCC_PLLM_DIV_42 01627 * @arg @ref LL_RCC_PLLM_DIV_43 01628 * @arg @ref LL_RCC_PLLM_DIV_44 01629 * @arg @ref LL_RCC_PLLM_DIV_45 01630 * @arg @ref LL_RCC_PLLM_DIV_46 01631 * @arg @ref LL_RCC_PLLM_DIV_47 01632 * @arg @ref LL_RCC_PLLM_DIV_48 01633 * @arg @ref LL_RCC_PLLM_DIV_49 01634 * @arg @ref LL_RCC_PLLM_DIV_50 01635 * @arg @ref LL_RCC_PLLM_DIV_51 01636 * @arg @ref LL_RCC_PLLM_DIV_52 01637 * @arg @ref LL_RCC_PLLM_DIV_53 01638 * @arg @ref LL_RCC_PLLM_DIV_54 01639 * @arg @ref LL_RCC_PLLM_DIV_55 01640 * @arg @ref LL_RCC_PLLM_DIV_56 01641 * @arg @ref LL_RCC_PLLM_DIV_57 01642 * @arg @ref LL_RCC_PLLM_DIV_58 01643 * @arg @ref LL_RCC_PLLM_DIV_59 01644 * @arg @ref LL_RCC_PLLM_DIV_60 01645 * @arg @ref LL_RCC_PLLM_DIV_61 01646 * @arg @ref LL_RCC_PLLM_DIV_62 01647 * @arg @ref LL_RCC_PLLM_DIV_63 01648 * @param __PLLN__ Between 50 and 432 01649 * @param __PLLR__ This parameter can be one of the following values: 01650 * @arg @ref LL_RCC_PLLR_DIV_2 01651 * @arg @ref LL_RCC_PLLR_DIV_3 01652 * @arg @ref LL_RCC_PLLR_DIV_4 01653 * @arg @ref LL_RCC_PLLR_DIV_5 01654 * @arg @ref LL_RCC_PLLR_DIV_6 01655 * @arg @ref LL_RCC_PLLR_DIV_7 01656 * @retval PLL clock frequency (in Hz) 01657 */ 01658 #define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01659 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 01660 01661 #endif /* RCC_PLLR_SYSCLK_SUPPORT */ 01662 01663 /** 01664 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain 01665 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (), 01666 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ()); 01667 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01668 * @param __PLLM__ This parameter can be one of the following values: 01669 * @arg @ref LL_RCC_PLLM_DIV_2 01670 * @arg @ref LL_RCC_PLLM_DIV_3 01671 * @arg @ref LL_RCC_PLLM_DIV_4 01672 * @arg @ref LL_RCC_PLLM_DIV_5 01673 * @arg @ref LL_RCC_PLLM_DIV_6 01674 * @arg @ref LL_RCC_PLLM_DIV_7 01675 * @arg @ref LL_RCC_PLLM_DIV_8 01676 * @arg @ref LL_RCC_PLLM_DIV_9 01677 * @arg @ref LL_RCC_PLLM_DIV_10 01678 * @arg @ref LL_RCC_PLLM_DIV_11 01679 * @arg @ref LL_RCC_PLLM_DIV_12 01680 * @arg @ref LL_RCC_PLLM_DIV_13 01681 * @arg @ref LL_RCC_PLLM_DIV_14 01682 * @arg @ref LL_RCC_PLLM_DIV_15 01683 * @arg @ref LL_RCC_PLLM_DIV_16 01684 * @arg @ref LL_RCC_PLLM_DIV_17 01685 * @arg @ref LL_RCC_PLLM_DIV_18 01686 * @arg @ref LL_RCC_PLLM_DIV_19 01687 * @arg @ref LL_RCC_PLLM_DIV_20 01688 * @arg @ref LL_RCC_PLLM_DIV_21 01689 * @arg @ref LL_RCC_PLLM_DIV_22 01690 * @arg @ref LL_RCC_PLLM_DIV_23 01691 * @arg @ref LL_RCC_PLLM_DIV_24 01692 * @arg @ref LL_RCC_PLLM_DIV_25 01693 * @arg @ref LL_RCC_PLLM_DIV_26 01694 * @arg @ref LL_RCC_PLLM_DIV_27 01695 * @arg @ref LL_RCC_PLLM_DIV_28 01696 * @arg @ref LL_RCC_PLLM_DIV_29 01697 * @arg @ref LL_RCC_PLLM_DIV_30 01698 * @arg @ref LL_RCC_PLLM_DIV_31 01699 * @arg @ref LL_RCC_PLLM_DIV_32 01700 * @arg @ref LL_RCC_PLLM_DIV_33 01701 * @arg @ref LL_RCC_PLLM_DIV_34 01702 * @arg @ref LL_RCC_PLLM_DIV_35 01703 * @arg @ref LL_RCC_PLLM_DIV_36 01704 * @arg @ref LL_RCC_PLLM_DIV_37 01705 * @arg @ref LL_RCC_PLLM_DIV_38 01706 * @arg @ref LL_RCC_PLLM_DIV_39 01707 * @arg @ref LL_RCC_PLLM_DIV_40 01708 * @arg @ref LL_RCC_PLLM_DIV_41 01709 * @arg @ref LL_RCC_PLLM_DIV_42 01710 * @arg @ref LL_RCC_PLLM_DIV_43 01711 * @arg @ref LL_RCC_PLLM_DIV_44 01712 * @arg @ref LL_RCC_PLLM_DIV_45 01713 * @arg @ref LL_RCC_PLLM_DIV_46 01714 * @arg @ref LL_RCC_PLLM_DIV_47 01715 * @arg @ref LL_RCC_PLLM_DIV_48 01716 * @arg @ref LL_RCC_PLLM_DIV_49 01717 * @arg @ref LL_RCC_PLLM_DIV_50 01718 * @arg @ref LL_RCC_PLLM_DIV_51 01719 * @arg @ref LL_RCC_PLLM_DIV_52 01720 * @arg @ref LL_RCC_PLLM_DIV_53 01721 * @arg @ref LL_RCC_PLLM_DIV_54 01722 * @arg @ref LL_RCC_PLLM_DIV_55 01723 * @arg @ref LL_RCC_PLLM_DIV_56 01724 * @arg @ref LL_RCC_PLLM_DIV_57 01725 * @arg @ref LL_RCC_PLLM_DIV_58 01726 * @arg @ref LL_RCC_PLLM_DIV_59 01727 * @arg @ref LL_RCC_PLLM_DIV_60 01728 * @arg @ref LL_RCC_PLLM_DIV_61 01729 * @arg @ref LL_RCC_PLLM_DIV_62 01730 * @arg @ref LL_RCC_PLLM_DIV_63 01731 * @param __PLLN__ Between 50/192(*) and 432 01732 * 01733 * (*) value not defined in all devices. 01734 * @param __PLLQ__ This parameter can be one of the following values: 01735 * @arg @ref LL_RCC_PLLQ_DIV_2 01736 * @arg @ref LL_RCC_PLLQ_DIV_3 01737 * @arg @ref LL_RCC_PLLQ_DIV_4 01738 * @arg @ref LL_RCC_PLLQ_DIV_5 01739 * @arg @ref LL_RCC_PLLQ_DIV_6 01740 * @arg @ref LL_RCC_PLLQ_DIV_7 01741 * @arg @ref LL_RCC_PLLQ_DIV_8 01742 * @arg @ref LL_RCC_PLLQ_DIV_9 01743 * @arg @ref LL_RCC_PLLQ_DIV_10 01744 * @arg @ref LL_RCC_PLLQ_DIV_11 01745 * @arg @ref LL_RCC_PLLQ_DIV_12 01746 * @arg @ref LL_RCC_PLLQ_DIV_13 01747 * @arg @ref LL_RCC_PLLQ_DIV_14 01748 * @arg @ref LL_RCC_PLLQ_DIV_15 01749 * @retval PLL clock frequency (in Hz) 01750 */ 01751 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01752 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos )) 01753 01754 #if defined(DSI) 01755 /** 01756 * @brief Helper macro to calculate the PLLCLK frequency used on DSI 01757 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), 01758 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01759 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01760 * @param __PLLM__ This parameter can be one of the following values: 01761 * @arg @ref LL_RCC_PLLM_DIV_2 01762 * @arg @ref LL_RCC_PLLM_DIV_3 01763 * @arg @ref LL_RCC_PLLM_DIV_4 01764 * @arg @ref LL_RCC_PLLM_DIV_5 01765 * @arg @ref LL_RCC_PLLM_DIV_6 01766 * @arg @ref LL_RCC_PLLM_DIV_7 01767 * @arg @ref LL_RCC_PLLM_DIV_8 01768 * @arg @ref LL_RCC_PLLM_DIV_9 01769 * @arg @ref LL_RCC_PLLM_DIV_10 01770 * @arg @ref LL_RCC_PLLM_DIV_11 01771 * @arg @ref LL_RCC_PLLM_DIV_12 01772 * @arg @ref LL_RCC_PLLM_DIV_13 01773 * @arg @ref LL_RCC_PLLM_DIV_14 01774 * @arg @ref LL_RCC_PLLM_DIV_15 01775 * @arg @ref LL_RCC_PLLM_DIV_16 01776 * @arg @ref LL_RCC_PLLM_DIV_17 01777 * @arg @ref LL_RCC_PLLM_DIV_18 01778 * @arg @ref LL_RCC_PLLM_DIV_19 01779 * @arg @ref LL_RCC_PLLM_DIV_20 01780 * @arg @ref LL_RCC_PLLM_DIV_21 01781 * @arg @ref LL_RCC_PLLM_DIV_22 01782 * @arg @ref LL_RCC_PLLM_DIV_23 01783 * @arg @ref LL_RCC_PLLM_DIV_24 01784 * @arg @ref LL_RCC_PLLM_DIV_25 01785 * @arg @ref LL_RCC_PLLM_DIV_26 01786 * @arg @ref LL_RCC_PLLM_DIV_27 01787 * @arg @ref LL_RCC_PLLM_DIV_28 01788 * @arg @ref LL_RCC_PLLM_DIV_29 01789 * @arg @ref LL_RCC_PLLM_DIV_30 01790 * @arg @ref LL_RCC_PLLM_DIV_31 01791 * @arg @ref LL_RCC_PLLM_DIV_32 01792 * @arg @ref LL_RCC_PLLM_DIV_33 01793 * @arg @ref LL_RCC_PLLM_DIV_34 01794 * @arg @ref LL_RCC_PLLM_DIV_35 01795 * @arg @ref LL_RCC_PLLM_DIV_36 01796 * @arg @ref LL_RCC_PLLM_DIV_37 01797 * @arg @ref LL_RCC_PLLM_DIV_38 01798 * @arg @ref LL_RCC_PLLM_DIV_39 01799 * @arg @ref LL_RCC_PLLM_DIV_40 01800 * @arg @ref LL_RCC_PLLM_DIV_41 01801 * @arg @ref LL_RCC_PLLM_DIV_42 01802 * @arg @ref LL_RCC_PLLM_DIV_43 01803 * @arg @ref LL_RCC_PLLM_DIV_44 01804 * @arg @ref LL_RCC_PLLM_DIV_45 01805 * @arg @ref LL_RCC_PLLM_DIV_46 01806 * @arg @ref LL_RCC_PLLM_DIV_47 01807 * @arg @ref LL_RCC_PLLM_DIV_48 01808 * @arg @ref LL_RCC_PLLM_DIV_49 01809 * @arg @ref LL_RCC_PLLM_DIV_50 01810 * @arg @ref LL_RCC_PLLM_DIV_51 01811 * @arg @ref LL_RCC_PLLM_DIV_52 01812 * @arg @ref LL_RCC_PLLM_DIV_53 01813 * @arg @ref LL_RCC_PLLM_DIV_54 01814 * @arg @ref LL_RCC_PLLM_DIV_55 01815 * @arg @ref LL_RCC_PLLM_DIV_56 01816 * @arg @ref LL_RCC_PLLM_DIV_57 01817 * @arg @ref LL_RCC_PLLM_DIV_58 01818 * @arg @ref LL_RCC_PLLM_DIV_59 01819 * @arg @ref LL_RCC_PLLM_DIV_60 01820 * @arg @ref LL_RCC_PLLM_DIV_61 01821 * @arg @ref LL_RCC_PLLM_DIV_62 01822 * @arg @ref LL_RCC_PLLM_DIV_63 01823 * @param __PLLN__ Between 50 and 432 01824 * @param __PLLR__ This parameter can be one of the following values: 01825 * @arg @ref LL_RCC_PLLR_DIV_2 01826 * @arg @ref LL_RCC_PLLR_DIV_3 01827 * @arg @ref LL_RCC_PLLR_DIV_4 01828 * @arg @ref LL_RCC_PLLR_DIV_5 01829 * @arg @ref LL_RCC_PLLR_DIV_6 01830 * @arg @ref LL_RCC_PLLR_DIV_7 01831 * @retval PLL clock frequency (in Hz) 01832 */ 01833 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01834 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 01835 #endif /* DSI */ 01836 01837 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) 01838 /** 01839 * @brief Helper macro to calculate the PLLCLK frequency used on I2S 01840 * @note ex: @ref __LL_RCC_CALC_PLLCLK_I2S_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), 01841 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01842 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01843 * @param __PLLM__ This parameter can be one of the following values: 01844 * @arg @ref LL_RCC_PLLM_DIV_2 01845 * @arg @ref LL_RCC_PLLM_DIV_3 01846 * @arg @ref LL_RCC_PLLM_DIV_4 01847 * @arg @ref LL_RCC_PLLM_DIV_5 01848 * @arg @ref LL_RCC_PLLM_DIV_6 01849 * @arg @ref LL_RCC_PLLM_DIV_7 01850 * @arg @ref LL_RCC_PLLM_DIV_8 01851 * @arg @ref LL_RCC_PLLM_DIV_9 01852 * @arg @ref LL_RCC_PLLM_DIV_10 01853 * @arg @ref LL_RCC_PLLM_DIV_11 01854 * @arg @ref LL_RCC_PLLM_DIV_12 01855 * @arg @ref LL_RCC_PLLM_DIV_13 01856 * @arg @ref LL_RCC_PLLM_DIV_14 01857 * @arg @ref LL_RCC_PLLM_DIV_15 01858 * @arg @ref LL_RCC_PLLM_DIV_16 01859 * @arg @ref LL_RCC_PLLM_DIV_17 01860 * @arg @ref LL_RCC_PLLM_DIV_18 01861 * @arg @ref LL_RCC_PLLM_DIV_19 01862 * @arg @ref LL_RCC_PLLM_DIV_20 01863 * @arg @ref LL_RCC_PLLM_DIV_21 01864 * @arg @ref LL_RCC_PLLM_DIV_22 01865 * @arg @ref LL_RCC_PLLM_DIV_23 01866 * @arg @ref LL_RCC_PLLM_DIV_24 01867 * @arg @ref LL_RCC_PLLM_DIV_25 01868 * @arg @ref LL_RCC_PLLM_DIV_26 01869 * @arg @ref LL_RCC_PLLM_DIV_27 01870 * @arg @ref LL_RCC_PLLM_DIV_28 01871 * @arg @ref LL_RCC_PLLM_DIV_29 01872 * @arg @ref LL_RCC_PLLM_DIV_30 01873 * @arg @ref LL_RCC_PLLM_DIV_31 01874 * @arg @ref LL_RCC_PLLM_DIV_32 01875 * @arg @ref LL_RCC_PLLM_DIV_33 01876 * @arg @ref LL_RCC_PLLM_DIV_34 01877 * @arg @ref LL_RCC_PLLM_DIV_35 01878 * @arg @ref LL_RCC_PLLM_DIV_36 01879 * @arg @ref LL_RCC_PLLM_DIV_37 01880 * @arg @ref LL_RCC_PLLM_DIV_38 01881 * @arg @ref LL_RCC_PLLM_DIV_39 01882 * @arg @ref LL_RCC_PLLM_DIV_40 01883 * @arg @ref LL_RCC_PLLM_DIV_41 01884 * @arg @ref LL_RCC_PLLM_DIV_42 01885 * @arg @ref LL_RCC_PLLM_DIV_43 01886 * @arg @ref LL_RCC_PLLM_DIV_44 01887 * @arg @ref LL_RCC_PLLM_DIV_45 01888 * @arg @ref LL_RCC_PLLM_DIV_46 01889 * @arg @ref LL_RCC_PLLM_DIV_47 01890 * @arg @ref LL_RCC_PLLM_DIV_48 01891 * @arg @ref LL_RCC_PLLM_DIV_49 01892 * @arg @ref LL_RCC_PLLM_DIV_50 01893 * @arg @ref LL_RCC_PLLM_DIV_51 01894 * @arg @ref LL_RCC_PLLM_DIV_52 01895 * @arg @ref LL_RCC_PLLM_DIV_53 01896 * @arg @ref LL_RCC_PLLM_DIV_54 01897 * @arg @ref LL_RCC_PLLM_DIV_55 01898 * @arg @ref LL_RCC_PLLM_DIV_56 01899 * @arg @ref LL_RCC_PLLM_DIV_57 01900 * @arg @ref LL_RCC_PLLM_DIV_58 01901 * @arg @ref LL_RCC_PLLM_DIV_59 01902 * @arg @ref LL_RCC_PLLM_DIV_60 01903 * @arg @ref LL_RCC_PLLM_DIV_61 01904 * @arg @ref LL_RCC_PLLM_DIV_62 01905 * @arg @ref LL_RCC_PLLM_DIV_63 01906 * @param __PLLN__ Between 50 and 432 01907 * @param __PLLR__ This parameter can be one of the following values: 01908 * @arg @ref LL_RCC_PLLR_DIV_2 01909 * @arg @ref LL_RCC_PLLR_DIV_3 01910 * @arg @ref LL_RCC_PLLR_DIV_4 01911 * @arg @ref LL_RCC_PLLR_DIV_5 01912 * @arg @ref LL_RCC_PLLR_DIV_6 01913 * @arg @ref LL_RCC_PLLR_DIV_7 01914 * @retval PLL clock frequency (in Hz) 01915 */ 01916 #define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 01917 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 01918 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ 01919 01920 #if defined(SPDIFRX) 01921 /** 01922 * @brief Helper macro to calculate the PLLCLK frequency used on SPDIFRX 01923 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), 01924 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ()); 01925 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 01926 * @param __PLLM__ This parameter can be one of the following values: 01927 * @arg @ref LL_RCC_PLLM_DIV_2 01928 * @arg @ref LL_RCC_PLLM_DIV_3 01929 * @arg @ref LL_RCC_PLLM_DIV_4 01930 * @arg @ref LL_RCC_PLLM_DIV_5 01931 * @arg @ref LL_RCC_PLLM_DIV_6 01932 * @arg @ref LL_RCC_PLLM_DIV_7 01933 * @arg @ref LL_RCC_PLLM_DIV_8 01934 * @arg @ref LL_RCC_PLLM_DIV_9 01935 * @arg @ref LL_RCC_PLLM_DIV_10 01936 * @arg @ref LL_RCC_PLLM_DIV_11 01937 * @arg @ref LL_RCC_PLLM_DIV_12 01938 * @arg @ref LL_RCC_PLLM_DIV_13 01939 * @arg @ref LL_RCC_PLLM_DIV_14 01940 * @arg @ref LL_RCC_PLLM_DIV_15 01941 * @arg @ref LL_RCC_PLLM_DIV_16 01942 * @arg @ref LL_RCC_PLLM_DIV_17 01943 * @arg @ref LL_RCC_PLLM_DIV_18 01944 * @arg @ref LL_RCC_PLLM_DIV_19 01945 * @arg @ref LL_RCC_PLLM_DIV_20 01946 * @arg @ref LL_RCC_PLLM_DIV_21 01947 * @arg @ref LL_RCC_PLLM_DIV_22 01948 * @arg @ref LL_RCC_PLLM_DIV_23 01949 * @arg @ref LL_RCC_PLLM_DIV_24 01950 * @arg @ref LL_RCC_PLLM_DIV_25 01951 * @arg @ref LL_RCC_PLLM_DIV_26 01952 * @arg @ref LL_RCC_PLLM_DIV_27 01953 * @arg @ref LL_RCC_PLLM_DIV_28 01954 * @arg @ref LL_RCC_PLLM_DIV_29 01955 * @arg @ref LL_RCC_PLLM_DIV_30 01956 * @arg @ref LL_RCC_PLLM_DIV_31 01957 * @arg @ref LL_RCC_PLLM_DIV_32 01958 * @arg @ref LL_RCC_PLLM_DIV_33 01959 * @arg @ref LL_RCC_PLLM_DIV_34 01960 * @arg @ref LL_RCC_PLLM_DIV_35 01961 * @arg @ref LL_RCC_PLLM_DIV_36 01962 * @arg @ref LL_RCC_PLLM_DIV_37 01963 * @arg @ref LL_RCC_PLLM_DIV_38 01964 * @arg @ref LL_RCC_PLLM_DIV_39 01965 * @arg @ref LL_RCC_PLLM_DIV_40 01966 * @arg @ref LL_RCC_PLLM_DIV_41 01967 * @arg @ref LL_RCC_PLLM_DIV_42 01968 * @arg @ref LL_RCC_PLLM_DIV_43 01969 * @arg @ref LL_RCC_PLLM_DIV_44 01970 * @arg @ref LL_RCC_PLLM_DIV_45 01971 * @arg @ref LL_RCC_PLLM_DIV_46 01972 * @arg @ref LL_RCC_PLLM_DIV_47 01973 * @arg @ref LL_RCC_PLLM_DIV_48 01974 * @arg @ref LL_RCC_PLLM_DIV_49 01975 * @arg @ref LL_RCC_PLLM_DIV_50 01976 * @arg @ref LL_RCC_PLLM_DIV_51 01977 * @arg @ref LL_RCC_PLLM_DIV_52 01978 * @arg @ref LL_RCC_PLLM_DIV_53 01979 * @arg @ref LL_RCC_PLLM_DIV_54 01980 * @arg @ref LL_RCC_PLLM_DIV_55 01981 * @arg @ref LL_RCC_PLLM_DIV_56 01982 * @arg @ref LL_RCC_PLLM_DIV_57 01983 * @arg @ref LL_RCC_PLLM_DIV_58 01984 * @arg @ref LL_RCC_PLLM_DIV_59 01985 * @arg @ref LL_RCC_PLLM_DIV_60 01986 * @arg @ref LL_RCC_PLLM_DIV_61 01987 * @arg @ref LL_RCC_PLLM_DIV_62 01988 * @arg @ref LL_RCC_PLLM_DIV_63 01989 * @param __PLLN__ Between 50 and 432 01990 * @param __PLLR__ This parameter can be one of the following values: 01991 * @arg @ref LL_RCC_PLLR_DIV_2 01992 * @arg @ref LL_RCC_PLLR_DIV_3 01993 * @arg @ref LL_RCC_PLLR_DIV_4 01994 * @arg @ref LL_RCC_PLLR_DIV_5 01995 * @arg @ref LL_RCC_PLLR_DIV_6 01996 * @arg @ref LL_RCC_PLLR_DIV_7 01997 * @retval PLL clock frequency (in Hz) 01998 */ 01999 #define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 02000 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 02001 #endif /* SPDIFRX */ 02002 02003 #if defined(RCC_PLLCFGR_PLLR) 02004 #if defined(SAI1) 02005 /** 02006 * @brief Helper macro to calculate the PLLCLK frequency used on SAI 02007 * @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (), 02008 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR (), @ref LL_RCC_PLL_GetDIVR ()); 02009 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02010 * @param __PLLM__ This parameter can be one of the following values: 02011 * @arg @ref LL_RCC_PLLM_DIV_2 02012 * @arg @ref LL_RCC_PLLM_DIV_3 02013 * @arg @ref LL_RCC_PLLM_DIV_4 02014 * @arg @ref LL_RCC_PLLM_DIV_5 02015 * @arg @ref LL_RCC_PLLM_DIV_6 02016 * @arg @ref LL_RCC_PLLM_DIV_7 02017 * @arg @ref LL_RCC_PLLM_DIV_8 02018 * @arg @ref LL_RCC_PLLM_DIV_9 02019 * @arg @ref LL_RCC_PLLM_DIV_10 02020 * @arg @ref LL_RCC_PLLM_DIV_11 02021 * @arg @ref LL_RCC_PLLM_DIV_12 02022 * @arg @ref LL_RCC_PLLM_DIV_13 02023 * @arg @ref LL_RCC_PLLM_DIV_14 02024 * @arg @ref LL_RCC_PLLM_DIV_15 02025 * @arg @ref LL_RCC_PLLM_DIV_16 02026 * @arg @ref LL_RCC_PLLM_DIV_17 02027 * @arg @ref LL_RCC_PLLM_DIV_18 02028 * @arg @ref LL_RCC_PLLM_DIV_19 02029 * @arg @ref LL_RCC_PLLM_DIV_20 02030 * @arg @ref LL_RCC_PLLM_DIV_21 02031 * @arg @ref LL_RCC_PLLM_DIV_22 02032 * @arg @ref LL_RCC_PLLM_DIV_23 02033 * @arg @ref LL_RCC_PLLM_DIV_24 02034 * @arg @ref LL_RCC_PLLM_DIV_25 02035 * @arg @ref LL_RCC_PLLM_DIV_26 02036 * @arg @ref LL_RCC_PLLM_DIV_27 02037 * @arg @ref LL_RCC_PLLM_DIV_28 02038 * @arg @ref LL_RCC_PLLM_DIV_29 02039 * @arg @ref LL_RCC_PLLM_DIV_30 02040 * @arg @ref LL_RCC_PLLM_DIV_31 02041 * @arg @ref LL_RCC_PLLM_DIV_32 02042 * @arg @ref LL_RCC_PLLM_DIV_33 02043 * @arg @ref LL_RCC_PLLM_DIV_34 02044 * @arg @ref LL_RCC_PLLM_DIV_35 02045 * @arg @ref LL_RCC_PLLM_DIV_36 02046 * @arg @ref LL_RCC_PLLM_DIV_37 02047 * @arg @ref LL_RCC_PLLM_DIV_38 02048 * @arg @ref LL_RCC_PLLM_DIV_39 02049 * @arg @ref LL_RCC_PLLM_DIV_40 02050 * @arg @ref LL_RCC_PLLM_DIV_41 02051 * @arg @ref LL_RCC_PLLM_DIV_42 02052 * @arg @ref LL_RCC_PLLM_DIV_43 02053 * @arg @ref LL_RCC_PLLM_DIV_44 02054 * @arg @ref LL_RCC_PLLM_DIV_45 02055 * @arg @ref LL_RCC_PLLM_DIV_46 02056 * @arg @ref LL_RCC_PLLM_DIV_47 02057 * @arg @ref LL_RCC_PLLM_DIV_48 02058 * @arg @ref LL_RCC_PLLM_DIV_49 02059 * @arg @ref LL_RCC_PLLM_DIV_50 02060 * @arg @ref LL_RCC_PLLM_DIV_51 02061 * @arg @ref LL_RCC_PLLM_DIV_52 02062 * @arg @ref LL_RCC_PLLM_DIV_53 02063 * @arg @ref LL_RCC_PLLM_DIV_54 02064 * @arg @ref LL_RCC_PLLM_DIV_55 02065 * @arg @ref LL_RCC_PLLM_DIV_56 02066 * @arg @ref LL_RCC_PLLM_DIV_57 02067 * @arg @ref LL_RCC_PLLM_DIV_58 02068 * @arg @ref LL_RCC_PLLM_DIV_59 02069 * @arg @ref LL_RCC_PLLM_DIV_60 02070 * @arg @ref LL_RCC_PLLM_DIV_61 02071 * @arg @ref LL_RCC_PLLM_DIV_62 02072 * @arg @ref LL_RCC_PLLM_DIV_63 02073 * @param __PLLN__ Between 50 and 432 02074 * @param __PLLR__ This parameter can be one of the following values: 02075 * @arg @ref LL_RCC_PLLR_DIV_2 02076 * @arg @ref LL_RCC_PLLR_DIV_3 02077 * @arg @ref LL_RCC_PLLR_DIV_4 02078 * @arg @ref LL_RCC_PLLR_DIV_5 02079 * @arg @ref LL_RCC_PLLR_DIV_6 02080 * @arg @ref LL_RCC_PLLR_DIV_7 02081 * @param __PLLDIVR__ This parameter can be one of the following values: 02082 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) 02083 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) 02084 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) 02085 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) 02086 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) 02087 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) 02088 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) 02089 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) 02090 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) 02091 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) 02092 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) 02093 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) 02094 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) 02095 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) 02096 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) 02097 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) 02098 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) 02099 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) 02100 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) 02101 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) 02102 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) 02103 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) 02104 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) 02105 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) 02106 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) 02107 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) 02108 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) 02109 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) 02110 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) 02111 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) 02112 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) 02113 * 02114 * (*) value not defined in all devices. 02115 * @retval PLL clock frequency (in Hz) 02116 */ 02117 #if defined(RCC_DCKCFGR_PLLDIVR) 02118 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 02119 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos )) 02120 #else 02121 #define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \ 02122 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) 02123 #endif /* RCC_DCKCFGR_PLLDIVR */ 02124 #endif /* SAI1 */ 02125 #endif /* RCC_PLLCFGR_PLLR */ 02126 02127 #if defined(RCC_PLLSAI_SUPPORT) 02128 /** 02129 * @brief Helper macro to calculate the PLLSAI frequency used for SAI domain 02130 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), 02131 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ()); 02132 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02133 * @param __PLLM__ This parameter can be one of the following values: 02134 * @arg @ref LL_RCC_PLLSAIM_DIV_2 02135 * @arg @ref LL_RCC_PLLSAIM_DIV_3 02136 * @arg @ref LL_RCC_PLLSAIM_DIV_4 02137 * @arg @ref LL_RCC_PLLSAIM_DIV_5 02138 * @arg @ref LL_RCC_PLLSAIM_DIV_6 02139 * @arg @ref LL_RCC_PLLSAIM_DIV_7 02140 * @arg @ref LL_RCC_PLLSAIM_DIV_8 02141 * @arg @ref LL_RCC_PLLSAIM_DIV_9 02142 * @arg @ref LL_RCC_PLLSAIM_DIV_10 02143 * @arg @ref LL_RCC_PLLSAIM_DIV_11 02144 * @arg @ref LL_RCC_PLLSAIM_DIV_12 02145 * @arg @ref LL_RCC_PLLSAIM_DIV_13 02146 * @arg @ref LL_RCC_PLLSAIM_DIV_14 02147 * @arg @ref LL_RCC_PLLSAIM_DIV_15 02148 * @arg @ref LL_RCC_PLLSAIM_DIV_16 02149 * @arg @ref LL_RCC_PLLSAIM_DIV_17 02150 * @arg @ref LL_RCC_PLLSAIM_DIV_18 02151 * @arg @ref LL_RCC_PLLSAIM_DIV_19 02152 * @arg @ref LL_RCC_PLLSAIM_DIV_20 02153 * @arg @ref LL_RCC_PLLSAIM_DIV_21 02154 * @arg @ref LL_RCC_PLLSAIM_DIV_22 02155 * @arg @ref LL_RCC_PLLSAIM_DIV_23 02156 * @arg @ref LL_RCC_PLLSAIM_DIV_24 02157 * @arg @ref LL_RCC_PLLSAIM_DIV_25 02158 * @arg @ref LL_RCC_PLLSAIM_DIV_26 02159 * @arg @ref LL_RCC_PLLSAIM_DIV_27 02160 * @arg @ref LL_RCC_PLLSAIM_DIV_28 02161 * @arg @ref LL_RCC_PLLSAIM_DIV_29 02162 * @arg @ref LL_RCC_PLLSAIM_DIV_30 02163 * @arg @ref LL_RCC_PLLSAIM_DIV_31 02164 * @arg @ref LL_RCC_PLLSAIM_DIV_32 02165 * @arg @ref LL_RCC_PLLSAIM_DIV_33 02166 * @arg @ref LL_RCC_PLLSAIM_DIV_34 02167 * @arg @ref LL_RCC_PLLSAIM_DIV_35 02168 * @arg @ref LL_RCC_PLLSAIM_DIV_36 02169 * @arg @ref LL_RCC_PLLSAIM_DIV_37 02170 * @arg @ref LL_RCC_PLLSAIM_DIV_38 02171 * @arg @ref LL_RCC_PLLSAIM_DIV_39 02172 * @arg @ref LL_RCC_PLLSAIM_DIV_40 02173 * @arg @ref LL_RCC_PLLSAIM_DIV_41 02174 * @arg @ref LL_RCC_PLLSAIM_DIV_42 02175 * @arg @ref LL_RCC_PLLSAIM_DIV_43 02176 * @arg @ref LL_RCC_PLLSAIM_DIV_44 02177 * @arg @ref LL_RCC_PLLSAIM_DIV_45 02178 * @arg @ref LL_RCC_PLLSAIM_DIV_46 02179 * @arg @ref LL_RCC_PLLSAIM_DIV_47 02180 * @arg @ref LL_RCC_PLLSAIM_DIV_48 02181 * @arg @ref LL_RCC_PLLSAIM_DIV_49 02182 * @arg @ref LL_RCC_PLLSAIM_DIV_50 02183 * @arg @ref LL_RCC_PLLSAIM_DIV_51 02184 * @arg @ref LL_RCC_PLLSAIM_DIV_52 02185 * @arg @ref LL_RCC_PLLSAIM_DIV_53 02186 * @arg @ref LL_RCC_PLLSAIM_DIV_54 02187 * @arg @ref LL_RCC_PLLSAIM_DIV_55 02188 * @arg @ref LL_RCC_PLLSAIM_DIV_56 02189 * @arg @ref LL_RCC_PLLSAIM_DIV_57 02190 * @arg @ref LL_RCC_PLLSAIM_DIV_58 02191 * @arg @ref LL_RCC_PLLSAIM_DIV_59 02192 * @arg @ref LL_RCC_PLLSAIM_DIV_60 02193 * @arg @ref LL_RCC_PLLSAIM_DIV_61 02194 * @arg @ref LL_RCC_PLLSAIM_DIV_62 02195 * @arg @ref LL_RCC_PLLSAIM_DIV_63 02196 * @param __PLLSAIN__ Between 49/50(*) and 432 02197 * 02198 * (*) value not defined in all devices. 02199 * @param __PLLSAIQ__ This parameter can be one of the following values: 02200 * @arg @ref LL_RCC_PLLSAIQ_DIV_2 02201 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 02202 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 02203 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 02204 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 02205 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 02206 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 02207 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 02208 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 02209 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 02210 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 02211 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 02212 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 02213 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 02214 * @param __PLLSAIDIVQ__ This parameter can be one of the following values: 02215 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 02216 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 02217 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 02218 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 02219 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 02220 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 02221 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 02222 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 02223 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 02224 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 02225 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 02226 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 02227 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 02228 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 02229 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 02230 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 02231 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 02232 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 02233 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 02234 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 02235 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 02236 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 02237 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 02238 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 02239 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 02240 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 02241 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 02242 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 02243 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 02244 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 02245 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 02246 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 02247 * @retval PLLSAI clock frequency (in Hz) 02248 */ 02249 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ 02250 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U))) 02251 02252 #if defined(RCC_PLLSAICFGR_PLLSAIP) 02253 /** 02254 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain 02255 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), 02256 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ()); 02257 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02258 * @param __PLLM__ This parameter can be one of the following values: 02259 * @arg @ref LL_RCC_PLLSAIM_DIV_2 02260 * @arg @ref LL_RCC_PLLSAIM_DIV_3 02261 * @arg @ref LL_RCC_PLLSAIM_DIV_4 02262 * @arg @ref LL_RCC_PLLSAIM_DIV_5 02263 * @arg @ref LL_RCC_PLLSAIM_DIV_6 02264 * @arg @ref LL_RCC_PLLSAIM_DIV_7 02265 * @arg @ref LL_RCC_PLLSAIM_DIV_8 02266 * @arg @ref LL_RCC_PLLSAIM_DIV_9 02267 * @arg @ref LL_RCC_PLLSAIM_DIV_10 02268 * @arg @ref LL_RCC_PLLSAIM_DIV_11 02269 * @arg @ref LL_RCC_PLLSAIM_DIV_12 02270 * @arg @ref LL_RCC_PLLSAIM_DIV_13 02271 * @arg @ref LL_RCC_PLLSAIM_DIV_14 02272 * @arg @ref LL_RCC_PLLSAIM_DIV_15 02273 * @arg @ref LL_RCC_PLLSAIM_DIV_16 02274 * @arg @ref LL_RCC_PLLSAIM_DIV_17 02275 * @arg @ref LL_RCC_PLLSAIM_DIV_18 02276 * @arg @ref LL_RCC_PLLSAIM_DIV_19 02277 * @arg @ref LL_RCC_PLLSAIM_DIV_20 02278 * @arg @ref LL_RCC_PLLSAIM_DIV_21 02279 * @arg @ref LL_RCC_PLLSAIM_DIV_22 02280 * @arg @ref LL_RCC_PLLSAIM_DIV_23 02281 * @arg @ref LL_RCC_PLLSAIM_DIV_24 02282 * @arg @ref LL_RCC_PLLSAIM_DIV_25 02283 * @arg @ref LL_RCC_PLLSAIM_DIV_26 02284 * @arg @ref LL_RCC_PLLSAIM_DIV_27 02285 * @arg @ref LL_RCC_PLLSAIM_DIV_28 02286 * @arg @ref LL_RCC_PLLSAIM_DIV_29 02287 * @arg @ref LL_RCC_PLLSAIM_DIV_30 02288 * @arg @ref LL_RCC_PLLSAIM_DIV_31 02289 * @arg @ref LL_RCC_PLLSAIM_DIV_32 02290 * @arg @ref LL_RCC_PLLSAIM_DIV_33 02291 * @arg @ref LL_RCC_PLLSAIM_DIV_34 02292 * @arg @ref LL_RCC_PLLSAIM_DIV_35 02293 * @arg @ref LL_RCC_PLLSAIM_DIV_36 02294 * @arg @ref LL_RCC_PLLSAIM_DIV_37 02295 * @arg @ref LL_RCC_PLLSAIM_DIV_38 02296 * @arg @ref LL_RCC_PLLSAIM_DIV_39 02297 * @arg @ref LL_RCC_PLLSAIM_DIV_40 02298 * @arg @ref LL_RCC_PLLSAIM_DIV_41 02299 * @arg @ref LL_RCC_PLLSAIM_DIV_42 02300 * @arg @ref LL_RCC_PLLSAIM_DIV_43 02301 * @arg @ref LL_RCC_PLLSAIM_DIV_44 02302 * @arg @ref LL_RCC_PLLSAIM_DIV_45 02303 * @arg @ref LL_RCC_PLLSAIM_DIV_46 02304 * @arg @ref LL_RCC_PLLSAIM_DIV_47 02305 * @arg @ref LL_RCC_PLLSAIM_DIV_48 02306 * @arg @ref LL_RCC_PLLSAIM_DIV_49 02307 * @arg @ref LL_RCC_PLLSAIM_DIV_50 02308 * @arg @ref LL_RCC_PLLSAIM_DIV_51 02309 * @arg @ref LL_RCC_PLLSAIM_DIV_52 02310 * @arg @ref LL_RCC_PLLSAIM_DIV_53 02311 * @arg @ref LL_RCC_PLLSAIM_DIV_54 02312 * @arg @ref LL_RCC_PLLSAIM_DIV_55 02313 * @arg @ref LL_RCC_PLLSAIM_DIV_56 02314 * @arg @ref LL_RCC_PLLSAIM_DIV_57 02315 * @arg @ref LL_RCC_PLLSAIM_DIV_58 02316 * @arg @ref LL_RCC_PLLSAIM_DIV_59 02317 * @arg @ref LL_RCC_PLLSAIM_DIV_60 02318 * @arg @ref LL_RCC_PLLSAIM_DIV_61 02319 * @arg @ref LL_RCC_PLLSAIM_DIV_62 02320 * @arg @ref LL_RCC_PLLSAIM_DIV_63 02321 * @param __PLLSAIN__ Between 50 and 432 02322 * @param __PLLSAIP__ This parameter can be one of the following values: 02323 * @arg @ref LL_RCC_PLLSAIP_DIV_2 02324 * @arg @ref LL_RCC_PLLSAIP_DIV_4 02325 * @arg @ref LL_RCC_PLLSAIP_DIV_6 02326 * @arg @ref LL_RCC_PLLSAIP_DIV_8 02327 * @retval PLLSAI clock frequency (in Hz) 02328 */ 02329 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ 02330 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U)) 02331 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 02332 02333 #if defined(LTDC) 02334 /** 02335 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain 02336 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI_GetDivider (), 02337 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ()); 02338 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02339 * @param __PLLM__ This parameter can be one of the following values: 02340 * @arg @ref LL_RCC_PLLSAIM_DIV_2 02341 * @arg @ref LL_RCC_PLLSAIM_DIV_3 02342 * @arg @ref LL_RCC_PLLSAIM_DIV_4 02343 * @arg @ref LL_RCC_PLLSAIM_DIV_5 02344 * @arg @ref LL_RCC_PLLSAIM_DIV_6 02345 * @arg @ref LL_RCC_PLLSAIM_DIV_7 02346 * @arg @ref LL_RCC_PLLSAIM_DIV_8 02347 * @arg @ref LL_RCC_PLLSAIM_DIV_9 02348 * @arg @ref LL_RCC_PLLSAIM_DIV_10 02349 * @arg @ref LL_RCC_PLLSAIM_DIV_11 02350 * @arg @ref LL_RCC_PLLSAIM_DIV_12 02351 * @arg @ref LL_RCC_PLLSAIM_DIV_13 02352 * @arg @ref LL_RCC_PLLSAIM_DIV_14 02353 * @arg @ref LL_RCC_PLLSAIM_DIV_15 02354 * @arg @ref LL_RCC_PLLSAIM_DIV_16 02355 * @arg @ref LL_RCC_PLLSAIM_DIV_17 02356 * @arg @ref LL_RCC_PLLSAIM_DIV_18 02357 * @arg @ref LL_RCC_PLLSAIM_DIV_19 02358 * @arg @ref LL_RCC_PLLSAIM_DIV_20 02359 * @arg @ref LL_RCC_PLLSAIM_DIV_21 02360 * @arg @ref LL_RCC_PLLSAIM_DIV_22 02361 * @arg @ref LL_RCC_PLLSAIM_DIV_23 02362 * @arg @ref LL_RCC_PLLSAIM_DIV_24 02363 * @arg @ref LL_RCC_PLLSAIM_DIV_25 02364 * @arg @ref LL_RCC_PLLSAIM_DIV_26 02365 * @arg @ref LL_RCC_PLLSAIM_DIV_27 02366 * @arg @ref LL_RCC_PLLSAIM_DIV_28 02367 * @arg @ref LL_RCC_PLLSAIM_DIV_29 02368 * @arg @ref LL_RCC_PLLSAIM_DIV_30 02369 * @arg @ref LL_RCC_PLLSAIM_DIV_31 02370 * @arg @ref LL_RCC_PLLSAIM_DIV_32 02371 * @arg @ref LL_RCC_PLLSAIM_DIV_33 02372 * @arg @ref LL_RCC_PLLSAIM_DIV_34 02373 * @arg @ref LL_RCC_PLLSAIM_DIV_35 02374 * @arg @ref LL_RCC_PLLSAIM_DIV_36 02375 * @arg @ref LL_RCC_PLLSAIM_DIV_37 02376 * @arg @ref LL_RCC_PLLSAIM_DIV_38 02377 * @arg @ref LL_RCC_PLLSAIM_DIV_39 02378 * @arg @ref LL_RCC_PLLSAIM_DIV_40 02379 * @arg @ref LL_RCC_PLLSAIM_DIV_41 02380 * @arg @ref LL_RCC_PLLSAIM_DIV_42 02381 * @arg @ref LL_RCC_PLLSAIM_DIV_43 02382 * @arg @ref LL_RCC_PLLSAIM_DIV_44 02383 * @arg @ref LL_RCC_PLLSAIM_DIV_45 02384 * @arg @ref LL_RCC_PLLSAIM_DIV_46 02385 * @arg @ref LL_RCC_PLLSAIM_DIV_47 02386 * @arg @ref LL_RCC_PLLSAIM_DIV_48 02387 * @arg @ref LL_RCC_PLLSAIM_DIV_49 02388 * @arg @ref LL_RCC_PLLSAIM_DIV_50 02389 * @arg @ref LL_RCC_PLLSAIM_DIV_51 02390 * @arg @ref LL_RCC_PLLSAIM_DIV_52 02391 * @arg @ref LL_RCC_PLLSAIM_DIV_53 02392 * @arg @ref LL_RCC_PLLSAIM_DIV_54 02393 * @arg @ref LL_RCC_PLLSAIM_DIV_55 02394 * @arg @ref LL_RCC_PLLSAIM_DIV_56 02395 * @arg @ref LL_RCC_PLLSAIM_DIV_57 02396 * @arg @ref LL_RCC_PLLSAIM_DIV_58 02397 * @arg @ref LL_RCC_PLLSAIM_DIV_59 02398 * @arg @ref LL_RCC_PLLSAIM_DIV_60 02399 * @arg @ref LL_RCC_PLLSAIM_DIV_61 02400 * @arg @ref LL_RCC_PLLSAIM_DIV_62 02401 * @arg @ref LL_RCC_PLLSAIM_DIV_63 02402 * @param __PLLSAIN__ Between 49/50(*) and 432 02403 * 02404 * (*) value not defined in all devices. 02405 * @param __PLLSAIR__ This parameter can be one of the following values: 02406 * @arg @ref LL_RCC_PLLSAIR_DIV_2 02407 * @arg @ref LL_RCC_PLLSAIR_DIV_3 02408 * @arg @ref LL_RCC_PLLSAIR_DIV_4 02409 * @arg @ref LL_RCC_PLLSAIR_DIV_5 02410 * @arg @ref LL_RCC_PLLSAIR_DIV_6 02411 * @arg @ref LL_RCC_PLLSAIR_DIV_7 02412 * @param __PLLSAIDIVR__ This parameter can be one of the following values: 02413 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 02414 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 02415 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 02416 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 02417 * @retval PLLSAI clock frequency (in Hz) 02418 */ 02419 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \ 02420 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos]))) 02421 #endif /* LTDC */ 02422 #endif /* RCC_PLLSAI_SUPPORT */ 02423 02424 #if defined(RCC_PLLI2S_SUPPORT) 02425 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR) 02426 /** 02427 * @brief Helper macro to calculate the PLLI2S frequency used for SAI domain 02428 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), 02429 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ()); 02430 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02431 * @param __PLLM__ This parameter can be one of the following values: 02432 * @arg @ref LL_RCC_PLLI2SM_DIV_2 02433 * @arg @ref LL_RCC_PLLI2SM_DIV_3 02434 * @arg @ref LL_RCC_PLLI2SM_DIV_4 02435 * @arg @ref LL_RCC_PLLI2SM_DIV_5 02436 * @arg @ref LL_RCC_PLLI2SM_DIV_6 02437 * @arg @ref LL_RCC_PLLI2SM_DIV_7 02438 * @arg @ref LL_RCC_PLLI2SM_DIV_8 02439 * @arg @ref LL_RCC_PLLI2SM_DIV_9 02440 * @arg @ref LL_RCC_PLLI2SM_DIV_10 02441 * @arg @ref LL_RCC_PLLI2SM_DIV_11 02442 * @arg @ref LL_RCC_PLLI2SM_DIV_12 02443 * @arg @ref LL_RCC_PLLI2SM_DIV_13 02444 * @arg @ref LL_RCC_PLLI2SM_DIV_14 02445 * @arg @ref LL_RCC_PLLI2SM_DIV_15 02446 * @arg @ref LL_RCC_PLLI2SM_DIV_16 02447 * @arg @ref LL_RCC_PLLI2SM_DIV_17 02448 * @arg @ref LL_RCC_PLLI2SM_DIV_18 02449 * @arg @ref LL_RCC_PLLI2SM_DIV_19 02450 * @arg @ref LL_RCC_PLLI2SM_DIV_20 02451 * @arg @ref LL_RCC_PLLI2SM_DIV_21 02452 * @arg @ref LL_RCC_PLLI2SM_DIV_22 02453 * @arg @ref LL_RCC_PLLI2SM_DIV_23 02454 * @arg @ref LL_RCC_PLLI2SM_DIV_24 02455 * @arg @ref LL_RCC_PLLI2SM_DIV_25 02456 * @arg @ref LL_RCC_PLLI2SM_DIV_26 02457 * @arg @ref LL_RCC_PLLI2SM_DIV_27 02458 * @arg @ref LL_RCC_PLLI2SM_DIV_28 02459 * @arg @ref LL_RCC_PLLI2SM_DIV_29 02460 * @arg @ref LL_RCC_PLLI2SM_DIV_30 02461 * @arg @ref LL_RCC_PLLI2SM_DIV_31 02462 * @arg @ref LL_RCC_PLLI2SM_DIV_32 02463 * @arg @ref LL_RCC_PLLI2SM_DIV_33 02464 * @arg @ref LL_RCC_PLLI2SM_DIV_34 02465 * @arg @ref LL_RCC_PLLI2SM_DIV_35 02466 * @arg @ref LL_RCC_PLLI2SM_DIV_36 02467 * @arg @ref LL_RCC_PLLI2SM_DIV_37 02468 * @arg @ref LL_RCC_PLLI2SM_DIV_38 02469 * @arg @ref LL_RCC_PLLI2SM_DIV_39 02470 * @arg @ref LL_RCC_PLLI2SM_DIV_40 02471 * @arg @ref LL_RCC_PLLI2SM_DIV_41 02472 * @arg @ref LL_RCC_PLLI2SM_DIV_42 02473 * @arg @ref LL_RCC_PLLI2SM_DIV_43 02474 * @arg @ref LL_RCC_PLLI2SM_DIV_44 02475 * @arg @ref LL_RCC_PLLI2SM_DIV_45 02476 * @arg @ref LL_RCC_PLLI2SM_DIV_46 02477 * @arg @ref LL_RCC_PLLI2SM_DIV_47 02478 * @arg @ref LL_RCC_PLLI2SM_DIV_48 02479 * @arg @ref LL_RCC_PLLI2SM_DIV_49 02480 * @arg @ref LL_RCC_PLLI2SM_DIV_50 02481 * @arg @ref LL_RCC_PLLI2SM_DIV_51 02482 * @arg @ref LL_RCC_PLLI2SM_DIV_52 02483 * @arg @ref LL_RCC_PLLI2SM_DIV_53 02484 * @arg @ref LL_RCC_PLLI2SM_DIV_54 02485 * @arg @ref LL_RCC_PLLI2SM_DIV_55 02486 * @arg @ref LL_RCC_PLLI2SM_DIV_56 02487 * @arg @ref LL_RCC_PLLI2SM_DIV_57 02488 * @arg @ref LL_RCC_PLLI2SM_DIV_58 02489 * @arg @ref LL_RCC_PLLI2SM_DIV_59 02490 * @arg @ref LL_RCC_PLLI2SM_DIV_60 02491 * @arg @ref LL_RCC_PLLI2SM_DIV_61 02492 * @arg @ref LL_RCC_PLLI2SM_DIV_62 02493 * @arg @ref LL_RCC_PLLI2SM_DIV_63 02494 * @param __PLLI2SN__ Between 50/192(*) and 432 02495 * 02496 * (*) value not defined in all devices. 02497 * @param __PLLI2SQ_R__ This parameter can be one of the following values: 02498 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) 02499 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) 02500 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) 02501 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) 02502 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) 02503 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) 02504 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) 02505 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) 02506 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) 02507 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) 02508 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) 02509 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) 02510 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) 02511 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) 02512 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) 02513 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) 02514 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) 02515 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) 02516 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) 02517 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) 02518 * 02519 * (*) value not defined in all devices. 02520 * @param __PLLI2SDIVQ_R__ This parameter can be one of the following values: 02521 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) 02522 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) 02523 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) 02524 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) 02525 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) 02526 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) 02527 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) 02528 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) 02529 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) 02530 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) 02531 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) 02532 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) 02533 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) 02534 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) 02535 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) 02536 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) 02537 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) 02538 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) 02539 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) 02540 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) 02541 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) 02542 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) 02543 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) 02544 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) 02545 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) 02546 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) 02547 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) 02548 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) 02549 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) 02550 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) 02551 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) 02552 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) 02553 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) 02554 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) 02555 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) 02556 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) 02557 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) 02558 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) 02559 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) 02560 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) 02561 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) 02562 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) 02563 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) 02564 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) 02565 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) 02566 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) 02567 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) 02568 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) 02569 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) 02570 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) 02571 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) 02572 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) 02573 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) 02574 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) 02575 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) 02576 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) 02577 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) 02578 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) 02579 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) 02580 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) 02581 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) 02582 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) 02583 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) 02584 * 02585 * (*) value not defined in all devices. 02586 * @retval PLLI2S clock frequency (in Hz) 02587 */ 02588 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 02589 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02590 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U))) 02591 #else 02592 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02593 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos))) 02594 02595 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 02596 #endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */ 02597 02598 #if defined(SPDIFRX) 02599 /** 02600 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain 02601 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), 02602 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ()); 02603 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02604 * @param __PLLM__ This parameter can be one of the following values: 02605 * @arg @ref LL_RCC_PLLI2SM_DIV_2 02606 * @arg @ref LL_RCC_PLLI2SM_DIV_3 02607 * @arg @ref LL_RCC_PLLI2SM_DIV_4 02608 * @arg @ref LL_RCC_PLLI2SM_DIV_5 02609 * @arg @ref LL_RCC_PLLI2SM_DIV_6 02610 * @arg @ref LL_RCC_PLLI2SM_DIV_7 02611 * @arg @ref LL_RCC_PLLI2SM_DIV_8 02612 * @arg @ref LL_RCC_PLLI2SM_DIV_9 02613 * @arg @ref LL_RCC_PLLI2SM_DIV_10 02614 * @arg @ref LL_RCC_PLLI2SM_DIV_11 02615 * @arg @ref LL_RCC_PLLI2SM_DIV_12 02616 * @arg @ref LL_RCC_PLLI2SM_DIV_13 02617 * @arg @ref LL_RCC_PLLI2SM_DIV_14 02618 * @arg @ref LL_RCC_PLLI2SM_DIV_15 02619 * @arg @ref LL_RCC_PLLI2SM_DIV_16 02620 * @arg @ref LL_RCC_PLLI2SM_DIV_17 02621 * @arg @ref LL_RCC_PLLI2SM_DIV_18 02622 * @arg @ref LL_RCC_PLLI2SM_DIV_19 02623 * @arg @ref LL_RCC_PLLI2SM_DIV_20 02624 * @arg @ref LL_RCC_PLLI2SM_DIV_21 02625 * @arg @ref LL_RCC_PLLI2SM_DIV_22 02626 * @arg @ref LL_RCC_PLLI2SM_DIV_23 02627 * @arg @ref LL_RCC_PLLI2SM_DIV_24 02628 * @arg @ref LL_RCC_PLLI2SM_DIV_25 02629 * @arg @ref LL_RCC_PLLI2SM_DIV_26 02630 * @arg @ref LL_RCC_PLLI2SM_DIV_27 02631 * @arg @ref LL_RCC_PLLI2SM_DIV_28 02632 * @arg @ref LL_RCC_PLLI2SM_DIV_29 02633 * @arg @ref LL_RCC_PLLI2SM_DIV_30 02634 * @arg @ref LL_RCC_PLLI2SM_DIV_31 02635 * @arg @ref LL_RCC_PLLI2SM_DIV_32 02636 * @arg @ref LL_RCC_PLLI2SM_DIV_33 02637 * @arg @ref LL_RCC_PLLI2SM_DIV_34 02638 * @arg @ref LL_RCC_PLLI2SM_DIV_35 02639 * @arg @ref LL_RCC_PLLI2SM_DIV_36 02640 * @arg @ref LL_RCC_PLLI2SM_DIV_37 02641 * @arg @ref LL_RCC_PLLI2SM_DIV_38 02642 * @arg @ref LL_RCC_PLLI2SM_DIV_39 02643 * @arg @ref LL_RCC_PLLI2SM_DIV_40 02644 * @arg @ref LL_RCC_PLLI2SM_DIV_41 02645 * @arg @ref LL_RCC_PLLI2SM_DIV_42 02646 * @arg @ref LL_RCC_PLLI2SM_DIV_43 02647 * @arg @ref LL_RCC_PLLI2SM_DIV_44 02648 * @arg @ref LL_RCC_PLLI2SM_DIV_45 02649 * @arg @ref LL_RCC_PLLI2SM_DIV_46 02650 * @arg @ref LL_RCC_PLLI2SM_DIV_47 02651 * @arg @ref LL_RCC_PLLI2SM_DIV_48 02652 * @arg @ref LL_RCC_PLLI2SM_DIV_49 02653 * @arg @ref LL_RCC_PLLI2SM_DIV_50 02654 * @arg @ref LL_RCC_PLLI2SM_DIV_51 02655 * @arg @ref LL_RCC_PLLI2SM_DIV_52 02656 * @arg @ref LL_RCC_PLLI2SM_DIV_53 02657 * @arg @ref LL_RCC_PLLI2SM_DIV_54 02658 * @arg @ref LL_RCC_PLLI2SM_DIV_55 02659 * @arg @ref LL_RCC_PLLI2SM_DIV_56 02660 * @arg @ref LL_RCC_PLLI2SM_DIV_57 02661 * @arg @ref LL_RCC_PLLI2SM_DIV_58 02662 * @arg @ref LL_RCC_PLLI2SM_DIV_59 02663 * @arg @ref LL_RCC_PLLI2SM_DIV_60 02664 * @arg @ref LL_RCC_PLLI2SM_DIV_61 02665 * @arg @ref LL_RCC_PLLI2SM_DIV_62 02666 * @arg @ref LL_RCC_PLLI2SM_DIV_63 02667 * @param __PLLI2SN__ Between 50 and 432 02668 * @param __PLLI2SP__ This parameter can be one of the following values: 02669 * @arg @ref LL_RCC_PLLI2SP_DIV_2 02670 * @arg @ref LL_RCC_PLLI2SP_DIV_4 02671 * @arg @ref LL_RCC_PLLI2SP_DIV_6 02672 * @arg @ref LL_RCC_PLLI2SP_DIV_8 02673 * @retval PLLI2S clock frequency (in Hz) 02674 */ 02675 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02676 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U)) 02677 02678 #endif /* SPDIFRX */ 02679 02680 /** 02681 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain 02682 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), 02683 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ()); 02684 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02685 * @param __PLLM__ This parameter can be one of the following values: 02686 * @arg @ref LL_RCC_PLLI2SM_DIV_2 02687 * @arg @ref LL_RCC_PLLI2SM_DIV_3 02688 * @arg @ref LL_RCC_PLLI2SM_DIV_4 02689 * @arg @ref LL_RCC_PLLI2SM_DIV_5 02690 * @arg @ref LL_RCC_PLLI2SM_DIV_6 02691 * @arg @ref LL_RCC_PLLI2SM_DIV_7 02692 * @arg @ref LL_RCC_PLLI2SM_DIV_8 02693 * @arg @ref LL_RCC_PLLI2SM_DIV_9 02694 * @arg @ref LL_RCC_PLLI2SM_DIV_10 02695 * @arg @ref LL_RCC_PLLI2SM_DIV_11 02696 * @arg @ref LL_RCC_PLLI2SM_DIV_12 02697 * @arg @ref LL_RCC_PLLI2SM_DIV_13 02698 * @arg @ref LL_RCC_PLLI2SM_DIV_14 02699 * @arg @ref LL_RCC_PLLI2SM_DIV_15 02700 * @arg @ref LL_RCC_PLLI2SM_DIV_16 02701 * @arg @ref LL_RCC_PLLI2SM_DIV_17 02702 * @arg @ref LL_RCC_PLLI2SM_DIV_18 02703 * @arg @ref LL_RCC_PLLI2SM_DIV_19 02704 * @arg @ref LL_RCC_PLLI2SM_DIV_20 02705 * @arg @ref LL_RCC_PLLI2SM_DIV_21 02706 * @arg @ref LL_RCC_PLLI2SM_DIV_22 02707 * @arg @ref LL_RCC_PLLI2SM_DIV_23 02708 * @arg @ref LL_RCC_PLLI2SM_DIV_24 02709 * @arg @ref LL_RCC_PLLI2SM_DIV_25 02710 * @arg @ref LL_RCC_PLLI2SM_DIV_26 02711 * @arg @ref LL_RCC_PLLI2SM_DIV_27 02712 * @arg @ref LL_RCC_PLLI2SM_DIV_28 02713 * @arg @ref LL_RCC_PLLI2SM_DIV_29 02714 * @arg @ref LL_RCC_PLLI2SM_DIV_30 02715 * @arg @ref LL_RCC_PLLI2SM_DIV_31 02716 * @arg @ref LL_RCC_PLLI2SM_DIV_32 02717 * @arg @ref LL_RCC_PLLI2SM_DIV_33 02718 * @arg @ref LL_RCC_PLLI2SM_DIV_34 02719 * @arg @ref LL_RCC_PLLI2SM_DIV_35 02720 * @arg @ref LL_RCC_PLLI2SM_DIV_36 02721 * @arg @ref LL_RCC_PLLI2SM_DIV_37 02722 * @arg @ref LL_RCC_PLLI2SM_DIV_38 02723 * @arg @ref LL_RCC_PLLI2SM_DIV_39 02724 * @arg @ref LL_RCC_PLLI2SM_DIV_40 02725 * @arg @ref LL_RCC_PLLI2SM_DIV_41 02726 * @arg @ref LL_RCC_PLLI2SM_DIV_42 02727 * @arg @ref LL_RCC_PLLI2SM_DIV_43 02728 * @arg @ref LL_RCC_PLLI2SM_DIV_44 02729 * @arg @ref LL_RCC_PLLI2SM_DIV_45 02730 * @arg @ref LL_RCC_PLLI2SM_DIV_46 02731 * @arg @ref LL_RCC_PLLI2SM_DIV_47 02732 * @arg @ref LL_RCC_PLLI2SM_DIV_48 02733 * @arg @ref LL_RCC_PLLI2SM_DIV_49 02734 * @arg @ref LL_RCC_PLLI2SM_DIV_50 02735 * @arg @ref LL_RCC_PLLI2SM_DIV_51 02736 * @arg @ref LL_RCC_PLLI2SM_DIV_52 02737 * @arg @ref LL_RCC_PLLI2SM_DIV_53 02738 * @arg @ref LL_RCC_PLLI2SM_DIV_54 02739 * @arg @ref LL_RCC_PLLI2SM_DIV_55 02740 * @arg @ref LL_RCC_PLLI2SM_DIV_56 02741 * @arg @ref LL_RCC_PLLI2SM_DIV_57 02742 * @arg @ref LL_RCC_PLLI2SM_DIV_58 02743 * @arg @ref LL_RCC_PLLI2SM_DIV_59 02744 * @arg @ref LL_RCC_PLLI2SM_DIV_60 02745 * @arg @ref LL_RCC_PLLI2SM_DIV_61 02746 * @arg @ref LL_RCC_PLLI2SM_DIV_62 02747 * @arg @ref LL_RCC_PLLI2SM_DIV_63 02748 * @param __PLLI2SN__ Between 50/192(*) and 432 02749 * 02750 * (*) value not defined in all devices. 02751 * @param __PLLI2SR__ This parameter can be one of the following values: 02752 * @arg @ref LL_RCC_PLLI2SR_DIV_2 02753 * @arg @ref LL_RCC_PLLI2SR_DIV_3 02754 * @arg @ref LL_RCC_PLLI2SR_DIV_4 02755 * @arg @ref LL_RCC_PLLI2SR_DIV_5 02756 * @arg @ref LL_RCC_PLLI2SR_DIV_6 02757 * @arg @ref LL_RCC_PLLI2SR_DIV_7 02758 * @retval PLLI2S clock frequency (in Hz) 02759 */ 02760 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02761 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos)) 02762 02763 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 02764 /** 02765 * @brief Helper macro to calculate the PLLI2S frequency used for 48Mhz domain 02766 * @note ex: @ref __LL_RCC_CALC_PLLI2S_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLI2S_GetDivider (), 02767 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ ()); 02768 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) 02769 * @param __PLLM__ This parameter can be one of the following values: 02770 * @arg @ref LL_RCC_PLLI2SM_DIV_2 02771 * @arg @ref LL_RCC_PLLI2SM_DIV_3 02772 * @arg @ref LL_RCC_PLLI2SM_DIV_4 02773 * @arg @ref LL_RCC_PLLI2SM_DIV_5 02774 * @arg @ref LL_RCC_PLLI2SM_DIV_6 02775 * @arg @ref LL_RCC_PLLI2SM_DIV_7 02776 * @arg @ref LL_RCC_PLLI2SM_DIV_8 02777 * @arg @ref LL_RCC_PLLI2SM_DIV_9 02778 * @arg @ref LL_RCC_PLLI2SM_DIV_10 02779 * @arg @ref LL_RCC_PLLI2SM_DIV_11 02780 * @arg @ref LL_RCC_PLLI2SM_DIV_12 02781 * @arg @ref LL_RCC_PLLI2SM_DIV_13 02782 * @arg @ref LL_RCC_PLLI2SM_DIV_14 02783 * @arg @ref LL_RCC_PLLI2SM_DIV_15 02784 * @arg @ref LL_RCC_PLLI2SM_DIV_16 02785 * @arg @ref LL_RCC_PLLI2SM_DIV_17 02786 * @arg @ref LL_RCC_PLLI2SM_DIV_18 02787 * @arg @ref LL_RCC_PLLI2SM_DIV_19 02788 * @arg @ref LL_RCC_PLLI2SM_DIV_20 02789 * @arg @ref LL_RCC_PLLI2SM_DIV_21 02790 * @arg @ref LL_RCC_PLLI2SM_DIV_22 02791 * @arg @ref LL_RCC_PLLI2SM_DIV_23 02792 * @arg @ref LL_RCC_PLLI2SM_DIV_24 02793 * @arg @ref LL_RCC_PLLI2SM_DIV_25 02794 * @arg @ref LL_RCC_PLLI2SM_DIV_26 02795 * @arg @ref LL_RCC_PLLI2SM_DIV_27 02796 * @arg @ref LL_RCC_PLLI2SM_DIV_28 02797 * @arg @ref LL_RCC_PLLI2SM_DIV_29 02798 * @arg @ref LL_RCC_PLLI2SM_DIV_30 02799 * @arg @ref LL_RCC_PLLI2SM_DIV_31 02800 * @arg @ref LL_RCC_PLLI2SM_DIV_32 02801 * @arg @ref LL_RCC_PLLI2SM_DIV_33 02802 * @arg @ref LL_RCC_PLLI2SM_DIV_34 02803 * @arg @ref LL_RCC_PLLI2SM_DIV_35 02804 * @arg @ref LL_RCC_PLLI2SM_DIV_36 02805 * @arg @ref LL_RCC_PLLI2SM_DIV_37 02806 * @arg @ref LL_RCC_PLLI2SM_DIV_38 02807 * @arg @ref LL_RCC_PLLI2SM_DIV_39 02808 * @arg @ref LL_RCC_PLLI2SM_DIV_40 02809 * @arg @ref LL_RCC_PLLI2SM_DIV_41 02810 * @arg @ref LL_RCC_PLLI2SM_DIV_42 02811 * @arg @ref LL_RCC_PLLI2SM_DIV_43 02812 * @arg @ref LL_RCC_PLLI2SM_DIV_44 02813 * @arg @ref LL_RCC_PLLI2SM_DIV_45 02814 * @arg @ref LL_RCC_PLLI2SM_DIV_46 02815 * @arg @ref LL_RCC_PLLI2SM_DIV_47 02816 * @arg @ref LL_RCC_PLLI2SM_DIV_48 02817 * @arg @ref LL_RCC_PLLI2SM_DIV_49 02818 * @arg @ref LL_RCC_PLLI2SM_DIV_50 02819 * @arg @ref LL_RCC_PLLI2SM_DIV_51 02820 * @arg @ref LL_RCC_PLLI2SM_DIV_52 02821 * @arg @ref LL_RCC_PLLI2SM_DIV_53 02822 * @arg @ref LL_RCC_PLLI2SM_DIV_54 02823 * @arg @ref LL_RCC_PLLI2SM_DIV_55 02824 * @arg @ref LL_RCC_PLLI2SM_DIV_56 02825 * @arg @ref LL_RCC_PLLI2SM_DIV_57 02826 * @arg @ref LL_RCC_PLLI2SM_DIV_58 02827 * @arg @ref LL_RCC_PLLI2SM_DIV_59 02828 * @arg @ref LL_RCC_PLLI2SM_DIV_60 02829 * @arg @ref LL_RCC_PLLI2SM_DIV_61 02830 * @arg @ref LL_RCC_PLLI2SM_DIV_62 02831 * @arg @ref LL_RCC_PLLI2SM_DIV_63 02832 * @param __PLLI2SN__ Between 50 and 432 02833 * @param __PLLI2SQ__ This parameter can be one of the following values: 02834 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 02835 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 02836 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 02837 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 02838 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 02839 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 02840 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 02841 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 02842 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 02843 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 02844 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 02845 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 02846 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 02847 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 02848 * @retval PLLI2S clock frequency (in Hz) 02849 */ 02850 #define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \ 02851 ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos)) 02852 02853 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 02854 #endif /* RCC_PLLI2S_SUPPORT */ 02855 02856 /** 02857 * @brief Helper macro to calculate the HCLK frequency 02858 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK) 02859 * @param __AHBPRESCALER__ This parameter can be one of the following values: 02860 * @arg @ref LL_RCC_SYSCLK_DIV_1 02861 * @arg @ref LL_RCC_SYSCLK_DIV_2 02862 * @arg @ref LL_RCC_SYSCLK_DIV_4 02863 * @arg @ref LL_RCC_SYSCLK_DIV_8 02864 * @arg @ref LL_RCC_SYSCLK_DIV_16 02865 * @arg @ref LL_RCC_SYSCLK_DIV_64 02866 * @arg @ref LL_RCC_SYSCLK_DIV_128 02867 * @arg @ref LL_RCC_SYSCLK_DIV_256 02868 * @arg @ref LL_RCC_SYSCLK_DIV_512 02869 * @retval HCLK clock frequency (in Hz) 02870 */ 02871 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) 02872 02873 /** 02874 * @brief Helper macro to calculate the PCLK1 frequency (ABP1) 02875 * @param __HCLKFREQ__ HCLK frequency 02876 * @param __APB1PRESCALER__ This parameter can be one of the following values: 02877 * @arg @ref LL_RCC_APB1_DIV_1 02878 * @arg @ref LL_RCC_APB1_DIV_2 02879 * @arg @ref LL_RCC_APB1_DIV_4 02880 * @arg @ref LL_RCC_APB1_DIV_8 02881 * @arg @ref LL_RCC_APB1_DIV_16 02882 * @retval PCLK1 clock frequency (in Hz) 02883 */ 02884 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) 02885 02886 /** 02887 * @brief Helper macro to calculate the PCLK2 frequency (ABP2) 02888 * @param __HCLKFREQ__ HCLK frequency 02889 * @param __APB2PRESCALER__ This parameter can be one of the following values: 02890 * @arg @ref LL_RCC_APB2_DIV_1 02891 * @arg @ref LL_RCC_APB2_DIV_2 02892 * @arg @ref LL_RCC_APB2_DIV_4 02893 * @arg @ref LL_RCC_APB2_DIV_8 02894 * @arg @ref LL_RCC_APB2_DIV_16 02895 * @retval PCLK2 clock frequency (in Hz) 02896 */ 02897 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) 02898 02899 /** 02900 * @} 02901 */ 02902 02903 /** 02904 * @} 02905 */ 02906 02907 /* Exported functions --------------------------------------------------------*/ 02908 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions 02909 * @{ 02910 */ 02911 02912 /** @defgroup RCC_LL_EF_HSE HSE 02913 * @{ 02914 */ 02915 02916 /** 02917 * @brief Enable the Clock Security System. 02918 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS 02919 * @retval None 02920 */ 02921 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) 02922 { 02923 SET_BIT(RCC->CR, RCC_CR_CSSON); 02924 } 02925 02926 /** 02927 * @brief Enable HSE external oscillator (HSE Bypass) 02928 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass 02929 * @retval None 02930 */ 02931 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) 02932 { 02933 SET_BIT(RCC->CR, RCC_CR_HSEBYP); 02934 } 02935 02936 /** 02937 * @brief Disable HSE external oscillator (HSE Bypass) 02938 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass 02939 * @retval None 02940 */ 02941 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) 02942 { 02943 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); 02944 } 02945 02946 /** 02947 * @brief Enable HSE crystal oscillator (HSE ON) 02948 * @rmtoll CR HSEON LL_RCC_HSE_Enable 02949 * @retval None 02950 */ 02951 __STATIC_INLINE void LL_RCC_HSE_Enable(void) 02952 { 02953 SET_BIT(RCC->CR, RCC_CR_HSEON); 02954 } 02955 02956 /** 02957 * @brief Disable HSE crystal oscillator (HSE ON) 02958 * @rmtoll CR HSEON LL_RCC_HSE_Disable 02959 * @retval None 02960 */ 02961 __STATIC_INLINE void LL_RCC_HSE_Disable(void) 02962 { 02963 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); 02964 } 02965 02966 /** 02967 * @brief Check if HSE oscillator Ready 02968 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady 02969 * @retval State of bit (1 or 0). 02970 */ 02971 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) 02972 { 02973 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)); 02974 } 02975 02976 /** 02977 * @} 02978 */ 02979 02980 /** @defgroup RCC_LL_EF_HSI HSI 02981 * @{ 02982 */ 02983 02984 /** 02985 * @brief Enable HSI oscillator 02986 * @rmtoll CR HSION LL_RCC_HSI_Enable 02987 * @retval None 02988 */ 02989 __STATIC_INLINE void LL_RCC_HSI_Enable(void) 02990 { 02991 SET_BIT(RCC->CR, RCC_CR_HSION); 02992 } 02993 02994 /** 02995 * @brief Disable HSI oscillator 02996 * @rmtoll CR HSION LL_RCC_HSI_Disable 02997 * @retval None 02998 */ 02999 __STATIC_INLINE void LL_RCC_HSI_Disable(void) 03000 { 03001 CLEAR_BIT(RCC->CR, RCC_CR_HSION); 03002 } 03003 03004 /** 03005 * @brief Check if HSI clock is ready 03006 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady 03007 * @retval State of bit (1 or 0). 03008 */ 03009 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) 03010 { 03011 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)); 03012 } 03013 03014 /** 03015 * @brief Get HSI Calibration value 03016 * @note When HSITRIM is written, HSICAL is updated with the sum of 03017 * HSITRIM and the factory trim value 03018 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration 03019 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF 03020 */ 03021 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) 03022 { 03023 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos); 03024 } 03025 03026 /** 03027 * @brief Set HSI Calibration trimming 03028 * @note user-programmable trimming value that is added to the HSICAL 03029 * @note Default value is 16, which, when added to the HSICAL value, 03030 * should trim the HSI to 16 MHz +/- 1 % 03031 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming 03032 * @param Value Between Min_Data = 0 and Max_Data = 31 03033 * @retval None 03034 */ 03035 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) 03036 { 03037 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos); 03038 } 03039 03040 /** 03041 * @brief Get HSI Calibration trimming 03042 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming 03043 * @retval Between Min_Data = 0 and Max_Data = 31 03044 */ 03045 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) 03046 { 03047 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos); 03048 } 03049 03050 /** 03051 * @} 03052 */ 03053 03054 /** @defgroup RCC_LL_EF_LSE LSE 03055 * @{ 03056 */ 03057 03058 /** 03059 * @brief Enable Low Speed External (LSE) crystal. 03060 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable 03061 * @retval None 03062 */ 03063 __STATIC_INLINE void LL_RCC_LSE_Enable(void) 03064 { 03065 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); 03066 } 03067 03068 /** 03069 * @brief Disable Low Speed External (LSE) crystal. 03070 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable 03071 * @retval None 03072 */ 03073 __STATIC_INLINE void LL_RCC_LSE_Disable(void) 03074 { 03075 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); 03076 } 03077 03078 /** 03079 * @brief Enable external clock source (LSE bypass). 03080 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass 03081 * @retval None 03082 */ 03083 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) 03084 { 03085 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 03086 } 03087 03088 /** 03089 * @brief Disable external clock source (LSE bypass). 03090 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass 03091 * @retval None 03092 */ 03093 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) 03094 { 03095 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); 03096 } 03097 03098 /** 03099 * @brief Check if LSE oscillator Ready 03100 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady 03101 * @retval State of bit (1 or 0). 03102 */ 03103 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) 03104 { 03105 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)); 03106 } 03107 03108 #if defined(RCC_BDCR_LSEMOD) 03109 /** 03110 * @brief Enable LSE high drive mode. 03111 * @note LSE high drive mode can be enabled only when the LSE clock is disabled 03112 * @rmtoll BDCR LSEMOD LL_RCC_LSE_EnableHighDriveMode 03113 * @retval None 03114 */ 03115 __STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void) 03116 { 03117 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); 03118 } 03119 03120 /** 03121 * @brief Disable LSE high drive mode. 03122 * @note LSE high drive mode can be disabled only when the LSE clock is disabled 03123 * @rmtoll BDCR LSEMOD LL_RCC_LSE_DisableHighDriveMode 03124 * @retval None 03125 */ 03126 __STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void) 03127 { 03128 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD); 03129 } 03130 #endif /* RCC_BDCR_LSEMOD */ 03131 03132 /** 03133 * @} 03134 */ 03135 03136 /** @defgroup RCC_LL_EF_LSI LSI 03137 * @{ 03138 */ 03139 03140 /** 03141 * @brief Enable LSI Oscillator 03142 * @rmtoll CSR LSION LL_RCC_LSI_Enable 03143 * @retval None 03144 */ 03145 __STATIC_INLINE void LL_RCC_LSI_Enable(void) 03146 { 03147 SET_BIT(RCC->CSR, RCC_CSR_LSION); 03148 } 03149 03150 /** 03151 * @brief Disable LSI Oscillator 03152 * @rmtoll CSR LSION LL_RCC_LSI_Disable 03153 * @retval None 03154 */ 03155 __STATIC_INLINE void LL_RCC_LSI_Disable(void) 03156 { 03157 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); 03158 } 03159 03160 /** 03161 * @brief Check if LSI is Ready 03162 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady 03163 * @retval State of bit (1 or 0). 03164 */ 03165 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) 03166 { 03167 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)); 03168 } 03169 03170 /** 03171 * @} 03172 */ 03173 03174 /** @defgroup RCC_LL_EF_System System 03175 * @{ 03176 */ 03177 03178 /** 03179 * @brief Configure the system clock source 03180 * @rmtoll CFGR SW LL_RCC_SetSysClkSource 03181 * @param Source This parameter can be one of the following values: 03182 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI 03183 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE 03184 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL 03185 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLLR (*) 03186 * 03187 * (*) value not defined in all devices. 03188 * @retval None 03189 */ 03190 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) 03191 { 03192 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); 03193 } 03194 03195 /** 03196 * @brief Get the system clock source 03197 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource 03198 * @retval Returned value can be one of the following values: 03199 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI 03200 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE 03201 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL 03202 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLLR (*) 03203 * 03204 * (*) value not defined in all devices. 03205 */ 03206 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) 03207 { 03208 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); 03209 } 03210 03211 /** 03212 * @brief Set AHB prescaler 03213 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler 03214 * @param Prescaler This parameter can be one of the following values: 03215 * @arg @ref LL_RCC_SYSCLK_DIV_1 03216 * @arg @ref LL_RCC_SYSCLK_DIV_2 03217 * @arg @ref LL_RCC_SYSCLK_DIV_4 03218 * @arg @ref LL_RCC_SYSCLK_DIV_8 03219 * @arg @ref LL_RCC_SYSCLK_DIV_16 03220 * @arg @ref LL_RCC_SYSCLK_DIV_64 03221 * @arg @ref LL_RCC_SYSCLK_DIV_128 03222 * @arg @ref LL_RCC_SYSCLK_DIV_256 03223 * @arg @ref LL_RCC_SYSCLK_DIV_512 03224 * @retval None 03225 */ 03226 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) 03227 { 03228 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); 03229 } 03230 03231 /** 03232 * @brief Set APB1 prescaler 03233 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler 03234 * @param Prescaler This parameter can be one of the following values: 03235 * @arg @ref LL_RCC_APB1_DIV_1 03236 * @arg @ref LL_RCC_APB1_DIV_2 03237 * @arg @ref LL_RCC_APB1_DIV_4 03238 * @arg @ref LL_RCC_APB1_DIV_8 03239 * @arg @ref LL_RCC_APB1_DIV_16 03240 * @retval None 03241 */ 03242 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) 03243 { 03244 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); 03245 } 03246 03247 /** 03248 * @brief Set APB2 prescaler 03249 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler 03250 * @param Prescaler This parameter can be one of the following values: 03251 * @arg @ref LL_RCC_APB2_DIV_1 03252 * @arg @ref LL_RCC_APB2_DIV_2 03253 * @arg @ref LL_RCC_APB2_DIV_4 03254 * @arg @ref LL_RCC_APB2_DIV_8 03255 * @arg @ref LL_RCC_APB2_DIV_16 03256 * @retval None 03257 */ 03258 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) 03259 { 03260 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); 03261 } 03262 03263 /** 03264 * @brief Get AHB prescaler 03265 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler 03266 * @retval Returned value can be one of the following values: 03267 * @arg @ref LL_RCC_SYSCLK_DIV_1 03268 * @arg @ref LL_RCC_SYSCLK_DIV_2 03269 * @arg @ref LL_RCC_SYSCLK_DIV_4 03270 * @arg @ref LL_RCC_SYSCLK_DIV_8 03271 * @arg @ref LL_RCC_SYSCLK_DIV_16 03272 * @arg @ref LL_RCC_SYSCLK_DIV_64 03273 * @arg @ref LL_RCC_SYSCLK_DIV_128 03274 * @arg @ref LL_RCC_SYSCLK_DIV_256 03275 * @arg @ref LL_RCC_SYSCLK_DIV_512 03276 */ 03277 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) 03278 { 03279 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); 03280 } 03281 03282 /** 03283 * @brief Get APB1 prescaler 03284 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler 03285 * @retval Returned value can be one of the following values: 03286 * @arg @ref LL_RCC_APB1_DIV_1 03287 * @arg @ref LL_RCC_APB1_DIV_2 03288 * @arg @ref LL_RCC_APB1_DIV_4 03289 * @arg @ref LL_RCC_APB1_DIV_8 03290 * @arg @ref LL_RCC_APB1_DIV_16 03291 */ 03292 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) 03293 { 03294 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); 03295 } 03296 03297 /** 03298 * @brief Get APB2 prescaler 03299 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler 03300 * @retval Returned value can be one of the following values: 03301 * @arg @ref LL_RCC_APB2_DIV_1 03302 * @arg @ref LL_RCC_APB2_DIV_2 03303 * @arg @ref LL_RCC_APB2_DIV_4 03304 * @arg @ref LL_RCC_APB2_DIV_8 03305 * @arg @ref LL_RCC_APB2_DIV_16 03306 */ 03307 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) 03308 { 03309 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); 03310 } 03311 03312 /** 03313 * @} 03314 */ 03315 03316 /** @defgroup RCC_LL_EF_MCO MCO 03317 * @{ 03318 */ 03319 03320 #if defined(RCC_CFGR_MCO1EN) 03321 /** 03322 * @brief Enable MCO1 output 03323 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Enable 03324 * @retval None 03325 */ 03326 __STATIC_INLINE void LL_RCC_MCO1_Enable(void) 03327 { 03328 SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); 03329 } 03330 03331 /** 03332 * @brief Disable MCO1 output 03333 * @rmtoll CFGR RCC_CFGR_MCO1EN LL_RCC_MCO1_Disable 03334 * @retval None 03335 */ 03336 __STATIC_INLINE void LL_RCC_MCO1_Disable(void) 03337 { 03338 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN); 03339 } 03340 #endif /* RCC_CFGR_MCO1EN */ 03341 03342 #if defined(RCC_CFGR_MCO2EN) 03343 /** 03344 * @brief Enable MCO2 output 03345 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Enable 03346 * @retval None 03347 */ 03348 __STATIC_INLINE void LL_RCC_MCO2_Enable(void) 03349 { 03350 SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); 03351 } 03352 03353 /** 03354 * @brief Disable MCO2 output 03355 * @rmtoll CFGR RCC_CFGR_MCO2EN LL_RCC_MCO2_Disable 03356 * @retval None 03357 */ 03358 __STATIC_INLINE void LL_RCC_MCO2_Disable(void) 03359 { 03360 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN); 03361 } 03362 #endif /* RCC_CFGR_MCO2EN */ 03363 03364 /** 03365 * @brief Configure MCOx 03366 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n 03367 * CFGR MCO1PRE LL_RCC_ConfigMCO\n 03368 * CFGR MCO2 LL_RCC_ConfigMCO\n 03369 * CFGR MCO2PRE LL_RCC_ConfigMCO 03370 * @param MCOxSource This parameter can be one of the following values: 03371 * @arg @ref LL_RCC_MCO1SOURCE_HSI 03372 * @arg @ref LL_RCC_MCO1SOURCE_LSE 03373 * @arg @ref LL_RCC_MCO1SOURCE_HSE 03374 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK 03375 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK 03376 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S 03377 * @arg @ref LL_RCC_MCO2SOURCE_HSE 03378 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK 03379 * @param MCOxPrescaler This parameter can be one of the following values: 03380 * @arg @ref LL_RCC_MCO1_DIV_1 03381 * @arg @ref LL_RCC_MCO1_DIV_2 03382 * @arg @ref LL_RCC_MCO1_DIV_3 03383 * @arg @ref LL_RCC_MCO1_DIV_4 03384 * @arg @ref LL_RCC_MCO1_DIV_5 03385 * @arg @ref LL_RCC_MCO2_DIV_1 03386 * @arg @ref LL_RCC_MCO2_DIV_2 03387 * @arg @ref LL_RCC_MCO2_DIV_3 03388 * @arg @ref LL_RCC_MCO2_DIV_4 03389 * @arg @ref LL_RCC_MCO2_DIV_5 03390 * @retval None 03391 */ 03392 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) 03393 { 03394 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U)); 03395 } 03396 03397 /** 03398 * @} 03399 */ 03400 03401 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source 03402 * @{ 03403 */ 03404 #if defined(FMPI2C1) 03405 /** 03406 * @brief Configure FMPI2C clock source 03407 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_SetFMPI2CClockSource 03408 * @param FMPI2CxSource This parameter can be one of the following values: 03409 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 03410 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK 03411 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI 03412 * @retval None 03413 */ 03414 __STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource) 03415 { 03416 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource); 03417 } 03418 #endif /* FMPI2C1 */ 03419 03420 #if defined(LPTIM1) 03421 /** 03422 * @brief Configure LPTIMx clock source 03423 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource 03424 * @param LPTIMxSource This parameter can be one of the following values: 03425 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03426 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 03427 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03428 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03429 * @retval None 03430 */ 03431 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) 03432 { 03433 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); 03434 } 03435 #endif /* LPTIM1 */ 03436 03437 #if defined(SAI1) 03438 /** 03439 * @brief Configure SAIx clock source 03440 * @rmtoll DCKCFGR SAI1SRC LL_RCC_SetSAIClockSource\n 03441 * DCKCFGR SAI2SRC LL_RCC_SetSAIClockSource\n 03442 * DCKCFGR SAI1ASRC LL_RCC_SetSAIClockSource\n 03443 * DCKCFGR SAI1BSRC LL_RCC_SetSAIClockSource 03444 * @param SAIxSource This parameter can be one of the following values: 03445 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) 03446 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) 03447 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) 03448 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) 03449 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) 03450 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) 03451 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 03452 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) 03453 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) 03454 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) 03455 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) 03456 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) 03457 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) 03458 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) 03459 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) 03460 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) 03461 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) 03462 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) 03463 * 03464 * (*) value not defined in all devices. 03465 * @retval None 03466 */ 03467 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) 03468 { 03469 MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U)); 03470 } 03471 #endif /* SAI1 */ 03472 03473 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) 03474 /** 03475 * @brief Configure SDIO clock source 03476 * @rmtoll DCKCFGR SDIOSEL LL_RCC_SetSDIOClockSource\n 03477 * DCKCFGR2 SDIOSEL LL_RCC_SetSDIOClockSource 03478 * @param SDIOxSource This parameter can be one of the following values: 03479 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK 03480 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK 03481 * @retval None 03482 */ 03483 __STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource) 03484 { 03485 #if defined(RCC_DCKCFGR_SDIOSEL) 03486 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource); 03487 #else 03488 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource); 03489 #endif /* RCC_DCKCFGR_SDIOSEL */ 03490 } 03491 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ 03492 03493 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 03494 /** 03495 * @brief Configure 48Mhz domain clock source 03496 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetCK48MClockSource\n 03497 * DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource 03498 * @param CK48MxSource This parameter can be one of the following values: 03499 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL 03500 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) 03501 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) 03502 * 03503 * (*) value not defined in all devices. 03504 * @retval None 03505 */ 03506 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource) 03507 { 03508 #if defined(RCC_DCKCFGR_CK48MSEL) 03509 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource); 03510 #else 03511 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); 03512 #endif /* RCC_DCKCFGR_CK48MSEL */ 03513 } 03514 03515 #if defined(RNG) 03516 /** 03517 * @brief Configure RNG clock source 03518 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetRNGClockSource\n 03519 * DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource 03520 * @param RNGxSource This parameter can be one of the following values: 03521 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 03522 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) 03523 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) 03524 * 03525 * (*) value not defined in all devices. 03526 * @retval None 03527 */ 03528 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) 03529 { 03530 #if defined(RCC_DCKCFGR_CK48MSEL) 03531 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource); 03532 #else 03533 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); 03534 #endif /* RCC_DCKCFGR_CK48MSEL */ 03535 } 03536 #endif /* RNG */ 03537 03538 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 03539 /** 03540 * @brief Configure USB clock source 03541 * @rmtoll DCKCFGR CK48MSEL LL_RCC_SetUSBClockSource\n 03542 * DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource 03543 * @param USBxSource This parameter can be one of the following values: 03544 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 03545 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) 03546 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) 03547 * 03548 * (*) value not defined in all devices. 03549 * @retval None 03550 */ 03551 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) 03552 { 03553 #if defined(RCC_DCKCFGR_CK48MSEL) 03554 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource); 03555 #else 03556 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); 03557 #endif /* RCC_DCKCFGR_CK48MSEL */ 03558 } 03559 #endif /* USB_OTG_FS || USB_OTG_HS */ 03560 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 03561 03562 #if defined(CEC) 03563 /** 03564 * @brief Configure CEC clock source 03565 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource 03566 * @param Source This parameter can be one of the following values: 03567 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 03568 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE 03569 * @retval None 03570 */ 03571 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source) 03572 { 03573 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); 03574 } 03575 #endif /* CEC */ 03576 03577 /** 03578 * @brief Configure I2S clock source 03579 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource\n 03580 * DCKCFGR I2SSRC LL_RCC_SetI2SClockSource\n 03581 * DCKCFGR I2S1SRC LL_RCC_SetI2SClockSource\n 03582 * DCKCFGR I2S2SRC LL_RCC_SetI2SClockSource 03583 * @param Source This parameter can be one of the following values: 03584 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) 03585 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN 03586 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) 03587 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) 03588 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) 03589 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) 03590 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) 03591 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) 03592 * 03593 * (*) value not defined in all devices. 03594 * @retval None 03595 */ 03596 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source) 03597 { 03598 #if defined(RCC_CFGR_I2SSRC) 03599 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source); 03600 #else 03601 MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U)); 03602 #endif /* RCC_CFGR_I2SSRC */ 03603 } 03604 03605 #if defined(DSI) 03606 /** 03607 * @brief Configure DSI clock source 03608 * @rmtoll DCKCFGR DSISEL LL_RCC_SetDSIClockSource 03609 * @param Source This parameter can be one of the following values: 03610 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03611 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL 03612 * @retval None 03613 */ 03614 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) 03615 { 03616 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source); 03617 } 03618 #endif /* DSI */ 03619 03620 #if defined(DFSDM1_Channel0) 03621 /** 03622 * @brief Configure DFSDM Audio clock source 03623 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_SetDFSDMAudioClockSource\n 03624 * DCKCFGR CKDFSDM2ASEL LL_RCC_SetDFSDMAudioClockSource 03625 * @param Source This parameter can be one of the following values: 03626 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 03627 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 03628 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) 03629 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) 03630 * 03631 * (*) value not defined in all devices. 03632 * @retval None 03633 */ 03634 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source) 03635 { 03636 MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U)); 03637 } 03638 03639 /** 03640 * @brief Configure DFSDM Kernel clock source 03641 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_SetDFSDMClockSource 03642 * @param Source This parameter can be one of the following values: 03643 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03644 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03645 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) 03646 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) 03647 * 03648 * (*) value not defined in all devices. 03649 * @retval None 03650 */ 03651 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source) 03652 { 03653 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source); 03654 } 03655 #endif /* DFSDM1_Channel0 */ 03656 03657 #if defined(SPDIFRX) 03658 /** 03659 * @brief Configure SPDIFRX clock source 03660 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_SetSPDIFRXClockSource 03661 * @param SPDIFRXxSource This parameter can be one of the following values: 03662 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL 03663 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S 03664 * 03665 * (*) value not defined in all devices. 03666 * @retval None 03667 */ 03668 __STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource) 03669 { 03670 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource); 03671 } 03672 #endif /* SPDIFRX */ 03673 03674 #if defined(FMPI2C1) 03675 /** 03676 * @brief Get FMPI2C clock source 03677 * @rmtoll DCKCFGR2 FMPI2C1SEL LL_RCC_GetFMPI2CClockSource 03678 * @param FMPI2Cx This parameter can be one of the following values: 03679 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE 03680 * @retval Returned value can be one of the following values: 03681 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 03682 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK 03683 * @arg @ref LL_RCC_FMPI2C1_CLKSOURCE_HSI 03684 */ 03685 __STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx) 03686 { 03687 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx)); 03688 } 03689 #endif /* FMPI2C1 */ 03690 03691 #if defined(LPTIM1) 03692 /** 03693 * @brief Get LPTIMx clock source 03694 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource 03695 * @param LPTIMx This parameter can be one of the following values: 03696 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE 03697 * @retval Returned value can be one of the following values: 03698 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 03699 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI 03700 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI 03701 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE 03702 */ 03703 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) 03704 { 03705 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); 03706 } 03707 #endif /* LPTIM1 */ 03708 03709 #if defined(SAI1) 03710 /** 03711 * @brief Get SAIx clock source 03712 * @rmtoll DCKCFGR SAI1SEL LL_RCC_GetSAIClockSource\n 03713 * DCKCFGR SAI2SEL LL_RCC_GetSAIClockSource\n 03714 * DCKCFGR SAI1ASRC LL_RCC_GetSAIClockSource\n 03715 * DCKCFGR SAI1BSRC LL_RCC_GetSAIClockSource 03716 * @param SAIx This parameter can be one of the following values: 03717 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*) 03718 * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) 03719 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE (*) 03720 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE (*) 03721 * 03722 * (*) value not defined in all devices. 03723 * @retval Returned value can be one of the following values: 03724 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI (*) 03725 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S (*) 03726 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL (*) 03727 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN (*) 03728 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI (*) 03729 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S (*) 03730 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*) 03731 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*) 03732 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (*) 03733 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (*) 03734 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PIN (*) 03735 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLL (*) 03736 * @arg @ref LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (*) 03737 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (*) 03738 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (*) 03739 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PIN (*) 03740 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLL (*) 03741 * @arg @ref LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (*) 03742 * 03743 * (*) value not defined in all devices. 03744 */ 03745 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) 03746 { 03747 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx); 03748 } 03749 #endif /* SAI1 */ 03750 03751 #if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL) 03752 /** 03753 * @brief Get SDIOx clock source 03754 * @rmtoll DCKCFGR SDIOSEL LL_RCC_GetSDIOClockSource\n 03755 * DCKCFGR2 SDIOSEL LL_RCC_GetSDIOClockSource 03756 * @param SDIOx This parameter can be one of the following values: 03757 * @arg @ref LL_RCC_SDIO_CLKSOURCE 03758 * @retval Returned value can be one of the following values: 03759 * @arg @ref LL_RCC_SDIO_CLKSOURCE_PLL48CLK 03760 * @arg @ref LL_RCC_SDIO_CLKSOURCE_SYSCLK 03761 */ 03762 __STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx) 03763 { 03764 #if defined(RCC_DCKCFGR_SDIOSEL) 03765 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx)); 03766 #else 03767 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx)); 03768 #endif /* RCC_DCKCFGR_SDIOSEL */ 03769 } 03770 #endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */ 03771 03772 #if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL) 03773 /** 03774 * @brief Get 48Mhz domain clock source 03775 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetCK48MClockSource\n 03776 * DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource 03777 * @param CK48Mx This parameter can be one of the following values: 03778 * @arg @ref LL_RCC_CK48M_CLKSOURCE 03779 * @retval Returned value can be one of the following values: 03780 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL 03781 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI (*) 03782 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLI2S (*) 03783 * 03784 * (*) value not defined in all devices. 03785 */ 03786 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx) 03787 { 03788 #if defined(RCC_DCKCFGR_CK48MSEL) 03789 return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx)); 03790 #else 03791 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); 03792 #endif /* RCC_DCKCFGR_CK48MSEL */ 03793 } 03794 03795 #if defined(RNG) 03796 /** 03797 * @brief Get RNGx clock source 03798 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetRNGClockSource\n 03799 * DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource 03800 * @param RNGx This parameter can be one of the following values: 03801 * @arg @ref LL_RCC_RNG_CLKSOURCE 03802 * @retval Returned value can be one of the following values: 03803 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL 03804 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI (*) 03805 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLI2S (*) 03806 * 03807 * (*) value not defined in all devices. 03808 */ 03809 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) 03810 { 03811 #if defined(RCC_DCKCFGR_CK48MSEL) 03812 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx)); 03813 #else 03814 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); 03815 #endif /* RCC_DCKCFGR_CK48MSEL */ 03816 } 03817 #endif /* RNG */ 03818 03819 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 03820 /** 03821 * @brief Get USBx clock source 03822 * @rmtoll DCKCFGR CK48MSEL LL_RCC_GetUSBClockSource\n 03823 * DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource 03824 * @param USBx This parameter can be one of the following values: 03825 * @arg @ref LL_RCC_USB_CLKSOURCE 03826 * @retval Returned value can be one of the following values: 03827 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL 03828 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI (*) 03829 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLI2S (*) 03830 * 03831 * (*) value not defined in all devices. 03832 */ 03833 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) 03834 { 03835 #if defined(RCC_DCKCFGR_CK48MSEL) 03836 return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx)); 03837 #else 03838 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); 03839 #endif /* RCC_DCKCFGR_CK48MSEL */ 03840 } 03841 #endif /* USB_OTG_FS || USB_OTG_HS */ 03842 #endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */ 03843 03844 #if defined(CEC) 03845 /** 03846 * @brief Get CEC Clock Source 03847 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource 03848 * @param CECx This parameter can be one of the following values: 03849 * @arg @ref LL_RCC_CEC_CLKSOURCE 03850 * @retval Returned value can be one of the following values: 03851 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488 03852 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE 03853 */ 03854 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx) 03855 { 03856 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); 03857 } 03858 #endif /* CEC */ 03859 03860 /** 03861 * @brief Get I2S Clock Source 03862 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource\n 03863 * DCKCFGR I2SSRC LL_RCC_GetI2SClockSource\n 03864 * DCKCFGR I2S1SRC LL_RCC_GetI2SClockSource\n 03865 * DCKCFGR I2S2SRC LL_RCC_GetI2SClockSource 03866 * @param I2Sx This parameter can be one of the following values: 03867 * @arg @ref LL_RCC_I2S1_CLKSOURCE 03868 * @arg @ref LL_RCC_I2S2_CLKSOURCE (*) 03869 * @retval Returned value can be one of the following values: 03870 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S (*) 03871 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN 03872 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLL (*) 03873 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLSRC (*) 03874 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLI2S (*) 03875 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PIN (*) 03876 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLL (*) 03877 * @arg @ref LL_RCC_I2S2_CLKSOURCE_PLLSRC (*) 03878 * 03879 * (*) value not defined in all devices. 03880 */ 03881 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx) 03882 { 03883 #if defined(RCC_CFGR_I2SSRC) 03884 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx)); 03885 #else 03886 return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx); 03887 #endif /* RCC_CFGR_I2SSRC */ 03888 } 03889 03890 #if defined(DFSDM1_Channel0) 03891 /** 03892 * @brief Get DFSDM Audio Clock Source 03893 * @rmtoll DCKCFGR CKDFSDM1ASEL LL_RCC_GetDFSDMAudioClockSource\n 03894 * DCKCFGR CKDFSDM2ASEL LL_RCC_GetDFSDMAudioClockSource 03895 * @param DFSDMx This parameter can be one of the following values: 03896 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE 03897 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE (*) 03898 * @retval Returned value can be one of the following values: 03899 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 03900 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 03901 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (*) 03902 * @arg @ref LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (*) 03903 * 03904 * (*) value not defined in all devices. 03905 */ 03906 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx) 03907 { 03908 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx); 03909 } 03910 03911 /** 03912 * @brief Get DFSDM Audio Clock Source 03913 * @rmtoll DCKCFGR CKDFSDM1SEL LL_RCC_GetDFSDMClockSource 03914 * @param DFSDMx This parameter can be one of the following values: 03915 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE 03916 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE (*) 03917 * @retval Returned value can be one of the following values: 03918 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2 03919 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK 03920 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2 (*) 03921 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (*) 03922 * 03923 * (*) value not defined in all devices. 03924 */ 03925 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx) 03926 { 03927 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx)); 03928 } 03929 #endif /* DFSDM1_Channel0 */ 03930 03931 #if defined(SPDIFRX) 03932 /** 03933 * @brief Get SPDIFRX clock source 03934 * @rmtoll DCKCFGR2 SPDIFRXSEL LL_RCC_GetSPDIFRXClockSource 03935 * @param SPDIFRXx This parameter can be one of the following values: 03936 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE 03937 * @retval Returned value can be one of the following values: 03938 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLL 03939 * @arg @ref LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S 03940 * 03941 * (*) value not defined in all devices. 03942 */ 03943 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx) 03944 { 03945 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx)); 03946 } 03947 #endif /* SPDIFRX */ 03948 03949 #if defined(DSI) 03950 /** 03951 * @brief Get DSI Clock Source 03952 * @rmtoll DCKCFGR DSISEL LL_RCC_GetDSIClockSource 03953 * @param DSIx This parameter can be one of the following values: 03954 * @arg @ref LL_RCC_DSI_CLKSOURCE 03955 * @retval Returned value can be one of the following values: 03956 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY 03957 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL 03958 */ 03959 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) 03960 { 03961 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx)); 03962 } 03963 #endif /* DSI */ 03964 03965 /** 03966 * @} 03967 */ 03968 03969 /** @defgroup RCC_LL_EF_RTC RTC 03970 * @{ 03971 */ 03972 03973 /** 03974 * @brief Set RTC Clock Source 03975 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless 03976 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is 03977 * set). The BDRST bit can be used to reset them. 03978 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource 03979 * @param Source This parameter can be one of the following values: 03980 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 03981 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 03982 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 03983 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE 03984 * @retval None 03985 */ 03986 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) 03987 { 03988 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); 03989 } 03990 03991 /** 03992 * @brief Get RTC Clock Source 03993 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource 03994 * @retval Returned value can be one of the following values: 03995 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE 03996 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE 03997 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI 03998 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE 03999 */ 04000 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) 04001 { 04002 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); 04003 } 04004 04005 /** 04006 * @brief Enable RTC 04007 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC 04008 * @retval None 04009 */ 04010 __STATIC_INLINE void LL_RCC_EnableRTC(void) 04011 { 04012 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 04013 } 04014 04015 /** 04016 * @brief Disable RTC 04017 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC 04018 * @retval None 04019 */ 04020 __STATIC_INLINE void LL_RCC_DisableRTC(void) 04021 { 04022 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); 04023 } 04024 04025 /** 04026 * @brief Check if RTC has been enabled or not 04027 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC 04028 * @retval State of bit (1 or 0). 04029 */ 04030 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) 04031 { 04032 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)); 04033 } 04034 04035 /** 04036 * @brief Force the Backup domain reset 04037 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset 04038 * @retval None 04039 */ 04040 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) 04041 { 04042 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); 04043 } 04044 04045 /** 04046 * @brief Release the Backup domain reset 04047 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset 04048 * @retval None 04049 */ 04050 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) 04051 { 04052 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); 04053 } 04054 04055 /** 04056 * @brief Set HSE Prescalers for RTC Clock 04057 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler 04058 * @param Prescaler This parameter can be one of the following values: 04059 * @arg @ref LL_RCC_RTC_NOCLOCK 04060 * @arg @ref LL_RCC_RTC_HSE_DIV_2 04061 * @arg @ref LL_RCC_RTC_HSE_DIV_3 04062 * @arg @ref LL_RCC_RTC_HSE_DIV_4 04063 * @arg @ref LL_RCC_RTC_HSE_DIV_5 04064 * @arg @ref LL_RCC_RTC_HSE_DIV_6 04065 * @arg @ref LL_RCC_RTC_HSE_DIV_7 04066 * @arg @ref LL_RCC_RTC_HSE_DIV_8 04067 * @arg @ref LL_RCC_RTC_HSE_DIV_9 04068 * @arg @ref LL_RCC_RTC_HSE_DIV_10 04069 * @arg @ref LL_RCC_RTC_HSE_DIV_11 04070 * @arg @ref LL_RCC_RTC_HSE_DIV_12 04071 * @arg @ref LL_RCC_RTC_HSE_DIV_13 04072 * @arg @ref LL_RCC_RTC_HSE_DIV_14 04073 * @arg @ref LL_RCC_RTC_HSE_DIV_15 04074 * @arg @ref LL_RCC_RTC_HSE_DIV_16 04075 * @arg @ref LL_RCC_RTC_HSE_DIV_17 04076 * @arg @ref LL_RCC_RTC_HSE_DIV_18 04077 * @arg @ref LL_RCC_RTC_HSE_DIV_19 04078 * @arg @ref LL_RCC_RTC_HSE_DIV_20 04079 * @arg @ref LL_RCC_RTC_HSE_DIV_21 04080 * @arg @ref LL_RCC_RTC_HSE_DIV_22 04081 * @arg @ref LL_RCC_RTC_HSE_DIV_23 04082 * @arg @ref LL_RCC_RTC_HSE_DIV_24 04083 * @arg @ref LL_RCC_RTC_HSE_DIV_25 04084 * @arg @ref LL_RCC_RTC_HSE_DIV_26 04085 * @arg @ref LL_RCC_RTC_HSE_DIV_27 04086 * @arg @ref LL_RCC_RTC_HSE_DIV_28 04087 * @arg @ref LL_RCC_RTC_HSE_DIV_29 04088 * @arg @ref LL_RCC_RTC_HSE_DIV_30 04089 * @arg @ref LL_RCC_RTC_HSE_DIV_31 04090 * @retval None 04091 */ 04092 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler) 04093 { 04094 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler); 04095 } 04096 04097 /** 04098 * @brief Get HSE Prescalers for RTC Clock 04099 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler 04100 * @retval Returned value can be one of the following values: 04101 * @arg @ref LL_RCC_RTC_NOCLOCK 04102 * @arg @ref LL_RCC_RTC_HSE_DIV_2 04103 * @arg @ref LL_RCC_RTC_HSE_DIV_3 04104 * @arg @ref LL_RCC_RTC_HSE_DIV_4 04105 * @arg @ref LL_RCC_RTC_HSE_DIV_5 04106 * @arg @ref LL_RCC_RTC_HSE_DIV_6 04107 * @arg @ref LL_RCC_RTC_HSE_DIV_7 04108 * @arg @ref LL_RCC_RTC_HSE_DIV_8 04109 * @arg @ref LL_RCC_RTC_HSE_DIV_9 04110 * @arg @ref LL_RCC_RTC_HSE_DIV_10 04111 * @arg @ref LL_RCC_RTC_HSE_DIV_11 04112 * @arg @ref LL_RCC_RTC_HSE_DIV_12 04113 * @arg @ref LL_RCC_RTC_HSE_DIV_13 04114 * @arg @ref LL_RCC_RTC_HSE_DIV_14 04115 * @arg @ref LL_RCC_RTC_HSE_DIV_15 04116 * @arg @ref LL_RCC_RTC_HSE_DIV_16 04117 * @arg @ref LL_RCC_RTC_HSE_DIV_17 04118 * @arg @ref LL_RCC_RTC_HSE_DIV_18 04119 * @arg @ref LL_RCC_RTC_HSE_DIV_19 04120 * @arg @ref LL_RCC_RTC_HSE_DIV_20 04121 * @arg @ref LL_RCC_RTC_HSE_DIV_21 04122 * @arg @ref LL_RCC_RTC_HSE_DIV_22 04123 * @arg @ref LL_RCC_RTC_HSE_DIV_23 04124 * @arg @ref LL_RCC_RTC_HSE_DIV_24 04125 * @arg @ref LL_RCC_RTC_HSE_DIV_25 04126 * @arg @ref LL_RCC_RTC_HSE_DIV_26 04127 * @arg @ref LL_RCC_RTC_HSE_DIV_27 04128 * @arg @ref LL_RCC_RTC_HSE_DIV_28 04129 * @arg @ref LL_RCC_RTC_HSE_DIV_29 04130 * @arg @ref LL_RCC_RTC_HSE_DIV_30 04131 * @arg @ref LL_RCC_RTC_HSE_DIV_31 04132 */ 04133 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void) 04134 { 04135 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)); 04136 } 04137 04138 /** 04139 * @} 04140 */ 04141 04142 #if defined(RCC_DCKCFGR_TIMPRE) 04143 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM 04144 * @{ 04145 */ 04146 04147 /** 04148 * @brief Set Timers Clock Prescalers 04149 * @rmtoll DCKCFGR TIMPRE LL_RCC_SetTIMPrescaler 04150 * @param Prescaler This parameter can be one of the following values: 04151 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE 04152 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES 04153 * @retval None 04154 */ 04155 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler) 04156 { 04157 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler); 04158 } 04159 04160 /** 04161 * @brief Get Timers Clock Prescalers 04162 * @rmtoll DCKCFGR TIMPRE LL_RCC_GetTIMPrescaler 04163 * @retval Returned value can be one of the following values: 04164 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE 04165 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES 04166 */ 04167 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void) 04168 { 04169 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE)); 04170 } 04171 04172 /** 04173 * @} 04174 */ 04175 #endif /* RCC_DCKCFGR_TIMPRE */ 04176 04177 /** @defgroup RCC_LL_EF_PLL PLL 04178 * @{ 04179 */ 04180 04181 /** 04182 * @brief Enable PLL 04183 * @rmtoll CR PLLON LL_RCC_PLL_Enable 04184 * @retval None 04185 */ 04186 __STATIC_INLINE void LL_RCC_PLL_Enable(void) 04187 { 04188 SET_BIT(RCC->CR, RCC_CR_PLLON); 04189 } 04190 04191 /** 04192 * @brief Disable PLL 04193 * @note Cannot be disabled if the PLL clock is used as the system clock 04194 * @rmtoll CR PLLON LL_RCC_PLL_Disable 04195 * @retval None 04196 */ 04197 __STATIC_INLINE void LL_RCC_PLL_Disable(void) 04198 { 04199 CLEAR_BIT(RCC->CR, RCC_CR_PLLON); 04200 } 04201 04202 /** 04203 * @brief Check if PLL Ready 04204 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady 04205 * @retval State of bit (1 or 0). 04206 */ 04207 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) 04208 { 04209 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)); 04210 } 04211 04212 /** 04213 * @brief Configure PLL used for SYSCLK Domain 04214 * @note PLL Source and PLLM Divider can be written only when PLL, 04215 * PLLI2S and PLLSAI(*) are disabled 04216 * @note PLLN/PLLP can be written only when PLL is disabled 04217 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n 04218 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n 04219 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n 04220 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS\n 04221 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS 04222 * @param Source This parameter can be one of the following values: 04223 * @arg @ref LL_RCC_PLLSOURCE_HSI 04224 * @arg @ref LL_RCC_PLLSOURCE_HSE 04225 * @param PLLM This parameter can be one of the following values: 04226 * @arg @ref LL_RCC_PLLM_DIV_2 04227 * @arg @ref LL_RCC_PLLM_DIV_3 04228 * @arg @ref LL_RCC_PLLM_DIV_4 04229 * @arg @ref LL_RCC_PLLM_DIV_5 04230 * @arg @ref LL_RCC_PLLM_DIV_6 04231 * @arg @ref LL_RCC_PLLM_DIV_7 04232 * @arg @ref LL_RCC_PLLM_DIV_8 04233 * @arg @ref LL_RCC_PLLM_DIV_9 04234 * @arg @ref LL_RCC_PLLM_DIV_10 04235 * @arg @ref LL_RCC_PLLM_DIV_11 04236 * @arg @ref LL_RCC_PLLM_DIV_12 04237 * @arg @ref LL_RCC_PLLM_DIV_13 04238 * @arg @ref LL_RCC_PLLM_DIV_14 04239 * @arg @ref LL_RCC_PLLM_DIV_15 04240 * @arg @ref LL_RCC_PLLM_DIV_16 04241 * @arg @ref LL_RCC_PLLM_DIV_17 04242 * @arg @ref LL_RCC_PLLM_DIV_18 04243 * @arg @ref LL_RCC_PLLM_DIV_19 04244 * @arg @ref LL_RCC_PLLM_DIV_20 04245 * @arg @ref LL_RCC_PLLM_DIV_21 04246 * @arg @ref LL_RCC_PLLM_DIV_22 04247 * @arg @ref LL_RCC_PLLM_DIV_23 04248 * @arg @ref LL_RCC_PLLM_DIV_24 04249 * @arg @ref LL_RCC_PLLM_DIV_25 04250 * @arg @ref LL_RCC_PLLM_DIV_26 04251 * @arg @ref LL_RCC_PLLM_DIV_27 04252 * @arg @ref LL_RCC_PLLM_DIV_28 04253 * @arg @ref LL_RCC_PLLM_DIV_29 04254 * @arg @ref LL_RCC_PLLM_DIV_30 04255 * @arg @ref LL_RCC_PLLM_DIV_31 04256 * @arg @ref LL_RCC_PLLM_DIV_32 04257 * @arg @ref LL_RCC_PLLM_DIV_33 04258 * @arg @ref LL_RCC_PLLM_DIV_34 04259 * @arg @ref LL_RCC_PLLM_DIV_35 04260 * @arg @ref LL_RCC_PLLM_DIV_36 04261 * @arg @ref LL_RCC_PLLM_DIV_37 04262 * @arg @ref LL_RCC_PLLM_DIV_38 04263 * @arg @ref LL_RCC_PLLM_DIV_39 04264 * @arg @ref LL_RCC_PLLM_DIV_40 04265 * @arg @ref LL_RCC_PLLM_DIV_41 04266 * @arg @ref LL_RCC_PLLM_DIV_42 04267 * @arg @ref LL_RCC_PLLM_DIV_43 04268 * @arg @ref LL_RCC_PLLM_DIV_44 04269 * @arg @ref LL_RCC_PLLM_DIV_45 04270 * @arg @ref LL_RCC_PLLM_DIV_46 04271 * @arg @ref LL_RCC_PLLM_DIV_47 04272 * @arg @ref LL_RCC_PLLM_DIV_48 04273 * @arg @ref LL_RCC_PLLM_DIV_49 04274 * @arg @ref LL_RCC_PLLM_DIV_50 04275 * @arg @ref LL_RCC_PLLM_DIV_51 04276 * @arg @ref LL_RCC_PLLM_DIV_52 04277 * @arg @ref LL_RCC_PLLM_DIV_53 04278 * @arg @ref LL_RCC_PLLM_DIV_54 04279 * @arg @ref LL_RCC_PLLM_DIV_55 04280 * @arg @ref LL_RCC_PLLM_DIV_56 04281 * @arg @ref LL_RCC_PLLM_DIV_57 04282 * @arg @ref LL_RCC_PLLM_DIV_58 04283 * @arg @ref LL_RCC_PLLM_DIV_59 04284 * @arg @ref LL_RCC_PLLM_DIV_60 04285 * @arg @ref LL_RCC_PLLM_DIV_61 04286 * @arg @ref LL_RCC_PLLM_DIV_62 04287 * @arg @ref LL_RCC_PLLM_DIV_63 04288 * @param PLLN Between 50/192(*) and 432 04289 * 04290 * (*) value not defined in all devices. 04291 * @param PLLP_R This parameter can be one of the following values: 04292 * @arg @ref LL_RCC_PLLP_DIV_2 04293 * @arg @ref LL_RCC_PLLP_DIV_4 04294 * @arg @ref LL_RCC_PLLP_DIV_6 04295 * @arg @ref LL_RCC_PLLP_DIV_8 04296 * @arg @ref LL_RCC_PLLR_DIV_2 (*) 04297 * @arg @ref LL_RCC_PLLR_DIV_3 (*) 04298 * @arg @ref LL_RCC_PLLR_DIV_4 (*) 04299 * @arg @ref LL_RCC_PLLR_DIV_5 (*) 04300 * @arg @ref LL_RCC_PLLR_DIV_6 (*) 04301 * @arg @ref LL_RCC_PLLR_DIV_7 (*) 04302 * 04303 * (*) value not defined in all devices. 04304 * @retval None 04305 */ 04306 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R) 04307 { 04308 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN, 04309 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos); 04310 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R); 04311 #if defined(RCC_PLLR_SYSCLK_SUPPORT) 04312 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R); 04313 #endif /* RCC_PLLR_SYSCLK_SUPPORT */ 04314 } 04315 04316 /** 04317 * @brief Configure PLL used for 48Mhz domain clock 04318 * @note PLL Source and PLLM Divider can be written only when PLL, 04319 * PLLI2S and PLLSAI(*) are disabled 04320 * @note PLLN/PLLQ can be written only when PLL is disabled 04321 * @note This can be selected for USB, RNG, SDIO 04322 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n 04323 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n 04324 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n 04325 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M 04326 * @param Source This parameter can be one of the following values: 04327 * @arg @ref LL_RCC_PLLSOURCE_HSI 04328 * @arg @ref LL_RCC_PLLSOURCE_HSE 04329 * @param PLLM This parameter can be one of the following values: 04330 * @arg @ref LL_RCC_PLLM_DIV_2 04331 * @arg @ref LL_RCC_PLLM_DIV_3 04332 * @arg @ref LL_RCC_PLLM_DIV_4 04333 * @arg @ref LL_RCC_PLLM_DIV_5 04334 * @arg @ref LL_RCC_PLLM_DIV_6 04335 * @arg @ref LL_RCC_PLLM_DIV_7 04336 * @arg @ref LL_RCC_PLLM_DIV_8 04337 * @arg @ref LL_RCC_PLLM_DIV_9 04338 * @arg @ref LL_RCC_PLLM_DIV_10 04339 * @arg @ref LL_RCC_PLLM_DIV_11 04340 * @arg @ref LL_RCC_PLLM_DIV_12 04341 * @arg @ref LL_RCC_PLLM_DIV_13 04342 * @arg @ref LL_RCC_PLLM_DIV_14 04343 * @arg @ref LL_RCC_PLLM_DIV_15 04344 * @arg @ref LL_RCC_PLLM_DIV_16 04345 * @arg @ref LL_RCC_PLLM_DIV_17 04346 * @arg @ref LL_RCC_PLLM_DIV_18 04347 * @arg @ref LL_RCC_PLLM_DIV_19 04348 * @arg @ref LL_RCC_PLLM_DIV_20 04349 * @arg @ref LL_RCC_PLLM_DIV_21 04350 * @arg @ref LL_RCC_PLLM_DIV_22 04351 * @arg @ref LL_RCC_PLLM_DIV_23 04352 * @arg @ref LL_RCC_PLLM_DIV_24 04353 * @arg @ref LL_RCC_PLLM_DIV_25 04354 * @arg @ref LL_RCC_PLLM_DIV_26 04355 * @arg @ref LL_RCC_PLLM_DIV_27 04356 * @arg @ref LL_RCC_PLLM_DIV_28 04357 * @arg @ref LL_RCC_PLLM_DIV_29 04358 * @arg @ref LL_RCC_PLLM_DIV_30 04359 * @arg @ref LL_RCC_PLLM_DIV_31 04360 * @arg @ref LL_RCC_PLLM_DIV_32 04361 * @arg @ref LL_RCC_PLLM_DIV_33 04362 * @arg @ref LL_RCC_PLLM_DIV_34 04363 * @arg @ref LL_RCC_PLLM_DIV_35 04364 * @arg @ref LL_RCC_PLLM_DIV_36 04365 * @arg @ref LL_RCC_PLLM_DIV_37 04366 * @arg @ref LL_RCC_PLLM_DIV_38 04367 * @arg @ref LL_RCC_PLLM_DIV_39 04368 * @arg @ref LL_RCC_PLLM_DIV_40 04369 * @arg @ref LL_RCC_PLLM_DIV_41 04370 * @arg @ref LL_RCC_PLLM_DIV_42 04371 * @arg @ref LL_RCC_PLLM_DIV_43 04372 * @arg @ref LL_RCC_PLLM_DIV_44 04373 * @arg @ref LL_RCC_PLLM_DIV_45 04374 * @arg @ref LL_RCC_PLLM_DIV_46 04375 * @arg @ref LL_RCC_PLLM_DIV_47 04376 * @arg @ref LL_RCC_PLLM_DIV_48 04377 * @arg @ref LL_RCC_PLLM_DIV_49 04378 * @arg @ref LL_RCC_PLLM_DIV_50 04379 * @arg @ref LL_RCC_PLLM_DIV_51 04380 * @arg @ref LL_RCC_PLLM_DIV_52 04381 * @arg @ref LL_RCC_PLLM_DIV_53 04382 * @arg @ref LL_RCC_PLLM_DIV_54 04383 * @arg @ref LL_RCC_PLLM_DIV_55 04384 * @arg @ref LL_RCC_PLLM_DIV_56 04385 * @arg @ref LL_RCC_PLLM_DIV_57 04386 * @arg @ref LL_RCC_PLLM_DIV_58 04387 * @arg @ref LL_RCC_PLLM_DIV_59 04388 * @arg @ref LL_RCC_PLLM_DIV_60 04389 * @arg @ref LL_RCC_PLLM_DIV_61 04390 * @arg @ref LL_RCC_PLLM_DIV_62 04391 * @arg @ref LL_RCC_PLLM_DIV_63 04392 * @param PLLN Between 50/192(*) and 432 04393 * 04394 * (*) value not defined in all devices. 04395 * @param PLLQ This parameter can be one of the following values: 04396 * @arg @ref LL_RCC_PLLQ_DIV_2 04397 * @arg @ref LL_RCC_PLLQ_DIV_3 04398 * @arg @ref LL_RCC_PLLQ_DIV_4 04399 * @arg @ref LL_RCC_PLLQ_DIV_5 04400 * @arg @ref LL_RCC_PLLQ_DIV_6 04401 * @arg @ref LL_RCC_PLLQ_DIV_7 04402 * @arg @ref LL_RCC_PLLQ_DIV_8 04403 * @arg @ref LL_RCC_PLLQ_DIV_9 04404 * @arg @ref LL_RCC_PLLQ_DIV_10 04405 * @arg @ref LL_RCC_PLLQ_DIV_11 04406 * @arg @ref LL_RCC_PLLQ_DIV_12 04407 * @arg @ref LL_RCC_PLLQ_DIV_13 04408 * @arg @ref LL_RCC_PLLQ_DIV_14 04409 * @arg @ref LL_RCC_PLLQ_DIV_15 04410 * @retval None 04411 */ 04412 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 04413 { 04414 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ, 04415 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ); 04416 } 04417 04418 #if defined(DSI) 04419 /** 04420 * @brief Configure PLL used for DSI clock 04421 * @note PLL Source and PLLM Divider can be written only when PLL, 04422 * PLLI2S and PLLSAI are disabled 04423 * @note PLLN/PLLR can be written only when PLL is disabled 04424 * @note This can be selected for DSI 04425 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n 04426 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n 04427 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n 04428 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI 04429 * @param Source This parameter can be one of the following values: 04430 * @arg @ref LL_RCC_PLLSOURCE_HSI 04431 * @arg @ref LL_RCC_PLLSOURCE_HSE 04432 * @param PLLM This parameter can be one of the following values: 04433 * @arg @ref LL_RCC_PLLM_DIV_2 04434 * @arg @ref LL_RCC_PLLM_DIV_3 04435 * @arg @ref LL_RCC_PLLM_DIV_4 04436 * @arg @ref LL_RCC_PLLM_DIV_5 04437 * @arg @ref LL_RCC_PLLM_DIV_6 04438 * @arg @ref LL_RCC_PLLM_DIV_7 04439 * @arg @ref LL_RCC_PLLM_DIV_8 04440 * @arg @ref LL_RCC_PLLM_DIV_9 04441 * @arg @ref LL_RCC_PLLM_DIV_10 04442 * @arg @ref LL_RCC_PLLM_DIV_11 04443 * @arg @ref LL_RCC_PLLM_DIV_12 04444 * @arg @ref LL_RCC_PLLM_DIV_13 04445 * @arg @ref LL_RCC_PLLM_DIV_14 04446 * @arg @ref LL_RCC_PLLM_DIV_15 04447 * @arg @ref LL_RCC_PLLM_DIV_16 04448 * @arg @ref LL_RCC_PLLM_DIV_17 04449 * @arg @ref LL_RCC_PLLM_DIV_18 04450 * @arg @ref LL_RCC_PLLM_DIV_19 04451 * @arg @ref LL_RCC_PLLM_DIV_20 04452 * @arg @ref LL_RCC_PLLM_DIV_21 04453 * @arg @ref LL_RCC_PLLM_DIV_22 04454 * @arg @ref LL_RCC_PLLM_DIV_23 04455 * @arg @ref LL_RCC_PLLM_DIV_24 04456 * @arg @ref LL_RCC_PLLM_DIV_25 04457 * @arg @ref LL_RCC_PLLM_DIV_26 04458 * @arg @ref LL_RCC_PLLM_DIV_27 04459 * @arg @ref LL_RCC_PLLM_DIV_28 04460 * @arg @ref LL_RCC_PLLM_DIV_29 04461 * @arg @ref LL_RCC_PLLM_DIV_30 04462 * @arg @ref LL_RCC_PLLM_DIV_31 04463 * @arg @ref LL_RCC_PLLM_DIV_32 04464 * @arg @ref LL_RCC_PLLM_DIV_33 04465 * @arg @ref LL_RCC_PLLM_DIV_34 04466 * @arg @ref LL_RCC_PLLM_DIV_35 04467 * @arg @ref LL_RCC_PLLM_DIV_36 04468 * @arg @ref LL_RCC_PLLM_DIV_37 04469 * @arg @ref LL_RCC_PLLM_DIV_38 04470 * @arg @ref LL_RCC_PLLM_DIV_39 04471 * @arg @ref LL_RCC_PLLM_DIV_40 04472 * @arg @ref LL_RCC_PLLM_DIV_41 04473 * @arg @ref LL_RCC_PLLM_DIV_42 04474 * @arg @ref LL_RCC_PLLM_DIV_43 04475 * @arg @ref LL_RCC_PLLM_DIV_44 04476 * @arg @ref LL_RCC_PLLM_DIV_45 04477 * @arg @ref LL_RCC_PLLM_DIV_46 04478 * @arg @ref LL_RCC_PLLM_DIV_47 04479 * @arg @ref LL_RCC_PLLM_DIV_48 04480 * @arg @ref LL_RCC_PLLM_DIV_49 04481 * @arg @ref LL_RCC_PLLM_DIV_50 04482 * @arg @ref LL_RCC_PLLM_DIV_51 04483 * @arg @ref LL_RCC_PLLM_DIV_52 04484 * @arg @ref LL_RCC_PLLM_DIV_53 04485 * @arg @ref LL_RCC_PLLM_DIV_54 04486 * @arg @ref LL_RCC_PLLM_DIV_55 04487 * @arg @ref LL_RCC_PLLM_DIV_56 04488 * @arg @ref LL_RCC_PLLM_DIV_57 04489 * @arg @ref LL_RCC_PLLM_DIV_58 04490 * @arg @ref LL_RCC_PLLM_DIV_59 04491 * @arg @ref LL_RCC_PLLM_DIV_60 04492 * @arg @ref LL_RCC_PLLM_DIV_61 04493 * @arg @ref LL_RCC_PLLM_DIV_62 04494 * @arg @ref LL_RCC_PLLM_DIV_63 04495 * @param PLLN Between 50 and 432 04496 * @param PLLR This parameter can be one of the following values: 04497 * @arg @ref LL_RCC_PLLR_DIV_2 04498 * @arg @ref LL_RCC_PLLR_DIV_3 04499 * @arg @ref LL_RCC_PLLR_DIV_4 04500 * @arg @ref LL_RCC_PLLR_DIV_5 04501 * @arg @ref LL_RCC_PLLR_DIV_6 04502 * @arg @ref LL_RCC_PLLR_DIV_7 04503 * @retval None 04504 */ 04505 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04506 { 04507 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 04508 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 04509 } 04510 #endif /* DSI */ 04511 04512 #if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT) 04513 /** 04514 * @brief Configure PLL used for I2S clock 04515 * @note PLL Source and PLLM Divider can be written only when PLL, 04516 * PLLI2S and PLLSAI are disabled 04517 * @note PLLN/PLLR can be written only when PLL is disabled 04518 * @note This can be selected for I2S 04519 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_I2S\n 04520 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_I2S\n 04521 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_I2S\n 04522 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_I2S 04523 * @param Source This parameter can be one of the following values: 04524 * @arg @ref LL_RCC_PLLSOURCE_HSI 04525 * @arg @ref LL_RCC_PLLSOURCE_HSE 04526 * @param PLLM This parameter can be one of the following values: 04527 * @arg @ref LL_RCC_PLLM_DIV_2 04528 * @arg @ref LL_RCC_PLLM_DIV_3 04529 * @arg @ref LL_RCC_PLLM_DIV_4 04530 * @arg @ref LL_RCC_PLLM_DIV_5 04531 * @arg @ref LL_RCC_PLLM_DIV_6 04532 * @arg @ref LL_RCC_PLLM_DIV_7 04533 * @arg @ref LL_RCC_PLLM_DIV_8 04534 * @arg @ref LL_RCC_PLLM_DIV_9 04535 * @arg @ref LL_RCC_PLLM_DIV_10 04536 * @arg @ref LL_RCC_PLLM_DIV_11 04537 * @arg @ref LL_RCC_PLLM_DIV_12 04538 * @arg @ref LL_RCC_PLLM_DIV_13 04539 * @arg @ref LL_RCC_PLLM_DIV_14 04540 * @arg @ref LL_RCC_PLLM_DIV_15 04541 * @arg @ref LL_RCC_PLLM_DIV_16 04542 * @arg @ref LL_RCC_PLLM_DIV_17 04543 * @arg @ref LL_RCC_PLLM_DIV_18 04544 * @arg @ref LL_RCC_PLLM_DIV_19 04545 * @arg @ref LL_RCC_PLLM_DIV_20 04546 * @arg @ref LL_RCC_PLLM_DIV_21 04547 * @arg @ref LL_RCC_PLLM_DIV_22 04548 * @arg @ref LL_RCC_PLLM_DIV_23 04549 * @arg @ref LL_RCC_PLLM_DIV_24 04550 * @arg @ref LL_RCC_PLLM_DIV_25 04551 * @arg @ref LL_RCC_PLLM_DIV_26 04552 * @arg @ref LL_RCC_PLLM_DIV_27 04553 * @arg @ref LL_RCC_PLLM_DIV_28 04554 * @arg @ref LL_RCC_PLLM_DIV_29 04555 * @arg @ref LL_RCC_PLLM_DIV_30 04556 * @arg @ref LL_RCC_PLLM_DIV_31 04557 * @arg @ref LL_RCC_PLLM_DIV_32 04558 * @arg @ref LL_RCC_PLLM_DIV_33 04559 * @arg @ref LL_RCC_PLLM_DIV_34 04560 * @arg @ref LL_RCC_PLLM_DIV_35 04561 * @arg @ref LL_RCC_PLLM_DIV_36 04562 * @arg @ref LL_RCC_PLLM_DIV_37 04563 * @arg @ref LL_RCC_PLLM_DIV_38 04564 * @arg @ref LL_RCC_PLLM_DIV_39 04565 * @arg @ref LL_RCC_PLLM_DIV_40 04566 * @arg @ref LL_RCC_PLLM_DIV_41 04567 * @arg @ref LL_RCC_PLLM_DIV_42 04568 * @arg @ref LL_RCC_PLLM_DIV_43 04569 * @arg @ref LL_RCC_PLLM_DIV_44 04570 * @arg @ref LL_RCC_PLLM_DIV_45 04571 * @arg @ref LL_RCC_PLLM_DIV_46 04572 * @arg @ref LL_RCC_PLLM_DIV_47 04573 * @arg @ref LL_RCC_PLLM_DIV_48 04574 * @arg @ref LL_RCC_PLLM_DIV_49 04575 * @arg @ref LL_RCC_PLLM_DIV_50 04576 * @arg @ref LL_RCC_PLLM_DIV_51 04577 * @arg @ref LL_RCC_PLLM_DIV_52 04578 * @arg @ref LL_RCC_PLLM_DIV_53 04579 * @arg @ref LL_RCC_PLLM_DIV_54 04580 * @arg @ref LL_RCC_PLLM_DIV_55 04581 * @arg @ref LL_RCC_PLLM_DIV_56 04582 * @arg @ref LL_RCC_PLLM_DIV_57 04583 * @arg @ref LL_RCC_PLLM_DIV_58 04584 * @arg @ref LL_RCC_PLLM_DIV_59 04585 * @arg @ref LL_RCC_PLLM_DIV_60 04586 * @arg @ref LL_RCC_PLLM_DIV_61 04587 * @arg @ref LL_RCC_PLLM_DIV_62 04588 * @arg @ref LL_RCC_PLLM_DIV_63 04589 * @param PLLN Between 50 and 432 04590 * @param PLLR This parameter can be one of the following values: 04591 * @arg @ref LL_RCC_PLLR_DIV_2 04592 * @arg @ref LL_RCC_PLLR_DIV_3 04593 * @arg @ref LL_RCC_PLLR_DIV_4 04594 * @arg @ref LL_RCC_PLLR_DIV_5 04595 * @arg @ref LL_RCC_PLLR_DIV_6 04596 * @arg @ref LL_RCC_PLLR_DIV_7 04597 * @retval None 04598 */ 04599 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04600 { 04601 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 04602 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 04603 } 04604 #endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */ 04605 04606 #if defined(SPDIFRX) 04607 /** 04608 * @brief Configure PLL used for SPDIFRX clock 04609 * @note PLL Source and PLLM Divider can be written only when PLL, 04610 * PLLI2S and PLLSAI are disabled 04611 * @note PLLN/PLLR can be written only when PLL is disabled 04612 * @note This can be selected for SPDIFRX 04613 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SPDIFRX\n 04614 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SPDIFRX\n 04615 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SPDIFRX\n 04616 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SPDIFRX 04617 * @param Source This parameter can be one of the following values: 04618 * @arg @ref LL_RCC_PLLSOURCE_HSI 04619 * @arg @ref LL_RCC_PLLSOURCE_HSE 04620 * @param PLLM This parameter can be one of the following values: 04621 * @arg @ref LL_RCC_PLLM_DIV_2 04622 * @arg @ref LL_RCC_PLLM_DIV_3 04623 * @arg @ref LL_RCC_PLLM_DIV_4 04624 * @arg @ref LL_RCC_PLLM_DIV_5 04625 * @arg @ref LL_RCC_PLLM_DIV_6 04626 * @arg @ref LL_RCC_PLLM_DIV_7 04627 * @arg @ref LL_RCC_PLLM_DIV_8 04628 * @arg @ref LL_RCC_PLLM_DIV_9 04629 * @arg @ref LL_RCC_PLLM_DIV_10 04630 * @arg @ref LL_RCC_PLLM_DIV_11 04631 * @arg @ref LL_RCC_PLLM_DIV_12 04632 * @arg @ref LL_RCC_PLLM_DIV_13 04633 * @arg @ref LL_RCC_PLLM_DIV_14 04634 * @arg @ref LL_RCC_PLLM_DIV_15 04635 * @arg @ref LL_RCC_PLLM_DIV_16 04636 * @arg @ref LL_RCC_PLLM_DIV_17 04637 * @arg @ref LL_RCC_PLLM_DIV_18 04638 * @arg @ref LL_RCC_PLLM_DIV_19 04639 * @arg @ref LL_RCC_PLLM_DIV_20 04640 * @arg @ref LL_RCC_PLLM_DIV_21 04641 * @arg @ref LL_RCC_PLLM_DIV_22 04642 * @arg @ref LL_RCC_PLLM_DIV_23 04643 * @arg @ref LL_RCC_PLLM_DIV_24 04644 * @arg @ref LL_RCC_PLLM_DIV_25 04645 * @arg @ref LL_RCC_PLLM_DIV_26 04646 * @arg @ref LL_RCC_PLLM_DIV_27 04647 * @arg @ref LL_RCC_PLLM_DIV_28 04648 * @arg @ref LL_RCC_PLLM_DIV_29 04649 * @arg @ref LL_RCC_PLLM_DIV_30 04650 * @arg @ref LL_RCC_PLLM_DIV_31 04651 * @arg @ref LL_RCC_PLLM_DIV_32 04652 * @arg @ref LL_RCC_PLLM_DIV_33 04653 * @arg @ref LL_RCC_PLLM_DIV_34 04654 * @arg @ref LL_RCC_PLLM_DIV_35 04655 * @arg @ref LL_RCC_PLLM_DIV_36 04656 * @arg @ref LL_RCC_PLLM_DIV_37 04657 * @arg @ref LL_RCC_PLLM_DIV_38 04658 * @arg @ref LL_RCC_PLLM_DIV_39 04659 * @arg @ref LL_RCC_PLLM_DIV_40 04660 * @arg @ref LL_RCC_PLLM_DIV_41 04661 * @arg @ref LL_RCC_PLLM_DIV_42 04662 * @arg @ref LL_RCC_PLLM_DIV_43 04663 * @arg @ref LL_RCC_PLLM_DIV_44 04664 * @arg @ref LL_RCC_PLLM_DIV_45 04665 * @arg @ref LL_RCC_PLLM_DIV_46 04666 * @arg @ref LL_RCC_PLLM_DIV_47 04667 * @arg @ref LL_RCC_PLLM_DIV_48 04668 * @arg @ref LL_RCC_PLLM_DIV_49 04669 * @arg @ref LL_RCC_PLLM_DIV_50 04670 * @arg @ref LL_RCC_PLLM_DIV_51 04671 * @arg @ref LL_RCC_PLLM_DIV_52 04672 * @arg @ref LL_RCC_PLLM_DIV_53 04673 * @arg @ref LL_RCC_PLLM_DIV_54 04674 * @arg @ref LL_RCC_PLLM_DIV_55 04675 * @arg @ref LL_RCC_PLLM_DIV_56 04676 * @arg @ref LL_RCC_PLLM_DIV_57 04677 * @arg @ref LL_RCC_PLLM_DIV_58 04678 * @arg @ref LL_RCC_PLLM_DIV_59 04679 * @arg @ref LL_RCC_PLLM_DIV_60 04680 * @arg @ref LL_RCC_PLLM_DIV_61 04681 * @arg @ref LL_RCC_PLLM_DIV_62 04682 * @arg @ref LL_RCC_PLLM_DIV_63 04683 * @param PLLN Between 50 and 432 04684 * @param PLLR This parameter can be one of the following values: 04685 * @arg @ref LL_RCC_PLLR_DIV_2 04686 * @arg @ref LL_RCC_PLLR_DIV_3 04687 * @arg @ref LL_RCC_PLLR_DIV_4 04688 * @arg @ref LL_RCC_PLLR_DIV_5 04689 * @arg @ref LL_RCC_PLLR_DIV_6 04690 * @arg @ref LL_RCC_PLLR_DIV_7 04691 * @retval None 04692 */ 04693 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04694 { 04695 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 04696 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 04697 } 04698 #endif /* SPDIFRX */ 04699 04700 #if defined(RCC_PLLCFGR_PLLR) 04701 #if defined(SAI1) 04702 /** 04703 * @brief Configure PLL used for SAI clock 04704 * @note PLL Source and PLLM Divider can be written only when PLL, 04705 * PLLI2S and PLLSAI are disabled 04706 * @note PLLN/PLLR can be written only when PLL is disabled 04707 * @note This can be selected for SAI 04708 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n 04709 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n 04710 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n 04711 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SAI\n 04712 * DCKCFGR PLLDIVR LL_RCC_PLL_ConfigDomain_SAI 04713 * @param Source This parameter can be one of the following values: 04714 * @arg @ref LL_RCC_PLLSOURCE_HSI 04715 * @arg @ref LL_RCC_PLLSOURCE_HSE 04716 * @param PLLM This parameter can be one of the following values: 04717 * @arg @ref LL_RCC_PLLM_DIV_2 04718 * @arg @ref LL_RCC_PLLM_DIV_3 04719 * @arg @ref LL_RCC_PLLM_DIV_4 04720 * @arg @ref LL_RCC_PLLM_DIV_5 04721 * @arg @ref LL_RCC_PLLM_DIV_6 04722 * @arg @ref LL_RCC_PLLM_DIV_7 04723 * @arg @ref LL_RCC_PLLM_DIV_8 04724 * @arg @ref LL_RCC_PLLM_DIV_9 04725 * @arg @ref LL_RCC_PLLM_DIV_10 04726 * @arg @ref LL_RCC_PLLM_DIV_11 04727 * @arg @ref LL_RCC_PLLM_DIV_12 04728 * @arg @ref LL_RCC_PLLM_DIV_13 04729 * @arg @ref LL_RCC_PLLM_DIV_14 04730 * @arg @ref LL_RCC_PLLM_DIV_15 04731 * @arg @ref LL_RCC_PLLM_DIV_16 04732 * @arg @ref LL_RCC_PLLM_DIV_17 04733 * @arg @ref LL_RCC_PLLM_DIV_18 04734 * @arg @ref LL_RCC_PLLM_DIV_19 04735 * @arg @ref LL_RCC_PLLM_DIV_20 04736 * @arg @ref LL_RCC_PLLM_DIV_21 04737 * @arg @ref LL_RCC_PLLM_DIV_22 04738 * @arg @ref LL_RCC_PLLM_DIV_23 04739 * @arg @ref LL_RCC_PLLM_DIV_24 04740 * @arg @ref LL_RCC_PLLM_DIV_25 04741 * @arg @ref LL_RCC_PLLM_DIV_26 04742 * @arg @ref LL_RCC_PLLM_DIV_27 04743 * @arg @ref LL_RCC_PLLM_DIV_28 04744 * @arg @ref LL_RCC_PLLM_DIV_29 04745 * @arg @ref LL_RCC_PLLM_DIV_30 04746 * @arg @ref LL_RCC_PLLM_DIV_31 04747 * @arg @ref LL_RCC_PLLM_DIV_32 04748 * @arg @ref LL_RCC_PLLM_DIV_33 04749 * @arg @ref LL_RCC_PLLM_DIV_34 04750 * @arg @ref LL_RCC_PLLM_DIV_35 04751 * @arg @ref LL_RCC_PLLM_DIV_36 04752 * @arg @ref LL_RCC_PLLM_DIV_37 04753 * @arg @ref LL_RCC_PLLM_DIV_38 04754 * @arg @ref LL_RCC_PLLM_DIV_39 04755 * @arg @ref LL_RCC_PLLM_DIV_40 04756 * @arg @ref LL_RCC_PLLM_DIV_41 04757 * @arg @ref LL_RCC_PLLM_DIV_42 04758 * @arg @ref LL_RCC_PLLM_DIV_43 04759 * @arg @ref LL_RCC_PLLM_DIV_44 04760 * @arg @ref LL_RCC_PLLM_DIV_45 04761 * @arg @ref LL_RCC_PLLM_DIV_46 04762 * @arg @ref LL_RCC_PLLM_DIV_47 04763 * @arg @ref LL_RCC_PLLM_DIV_48 04764 * @arg @ref LL_RCC_PLLM_DIV_49 04765 * @arg @ref LL_RCC_PLLM_DIV_50 04766 * @arg @ref LL_RCC_PLLM_DIV_51 04767 * @arg @ref LL_RCC_PLLM_DIV_52 04768 * @arg @ref LL_RCC_PLLM_DIV_53 04769 * @arg @ref LL_RCC_PLLM_DIV_54 04770 * @arg @ref LL_RCC_PLLM_DIV_55 04771 * @arg @ref LL_RCC_PLLM_DIV_56 04772 * @arg @ref LL_RCC_PLLM_DIV_57 04773 * @arg @ref LL_RCC_PLLM_DIV_58 04774 * @arg @ref LL_RCC_PLLM_DIV_59 04775 * @arg @ref LL_RCC_PLLM_DIV_60 04776 * @arg @ref LL_RCC_PLLM_DIV_61 04777 * @arg @ref LL_RCC_PLLM_DIV_62 04778 * @arg @ref LL_RCC_PLLM_DIV_63 04779 * @param PLLN Between 50 and 432 04780 * @param PLLR This parameter can be one of the following values: 04781 * @arg @ref LL_RCC_PLLR_DIV_2 04782 * @arg @ref LL_RCC_PLLR_DIV_3 04783 * @arg @ref LL_RCC_PLLR_DIV_4 04784 * @arg @ref LL_RCC_PLLR_DIV_5 04785 * @arg @ref LL_RCC_PLLR_DIV_6 04786 * @arg @ref LL_RCC_PLLR_DIV_7 04787 * @param PLLDIVR This parameter can be one of the following values: 04788 * @arg @ref LL_RCC_PLLDIVR_DIV_1 (*) 04789 * @arg @ref LL_RCC_PLLDIVR_DIV_2 (*) 04790 * @arg @ref LL_RCC_PLLDIVR_DIV_3 (*) 04791 * @arg @ref LL_RCC_PLLDIVR_DIV_4 (*) 04792 * @arg @ref LL_RCC_PLLDIVR_DIV_5 (*) 04793 * @arg @ref LL_RCC_PLLDIVR_DIV_6 (*) 04794 * @arg @ref LL_RCC_PLLDIVR_DIV_7 (*) 04795 * @arg @ref LL_RCC_PLLDIVR_DIV_8 (*) 04796 * @arg @ref LL_RCC_PLLDIVR_DIV_9 (*) 04797 * @arg @ref LL_RCC_PLLDIVR_DIV_10 (*) 04798 * @arg @ref LL_RCC_PLLDIVR_DIV_11 (*) 04799 * @arg @ref LL_RCC_PLLDIVR_DIV_12 (*) 04800 * @arg @ref LL_RCC_PLLDIVR_DIV_13 (*) 04801 * @arg @ref LL_RCC_PLLDIVR_DIV_14 (*) 04802 * @arg @ref LL_RCC_PLLDIVR_DIV_15 (*) 04803 * @arg @ref LL_RCC_PLLDIVR_DIV_16 (*) 04804 * @arg @ref LL_RCC_PLLDIVR_DIV_17 (*) 04805 * @arg @ref LL_RCC_PLLDIVR_DIV_18 (*) 04806 * @arg @ref LL_RCC_PLLDIVR_DIV_19 (*) 04807 * @arg @ref LL_RCC_PLLDIVR_DIV_20 (*) 04808 * @arg @ref LL_RCC_PLLDIVR_DIV_21 (*) 04809 * @arg @ref LL_RCC_PLLDIVR_DIV_22 (*) 04810 * @arg @ref LL_RCC_PLLDIVR_DIV_23 (*) 04811 * @arg @ref LL_RCC_PLLDIVR_DIV_24 (*) 04812 * @arg @ref LL_RCC_PLLDIVR_DIV_25 (*) 04813 * @arg @ref LL_RCC_PLLDIVR_DIV_26 (*) 04814 * @arg @ref LL_RCC_PLLDIVR_DIV_27 (*) 04815 * @arg @ref LL_RCC_PLLDIVR_DIV_28 (*) 04816 * @arg @ref LL_RCC_PLLDIVR_DIV_29 (*) 04817 * @arg @ref LL_RCC_PLLDIVR_DIV_30 (*) 04818 * @arg @ref LL_RCC_PLLDIVR_DIV_31 (*) 04819 * 04820 * (*) value not defined in all devices. 04821 * @retval None 04822 */ 04823 #if defined(RCC_DCKCFGR_PLLDIVR) 04824 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) 04825 #else 04826 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 04827 #endif /* RCC_DCKCFGR_PLLDIVR */ 04828 { 04829 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR, 04830 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR); 04831 #if defined(RCC_DCKCFGR_PLLDIVR) 04832 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR); 04833 #endif /* RCC_DCKCFGR_PLLDIVR */ 04834 } 04835 #endif /* SAI1 */ 04836 #endif /* RCC_PLLCFGR_PLLR */ 04837 04838 /** 04839 * @brief Configure PLL clock source 04840 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource 04841 * @param PLLSource This parameter can be one of the following values: 04842 * @arg @ref LL_RCC_PLLSOURCE_HSI 04843 * @arg @ref LL_RCC_PLLSOURCE_HSE 04844 * @retval None 04845 */ 04846 __STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) 04847 { 04848 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); 04849 } 04850 04851 /** 04852 * @brief Get the oscillator used as PLL clock source. 04853 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource 04854 * @retval Returned value can be one of the following values: 04855 * @arg @ref LL_RCC_PLLSOURCE_HSI 04856 * @arg @ref LL_RCC_PLLSOURCE_HSE 04857 */ 04858 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) 04859 { 04860 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 04861 } 04862 04863 /** 04864 * @brief Get Main PLL multiplication factor for VCO 04865 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN 04866 * @retval Between 50/192(*) and 432 04867 * 04868 * (*) value not defined in all devices. 04869 */ 04870 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) 04871 { 04872 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); 04873 } 04874 04875 /** 04876 * @brief Get Main PLL division factor for PLLP 04877 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP 04878 * @retval Returned value can be one of the following values: 04879 * @arg @ref LL_RCC_PLLP_DIV_2 04880 * @arg @ref LL_RCC_PLLP_DIV_4 04881 * @arg @ref LL_RCC_PLLP_DIV_6 04882 * @arg @ref LL_RCC_PLLP_DIV_8 04883 */ 04884 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void) 04885 { 04886 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP)); 04887 } 04888 04889 /** 04890 * @brief Get Main PLL division factor for PLLQ 04891 * @note used for PLL48MCLK selected for USB, RNG, SDIO (48 MHz clock) 04892 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ 04893 * @retval Returned value can be one of the following values: 04894 * @arg @ref LL_RCC_PLLQ_DIV_2 04895 * @arg @ref LL_RCC_PLLQ_DIV_3 04896 * @arg @ref LL_RCC_PLLQ_DIV_4 04897 * @arg @ref LL_RCC_PLLQ_DIV_5 04898 * @arg @ref LL_RCC_PLLQ_DIV_6 04899 * @arg @ref LL_RCC_PLLQ_DIV_7 04900 * @arg @ref LL_RCC_PLLQ_DIV_8 04901 * @arg @ref LL_RCC_PLLQ_DIV_9 04902 * @arg @ref LL_RCC_PLLQ_DIV_10 04903 * @arg @ref LL_RCC_PLLQ_DIV_11 04904 * @arg @ref LL_RCC_PLLQ_DIV_12 04905 * @arg @ref LL_RCC_PLLQ_DIV_13 04906 * @arg @ref LL_RCC_PLLQ_DIV_14 04907 * @arg @ref LL_RCC_PLLQ_DIV_15 04908 */ 04909 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void) 04910 { 04911 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ)); 04912 } 04913 04914 #if defined(RCC_PLLCFGR_PLLR) 04915 /** 04916 * @brief Get Main PLL division factor for PLLR 04917 * @note used for PLLCLK (system clock) 04918 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR 04919 * @retval Returned value can be one of the following values: 04920 * @arg @ref LL_RCC_PLLR_DIV_2 04921 * @arg @ref LL_RCC_PLLR_DIV_3 04922 * @arg @ref LL_RCC_PLLR_DIV_4 04923 * @arg @ref LL_RCC_PLLR_DIV_5 04924 * @arg @ref LL_RCC_PLLR_DIV_6 04925 * @arg @ref LL_RCC_PLLR_DIV_7 04926 */ 04927 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) 04928 { 04929 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); 04930 } 04931 #endif /* RCC_PLLCFGR_PLLR */ 04932 04933 #if defined(RCC_DCKCFGR_PLLDIVR) 04934 /** 04935 * @brief Get Main PLL division factor for PLLDIVR 04936 * @note used for PLLSAICLK (SAI1 and SAI2 clock) 04937 * @rmtoll DCKCFGR PLLDIVR LL_RCC_PLL_GetDIVR 04938 * @retval Returned value can be one of the following values: 04939 * @arg @ref LL_RCC_PLLDIVR_DIV_1 04940 * @arg @ref LL_RCC_PLLDIVR_DIV_2 04941 * @arg @ref LL_RCC_PLLDIVR_DIV_3 04942 * @arg @ref LL_RCC_PLLDIVR_DIV_4 04943 * @arg @ref LL_RCC_PLLDIVR_DIV_5 04944 * @arg @ref LL_RCC_PLLDIVR_DIV_6 04945 * @arg @ref LL_RCC_PLLDIVR_DIV_7 04946 * @arg @ref LL_RCC_PLLDIVR_DIV_8 04947 * @arg @ref LL_RCC_PLLDIVR_DIV_9 04948 * @arg @ref LL_RCC_PLLDIVR_DIV_10 04949 * @arg @ref LL_RCC_PLLDIVR_DIV_11 04950 * @arg @ref LL_RCC_PLLDIVR_DIV_12 04951 * @arg @ref LL_RCC_PLLDIVR_DIV_13 04952 * @arg @ref LL_RCC_PLLDIVR_DIV_14 04953 * @arg @ref LL_RCC_PLLDIVR_DIV_15 04954 * @arg @ref LL_RCC_PLLDIVR_DIV_16 04955 * @arg @ref LL_RCC_PLLDIVR_DIV_17 04956 * @arg @ref LL_RCC_PLLDIVR_DIV_18 04957 * @arg @ref LL_RCC_PLLDIVR_DIV_19 04958 * @arg @ref LL_RCC_PLLDIVR_DIV_20 04959 * @arg @ref LL_RCC_PLLDIVR_DIV_21 04960 * @arg @ref LL_RCC_PLLDIVR_DIV_22 04961 * @arg @ref LL_RCC_PLLDIVR_DIV_23 04962 * @arg @ref LL_RCC_PLLDIVR_DIV_24 04963 * @arg @ref LL_RCC_PLLDIVR_DIV_25 04964 * @arg @ref LL_RCC_PLLDIVR_DIV_26 04965 * @arg @ref LL_RCC_PLLDIVR_DIV_27 04966 * @arg @ref LL_RCC_PLLDIVR_DIV_28 04967 * @arg @ref LL_RCC_PLLDIVR_DIV_29 04968 * @arg @ref LL_RCC_PLLDIVR_DIV_30 04969 * @arg @ref LL_RCC_PLLDIVR_DIV_31 04970 */ 04971 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void) 04972 { 04973 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR)); 04974 } 04975 #endif /* RCC_DCKCFGR_PLLDIVR */ 04976 04977 /** 04978 * @brief Get Division factor for the main PLL and other PLL 04979 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider 04980 * @retval Returned value can be one of the following values: 04981 * @arg @ref LL_RCC_PLLM_DIV_2 04982 * @arg @ref LL_RCC_PLLM_DIV_3 04983 * @arg @ref LL_RCC_PLLM_DIV_4 04984 * @arg @ref LL_RCC_PLLM_DIV_5 04985 * @arg @ref LL_RCC_PLLM_DIV_6 04986 * @arg @ref LL_RCC_PLLM_DIV_7 04987 * @arg @ref LL_RCC_PLLM_DIV_8 04988 * @arg @ref LL_RCC_PLLM_DIV_9 04989 * @arg @ref LL_RCC_PLLM_DIV_10 04990 * @arg @ref LL_RCC_PLLM_DIV_11 04991 * @arg @ref LL_RCC_PLLM_DIV_12 04992 * @arg @ref LL_RCC_PLLM_DIV_13 04993 * @arg @ref LL_RCC_PLLM_DIV_14 04994 * @arg @ref LL_RCC_PLLM_DIV_15 04995 * @arg @ref LL_RCC_PLLM_DIV_16 04996 * @arg @ref LL_RCC_PLLM_DIV_17 04997 * @arg @ref LL_RCC_PLLM_DIV_18 04998 * @arg @ref LL_RCC_PLLM_DIV_19 04999 * @arg @ref LL_RCC_PLLM_DIV_20 05000 * @arg @ref LL_RCC_PLLM_DIV_21 05001 * @arg @ref LL_RCC_PLLM_DIV_22 05002 * @arg @ref LL_RCC_PLLM_DIV_23 05003 * @arg @ref LL_RCC_PLLM_DIV_24 05004 * @arg @ref LL_RCC_PLLM_DIV_25 05005 * @arg @ref LL_RCC_PLLM_DIV_26 05006 * @arg @ref LL_RCC_PLLM_DIV_27 05007 * @arg @ref LL_RCC_PLLM_DIV_28 05008 * @arg @ref LL_RCC_PLLM_DIV_29 05009 * @arg @ref LL_RCC_PLLM_DIV_30 05010 * @arg @ref LL_RCC_PLLM_DIV_31 05011 * @arg @ref LL_RCC_PLLM_DIV_32 05012 * @arg @ref LL_RCC_PLLM_DIV_33 05013 * @arg @ref LL_RCC_PLLM_DIV_34 05014 * @arg @ref LL_RCC_PLLM_DIV_35 05015 * @arg @ref LL_RCC_PLLM_DIV_36 05016 * @arg @ref LL_RCC_PLLM_DIV_37 05017 * @arg @ref LL_RCC_PLLM_DIV_38 05018 * @arg @ref LL_RCC_PLLM_DIV_39 05019 * @arg @ref LL_RCC_PLLM_DIV_40 05020 * @arg @ref LL_RCC_PLLM_DIV_41 05021 * @arg @ref LL_RCC_PLLM_DIV_42 05022 * @arg @ref LL_RCC_PLLM_DIV_43 05023 * @arg @ref LL_RCC_PLLM_DIV_44 05024 * @arg @ref LL_RCC_PLLM_DIV_45 05025 * @arg @ref LL_RCC_PLLM_DIV_46 05026 * @arg @ref LL_RCC_PLLM_DIV_47 05027 * @arg @ref LL_RCC_PLLM_DIV_48 05028 * @arg @ref LL_RCC_PLLM_DIV_49 05029 * @arg @ref LL_RCC_PLLM_DIV_50 05030 * @arg @ref LL_RCC_PLLM_DIV_51 05031 * @arg @ref LL_RCC_PLLM_DIV_52 05032 * @arg @ref LL_RCC_PLLM_DIV_53 05033 * @arg @ref LL_RCC_PLLM_DIV_54 05034 * @arg @ref LL_RCC_PLLM_DIV_55 05035 * @arg @ref LL_RCC_PLLM_DIV_56 05036 * @arg @ref LL_RCC_PLLM_DIV_57 05037 * @arg @ref LL_RCC_PLLM_DIV_58 05038 * @arg @ref LL_RCC_PLLM_DIV_59 05039 * @arg @ref LL_RCC_PLLM_DIV_60 05040 * @arg @ref LL_RCC_PLLM_DIV_61 05041 * @arg @ref LL_RCC_PLLM_DIV_62 05042 * @arg @ref LL_RCC_PLLM_DIV_63 05043 */ 05044 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) 05045 { 05046 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 05047 } 05048 05049 /** 05050 * @brief Configure Spread Spectrum used for PLL 05051 * @note These bits must be written before enabling PLL 05052 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n 05053 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n 05054 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum 05055 * @param Mod Between Min_Data=0 and Max_Data=8191 05056 * @param Inc Between Min_Data=0 and Max_Data=32767 05057 * @param Sel This parameter can be one of the following values: 05058 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER 05059 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN 05060 * @retval None 05061 */ 05062 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel) 05063 { 05064 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel); 05065 } 05066 05067 /** 05068 * @brief Get Spread Spectrum Modulation Period for PLL 05069 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation 05070 * @retval Between Min_Data=0 and Max_Data=8191 05071 */ 05072 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void) 05073 { 05074 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER)); 05075 } 05076 05077 /** 05078 * @brief Get Spread Spectrum Incrementation Step for PLL 05079 * @note Must be written before enabling PLL 05080 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation 05081 * @retval Between Min_Data=0 and Max_Data=32767 05082 */ 05083 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void) 05084 { 05085 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos); 05086 } 05087 05088 /** 05089 * @brief Get Spread Spectrum Selection for PLL 05090 * @note Must be written before enabling PLL 05091 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection 05092 * @retval Returned value can be one of the following values: 05093 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER 05094 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN 05095 */ 05096 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void) 05097 { 05098 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL)); 05099 } 05100 05101 /** 05102 * @brief Enable Spread Spectrum for PLL. 05103 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable 05104 * @retval None 05105 */ 05106 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void) 05107 { 05108 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); 05109 } 05110 05111 /** 05112 * @brief Disable Spread Spectrum for PLL. 05113 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable 05114 * @retval None 05115 */ 05116 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void) 05117 { 05118 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN); 05119 } 05120 05121 /** 05122 * @} 05123 */ 05124 05125 #if defined(RCC_PLLI2S_SUPPORT) 05126 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S 05127 * @{ 05128 */ 05129 05130 /** 05131 * @brief Enable PLLI2S 05132 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable 05133 * @retval None 05134 */ 05135 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void) 05136 { 05137 SET_BIT(RCC->CR, RCC_CR_PLLI2SON); 05138 } 05139 05140 /** 05141 * @brief Disable PLLI2S 05142 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable 05143 * @retval None 05144 */ 05145 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void) 05146 { 05147 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON); 05148 } 05149 05150 /** 05151 * @brief Check if PLLI2S Ready 05152 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady 05153 * @retval State of bit (1 or 0). 05154 */ 05155 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void) 05156 { 05157 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY)); 05158 } 05159 05160 #if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)) 05161 /** 05162 * @brief Configure PLLI2S used for SAI domain clock 05163 * @note PLL Source and PLLM Divider can be written only when PLL, 05164 * PLLI2S and PLLSAI(*) are disabled 05165 * @note PLLN/PLLQ/PLLR can be written only when PLLI2S is disabled 05166 * @note This can be selected for SAI 05167 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n 05168 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n 05169 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n 05170 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SAI\n 05171 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n 05172 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n 05173 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_SAI\n 05174 * DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI\n 05175 * DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_ConfigDomain_SAI 05176 * @param Source This parameter can be one of the following values: 05177 * @arg @ref LL_RCC_PLLSOURCE_HSI 05178 * @arg @ref LL_RCC_PLLSOURCE_HSE 05179 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) 05180 * 05181 * (*) value not defined in all devices. 05182 * @param PLLM This parameter can be one of the following values: 05183 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05184 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05185 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05186 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05187 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05188 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05189 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05190 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05191 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05192 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05193 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05194 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05195 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05196 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05197 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05198 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05199 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05200 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05201 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05202 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05203 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05204 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05205 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05206 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05207 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05208 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05209 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05210 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05211 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05212 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05213 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05214 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05215 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05216 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05217 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05218 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05219 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05220 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05221 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05222 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05223 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05224 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05225 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05226 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05227 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05228 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05229 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05230 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05231 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05232 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05233 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05234 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05235 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05236 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05237 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05238 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05239 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05240 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05241 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05242 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05243 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05244 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05245 * @param PLLN Between 50/192(*) and 432 05246 * 05247 * (*) value not defined in all devices. 05248 * @param PLLQ_R This parameter can be one of the following values: 05249 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 (*) 05250 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 (*) 05251 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 (*) 05252 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 (*) 05253 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 (*) 05254 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 (*) 05255 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 (*) 05256 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 (*) 05257 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 (*) 05258 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 (*) 05259 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 (*) 05260 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 (*) 05261 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 (*) 05262 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 (*) 05263 * @arg @ref LL_RCC_PLLI2SR_DIV_2 (*) 05264 * @arg @ref LL_RCC_PLLI2SR_DIV_3 (*) 05265 * @arg @ref LL_RCC_PLLI2SR_DIV_4 (*) 05266 * @arg @ref LL_RCC_PLLI2SR_DIV_5 (*) 05267 * @arg @ref LL_RCC_PLLI2SR_DIV_6 (*) 05268 * @arg @ref LL_RCC_PLLI2SR_DIV_7 (*) 05269 * 05270 * (*) value not defined in all devices. 05271 * @param PLLDIVQ_R This parameter can be one of the following values: 05272 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 (*) 05273 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 (*) 05274 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 (*) 05275 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 (*) 05276 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 (*) 05277 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 (*) 05278 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 (*) 05279 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 (*) 05280 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 (*) 05281 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 (*) 05282 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 (*) 05283 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 (*) 05284 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 (*) 05285 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 (*) 05286 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 (*) 05287 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 (*) 05288 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 (*) 05289 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 (*) 05290 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 (*) 05291 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 (*) 05292 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 (*) 05293 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 (*) 05294 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 (*) 05295 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 (*) 05296 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 (*) 05297 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 (*) 05298 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 (*) 05299 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 (*) 05300 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 (*) 05301 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 (*) 05302 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 (*) 05303 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 (*) 05304 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 (*) 05305 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 (*) 05306 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 (*) 05307 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 (*) 05308 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 (*) 05309 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 (*) 05310 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 (*) 05311 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 (*) 05312 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 (*) 05313 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 (*) 05314 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 (*) 05315 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 (*) 05316 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 (*) 05317 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 (*) 05318 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 (*) 05319 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 (*) 05320 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 (*) 05321 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 (*) 05322 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 (*) 05323 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 (*) 05324 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 (*) 05325 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 (*) 05326 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 (*) 05327 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 (*) 05328 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 (*) 05329 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 (*) 05330 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 (*) 05331 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 (*) 05332 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 (*) 05333 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 (*) 05334 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 (*) 05335 * 05336 * (*) value not defined in all devices. 05337 * @retval None 05338 */ 05339 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R) 05340 { 05341 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); 05342 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); 05343 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05344 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); 05345 #else 05346 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 05347 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05348 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos); 05349 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 05350 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R); 05351 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R); 05352 #else 05353 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R); 05354 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R); 05355 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 05356 } 05357 #endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */ 05358 05359 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ) 05360 /** 05361 * @brief Configure PLLI2S used for 48Mhz domain clock 05362 * @note PLL Source and PLLM Divider can be written only when PLL, 05363 * PLLI2S and PLLSAI(*) are disabled 05364 * @note PLLN/PLLQ can be written only when PLLI2S is disabled 05365 * @note This can be selected for RNG, USB, SDIO 05366 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_48M\n 05367 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_48M\n 05368 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_48M\n 05369 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_48M\n 05370 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_48M\n 05371 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_48M 05372 * @param Source This parameter can be one of the following values: 05373 * @arg @ref LL_RCC_PLLSOURCE_HSI 05374 * @arg @ref LL_RCC_PLLSOURCE_HSE 05375 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) 05376 * 05377 * (*) value not defined in all devices. 05378 * @param PLLM This parameter can be one of the following values: 05379 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05380 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05381 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05382 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05383 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05384 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05385 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05386 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05387 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05388 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05389 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05390 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05391 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05392 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05393 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05394 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05395 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05396 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05397 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05398 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05399 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05400 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05401 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05402 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05403 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05404 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05405 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05406 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05407 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05408 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05409 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05410 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05411 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05412 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05413 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05414 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05415 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05416 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05417 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05418 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05419 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05420 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05421 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05422 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05423 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05424 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05425 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05426 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05427 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05428 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05429 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05430 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05431 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05432 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05433 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05434 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05435 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05436 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05437 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05438 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05439 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05440 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05441 * @param PLLN Between 50 and 432 05442 * @param PLLQ This parameter can be one of the following values: 05443 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 05444 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 05445 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 05446 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 05447 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 05448 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 05449 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 05450 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 05451 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 05452 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 05453 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 05454 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 05455 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 05456 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 05457 * @retval None 05458 */ 05459 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) 05460 { 05461 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); 05462 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); 05463 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05464 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); 05465 #else 05466 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 05467 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05468 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ); 05469 } 05470 #endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */ 05471 05472 #if defined(SPDIFRX) 05473 /** 05474 * @brief Configure PLLI2S used for SPDIFRX domain clock 05475 * @note PLL Source and PLLM Divider can be written only when PLL, 05476 * PLLI2S and PLLSAI(*) are disabled 05477 * @note PLLN/PLLP can be written only when PLLI2S is disabled 05478 * @note This can be selected for SPDIFRX 05479 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n 05480 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n 05481 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n 05482 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n 05483 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX 05484 * @param Source This parameter can be one of the following values: 05485 * @arg @ref LL_RCC_PLLSOURCE_HSI 05486 * @arg @ref LL_RCC_PLLSOURCE_HSE 05487 * @param PLLM This parameter can be one of the following values: 05488 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05489 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05490 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05491 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05492 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05493 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05494 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05495 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05496 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05497 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05498 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05499 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05500 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05501 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05502 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05503 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05504 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05505 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05506 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05507 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05508 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05509 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05510 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05511 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05512 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05513 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05514 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05515 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05516 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05517 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05518 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05519 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05520 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05521 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05522 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05523 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05524 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05525 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05526 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05527 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05528 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05529 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05530 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05531 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05532 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05533 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05534 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05535 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05536 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05537 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05538 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05539 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05540 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05541 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05542 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05543 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05544 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05545 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05546 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05547 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05548 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05549 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05550 * @param PLLN Between 50 and 432 05551 * @param PLLP This parameter can be one of the following values: 05552 * @arg @ref LL_RCC_PLLI2SP_DIV_2 05553 * @arg @ref LL_RCC_PLLI2SP_DIV_4 05554 * @arg @ref LL_RCC_PLLI2SP_DIV_6 05555 * @arg @ref LL_RCC_PLLI2SP_DIV_8 05556 * @retval None 05557 */ 05558 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 05559 { 05560 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 05561 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05562 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); 05563 #else 05564 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 05565 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05566 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP); 05567 } 05568 #endif /* SPDIFRX */ 05569 05570 /** 05571 * @brief Configure PLLI2S used for I2S1 domain clock 05572 * @note PLL Source and PLLM Divider can be written only when PLL, 05573 * PLLI2S and PLLSAI(*) are disabled 05574 * @note PLLN/PLLR can be written only when PLLI2S is disabled 05575 * @note This can be selected for I2S 05576 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n 05577 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n 05578 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n 05579 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_ConfigDomain_I2S\n 05580 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n 05581 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S 05582 * @param Source This parameter can be one of the following values: 05583 * @arg @ref LL_RCC_PLLSOURCE_HSI 05584 * @arg @ref LL_RCC_PLLSOURCE_HSE 05585 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) 05586 * 05587 * (*) value not defined in all devices. 05588 * @param PLLM This parameter can be one of the following values: 05589 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05590 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05591 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05592 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05593 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05594 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05595 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05596 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05597 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05598 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05599 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05600 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05601 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05602 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05603 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05604 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05605 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05606 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05607 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05608 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05609 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05610 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05611 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05612 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05613 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05614 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05615 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05616 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05617 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05618 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05619 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05620 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05621 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05622 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05623 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05624 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05625 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05626 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05627 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05628 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05629 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05630 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05631 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05632 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05633 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05634 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05635 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05636 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05637 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05638 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05639 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05640 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05641 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05642 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05643 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05644 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05645 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05646 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05647 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05648 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05649 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05650 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05651 * @param PLLN Between 50/192(*) and 432 05652 * 05653 * (*) value not defined in all devices. 05654 * @param PLLR This parameter can be one of the following values: 05655 * @arg @ref LL_RCC_PLLI2SR_DIV_2 05656 * @arg @ref LL_RCC_PLLI2SR_DIV_3 05657 * @arg @ref LL_RCC_PLLI2SR_DIV_4 05658 * @arg @ref LL_RCC_PLLI2SR_DIV_5 05659 * @arg @ref LL_RCC_PLLI2SR_DIV_6 05660 * @arg @ref LL_RCC_PLLI2SR_DIV_7 05661 * @retval None 05662 */ 05663 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) 05664 { 05665 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U))); 05666 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U))); 05667 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05668 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM); 05669 #else 05670 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 05671 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05672 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR); 05673 } 05674 05675 /** 05676 * @brief Get I2SPLL multiplication factor for VCO 05677 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN 05678 * @retval Between 50/192(*) and 432 05679 * 05680 * (*) value not defined in all devices. 05681 */ 05682 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void) 05683 { 05684 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos); 05685 } 05686 05687 #if defined(RCC_PLLI2SCFGR_PLLI2SQ) 05688 /** 05689 * @brief Get I2SPLL division factor for PLLI2SQ 05690 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ 05691 * @retval Returned value can be one of the following values: 05692 * @arg @ref LL_RCC_PLLI2SQ_DIV_2 05693 * @arg @ref LL_RCC_PLLI2SQ_DIV_3 05694 * @arg @ref LL_RCC_PLLI2SQ_DIV_4 05695 * @arg @ref LL_RCC_PLLI2SQ_DIV_5 05696 * @arg @ref LL_RCC_PLLI2SQ_DIV_6 05697 * @arg @ref LL_RCC_PLLI2SQ_DIV_7 05698 * @arg @ref LL_RCC_PLLI2SQ_DIV_8 05699 * @arg @ref LL_RCC_PLLI2SQ_DIV_9 05700 * @arg @ref LL_RCC_PLLI2SQ_DIV_10 05701 * @arg @ref LL_RCC_PLLI2SQ_DIV_11 05702 * @arg @ref LL_RCC_PLLI2SQ_DIV_12 05703 * @arg @ref LL_RCC_PLLI2SQ_DIV_13 05704 * @arg @ref LL_RCC_PLLI2SQ_DIV_14 05705 * @arg @ref LL_RCC_PLLI2SQ_DIV_15 05706 */ 05707 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void) 05708 { 05709 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ)); 05710 } 05711 #endif /* RCC_PLLI2SCFGR_PLLI2SQ */ 05712 05713 /** 05714 * @brief Get I2SPLL division factor for PLLI2SR 05715 * @note used for PLLI2SCLK (I2S clock) 05716 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR 05717 * @retval Returned value can be one of the following values: 05718 * @arg @ref LL_RCC_PLLI2SR_DIV_2 05719 * @arg @ref LL_RCC_PLLI2SR_DIV_3 05720 * @arg @ref LL_RCC_PLLI2SR_DIV_4 05721 * @arg @ref LL_RCC_PLLI2SR_DIV_5 05722 * @arg @ref LL_RCC_PLLI2SR_DIV_6 05723 * @arg @ref LL_RCC_PLLI2SR_DIV_7 05724 */ 05725 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void) 05726 { 05727 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR)); 05728 } 05729 05730 #if defined(RCC_PLLI2SCFGR_PLLI2SP) 05731 /** 05732 * @brief Get I2SPLL division factor for PLLI2SP 05733 * @note used for PLLSPDIFRXCLK (SPDIFRX clock) 05734 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP 05735 * @retval Returned value can be one of the following values: 05736 * @arg @ref LL_RCC_PLLI2SP_DIV_2 05737 * @arg @ref LL_RCC_PLLI2SP_DIV_4 05738 * @arg @ref LL_RCC_PLLI2SP_DIV_6 05739 * @arg @ref LL_RCC_PLLI2SP_DIV_8 05740 */ 05741 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void) 05742 { 05743 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP)); 05744 } 05745 #endif /* RCC_PLLI2SCFGR_PLLI2SP */ 05746 05747 #if defined(RCC_DCKCFGR_PLLI2SDIVQ) 05748 /** 05749 * @brief Get I2SPLL division factor for PLLI2SDIVQ 05750 * @note used PLLSAICLK selected (SAI clock) 05751 * @rmtoll DCKCFGR PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ 05752 * @retval Returned value can be one of the following values: 05753 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1 05754 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2 05755 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3 05756 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4 05757 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5 05758 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6 05759 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7 05760 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8 05761 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9 05762 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10 05763 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11 05764 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12 05765 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13 05766 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14 05767 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15 05768 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16 05769 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17 05770 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18 05771 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19 05772 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20 05773 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21 05774 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22 05775 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23 05776 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24 05777 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25 05778 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26 05779 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27 05780 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28 05781 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29 05782 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30 05783 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31 05784 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32 05785 */ 05786 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void) 05787 { 05788 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ)); 05789 } 05790 #endif /* RCC_DCKCFGR_PLLI2SDIVQ */ 05791 05792 #if defined(RCC_DCKCFGR_PLLI2SDIVR) 05793 /** 05794 * @brief Get I2SPLL division factor for PLLI2SDIVR 05795 * @note used PLLSAICLK selected (SAI clock) 05796 * @rmtoll DCKCFGR PLLI2SDIVR LL_RCC_PLLI2S_GetDIVR 05797 * @retval Returned value can be one of the following values: 05798 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_1 05799 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_2 05800 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_3 05801 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_4 05802 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_5 05803 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_6 05804 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_7 05805 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_8 05806 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_9 05807 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_10 05808 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_11 05809 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_12 05810 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_13 05811 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_14 05812 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_15 05813 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_16 05814 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_17 05815 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_18 05816 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_19 05817 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_20 05818 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_21 05819 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_22 05820 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_23 05821 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_24 05822 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_25 05823 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_26 05824 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_27 05825 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_28 05826 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_29 05827 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_30 05828 * @arg @ref LL_RCC_PLLI2SDIVR_DIV_31 05829 */ 05830 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void) 05831 { 05832 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR)); 05833 } 05834 #endif /* RCC_DCKCFGR_PLLI2SDIVR */ 05835 05836 /** 05837 * @brief Get division factor for PLLI2S input clock 05838 * @rmtoll PLLCFGR PLLM LL_RCC_PLLI2S_GetDivider\n 05839 * PLLI2SCFGR PLLI2SM LL_RCC_PLLI2S_GetDivider 05840 * @retval Returned value can be one of the following values: 05841 * @arg @ref LL_RCC_PLLI2SM_DIV_2 05842 * @arg @ref LL_RCC_PLLI2SM_DIV_3 05843 * @arg @ref LL_RCC_PLLI2SM_DIV_4 05844 * @arg @ref LL_RCC_PLLI2SM_DIV_5 05845 * @arg @ref LL_RCC_PLLI2SM_DIV_6 05846 * @arg @ref LL_RCC_PLLI2SM_DIV_7 05847 * @arg @ref LL_RCC_PLLI2SM_DIV_8 05848 * @arg @ref LL_RCC_PLLI2SM_DIV_9 05849 * @arg @ref LL_RCC_PLLI2SM_DIV_10 05850 * @arg @ref LL_RCC_PLLI2SM_DIV_11 05851 * @arg @ref LL_RCC_PLLI2SM_DIV_12 05852 * @arg @ref LL_RCC_PLLI2SM_DIV_13 05853 * @arg @ref LL_RCC_PLLI2SM_DIV_14 05854 * @arg @ref LL_RCC_PLLI2SM_DIV_15 05855 * @arg @ref LL_RCC_PLLI2SM_DIV_16 05856 * @arg @ref LL_RCC_PLLI2SM_DIV_17 05857 * @arg @ref LL_RCC_PLLI2SM_DIV_18 05858 * @arg @ref LL_RCC_PLLI2SM_DIV_19 05859 * @arg @ref LL_RCC_PLLI2SM_DIV_20 05860 * @arg @ref LL_RCC_PLLI2SM_DIV_21 05861 * @arg @ref LL_RCC_PLLI2SM_DIV_22 05862 * @arg @ref LL_RCC_PLLI2SM_DIV_23 05863 * @arg @ref LL_RCC_PLLI2SM_DIV_24 05864 * @arg @ref LL_RCC_PLLI2SM_DIV_25 05865 * @arg @ref LL_RCC_PLLI2SM_DIV_26 05866 * @arg @ref LL_RCC_PLLI2SM_DIV_27 05867 * @arg @ref LL_RCC_PLLI2SM_DIV_28 05868 * @arg @ref LL_RCC_PLLI2SM_DIV_29 05869 * @arg @ref LL_RCC_PLLI2SM_DIV_30 05870 * @arg @ref LL_RCC_PLLI2SM_DIV_31 05871 * @arg @ref LL_RCC_PLLI2SM_DIV_32 05872 * @arg @ref LL_RCC_PLLI2SM_DIV_33 05873 * @arg @ref LL_RCC_PLLI2SM_DIV_34 05874 * @arg @ref LL_RCC_PLLI2SM_DIV_35 05875 * @arg @ref LL_RCC_PLLI2SM_DIV_36 05876 * @arg @ref LL_RCC_PLLI2SM_DIV_37 05877 * @arg @ref LL_RCC_PLLI2SM_DIV_38 05878 * @arg @ref LL_RCC_PLLI2SM_DIV_39 05879 * @arg @ref LL_RCC_PLLI2SM_DIV_40 05880 * @arg @ref LL_RCC_PLLI2SM_DIV_41 05881 * @arg @ref LL_RCC_PLLI2SM_DIV_42 05882 * @arg @ref LL_RCC_PLLI2SM_DIV_43 05883 * @arg @ref LL_RCC_PLLI2SM_DIV_44 05884 * @arg @ref LL_RCC_PLLI2SM_DIV_45 05885 * @arg @ref LL_RCC_PLLI2SM_DIV_46 05886 * @arg @ref LL_RCC_PLLI2SM_DIV_47 05887 * @arg @ref LL_RCC_PLLI2SM_DIV_48 05888 * @arg @ref LL_RCC_PLLI2SM_DIV_49 05889 * @arg @ref LL_RCC_PLLI2SM_DIV_50 05890 * @arg @ref LL_RCC_PLLI2SM_DIV_51 05891 * @arg @ref LL_RCC_PLLI2SM_DIV_52 05892 * @arg @ref LL_RCC_PLLI2SM_DIV_53 05893 * @arg @ref LL_RCC_PLLI2SM_DIV_54 05894 * @arg @ref LL_RCC_PLLI2SM_DIV_55 05895 * @arg @ref LL_RCC_PLLI2SM_DIV_56 05896 * @arg @ref LL_RCC_PLLI2SM_DIV_57 05897 * @arg @ref LL_RCC_PLLI2SM_DIV_58 05898 * @arg @ref LL_RCC_PLLI2SM_DIV_59 05899 * @arg @ref LL_RCC_PLLI2SM_DIV_60 05900 * @arg @ref LL_RCC_PLLI2SM_DIV_61 05901 * @arg @ref LL_RCC_PLLI2SM_DIV_62 05902 * @arg @ref LL_RCC_PLLI2SM_DIV_63 05903 */ 05904 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void) 05905 { 05906 #if defined(RCC_PLLI2SCFGR_PLLI2SM) 05907 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM)); 05908 #else 05909 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 05910 #endif /* RCC_PLLI2SCFGR_PLLI2SM */ 05911 } 05912 05913 /** 05914 * @brief Get the oscillator used as PLL clock source. 05915 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_GetMainSource\n 05916 * PLLI2SCFGR PLLI2SSRC LL_RCC_PLLI2S_GetMainSource 05917 * @retval Returned value can be one of the following values: 05918 * @arg @ref LL_RCC_PLLSOURCE_HSI 05919 * @arg @ref LL_RCC_PLLSOURCE_HSE 05920 * @arg @ref LL_RCC_PLLI2SSOURCE_PIN (*) 05921 * 05922 * (*) value not defined in all devices. 05923 */ 05924 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void) 05925 { 05926 #if defined(RCC_PLLI2SCFGR_PLLI2SSRC) 05927 uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC); 05928 uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC); 05929 uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U; 05930 return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1); 05931 #else 05932 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); 05933 #endif /* RCC_PLLI2SCFGR_PLLI2SSRC */ 05934 } 05935 05936 /** 05937 * @} 05938 */ 05939 #endif /* RCC_PLLI2S_SUPPORT */ 05940 05941 #if defined(RCC_PLLSAI_SUPPORT) 05942 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI 05943 * @{ 05944 */ 05945 05946 /** 05947 * @brief Enable PLLSAI 05948 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable 05949 * @retval None 05950 */ 05951 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void) 05952 { 05953 SET_BIT(RCC->CR, RCC_CR_PLLSAION); 05954 } 05955 05956 /** 05957 * @brief Disable PLLSAI 05958 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable 05959 * @retval None 05960 */ 05961 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void) 05962 { 05963 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION); 05964 } 05965 05966 /** 05967 * @brief Check if PLLSAI Ready 05968 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady 05969 * @retval State of bit (1 or 0). 05970 */ 05971 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void) 05972 { 05973 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY)); 05974 } 05975 05976 /** 05977 * @brief Configure PLLSAI used for SAI domain clock 05978 * @note PLL Source and PLLM Divider can be written only when PLL, 05979 * PLLI2S and PLLSAI(*) are disabled 05980 * @note PLLN/PLLQ can be written only when PLLSAI is disabled 05981 * @note This can be selected for SAI 05982 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n 05983 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n 05984 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_SAI\n 05985 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n 05986 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n 05987 * DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI 05988 * @param Source This parameter can be one of the following values: 05989 * @arg @ref LL_RCC_PLLSOURCE_HSI 05990 * @arg @ref LL_RCC_PLLSOURCE_HSE 05991 * @param PLLM This parameter can be one of the following values: 05992 * @arg @ref LL_RCC_PLLSAIM_DIV_2 05993 * @arg @ref LL_RCC_PLLSAIM_DIV_3 05994 * @arg @ref LL_RCC_PLLSAIM_DIV_4 05995 * @arg @ref LL_RCC_PLLSAIM_DIV_5 05996 * @arg @ref LL_RCC_PLLSAIM_DIV_6 05997 * @arg @ref LL_RCC_PLLSAIM_DIV_7 05998 * @arg @ref LL_RCC_PLLSAIM_DIV_8 05999 * @arg @ref LL_RCC_PLLSAIM_DIV_9 06000 * @arg @ref LL_RCC_PLLSAIM_DIV_10 06001 * @arg @ref LL_RCC_PLLSAIM_DIV_11 06002 * @arg @ref LL_RCC_PLLSAIM_DIV_12 06003 * @arg @ref LL_RCC_PLLSAIM_DIV_13 06004 * @arg @ref LL_RCC_PLLSAIM_DIV_14 06005 * @arg @ref LL_RCC_PLLSAIM_DIV_15 06006 * @arg @ref LL_RCC_PLLSAIM_DIV_16 06007 * @arg @ref LL_RCC_PLLSAIM_DIV_17 06008 * @arg @ref LL_RCC_PLLSAIM_DIV_18 06009 * @arg @ref LL_RCC_PLLSAIM_DIV_19 06010 * @arg @ref LL_RCC_PLLSAIM_DIV_20 06011 * @arg @ref LL_RCC_PLLSAIM_DIV_21 06012 * @arg @ref LL_RCC_PLLSAIM_DIV_22 06013 * @arg @ref LL_RCC_PLLSAIM_DIV_23 06014 * @arg @ref LL_RCC_PLLSAIM_DIV_24 06015 * @arg @ref LL_RCC_PLLSAIM_DIV_25 06016 * @arg @ref LL_RCC_PLLSAIM_DIV_26 06017 * @arg @ref LL_RCC_PLLSAIM_DIV_27 06018 * @arg @ref LL_RCC_PLLSAIM_DIV_28 06019 * @arg @ref LL_RCC_PLLSAIM_DIV_29 06020 * @arg @ref LL_RCC_PLLSAIM_DIV_30 06021 * @arg @ref LL_RCC_PLLSAIM_DIV_31 06022 * @arg @ref LL_RCC_PLLSAIM_DIV_32 06023 * @arg @ref LL_RCC_PLLSAIM_DIV_33 06024 * @arg @ref LL_RCC_PLLSAIM_DIV_34 06025 * @arg @ref LL_RCC_PLLSAIM_DIV_35 06026 * @arg @ref LL_RCC_PLLSAIM_DIV_36 06027 * @arg @ref LL_RCC_PLLSAIM_DIV_37 06028 * @arg @ref LL_RCC_PLLSAIM_DIV_38 06029 * @arg @ref LL_RCC_PLLSAIM_DIV_39 06030 * @arg @ref LL_RCC_PLLSAIM_DIV_40 06031 * @arg @ref LL_RCC_PLLSAIM_DIV_41 06032 * @arg @ref LL_RCC_PLLSAIM_DIV_42 06033 * @arg @ref LL_RCC_PLLSAIM_DIV_43 06034 * @arg @ref LL_RCC_PLLSAIM_DIV_44 06035 * @arg @ref LL_RCC_PLLSAIM_DIV_45 06036 * @arg @ref LL_RCC_PLLSAIM_DIV_46 06037 * @arg @ref LL_RCC_PLLSAIM_DIV_47 06038 * @arg @ref LL_RCC_PLLSAIM_DIV_48 06039 * @arg @ref LL_RCC_PLLSAIM_DIV_49 06040 * @arg @ref LL_RCC_PLLSAIM_DIV_50 06041 * @arg @ref LL_RCC_PLLSAIM_DIV_51 06042 * @arg @ref LL_RCC_PLLSAIM_DIV_52 06043 * @arg @ref LL_RCC_PLLSAIM_DIV_53 06044 * @arg @ref LL_RCC_PLLSAIM_DIV_54 06045 * @arg @ref LL_RCC_PLLSAIM_DIV_55 06046 * @arg @ref LL_RCC_PLLSAIM_DIV_56 06047 * @arg @ref LL_RCC_PLLSAIM_DIV_57 06048 * @arg @ref LL_RCC_PLLSAIM_DIV_58 06049 * @arg @ref LL_RCC_PLLSAIM_DIV_59 06050 * @arg @ref LL_RCC_PLLSAIM_DIV_60 06051 * @arg @ref LL_RCC_PLLSAIM_DIV_61 06052 * @arg @ref LL_RCC_PLLSAIM_DIV_62 06053 * @arg @ref LL_RCC_PLLSAIM_DIV_63 06054 * @param PLLN Between 49/50(*) and 432 06055 * 06056 * (*) value not defined in all devices. 06057 * @param PLLQ This parameter can be one of the following values: 06058 * @arg @ref LL_RCC_PLLSAIQ_DIV_2 06059 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 06060 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 06061 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 06062 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 06063 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 06064 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 06065 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 06066 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 06067 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 06068 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 06069 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 06070 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 06071 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 06072 * @param PLLDIVQ This parameter can be one of the following values: 06073 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 06074 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 06075 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 06076 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 06077 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 06078 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 06079 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 06080 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 06081 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 06082 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 06083 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 06084 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 06085 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 06086 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 06087 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 06088 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 06089 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 06090 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 06091 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 06092 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 06093 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 06094 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 06095 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 06096 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 06097 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 06098 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 06099 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 06100 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 06101 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 06102 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 06103 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 06104 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 06105 * @retval None 06106 */ 06107 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) 06108 { 06109 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 06110 #if defined(RCC_PLLSAICFGR_PLLSAIM) 06111 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); 06112 #else 06113 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 06114 #endif /* RCC_PLLSAICFGR_PLLSAIM */ 06115 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ); 06116 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ); 06117 } 06118 06119 #if defined(RCC_PLLSAICFGR_PLLSAIP) 06120 /** 06121 * @brief Configure PLLSAI used for 48Mhz domain clock 06122 * @note PLL Source and PLLM Divider can be written only when PLL, 06123 * PLLI2S and PLLSAI(*) are disabled 06124 * @note PLLN/PLLP can be written only when PLLSAI is disabled 06125 * @note This can be selected for USB, RNG, SDIO 06126 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n 06127 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n 06128 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_ConfigDomain_48M\n 06129 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n 06130 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M 06131 * @param Source This parameter can be one of the following values: 06132 * @arg @ref LL_RCC_PLLSOURCE_HSI 06133 * @arg @ref LL_RCC_PLLSOURCE_HSE 06134 * @param PLLM This parameter can be one of the following values: 06135 * @arg @ref LL_RCC_PLLSAIM_DIV_2 06136 * @arg @ref LL_RCC_PLLSAIM_DIV_3 06137 * @arg @ref LL_RCC_PLLSAIM_DIV_4 06138 * @arg @ref LL_RCC_PLLSAIM_DIV_5 06139 * @arg @ref LL_RCC_PLLSAIM_DIV_6 06140 * @arg @ref LL_RCC_PLLSAIM_DIV_7 06141 * @arg @ref LL_RCC_PLLSAIM_DIV_8 06142 * @arg @ref LL_RCC_PLLSAIM_DIV_9 06143 * @arg @ref LL_RCC_PLLSAIM_DIV_10 06144 * @arg @ref LL_RCC_PLLSAIM_DIV_11 06145 * @arg @ref LL_RCC_PLLSAIM_DIV_12 06146 * @arg @ref LL_RCC_PLLSAIM_DIV_13 06147 * @arg @ref LL_RCC_PLLSAIM_DIV_14 06148 * @arg @ref LL_RCC_PLLSAIM_DIV_15 06149 * @arg @ref LL_RCC_PLLSAIM_DIV_16 06150 * @arg @ref LL_RCC_PLLSAIM_DIV_17 06151 * @arg @ref LL_RCC_PLLSAIM_DIV_18 06152 * @arg @ref LL_RCC_PLLSAIM_DIV_19 06153 * @arg @ref LL_RCC_PLLSAIM_DIV_20 06154 * @arg @ref LL_RCC_PLLSAIM_DIV_21 06155 * @arg @ref LL_RCC_PLLSAIM_DIV_22 06156 * @arg @ref LL_RCC_PLLSAIM_DIV_23 06157 * @arg @ref LL_RCC_PLLSAIM_DIV_24 06158 * @arg @ref LL_RCC_PLLSAIM_DIV_25 06159 * @arg @ref LL_RCC_PLLSAIM_DIV_26 06160 * @arg @ref LL_RCC_PLLSAIM_DIV_27 06161 * @arg @ref LL_RCC_PLLSAIM_DIV_28 06162 * @arg @ref LL_RCC_PLLSAIM_DIV_29 06163 * @arg @ref LL_RCC_PLLSAIM_DIV_30 06164 * @arg @ref LL_RCC_PLLSAIM_DIV_31 06165 * @arg @ref LL_RCC_PLLSAIM_DIV_32 06166 * @arg @ref LL_RCC_PLLSAIM_DIV_33 06167 * @arg @ref LL_RCC_PLLSAIM_DIV_34 06168 * @arg @ref LL_RCC_PLLSAIM_DIV_35 06169 * @arg @ref LL_RCC_PLLSAIM_DIV_36 06170 * @arg @ref LL_RCC_PLLSAIM_DIV_37 06171 * @arg @ref LL_RCC_PLLSAIM_DIV_38 06172 * @arg @ref LL_RCC_PLLSAIM_DIV_39 06173 * @arg @ref LL_RCC_PLLSAIM_DIV_40 06174 * @arg @ref LL_RCC_PLLSAIM_DIV_41 06175 * @arg @ref LL_RCC_PLLSAIM_DIV_42 06176 * @arg @ref LL_RCC_PLLSAIM_DIV_43 06177 * @arg @ref LL_RCC_PLLSAIM_DIV_44 06178 * @arg @ref LL_RCC_PLLSAIM_DIV_45 06179 * @arg @ref LL_RCC_PLLSAIM_DIV_46 06180 * @arg @ref LL_RCC_PLLSAIM_DIV_47 06181 * @arg @ref LL_RCC_PLLSAIM_DIV_48 06182 * @arg @ref LL_RCC_PLLSAIM_DIV_49 06183 * @arg @ref LL_RCC_PLLSAIM_DIV_50 06184 * @arg @ref LL_RCC_PLLSAIM_DIV_51 06185 * @arg @ref LL_RCC_PLLSAIM_DIV_52 06186 * @arg @ref LL_RCC_PLLSAIM_DIV_53 06187 * @arg @ref LL_RCC_PLLSAIM_DIV_54 06188 * @arg @ref LL_RCC_PLLSAIM_DIV_55 06189 * @arg @ref LL_RCC_PLLSAIM_DIV_56 06190 * @arg @ref LL_RCC_PLLSAIM_DIV_57 06191 * @arg @ref LL_RCC_PLLSAIM_DIV_58 06192 * @arg @ref LL_RCC_PLLSAIM_DIV_59 06193 * @arg @ref LL_RCC_PLLSAIM_DIV_60 06194 * @arg @ref LL_RCC_PLLSAIM_DIV_61 06195 * @arg @ref LL_RCC_PLLSAIM_DIV_62 06196 * @arg @ref LL_RCC_PLLSAIM_DIV_63 06197 * @param PLLN Between 50 and 432 06198 * @param PLLP This parameter can be one of the following values: 06199 * @arg @ref LL_RCC_PLLSAIP_DIV_2 06200 * @arg @ref LL_RCC_PLLSAIP_DIV_4 06201 * @arg @ref LL_RCC_PLLSAIP_DIV_6 06202 * @arg @ref LL_RCC_PLLSAIP_DIV_8 06203 * @retval None 06204 */ 06205 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) 06206 { 06207 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source); 06208 #if defined(RCC_PLLSAICFGR_PLLSAIM) 06209 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM); 06210 #else 06211 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM); 06212 #endif /* RCC_PLLSAICFGR_PLLSAIM */ 06213 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP); 06214 } 06215 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 06216 06217 #if defined(LTDC) 06218 /** 06219 * @brief Configure PLLSAI used for LTDC domain clock 06220 * @note PLL Source and PLLM Divider can be written only when PLL, 06221 * PLLI2S and PLLSAI(*) are disabled 06222 * @note PLLN/PLLR can be written only when PLLSAI is disabled 06223 * @note This can be selected for LTDC 06224 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n 06225 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n 06226 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n 06227 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n 06228 * DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC 06229 * @param Source This parameter can be one of the following values: 06230 * @arg @ref LL_RCC_PLLSOURCE_HSI 06231 * @arg @ref LL_RCC_PLLSOURCE_HSE 06232 * @param PLLM This parameter can be one of the following values: 06233 * @arg @ref LL_RCC_PLLSAIM_DIV_2 06234 * @arg @ref LL_RCC_PLLSAIM_DIV_3 06235 * @arg @ref LL_RCC_PLLSAIM_DIV_4 06236 * @arg @ref LL_RCC_PLLSAIM_DIV_5 06237 * @arg @ref LL_RCC_PLLSAIM_DIV_6 06238 * @arg @ref LL_RCC_PLLSAIM_DIV_7 06239 * @arg @ref LL_RCC_PLLSAIM_DIV_8 06240 * @arg @ref LL_RCC_PLLSAIM_DIV_9 06241 * @arg @ref LL_RCC_PLLSAIM_DIV_10 06242 * @arg @ref LL_RCC_PLLSAIM_DIV_11 06243 * @arg @ref LL_RCC_PLLSAIM_DIV_12 06244 * @arg @ref LL_RCC_PLLSAIM_DIV_13 06245 * @arg @ref LL_RCC_PLLSAIM_DIV_14 06246 * @arg @ref LL_RCC_PLLSAIM_DIV_15 06247 * @arg @ref LL_RCC_PLLSAIM_DIV_16 06248 * @arg @ref LL_RCC_PLLSAIM_DIV_17 06249 * @arg @ref LL_RCC_PLLSAIM_DIV_18 06250 * @arg @ref LL_RCC_PLLSAIM_DIV_19 06251 * @arg @ref LL_RCC_PLLSAIM_DIV_20 06252 * @arg @ref LL_RCC_PLLSAIM_DIV_21 06253 * @arg @ref LL_RCC_PLLSAIM_DIV_22 06254 * @arg @ref LL_RCC_PLLSAIM_DIV_23 06255 * @arg @ref LL_RCC_PLLSAIM_DIV_24 06256 * @arg @ref LL_RCC_PLLSAIM_DIV_25 06257 * @arg @ref LL_RCC_PLLSAIM_DIV_26 06258 * @arg @ref LL_RCC_PLLSAIM_DIV_27 06259 * @arg @ref LL_RCC_PLLSAIM_DIV_28 06260 * @arg @ref LL_RCC_PLLSAIM_DIV_29 06261 * @arg @ref LL_RCC_PLLSAIM_DIV_30 06262 * @arg @ref LL_RCC_PLLSAIM_DIV_31 06263 * @arg @ref LL_RCC_PLLSAIM_DIV_32 06264 * @arg @ref LL_RCC_PLLSAIM_DIV_33 06265 * @arg @ref LL_RCC_PLLSAIM_DIV_34 06266 * @arg @ref LL_RCC_PLLSAIM_DIV_35 06267 * @arg @ref LL_RCC_PLLSAIM_DIV_36 06268 * @arg @ref LL_RCC_PLLSAIM_DIV_37 06269 * @arg @ref LL_RCC_PLLSAIM_DIV_38 06270 * @arg @ref LL_RCC_PLLSAIM_DIV_39 06271 * @arg @ref LL_RCC_PLLSAIM_DIV_40 06272 * @arg @ref LL_RCC_PLLSAIM_DIV_41 06273 * @arg @ref LL_RCC_PLLSAIM_DIV_42 06274 * @arg @ref LL_RCC_PLLSAIM_DIV_43 06275 * @arg @ref LL_RCC_PLLSAIM_DIV_44 06276 * @arg @ref LL_RCC_PLLSAIM_DIV_45 06277 * @arg @ref LL_RCC_PLLSAIM_DIV_46 06278 * @arg @ref LL_RCC_PLLSAIM_DIV_47 06279 * @arg @ref LL_RCC_PLLSAIM_DIV_48 06280 * @arg @ref LL_RCC_PLLSAIM_DIV_49 06281 * @arg @ref LL_RCC_PLLSAIM_DIV_50 06282 * @arg @ref LL_RCC_PLLSAIM_DIV_51 06283 * @arg @ref LL_RCC_PLLSAIM_DIV_52 06284 * @arg @ref LL_RCC_PLLSAIM_DIV_53 06285 * @arg @ref LL_RCC_PLLSAIM_DIV_54 06286 * @arg @ref LL_RCC_PLLSAIM_DIV_55 06287 * @arg @ref LL_RCC_PLLSAIM_DIV_56 06288 * @arg @ref LL_RCC_PLLSAIM_DIV_57 06289 * @arg @ref LL_RCC_PLLSAIM_DIV_58 06290 * @arg @ref LL_RCC_PLLSAIM_DIV_59 06291 * @arg @ref LL_RCC_PLLSAIM_DIV_60 06292 * @arg @ref LL_RCC_PLLSAIM_DIV_61 06293 * @arg @ref LL_RCC_PLLSAIM_DIV_62 06294 * @arg @ref LL_RCC_PLLSAIM_DIV_63 06295 * @param PLLN Between 49/50(*) and 432 06296 * 06297 * (*) value not defined in all devices. 06298 * @param PLLR This parameter can be one of the following values: 06299 * @arg @ref LL_RCC_PLLSAIR_DIV_2 06300 * @arg @ref LL_RCC_PLLSAIR_DIV_3 06301 * @arg @ref LL_RCC_PLLSAIR_DIV_4 06302 * @arg @ref LL_RCC_PLLSAIR_DIV_5 06303 * @arg @ref LL_RCC_PLLSAIR_DIV_6 06304 * @arg @ref LL_RCC_PLLSAIR_DIV_7 06305 * @param PLLDIVR This parameter can be one of the following values: 06306 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 06307 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 06308 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 06309 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 06310 * @retval None 06311 */ 06312 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) 06313 { 06314 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM); 06315 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR); 06316 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR); 06317 } 06318 #endif /* LTDC */ 06319 06320 /** 06321 * @brief Get division factor for PLLSAI input clock 06322 * @rmtoll PLLCFGR PLLM LL_RCC_PLLSAI_GetDivider\n 06323 * PLLSAICFGR PLLSAIM LL_RCC_PLLSAI_GetDivider 06324 * @retval Returned value can be one of the following values: 06325 * @arg @ref LL_RCC_PLLSAIM_DIV_2 06326 * @arg @ref LL_RCC_PLLSAIM_DIV_3 06327 * @arg @ref LL_RCC_PLLSAIM_DIV_4 06328 * @arg @ref LL_RCC_PLLSAIM_DIV_5 06329 * @arg @ref LL_RCC_PLLSAIM_DIV_6 06330 * @arg @ref LL_RCC_PLLSAIM_DIV_7 06331 * @arg @ref LL_RCC_PLLSAIM_DIV_8 06332 * @arg @ref LL_RCC_PLLSAIM_DIV_9 06333 * @arg @ref LL_RCC_PLLSAIM_DIV_10 06334 * @arg @ref LL_RCC_PLLSAIM_DIV_11 06335 * @arg @ref LL_RCC_PLLSAIM_DIV_12 06336 * @arg @ref LL_RCC_PLLSAIM_DIV_13 06337 * @arg @ref LL_RCC_PLLSAIM_DIV_14 06338 * @arg @ref LL_RCC_PLLSAIM_DIV_15 06339 * @arg @ref LL_RCC_PLLSAIM_DIV_16 06340 * @arg @ref LL_RCC_PLLSAIM_DIV_17 06341 * @arg @ref LL_RCC_PLLSAIM_DIV_18 06342 * @arg @ref LL_RCC_PLLSAIM_DIV_19 06343 * @arg @ref LL_RCC_PLLSAIM_DIV_20 06344 * @arg @ref LL_RCC_PLLSAIM_DIV_21 06345 * @arg @ref LL_RCC_PLLSAIM_DIV_22 06346 * @arg @ref LL_RCC_PLLSAIM_DIV_23 06347 * @arg @ref LL_RCC_PLLSAIM_DIV_24 06348 * @arg @ref LL_RCC_PLLSAIM_DIV_25 06349 * @arg @ref LL_RCC_PLLSAIM_DIV_26 06350 * @arg @ref LL_RCC_PLLSAIM_DIV_27 06351 * @arg @ref LL_RCC_PLLSAIM_DIV_28 06352 * @arg @ref LL_RCC_PLLSAIM_DIV_29 06353 * @arg @ref LL_RCC_PLLSAIM_DIV_30 06354 * @arg @ref LL_RCC_PLLSAIM_DIV_31 06355 * @arg @ref LL_RCC_PLLSAIM_DIV_32 06356 * @arg @ref LL_RCC_PLLSAIM_DIV_33 06357 * @arg @ref LL_RCC_PLLSAIM_DIV_34 06358 * @arg @ref LL_RCC_PLLSAIM_DIV_35 06359 * @arg @ref LL_RCC_PLLSAIM_DIV_36 06360 * @arg @ref LL_RCC_PLLSAIM_DIV_37 06361 * @arg @ref LL_RCC_PLLSAIM_DIV_38 06362 * @arg @ref LL_RCC_PLLSAIM_DIV_39 06363 * @arg @ref LL_RCC_PLLSAIM_DIV_40 06364 * @arg @ref LL_RCC_PLLSAIM_DIV_41 06365 * @arg @ref LL_RCC_PLLSAIM_DIV_42 06366 * @arg @ref LL_RCC_PLLSAIM_DIV_43 06367 * @arg @ref LL_RCC_PLLSAIM_DIV_44 06368 * @arg @ref LL_RCC_PLLSAIM_DIV_45 06369 * @arg @ref LL_RCC_PLLSAIM_DIV_46 06370 * @arg @ref LL_RCC_PLLSAIM_DIV_47 06371 * @arg @ref LL_RCC_PLLSAIM_DIV_48 06372 * @arg @ref LL_RCC_PLLSAIM_DIV_49 06373 * @arg @ref LL_RCC_PLLSAIM_DIV_50 06374 * @arg @ref LL_RCC_PLLSAIM_DIV_51 06375 * @arg @ref LL_RCC_PLLSAIM_DIV_52 06376 * @arg @ref LL_RCC_PLLSAIM_DIV_53 06377 * @arg @ref LL_RCC_PLLSAIM_DIV_54 06378 * @arg @ref LL_RCC_PLLSAIM_DIV_55 06379 * @arg @ref LL_RCC_PLLSAIM_DIV_56 06380 * @arg @ref LL_RCC_PLLSAIM_DIV_57 06381 * @arg @ref LL_RCC_PLLSAIM_DIV_58 06382 * @arg @ref LL_RCC_PLLSAIM_DIV_59 06383 * @arg @ref LL_RCC_PLLSAIM_DIV_60 06384 * @arg @ref LL_RCC_PLLSAIM_DIV_61 06385 * @arg @ref LL_RCC_PLLSAIM_DIV_62 06386 * @arg @ref LL_RCC_PLLSAIM_DIV_63 06387 */ 06388 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void) 06389 { 06390 #if defined(RCC_PLLSAICFGR_PLLSAIM) 06391 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM)); 06392 #else 06393 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); 06394 #endif /* RCC_PLLSAICFGR_PLLSAIM */ 06395 } 06396 06397 /** 06398 * @brief Get SAIPLL multiplication factor for VCO 06399 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN 06400 * @retval Between 49/50(*) and 432 06401 * 06402 * (*) value not defined in all devices. 06403 */ 06404 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void) 06405 { 06406 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos); 06407 } 06408 06409 /** 06410 * @brief Get SAIPLL division factor for PLLSAIQ 06411 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ 06412 * @retval Returned value can be one of the following values: 06413 * @arg @ref LL_RCC_PLLSAIQ_DIV_2 06414 * @arg @ref LL_RCC_PLLSAIQ_DIV_3 06415 * @arg @ref LL_RCC_PLLSAIQ_DIV_4 06416 * @arg @ref LL_RCC_PLLSAIQ_DIV_5 06417 * @arg @ref LL_RCC_PLLSAIQ_DIV_6 06418 * @arg @ref LL_RCC_PLLSAIQ_DIV_7 06419 * @arg @ref LL_RCC_PLLSAIQ_DIV_8 06420 * @arg @ref LL_RCC_PLLSAIQ_DIV_9 06421 * @arg @ref LL_RCC_PLLSAIQ_DIV_10 06422 * @arg @ref LL_RCC_PLLSAIQ_DIV_11 06423 * @arg @ref LL_RCC_PLLSAIQ_DIV_12 06424 * @arg @ref LL_RCC_PLLSAIQ_DIV_13 06425 * @arg @ref LL_RCC_PLLSAIQ_DIV_14 06426 * @arg @ref LL_RCC_PLLSAIQ_DIV_15 06427 */ 06428 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void) 06429 { 06430 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ)); 06431 } 06432 06433 #if defined(RCC_PLLSAICFGR_PLLSAIR) 06434 /** 06435 * @brief Get SAIPLL division factor for PLLSAIR 06436 * @note used for PLLSAICLK (SAI clock) 06437 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR 06438 * @retval Returned value can be one of the following values: 06439 * @arg @ref LL_RCC_PLLSAIR_DIV_2 06440 * @arg @ref LL_RCC_PLLSAIR_DIV_3 06441 * @arg @ref LL_RCC_PLLSAIR_DIV_4 06442 * @arg @ref LL_RCC_PLLSAIR_DIV_5 06443 * @arg @ref LL_RCC_PLLSAIR_DIV_6 06444 * @arg @ref LL_RCC_PLLSAIR_DIV_7 06445 */ 06446 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void) 06447 { 06448 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR)); 06449 } 06450 #endif /* RCC_PLLSAICFGR_PLLSAIR */ 06451 06452 #if defined(RCC_PLLSAICFGR_PLLSAIP) 06453 /** 06454 * @brief Get SAIPLL division factor for PLLSAIP 06455 * @note used for PLL48MCLK (48M domain clock) 06456 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP 06457 * @retval Returned value can be one of the following values: 06458 * @arg @ref LL_RCC_PLLSAIP_DIV_2 06459 * @arg @ref LL_RCC_PLLSAIP_DIV_4 06460 * @arg @ref LL_RCC_PLLSAIP_DIV_6 06461 * @arg @ref LL_RCC_PLLSAIP_DIV_8 06462 */ 06463 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void) 06464 { 06465 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP)); 06466 } 06467 #endif /* RCC_PLLSAICFGR_PLLSAIP */ 06468 06469 /** 06470 * @brief Get SAIPLL division factor for PLLSAIDIVQ 06471 * @note used PLLSAICLK selected (SAI clock) 06472 * @rmtoll DCKCFGR PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ 06473 * @retval Returned value can be one of the following values: 06474 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1 06475 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2 06476 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3 06477 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4 06478 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5 06479 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6 06480 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7 06481 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8 06482 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9 06483 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10 06484 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11 06485 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12 06486 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13 06487 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14 06488 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15 06489 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16 06490 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17 06491 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18 06492 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19 06493 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20 06494 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21 06495 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22 06496 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23 06497 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24 06498 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25 06499 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26 06500 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27 06501 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28 06502 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29 06503 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30 06504 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31 06505 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32 06506 */ 06507 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void) 06508 { 06509 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ)); 06510 } 06511 06512 #if defined(RCC_DCKCFGR_PLLSAIDIVR) 06513 /** 06514 * @brief Get SAIPLL division factor for PLLSAIDIVR 06515 * @note used for LTDC domain clock 06516 * @rmtoll DCKCFGR PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR 06517 * @retval Returned value can be one of the following values: 06518 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2 06519 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4 06520 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8 06521 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16 06522 */ 06523 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void) 06524 { 06525 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR)); 06526 } 06527 #endif /* RCC_DCKCFGR_PLLSAIDIVR */ 06528 06529 /** 06530 * @} 06531 */ 06532 #endif /* RCC_PLLSAI_SUPPORT */ 06533 06534 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management 06535 * @{ 06536 */ 06537 06538 /** 06539 * @brief Clear LSI ready interrupt flag 06540 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY 06541 * @retval None 06542 */ 06543 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) 06544 { 06545 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC); 06546 } 06547 06548 /** 06549 * @brief Clear LSE ready interrupt flag 06550 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY 06551 * @retval None 06552 */ 06553 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) 06554 { 06555 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC); 06556 } 06557 06558 /** 06559 * @brief Clear HSI ready interrupt flag 06560 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY 06561 * @retval None 06562 */ 06563 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) 06564 { 06565 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC); 06566 } 06567 06568 /** 06569 * @brief Clear HSE ready interrupt flag 06570 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY 06571 * @retval None 06572 */ 06573 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) 06574 { 06575 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC); 06576 } 06577 06578 /** 06579 * @brief Clear PLL ready interrupt flag 06580 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY 06581 * @retval None 06582 */ 06583 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) 06584 { 06585 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC); 06586 } 06587 06588 #if defined(RCC_PLLI2S_SUPPORT) 06589 /** 06590 * @brief Clear PLLI2S ready interrupt flag 06591 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY 06592 * @retval None 06593 */ 06594 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void) 06595 { 06596 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC); 06597 } 06598 06599 #endif /* RCC_PLLI2S_SUPPORT */ 06600 06601 #if defined(RCC_PLLSAI_SUPPORT) 06602 /** 06603 * @brief Clear PLLSAI ready interrupt flag 06604 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY 06605 * @retval None 06606 */ 06607 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void) 06608 { 06609 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC); 06610 } 06611 06612 #endif /* RCC_PLLSAI_SUPPORT */ 06613 06614 /** 06615 * @brief Clear Clock security system interrupt flag 06616 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS 06617 * @retval None 06618 */ 06619 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) 06620 { 06621 SET_BIT(RCC->CIR, RCC_CIR_CSSC); 06622 } 06623 06624 /** 06625 * @brief Check if LSI ready interrupt occurred or not 06626 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY 06627 * @retval State of bit (1 or 0). 06628 */ 06629 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) 06630 { 06631 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF)); 06632 } 06633 06634 /** 06635 * @brief Check if LSE ready interrupt occurred or not 06636 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY 06637 * @retval State of bit (1 or 0). 06638 */ 06639 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) 06640 { 06641 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF)); 06642 } 06643 06644 /** 06645 * @brief Check if HSI ready interrupt occurred or not 06646 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY 06647 * @retval State of bit (1 or 0). 06648 */ 06649 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) 06650 { 06651 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF)); 06652 } 06653 06654 /** 06655 * @brief Check if HSE ready interrupt occurred or not 06656 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY 06657 * @retval State of bit (1 or 0). 06658 */ 06659 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) 06660 { 06661 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF)); 06662 } 06663 06664 /** 06665 * @brief Check if PLL ready interrupt occurred or not 06666 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY 06667 * @retval State of bit (1 or 0). 06668 */ 06669 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) 06670 { 06671 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF)); 06672 } 06673 06674 #if defined(RCC_PLLI2S_SUPPORT) 06675 /** 06676 * @brief Check if PLLI2S ready interrupt occurred or not 06677 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY 06678 * @retval State of bit (1 or 0). 06679 */ 06680 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void) 06681 { 06682 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF)); 06683 } 06684 #endif /* RCC_PLLI2S_SUPPORT */ 06685 06686 #if defined(RCC_PLLSAI_SUPPORT) 06687 /** 06688 * @brief Check if PLLSAI ready interrupt occurred or not 06689 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY 06690 * @retval State of bit (1 or 0). 06691 */ 06692 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void) 06693 { 06694 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF)); 06695 } 06696 #endif /* RCC_PLLSAI_SUPPORT */ 06697 06698 /** 06699 * @brief Check if Clock security system interrupt occurred or not 06700 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS 06701 * @retval State of bit (1 or 0). 06702 */ 06703 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) 06704 { 06705 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF)); 06706 } 06707 06708 /** 06709 * @brief Check if RCC flag Independent Watchdog reset is set or not. 06710 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST 06711 * @retval State of bit (1 or 0). 06712 */ 06713 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) 06714 { 06715 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)); 06716 } 06717 06718 /** 06719 * @brief Check if RCC flag Low Power reset is set or not. 06720 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST 06721 * @retval State of bit (1 or 0). 06722 */ 06723 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) 06724 { 06725 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF)); 06726 } 06727 06728 /** 06729 * @brief Check if RCC flag Pin reset is set or not. 06730 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST 06731 * @retval State of bit (1 or 0). 06732 */ 06733 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) 06734 { 06735 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)); 06736 } 06737 06738 /** 06739 * @brief Check if RCC flag POR/PDR reset is set or not. 06740 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST 06741 * @retval State of bit (1 or 0). 06742 */ 06743 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void) 06744 { 06745 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF)); 06746 } 06747 06748 /** 06749 * @brief Check if RCC flag Software reset is set or not. 06750 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST 06751 * @retval State of bit (1 or 0). 06752 */ 06753 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) 06754 { 06755 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)); 06756 } 06757 06758 /** 06759 * @brief Check if RCC flag Window Watchdog reset is set or not. 06760 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST 06761 * @retval State of bit (1 or 0). 06762 */ 06763 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) 06764 { 06765 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)); 06766 } 06767 06768 #if defined(RCC_CSR_BORRSTF) 06769 /** 06770 * @brief Check if RCC flag BOR reset is set or not. 06771 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST 06772 * @retval State of bit (1 or 0). 06773 */ 06774 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) 06775 { 06776 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF)); 06777 } 06778 #endif /* RCC_CSR_BORRSTF */ 06779 06780 /** 06781 * @brief Set RMVF bit to clear the reset flags. 06782 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags 06783 * @retval None 06784 */ 06785 __STATIC_INLINE void LL_RCC_ClearResetFlags(void) 06786 { 06787 SET_BIT(RCC->CSR, RCC_CSR_RMVF); 06788 } 06789 06790 /** 06791 * @} 06792 */ 06793 06794 /** @defgroup RCC_LL_EF_IT_Management IT Management 06795 * @{ 06796 */ 06797 06798 /** 06799 * @brief Enable LSI ready interrupt 06800 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY 06801 * @retval None 06802 */ 06803 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) 06804 { 06805 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); 06806 } 06807 06808 /** 06809 * @brief Enable LSE ready interrupt 06810 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY 06811 * @retval None 06812 */ 06813 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) 06814 { 06815 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE); 06816 } 06817 06818 /** 06819 * @brief Enable HSI ready interrupt 06820 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY 06821 * @retval None 06822 */ 06823 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) 06824 { 06825 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); 06826 } 06827 06828 /** 06829 * @brief Enable HSE ready interrupt 06830 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY 06831 * @retval None 06832 */ 06833 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) 06834 { 06835 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE); 06836 } 06837 06838 /** 06839 * @brief Enable PLL ready interrupt 06840 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY 06841 * @retval None 06842 */ 06843 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) 06844 { 06845 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); 06846 } 06847 06848 #if defined(RCC_PLLI2S_SUPPORT) 06849 /** 06850 * @brief Enable PLLI2S ready interrupt 06851 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY 06852 * @retval None 06853 */ 06854 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void) 06855 { 06856 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); 06857 } 06858 #endif /* RCC_PLLI2S_SUPPORT */ 06859 06860 #if defined(RCC_PLLSAI_SUPPORT) 06861 /** 06862 * @brief Enable PLLSAI ready interrupt 06863 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY 06864 * @retval None 06865 */ 06866 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void) 06867 { 06868 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); 06869 } 06870 #endif /* RCC_PLLSAI_SUPPORT */ 06871 06872 /** 06873 * @brief Disable LSI ready interrupt 06874 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY 06875 * @retval None 06876 */ 06877 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) 06878 { 06879 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE); 06880 } 06881 06882 /** 06883 * @brief Disable LSE ready interrupt 06884 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY 06885 * @retval None 06886 */ 06887 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) 06888 { 06889 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE); 06890 } 06891 06892 /** 06893 * @brief Disable HSI ready interrupt 06894 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY 06895 * @retval None 06896 */ 06897 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) 06898 { 06899 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE); 06900 } 06901 06902 /** 06903 * @brief Disable HSE ready interrupt 06904 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY 06905 * @retval None 06906 */ 06907 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) 06908 { 06909 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE); 06910 } 06911 06912 /** 06913 * @brief Disable PLL ready interrupt 06914 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY 06915 * @retval None 06916 */ 06917 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) 06918 { 06919 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE); 06920 } 06921 06922 #if defined(RCC_PLLI2S_SUPPORT) 06923 /** 06924 * @brief Disable PLLI2S ready interrupt 06925 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY 06926 * @retval None 06927 */ 06928 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void) 06929 { 06930 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE); 06931 } 06932 06933 #endif /* RCC_PLLI2S_SUPPORT */ 06934 06935 #if defined(RCC_PLLSAI_SUPPORT) 06936 /** 06937 * @brief Disable PLLSAI ready interrupt 06938 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY 06939 * @retval None 06940 */ 06941 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void) 06942 { 06943 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE); 06944 } 06945 #endif /* RCC_PLLSAI_SUPPORT */ 06946 06947 /** 06948 * @brief Checks if LSI ready interrupt source is enabled or disabled. 06949 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY 06950 * @retval State of bit (1 or 0). 06951 */ 06952 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) 06953 { 06954 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE)); 06955 } 06956 06957 /** 06958 * @brief Checks if LSE ready interrupt source is enabled or disabled. 06959 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY 06960 * @retval State of bit (1 or 0). 06961 */ 06962 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) 06963 { 06964 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE)); 06965 } 06966 06967 /** 06968 * @brief Checks if HSI ready interrupt source is enabled or disabled. 06969 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY 06970 * @retval State of bit (1 or 0). 06971 */ 06972 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) 06973 { 06974 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE)); 06975 } 06976 06977 /** 06978 * @brief Checks if HSE ready interrupt source is enabled or disabled. 06979 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY 06980 * @retval State of bit (1 or 0). 06981 */ 06982 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) 06983 { 06984 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE)); 06985 } 06986 06987 /** 06988 * @brief Checks if PLL ready interrupt source is enabled or disabled. 06989 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY 06990 * @retval State of bit (1 or 0). 06991 */ 06992 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) 06993 { 06994 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE)); 06995 } 06996 06997 #if defined(RCC_PLLI2S_SUPPORT) 06998 /** 06999 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled. 07000 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY 07001 * @retval State of bit (1 or 0). 07002 */ 07003 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void) 07004 { 07005 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE)); 07006 } 07007 07008 #endif /* RCC_PLLI2S_SUPPORT */ 07009 07010 #if defined(RCC_PLLSAI_SUPPORT) 07011 /** 07012 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled. 07013 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY 07014 * @retval State of bit (1 or 0). 07015 */ 07016 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void) 07017 { 07018 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE)); 07019 } 07020 #endif /* RCC_PLLSAI_SUPPORT */ 07021 07022 /** 07023 * @} 07024 */ 07025 07026 #if defined(USE_FULL_LL_DRIVER) 07027 /** @defgroup RCC_LL_EF_Init De-initialization function 07028 * @{ 07029 */ 07030 ErrorStatus LL_RCC_DeInit(void); 07031 /** 07032 * @} 07033 */ 07034 07035 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions 07036 * @{ 07037 */ 07038 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); 07039 #if defined(FMPI2C1) 07040 uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource); 07041 #endif /* FMPI2C1 */ 07042 #if defined(LPTIM1) 07043 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); 07044 #endif /* LPTIM1 */ 07045 #if defined(SAI1) 07046 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); 07047 #endif /* SAI1 */ 07048 #if defined(SDIO) 07049 uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource); 07050 #endif /* SDIO */ 07051 #if defined(RNG) 07052 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); 07053 #endif /* RNG */ 07054 #if defined(USB_OTG_FS) || defined(USB_OTG_HS) 07055 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); 07056 #endif /* USB_OTG_FS || USB_OTG_HS */ 07057 #if defined(DFSDM1_Channel0) 07058 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource); 07059 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource); 07060 #endif /* DFSDM1_Channel0 */ 07061 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource); 07062 #if defined(CEC) 07063 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource); 07064 #endif /* CEC */ 07065 #if defined(LTDC) 07066 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); 07067 #endif /* LTDC */ 07068 #if defined(SPDIFRX) 07069 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource); 07070 #endif /* SPDIFRX */ 07071 #if defined(DSI) 07072 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); 07073 #endif /* DSI */ 07074 /** 07075 * @} 07076 */ 07077 #endif /* USE_FULL_LL_DRIVER */ 07078 07079 /** 07080 * @} 07081 */ 07082 07083 /** 07084 * @} 07085 */ 07086 07087 #endif /* defined(RCC) */ 07088 07089 /** 07090 * @} 07091 */ 07092 07093 #ifdef __cplusplus 07094 } 07095 #endif 07096 07097 #endif /* __STM32F4xx_LL_RCC_H */ 07098 07099 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1