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STM32F479xx HAL User Manual
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Header file of TIM LL module. More...
#include "stm32f4xx.h"Go to the source code of this file.
Data Structures | |
| struct | LL_TIM_InitTypeDef |
| TIM Time Base configuration structure definition. More... | |
| struct | LL_TIM_OC_InitTypeDef |
| TIM Output Compare configuration structure definition. More... | |
| struct | LL_TIM_IC_InitTypeDef |
| TIM Input Capture configuration structure definition. More... | |
| struct | LL_TIM_ENCODER_InitTypeDef |
| TIM Encoder interface configuration structure definition. More... | |
| struct | LL_TIM_HALLSENSOR_InitTypeDef |
| TIM Hall sensor interface configuration structure definition. More... | |
| struct | LL_TIM_BDTR_InitTypeDef |
| BDTR (Break and Dead Time) structure definition. More... | |
Defines | |
| #define | TIMx_OR_RMP_SHIFT 16U |
| #define | TIMx_OR_RMP_MASK 0x0000FFFFU |
| #define | TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) |
| #define | TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) |
| #define | TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) |
| #define | DT_DELAY_1 ((uint8_t)0x7F) |
| #define | DT_DELAY_2 ((uint8_t)0x3F) |
| #define | DT_DELAY_3 ((uint8_t)0x1F) |
| #define | DT_DELAY_4 ((uint8_t)0x1F) |
| #define | DT_RANGE_1 ((uint8_t)0x00) |
| #define | DT_RANGE_2 ((uint8_t)0x80) |
| #define | DT_RANGE_3 ((uint8_t)0xC0) |
| #define | DT_RANGE_4 ((uint8_t)0xE0) |
| #define | TIM_GET_CHANNEL_INDEX(__CHANNEL__) |
| Convert channel id into channel index. | |
| #define | TIM_CALC_DTS(__TIMCLK__, __CKD__) |
| Calculate the deadtime sampling period(in ps). | |
| #define | LL_TIM_SR_UIF TIM_SR_UIF |
| #define | LL_TIM_SR_CC1IF TIM_SR_CC1IF |
| #define | LL_TIM_SR_CC2IF TIM_SR_CC2IF |
| #define | LL_TIM_SR_CC3IF TIM_SR_CC3IF |
| #define | LL_TIM_SR_CC4IF TIM_SR_CC4IF |
| #define | LL_TIM_SR_COMIF TIM_SR_COMIF |
| #define | LL_TIM_SR_TIF TIM_SR_TIF |
| #define | LL_TIM_SR_BIF TIM_SR_BIF |
| #define | LL_TIM_SR_CC1OF TIM_SR_CC1OF |
| #define | LL_TIM_SR_CC2OF TIM_SR_CC2OF |
| #define | LL_TIM_SR_CC3OF TIM_SR_CC3OF |
| #define | LL_TIM_SR_CC4OF TIM_SR_CC4OF |
| #define | LL_TIM_BREAK_DISABLE 0x00000000U |
| #define | LL_TIM_BREAK_ENABLE TIM_BDTR_BKE |
| #define | LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U |
| #define | LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE |
| #define | LL_TIM_DIER_UIE TIM_DIER_UIE |
| #define | LL_TIM_DIER_CC1IE TIM_DIER_CC1IE |
| #define | LL_TIM_DIER_CC2IE TIM_DIER_CC2IE |
| #define | LL_TIM_DIER_CC3IE TIM_DIER_CC3IE |
| #define | LL_TIM_DIER_CC4IE TIM_DIER_CC4IE |
| #define | LL_TIM_DIER_COMIE TIM_DIER_COMIE |
| #define | LL_TIM_DIER_TIE TIM_DIER_TIE |
| #define | LL_TIM_DIER_BIE TIM_DIER_BIE |
| #define | LL_TIM_UPDATESOURCE_REGULAR 0x00000000U |
| #define | LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS |
| #define | LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM |
| #define | LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U |
| #define | LL_TIM_COUNTERMODE_UP 0x00000000U |
| #define | LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
| #define | LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 |
| #define | LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 |
| #define | LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS |
| #define | LL_TIM_CLOCKDIVISION_DIV1 0x00000000U |
| #define | LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 |
| #define | LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 |
| #define | LL_TIM_COUNTERDIRECTION_UP 0x00000000U |
| #define | LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR |
| #define | LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U |
| #define | LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS |
| #define | LL_TIM_CCDMAREQUEST_CC 0x00000000U |
| #define | LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS |
| #define | LL_TIM_LOCKLEVEL_OFF 0x00000000U |
| #define | LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 |
| #define | LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 |
| #define | LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK |
| #define | LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E |
| #define | LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE |
| #define | LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E |
| #define | LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE |
| #define | LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E |
| #define | LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE |
| #define | LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E |
| #define | LL_TIM_OCSTATE_DISABLE 0x00000000U |
| #define | LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E |
| #define | LL_TIM_OCMODE_FROZEN 0x00000000U |
| #define | LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 |
| #define | LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 |
| #define | LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
| #define | LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 |
| #define | LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) |
| #define | LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) |
| #define | LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) |
| #define | LL_TIM_OCPOLARITY_HIGH 0x00000000U |
| #define | LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P |
| #define | LL_TIM_OCIDLESTATE_LOW 0x00000000U |
| #define | LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 |
| #define | LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) |
| #define | LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) |
| #define | LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) |
| #define | LL_TIM_ICPSC_DIV1 0x00000000U |
| #define | LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) |
| #define | LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) |
| #define | LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV1 0x00000000U |
| #define | LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) |
| #define | LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) |
| #define | LL_TIM_IC_POLARITY_RISING 0x00000000U |
| #define | LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P |
| #define | LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) |
| #define | LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U |
| #define | LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
| #define | LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE |
| #define | LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 |
| #define | LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 |
| #define | LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
| #define | LL_TIM_TRGO_RESET 0x00000000U |
| #define | LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 |
| #define | LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 |
| #define | LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) |
| #define | LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 |
| #define | LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) |
| #define | LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) |
| #define | LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) |
| #define | LL_TIM_SLAVEMODE_DISABLED 0x00000000U |
| #define | LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 |
| #define | LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) |
| #define | LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) |
| #define | LL_TIM_TS_ITR0 0x00000000U |
| #define | LL_TIM_TS_ITR1 TIM_SMCR_TS_0 |
| #define | LL_TIM_TS_ITR2 TIM_SMCR_TS_1 |
| #define | LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
| #define | LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 |
| #define | LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) |
| #define | LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) |
| #define | LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) |
| #define | LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U |
| #define | LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP |
| #define | LL_TIM_ETR_PRESCALER_DIV1 0x00000000U |
| #define | LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 |
| #define | LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 |
| #define | LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS |
| #define | LL_TIM_ETR_FILTER_FDIV1 0x00000000U |
| #define | LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 |
| #define | LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 |
| #define | LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) |
| #define | LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 |
| #define | LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) |
| #define | LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) |
| #define | LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) |
| #define | LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 |
| #define | LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) |
| #define | LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) |
| #define | LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) |
| #define | LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) |
| #define | LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) |
| #define | LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) |
| #define | LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF |
| #define | LL_TIM_BREAK_POLARITY_LOW 0x00000000U |
| #define | LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP |
| #define | LL_TIM_OSSI_DISABLE 0x00000000U |
| #define | LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI |
| #define | LL_TIM_OSSR_DISABLE 0x00000000U |
| #define | LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR |
| #define | LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U |
| #define | LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 |
| #define | LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 |
| #define | LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 |
| #define | LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) |
| #define | LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 |
| #define | LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) |
| #define | LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) |
| #define | LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) |
| #define | LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 |
| #define | LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) |
| #define | LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U |
| #define | LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 |
| #define | LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 |
| #define | LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 |
| #define | LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) |
| #define | LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 |
| #define | LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) |
| #define | LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) |
| #define | LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) |
| #define | LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) |
| #define | LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 |
| #define | LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) |
| #define | LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK |
| #define | LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) |
| #define | LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) |
| #define | LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) |
| #define | LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK |
| #define | LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) |
| #define | LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) |
| #define | LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) |
| #define | LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK |
| #define | LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) |
| #define | LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) |
| #define | LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) |
| #define | LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) |
| Write a value in TIM register. | |
| #define | LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) |
| Read a value in TIM register. | |
| #define | __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) |
| HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. | |
| #define | __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) |
| HELPER macro calculating the prescaler value to achieve the required counter clock frequency. | |
| #define | __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) |
| HELPER macro calculating the auto-reload value to achieve the required output signal frequency. | |
| #define | __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) |
| HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. | |
| #define | __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) |
| HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). | |
| #define | __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
| HELPER macro retrieving the ratio of the input capture prescaler. | |
Functions | |
| __STATIC_INLINE void | LL_TIM_EnableCounter (TIM_TypeDef *TIMx) |
| Enable timer counter. | |
| __STATIC_INLINE void | LL_TIM_DisableCounter (TIM_TypeDef *TIMx) |
| Disable timer counter. | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledCounter (TIM_TypeDef *TIMx) |
| Indicates whether the timer counter is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableUpdateEvent (TIM_TypeDef *TIMx) |
| Enable update event generation. | |
| __STATIC_INLINE void | LL_TIM_DisableUpdateEvent (TIM_TypeDef *TIMx) |
| Disable update event generation. | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledUpdateEvent (TIM_TypeDef *TIMx) |
| Indicates whether update event generation is enabled. | |
| __STATIC_INLINE void | LL_TIM_SetUpdateSource (TIM_TypeDef *TIMx, uint32_t UpdateSource) |
| Set update event source. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetUpdateSource (TIM_TypeDef *TIMx) |
| Get actual event update source. | |
| __STATIC_INLINE void | LL_TIM_SetOnePulseMode (TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
| Set one pulse mode (one shot v.s. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetOnePulseMode (TIM_TypeDef *TIMx) |
| Get actual one pulse mode. | |
| __STATIC_INLINE void | LL_TIM_SetCounterMode (TIM_TypeDef *TIMx, uint32_t CounterMode) |
| Set the timer counter counting mode. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetCounterMode (TIM_TypeDef *TIMx) |
| Get actual counter mode. | |
| __STATIC_INLINE void | LL_TIM_EnableARRPreload (TIM_TypeDef *TIMx) |
| Enable auto-reload (ARR) preload. | |
| __STATIC_INLINE void | LL_TIM_DisableARRPreload (TIM_TypeDef *TIMx) |
| Disable auto-reload (ARR) preload. | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledARRPreload (TIM_TypeDef *TIMx) |
| Indicates whether auto-reload (ARR) preload is enabled. | |
| __STATIC_INLINE void | LL_TIM_SetClockDivision (TIM_TypeDef *TIMx, uint32_t ClockDivision) |
| Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetClockDivision (TIM_TypeDef *TIMx) |
| Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. | |
| __STATIC_INLINE void | LL_TIM_SetCounter (TIM_TypeDef *TIMx, uint32_t Counter) |
| Set the counter value. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetCounter (TIM_TypeDef *TIMx) |
| Get the counter value. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetDirection (TIM_TypeDef *TIMx) |
| Get the current direction of the counter. | |
| __STATIC_INLINE void | LL_TIM_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Prescaler) |
| Set the prescaler value. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetPrescaler (TIM_TypeDef *TIMx) |
| Get the prescaler value. | |
| __STATIC_INLINE void | LL_TIM_SetAutoReload (TIM_TypeDef *TIMx, uint32_t AutoReload) |
| Set the auto-reload value. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetAutoReload (TIM_TypeDef *TIMx) |
| Get the auto-reload value. | |
| __STATIC_INLINE void | LL_TIM_SetRepetitionCounter (TIM_TypeDef *TIMx, uint32_t RepetitionCounter) |
| Set the repetition counter value. | |
| __STATIC_INLINE uint32_t | LL_TIM_GetRepetitionCounter (TIM_TypeDef *TIMx) |
| Get the repetition counter value. | |
| __STATIC_INLINE void | LL_TIM_CC_EnablePreload (TIM_TypeDef *TIMx) |
| Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. | |
| __STATIC_INLINE void | LL_TIM_CC_DisablePreload (TIM_TypeDef *TIMx) |
| Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. | |
| __STATIC_INLINE void | LL_TIM_CC_SetUpdate (TIM_TypeDef *TIMx, uint32_t CCUpdateSource) |
| Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). | |
| __STATIC_INLINE void | LL_TIM_CC_SetDMAReqTrigger (TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
| Set the trigger of the capture/compare DMA request. | |
| __STATIC_INLINE uint32_t | LL_TIM_CC_GetDMAReqTrigger (TIM_TypeDef *TIMx) |
| Get actual trigger of the capture/compare DMA request. | |
| __STATIC_INLINE void | LL_TIM_CC_SetLockLevel (TIM_TypeDef *TIMx, uint32_t LockLevel) |
| Set the lock level to freeze the configuration of several capture/compare parameters. | |
| __STATIC_INLINE void | LL_TIM_CC_EnableChannel (TIM_TypeDef *TIMx, uint32_t Channels) |
| Enable capture/compare channels. | |
| __STATIC_INLINE void | LL_TIM_CC_DisableChannel (TIM_TypeDef *TIMx, uint32_t Channels) |
| Disable capture/compare channels. | |
| __STATIC_INLINE uint32_t | LL_TIM_CC_IsEnabledChannel (TIM_TypeDef *TIMx, uint32_t Channels) |
| Indicate whether channel(s) is(are) enabled. | |
| __STATIC_INLINE void | LL_TIM_OC_ConfigOutput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
| Configure an output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_SetMode (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
| Define the behavior of the output reference signal OCxREF from which OCx and OCxN (when relevant) are derived. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_GetMode (TIM_TypeDef *TIMx, uint32_t Channel) |
| Get the output compare mode of an output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
| Set the polarity of an output channel. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel) |
| Get the polarity of an output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_SetIdleState (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) |
| Set the IDLE state of an output channel. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_GetIdleState (TIM_TypeDef *TIMx, uint32_t Channel) |
| Get the IDLE state of an output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_EnableFast (TIM_TypeDef *TIMx, uint32_t Channel) |
| Enable fast mode for the output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_DisableFast (TIM_TypeDef *TIMx, uint32_t Channel) |
| Disable fast mode for the output channel. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledFast (TIM_TypeDef *TIMx, uint32_t Channel) |
| Indicates whether fast mode is enabled for the output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_EnablePreload (TIM_TypeDef *TIMx, uint32_t Channel) |
| Enable compare register (TIMx_CCRx) preload for the output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_DisablePreload (TIM_TypeDef *TIMx, uint32_t Channel) |
| Disable compare register (TIMx_CCRx) preload for the output channel. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledPreload (TIM_TypeDef *TIMx, uint32_t Channel) |
| Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_EnableClear (TIM_TypeDef *TIMx, uint32_t Channel) |
| Enable clearing the output channel on an external event. | |
| __STATIC_INLINE void | LL_TIM_OC_DisableClear (TIM_TypeDef *TIMx, uint32_t Channel) |
| Disable clearing the output channel on an external event. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_IsEnabledClear (TIM_TypeDef *TIMx, uint32_t Channel) |
| Indicates clearing the output channel on an external event is enabled for the output channel. | |
| __STATIC_INLINE void | LL_TIM_OC_SetDeadTime (TIM_TypeDef *TIMx, uint32_t DeadTime) |
| Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). | |
| __STATIC_INLINE void | LL_TIM_OC_SetCompareCH1 (TIM_TypeDef *TIMx, uint32_t CompareValue) |
| Set compare value for output channel 1 (TIMx_CCR1). | |
| __STATIC_INLINE void | LL_TIM_OC_SetCompareCH2 (TIM_TypeDef *TIMx, uint32_t CompareValue) |
| Set compare value for output channel 2 (TIMx_CCR2). | |
| __STATIC_INLINE void | LL_TIM_OC_SetCompareCH3 (TIM_TypeDef *TIMx, uint32_t CompareValue) |
| Set compare value for output channel 3 (TIMx_CCR3). | |
| __STATIC_INLINE void | LL_TIM_OC_SetCompareCH4 (TIM_TypeDef *TIMx, uint32_t CompareValue) |
| Set compare value for output channel 4 (TIMx_CCR4). | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH1 (TIM_TypeDef *TIMx) |
| Get compare value (TIMx_CCR1) set for output channel 1. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH2 (TIM_TypeDef *TIMx) |
| Get compare value (TIMx_CCR2) set for output channel 2. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH3 (TIM_TypeDef *TIMx) |
| Get compare value (TIMx_CCR3) set for output channel 3. | |
| __STATIC_INLINE uint32_t | LL_TIM_OC_GetCompareCH4 (TIM_TypeDef *TIMx) |
| Get compare value (TIMx_CCR4) set for output channel 4. | |
| __STATIC_INLINE void | LL_TIM_IC_Config (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
| Configure input channel. | |
| __STATIC_INLINE void | LL_TIM_IC_SetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
| Set the active input. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_GetActiveInput (TIM_TypeDef *TIMx, uint32_t Channel) |
| Get the current active input. | |
| __STATIC_INLINE void | LL_TIM_IC_SetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
| Set the prescaler of input channel. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_GetPrescaler (TIM_TypeDef *TIMx, uint32_t Channel) |
| Get the current prescaler value acting on an input channel. | |
| __STATIC_INLINE void | LL_TIM_IC_SetFilter (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
| Set the input filter duration. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_GetFilter (TIM_TypeDef *TIMx, uint32_t Channel) |
| Get the input filter duration. | |
| __STATIC_INLINE void | LL_TIM_IC_SetPolarity (TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
| Set the input channel polarity. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_GetPolarity (TIM_TypeDef *TIMx, uint32_t Channel) |
| Get the current input channel polarity. | |
| __STATIC_INLINE void | LL_TIM_IC_EnableXORCombination (TIM_TypeDef *TIMx) |
| Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). | |
| __STATIC_INLINE void | LL_TIM_IC_DisableXORCombination (TIM_TypeDef *TIMx) |
| Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_IsEnabledXORCombination (TIM_TypeDef *TIMx) |
| Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH1 (TIM_TypeDef *TIMx) |
| Get captured value for input channel 1. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH2 (TIM_TypeDef *TIMx) |
| Get captured value for input channel 2. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH3 (TIM_TypeDef *TIMx) |
| Get captured value for input channel 3. | |
| __STATIC_INLINE uint32_t | LL_TIM_IC_GetCaptureCH4 (TIM_TypeDef *TIMx) |
| Get captured value for input channel 4. | |
| __STATIC_INLINE void | LL_TIM_EnableExternalClock (TIM_TypeDef *TIMx) |
| Enable external clock mode 2. | |
| __STATIC_INLINE void | LL_TIM_DisableExternalClock (TIM_TypeDef *TIMx) |
| Disable external clock mode 2. | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledExternalClock (TIM_TypeDef *TIMx) |
| Indicate whether external clock mode 2 is enabled. | |
| __STATIC_INLINE void | LL_TIM_SetClockSource (TIM_TypeDef *TIMx, uint32_t ClockSource) |
| Set the clock source of the counter clock. | |
| __STATIC_INLINE void | LL_TIM_SetEncoderMode (TIM_TypeDef *TIMx, uint32_t EncoderMode) |
| Set the encoder interface mode. | |
| __STATIC_INLINE void | LL_TIM_SetTriggerOutput (TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
| Set the trigger output (TRGO) used for timer synchronization . | |
| __STATIC_INLINE void | LL_TIM_SetSlaveMode (TIM_TypeDef *TIMx, uint32_t SlaveMode) |
| Set the synchronization mode of a slave timer. | |
| __STATIC_INLINE void | LL_TIM_SetTriggerInput (TIM_TypeDef *TIMx, uint32_t TriggerInput) |
| Set the selects the trigger input to be used to synchronize the counter. | |
| __STATIC_INLINE void | LL_TIM_EnableMasterSlaveMode (TIM_TypeDef *TIMx) |
| Enable the Master/Slave mode. | |
| __STATIC_INLINE void | LL_TIM_DisableMasterSlaveMode (TIM_TypeDef *TIMx) |
| Disable the Master/Slave mode. | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledMasterSlaveMode (TIM_TypeDef *TIMx) |
| Indicates whether the Master/Slave mode is enabled. | |
| __STATIC_INLINE void | LL_TIM_ConfigETR (TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, uint32_t ETRFilter) |
| Configure the external trigger (ETR) input. | |
| __STATIC_INLINE void | LL_TIM_EnableBRK (TIM_TypeDef *TIMx) |
| Enable the break function. | |
| __STATIC_INLINE void | LL_TIM_DisableBRK (TIM_TypeDef *TIMx) |
| Disable the break function. | |
| __STATIC_INLINE void | LL_TIM_ConfigBRK (TIM_TypeDef *TIMx, uint32_t BreakPolarity) |
| Configure the break input. | |
| __STATIC_INLINE void | LL_TIM_SetOffStates (TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) |
| Select the outputs off state (enabled v.s. | |
| __STATIC_INLINE void | LL_TIM_EnableAutomaticOutput (TIM_TypeDef *TIMx) |
| Enable automatic output (MOE can be set by software or automatically when a break input is active). | |
| __STATIC_INLINE void | LL_TIM_DisableAutomaticOutput (TIM_TypeDef *TIMx) |
| Disable automatic output (MOE can be set only by software). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledAutomaticOutput (TIM_TypeDef *TIMx) |
| Indicate whether automatic output is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableAllOutputs (TIM_TypeDef *TIMx) |
| Enable the outputs (set the MOE bit in TIMx_BDTR register). | |
| __STATIC_INLINE void | LL_TIM_DisableAllOutputs (TIM_TypeDef *TIMx) |
| Disable the outputs (reset the MOE bit in TIMx_BDTR register). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledAllOutputs (TIM_TypeDef *TIMx) |
| Indicates whether outputs are enabled. | |
| __STATIC_INLINE void | LL_TIM_ConfigDMABurst (TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
| Configures the timer DMA burst feature. | |
| __STATIC_INLINE void | LL_TIM_SetRemap (TIM_TypeDef *TIMx, uint32_t Remap) |
| Remap TIM inputs (input channel, internal/external triggers). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_UPDATE (TIM_TypeDef *TIMx) |
| Clear the update interrupt flag (UIF). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_UPDATE (TIM_TypeDef *TIMx) |
| Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_CC1 (TIM_TypeDef *TIMx) |
| Clear the Capture/Compare 1 interrupt flag (CC1F). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1 (TIM_TypeDef *TIMx) |
| Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_CC2 (TIM_TypeDef *TIMx) |
| Clear the Capture/Compare 2 interrupt flag (CC2F). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2 (TIM_TypeDef *TIMx) |
| Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_CC3 (TIM_TypeDef *TIMx) |
| Clear the Capture/Compare 3 interrupt flag (CC3F). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3 (TIM_TypeDef *TIMx) |
| Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_CC4 (TIM_TypeDef *TIMx) |
| Clear the Capture/Compare 4 interrupt flag (CC4F). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4 (TIM_TypeDef *TIMx) |
| Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_COM (TIM_TypeDef *TIMx) |
| Clear the commutation interrupt flag (COMIF). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_COM (TIM_TypeDef *TIMx) |
| Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_TRIG (TIM_TypeDef *TIMx) |
| Clear the trigger interrupt flag (TIF). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_TRIG (TIM_TypeDef *TIMx) |
| Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_BRK (TIM_TypeDef *TIMx) |
| Clear the break interrupt flag (BIF). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_BRK (TIM_TypeDef *TIMx) |
| Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_CC1OVR (TIM_TypeDef *TIMx) |
| Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC1OVR (TIM_TypeDef *TIMx) |
| Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_CC2OVR (TIM_TypeDef *TIMx) |
| Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC2OVR (TIM_TypeDef *TIMx) |
| Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_CC3OVR (TIM_TypeDef *TIMx) |
| Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC3OVR (TIM_TypeDef *TIMx) |
| Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_ClearFlag_CC4OVR (TIM_TypeDef *TIMx) |
| Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsActiveFlag_CC4OVR (TIM_TypeDef *TIMx) |
| Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). | |
| __STATIC_INLINE void | LL_TIM_EnableIT_UPDATE (TIM_TypeDef *TIMx) |
| Enable update interrupt (UIE). | |
| __STATIC_INLINE void | LL_TIM_DisableIT_UPDATE (TIM_TypeDef *TIMx) |
| Disable update interrupt (UIE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_UPDATE (TIM_TypeDef *TIMx) |
| Indicates whether the update interrupt (UIE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableIT_CC1 (TIM_TypeDef *TIMx) |
| Enable capture/compare 1 interrupt (CC1IE). | |
| __STATIC_INLINE void | LL_TIM_DisableIT_CC1 (TIM_TypeDef *TIMx) |
| Disable capture/compare 1 interrupt (CC1IE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC1 (TIM_TypeDef *TIMx) |
| Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableIT_CC2 (TIM_TypeDef *TIMx) |
| Enable capture/compare 2 interrupt (CC2IE). | |
| __STATIC_INLINE void | LL_TIM_DisableIT_CC2 (TIM_TypeDef *TIMx) |
| Disable capture/compare 2 interrupt (CC2IE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC2 (TIM_TypeDef *TIMx) |
| Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableIT_CC3 (TIM_TypeDef *TIMx) |
| Enable capture/compare 3 interrupt (CC3IE). | |
| __STATIC_INLINE void | LL_TIM_DisableIT_CC3 (TIM_TypeDef *TIMx) |
| Disable capture/compare 3 interrupt (CC3IE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC3 (TIM_TypeDef *TIMx) |
| Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableIT_CC4 (TIM_TypeDef *TIMx) |
| Enable capture/compare 4 interrupt (CC4IE). | |
| __STATIC_INLINE void | LL_TIM_DisableIT_CC4 (TIM_TypeDef *TIMx) |
| Disable capture/compare 4 interrupt (CC4IE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_CC4 (TIM_TypeDef *TIMx) |
| Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableIT_COM (TIM_TypeDef *TIMx) |
| Enable commutation interrupt (COMIE). | |
| __STATIC_INLINE void | LL_TIM_DisableIT_COM (TIM_TypeDef *TIMx) |
| Disable commutation interrupt (COMIE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_COM (TIM_TypeDef *TIMx) |
| Indicates whether the commutation interrupt (COMIE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableIT_TRIG (TIM_TypeDef *TIMx) |
| Enable trigger interrupt (TIE). | |
| __STATIC_INLINE void | LL_TIM_DisableIT_TRIG (TIM_TypeDef *TIMx) |
| Disable trigger interrupt (TIE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_TRIG (TIM_TypeDef *TIMx) |
| Indicates whether the trigger interrupt (TIE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableIT_BRK (TIM_TypeDef *TIMx) |
| Enable break interrupt (BIE). | |
| __STATIC_INLINE void | LL_TIM_DisableIT_BRK (TIM_TypeDef *TIMx) |
| Disable break interrupt (BIE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledIT_BRK (TIM_TypeDef *TIMx) |
| Indicates whether the break interrupt (BIE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableDMAReq_UPDATE (TIM_TypeDef *TIMx) |
| Enable update DMA request (UDE). | |
| __STATIC_INLINE void | LL_TIM_DisableDMAReq_UPDATE (TIM_TypeDef *TIMx) |
| Disable update DMA request (UDE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_UPDATE (TIM_TypeDef *TIMx) |
| Indicates whether the update DMA request (UDE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableDMAReq_CC1 (TIM_TypeDef *TIMx) |
| Enable capture/compare 1 DMA request (CC1DE). | |
| __STATIC_INLINE void | LL_TIM_DisableDMAReq_CC1 (TIM_TypeDef *TIMx) |
| Disable capture/compare 1 DMA request (CC1DE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC1 (TIM_TypeDef *TIMx) |
| Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableDMAReq_CC2 (TIM_TypeDef *TIMx) |
| Enable capture/compare 2 DMA request (CC2DE). | |
| __STATIC_INLINE void | LL_TIM_DisableDMAReq_CC2 (TIM_TypeDef *TIMx) |
| Disable capture/compare 2 DMA request (CC2DE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC2 (TIM_TypeDef *TIMx) |
| Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableDMAReq_CC3 (TIM_TypeDef *TIMx) |
| Enable capture/compare 3 DMA request (CC3DE). | |
| __STATIC_INLINE void | LL_TIM_DisableDMAReq_CC3 (TIM_TypeDef *TIMx) |
| Disable capture/compare 3 DMA request (CC3DE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC3 (TIM_TypeDef *TIMx) |
| Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableDMAReq_CC4 (TIM_TypeDef *TIMx) |
| Enable capture/compare 4 DMA request (CC4DE). | |
| __STATIC_INLINE void | LL_TIM_DisableDMAReq_CC4 (TIM_TypeDef *TIMx) |
| Disable capture/compare 4 DMA request (CC4DE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_CC4 (TIM_TypeDef *TIMx) |
| Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableDMAReq_COM (TIM_TypeDef *TIMx) |
| Enable commutation DMA request (COMDE). | |
| __STATIC_INLINE void | LL_TIM_DisableDMAReq_COM (TIM_TypeDef *TIMx) |
| Disable commutation DMA request (COMDE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_COM (TIM_TypeDef *TIMx) |
| Indicates whether the commutation DMA request (COMDE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_EnableDMAReq_TRIG (TIM_TypeDef *TIMx) |
| Enable trigger interrupt (TDE). | |
| __STATIC_INLINE void | LL_TIM_DisableDMAReq_TRIG (TIM_TypeDef *TIMx) |
| Disable trigger interrupt (TDE). | |
| __STATIC_INLINE uint32_t | LL_TIM_IsEnabledDMAReq_TRIG (TIM_TypeDef *TIMx) |
| Indicates whether the trigger interrupt (TDE) is enabled. | |
| __STATIC_INLINE void | LL_TIM_GenerateEvent_UPDATE (TIM_TypeDef *TIMx) |
| Generate an update event. | |
| __STATIC_INLINE void | LL_TIM_GenerateEvent_CC1 (TIM_TypeDef *TIMx) |
| Generate Capture/Compare 1 event. | |
| __STATIC_INLINE void | LL_TIM_GenerateEvent_CC2 (TIM_TypeDef *TIMx) |
| Generate Capture/Compare 2 event. | |
| __STATIC_INLINE void | LL_TIM_GenerateEvent_CC3 (TIM_TypeDef *TIMx) |
| Generate Capture/Compare 3 event. | |
| __STATIC_INLINE void | LL_TIM_GenerateEvent_CC4 (TIM_TypeDef *TIMx) |
| Generate Capture/Compare 4 event. | |
| __STATIC_INLINE void | LL_TIM_GenerateEvent_COM (TIM_TypeDef *TIMx) |
| Generate commutation event. | |
| __STATIC_INLINE void | LL_TIM_GenerateEvent_TRIG (TIM_TypeDef *TIMx) |
| Generate trigger event. | |
| __STATIC_INLINE void | LL_TIM_GenerateEvent_BRK (TIM_TypeDef *TIMx) |
| Generate break event. | |
| ErrorStatus | LL_TIM_DeInit (TIM_TypeDef *TIMx) |
| Set TIMx registers to their reset values. | |
| void | LL_TIM_StructInit (LL_TIM_InitTypeDef *TIM_InitStruct) |
| Set the fields of the time base unit configuration data structure to their default values. | |
| ErrorStatus | LL_TIM_Init (TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) |
| Configure the TIMx time base unit. | |
| void | LL_TIM_OC_StructInit (LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) |
| Set the fields of the TIMx output channel configuration data structure to their default values. | |
| ErrorStatus | LL_TIM_OC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) |
| Configure the TIMx output channel. | |
| void | LL_TIM_IC_StructInit (LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
| Set the fields of the TIMx input channel configuration data structure to their default values. | |
| ErrorStatus | LL_TIM_IC_Init (TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) |
| Configure the TIMx input channel. | |
| void | LL_TIM_ENCODER_StructInit (LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) |
| Fills each TIM_EncoderInitStruct field with its default value. | |
| ErrorStatus | LL_TIM_ENCODER_Init (TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) |
| Configure the encoder interface of the timer instance. | |
| void | LL_TIM_HALLSENSOR_StructInit (LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) |
| Set the fields of the TIMx Hall sensor interface configuration data structure to their default values. | |
| ErrorStatus | LL_TIM_HALLSENSOR_Init (TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) |
| Configure the Hall sensor interface of the timer instance. | |
| void | LL_TIM_BDTR_StructInit (LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) |
| Set the fields of the Break and Dead Time configuration data structure to their default values. | |
| ErrorStatus | LL_TIM_BDTR_Init (TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) |
| Configure the Break and Dead Time feature of the timer instance. | |
Variables | |
| static const uint8_t | OFFSET_TAB_CCMRx [] |
| static const uint8_t | SHIFT_TAB_OCxx [] |
| static const uint8_t | SHIFT_TAB_ICxx [] |
| static const uint8_t | SHIFT_TAB_CCxP [] |
| static const uint8_t | SHIFT_TAB_OISx [] |
Header file of TIM LL module.
This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause
Definition in file stm32f4xx_ll_tim.h.
1.7.6.1