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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal.h 00004 * @author MCD Application Team 00005 * @brief This file contains all the functions prototypes for the HAL 00006 * module driver. 00007 ****************************************************************************** 00008 * @attention 00009 * 00010 * Copyright (c) 2017 STMicroelectronics. 00011 * All rights reserved.</center></h2> 00012 * 00013 * This software is licensed under terms that can be found in the LICENSE file 00014 * in the root directory of this software component. 00015 * If no LICENSE file comes with this software, it is provided AS-IS. 00016 * 00017 ****************************************************************************** 00018 */ 00019 00020 /* Define to prevent recursive inclusion -------------------------------------*/ 00021 #ifndef STM32H7xx_HAL_H 00022 #define STM32H7xx_HAL_H 00023 00024 #ifdef __cplusplus 00025 extern "C" { 00026 #endif 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32h7xx_hal_conf.h" 00030 00031 /** @addtogroup STM32H7xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup HAL 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 /** @defgroup HAL_TICK_FREQ Tick Frequency 00041 * @{ 00042 */ 00043 typedef enum 00044 { 00045 HAL_TICK_FREQ_10HZ = 100U, 00046 HAL_TICK_FREQ_100HZ = 10U, 00047 HAL_TICK_FREQ_1KHZ = 1U, 00048 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 00049 } HAL_TickFreqTypeDef; 00050 /** 00051 * @} 00052 */ 00053 00054 /* Exported constants --------------------------------------------------------*/ 00055 00056 /** @defgroup REV_ID device revision ID 00057 * @{ 00058 */ 00059 #define REV_ID_Y ((uint32_t)0x1003) /*!< STM32H7 rev.Y */ 00060 #define REV_ID_B ((uint32_t)0x2000) /*!< STM32H7 rev.B */ 00061 #define REV_ID_X ((uint32_t)0x2001) /*!< STM32H7 rev.X */ 00062 #define REV_ID_V ((uint32_t)0x2003) /*!< STM32H7 rev.V */ 00063 00064 /** 00065 * @} 00066 */ 00067 00068 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 00069 * @{ 00070 */ 00071 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_CSR_VRS_OUT1 /*!< Voltage reference scale 0 (VREF_OUT1) */ 00072 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_OUT2 /*!< Voltage reference scale 1 (VREF_OUT2) */ 00073 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_OUT3 /*!< Voltage reference scale 2 (VREF_OUT3) */ 00074 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_OUT4 /*!< Voltage reference scale 3 (VREF_OUT4) */ 00075 00076 00077 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 00078 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ 00079 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ 00080 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) 00081 00082 00083 /** 00084 * @} 00085 */ 00086 00087 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 00088 * @{ 00089 */ 00090 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 00091 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 00092 00093 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 00094 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 00095 00096 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 00097 00098 /** 00099 * @} 00100 */ 00101 00102 #if !defined(SYSCFG_PMCR_BOOSTEN) 00103 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 00104 * @{ 00105 */ 00106 00107 /** @brief Fast-mode Plus driving capability on a specific GPIO 00108 */ 00109 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_PMCR_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 00110 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_PMCR_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 00111 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_PMCR_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 00112 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_PMCR_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 00113 00114 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00115 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 00116 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 00117 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 00118 00119 /** 00120 * @} 00121 */ 00122 #endif /* ! SYSCFG_PMCR_BOOSTEN */ 00123 00124 00125 #if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) || defined(SYSCFG_ADC2ALT_ADC2_ROUT1) 00126 /** @defgroup SYSCFG_Adc2_Alternate_Connection SYSCFG ADC2 Alternate Connection 00127 * @{ 00128 */ 00129 00130 /** @brief Adc2 Alternate Connection on Vinp[16] and Vinp[17] 00131 */ 00132 #define SYSCFG_ADC2_ROUT0_DAC1_1 ((uint32_t)0x00000000) /*!< DAC1_out1 connected to ADC2 VINP[16] */ 00133 #define SYSCFG_ADC2_ROUT0_VBAT4 SYSCFG_ADC2ALT_ADC2_ROUT0 /*!< VBAT/4 connected to ADC2 VINP[16] */ 00134 #define SYSCFG_ADC2_ROUT1_DAC1_2 ((uint32_t)0x00000000) /*!< DAC1_out2 connected to ADC2 VINP[17] */ 00135 #define SYSCFG_ADC2_ROUT1_VREFINT SYSCFG_ADC2ALT_ADC2_ROUT1 /*!< VREFINT connected to ADC2 VINP[17] */ 00136 00137 #define IS_SYSCFG_ADC2ALT_ROUT0(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT0_DAC1_1) || \ 00138 ((__VALUE__) == SYSCFG_ADC2_ROUT0_VBAT4)) 00139 #define IS_SYSCFG_ADC2ALT_ROUT1(__VALUE__) (((__VALUE__) == SYSCFG_ADC2_ROUT1_DAC1_2) || \ 00140 ((__VALUE__) == SYSCFG_ADC2_ROUT1_VREFINT)) 00141 00142 /** 00143 * @} 00144 */ 00145 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT0 || SYSCFG_ADC2ALT_ADC2_ROUT1*/ 00146 00147 00148 /** @defgroup SYSCFG_Ethernet_Config Ethernet Config 00149 * @{ 00150 */ 00151 #define SYSCFG_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface */ 00152 #define SYSCFG_ETH_RMII SYSCFG_PMCR_EPIS_SEL_2 /*!< Select the Reduced Media Independent Interface */ 00153 00154 #define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII) || \ 00155 ((CONFIG) == SYSCFG_ETH_RMII)) 00156 00157 /** 00158 * @} 00159 */ 00160 00161 00162 /** @defgroup SYSCFG_Analog_Switch_Config Analog Switch Config 00163 * @{ 00164 */ 00165 #define SYSCFG_SWITCH_PA0 SYSCFG_PMCR_PA0SO /*!< Select PA0 analog switch */ 00166 #define SYSCFG_SWITCH_PA1 SYSCFG_PMCR_PA1SO /*!< Select PA1 analog switch */ 00167 #define SYSCFG_SWITCH_PC2 SYSCFG_PMCR_PC2SO /*!< Select PC2 analog switch */ 00168 #define SYSCFG_SWITCH_PC3 SYSCFG_PMCR_PC3SO /*!< Select PC3 analog switch */ 00169 00170 00171 00172 00173 #define SYSCFG_SWITCH_PA0_OPEN SYSCFG_PMCR_PA0SO /*!< PA0 analog switch opened */ 00174 #define SYSCFG_SWITCH_PA0_CLOSE ((uint32_t)0x00000000) /*!< PA0 analog switch closed */ 00175 #define SYSCFG_SWITCH_PA1_OPEN SYSCFG_PMCR_PA1SO /*!< PA1 analog switch opened */ 00176 #define SYSCFG_SWITCH_PA1_CLOSE ((uint32_t)0x00000000) /*!< PA1 analog switch closed*/ 00177 #define SYSCFG_SWITCH_PC2_OPEN SYSCFG_PMCR_PC2SO /*!< PC2 analog switch opened */ 00178 #define SYSCFG_SWITCH_PC2_CLOSE ((uint32_t)0x00000000) /*!< PC2 analog switch closed */ 00179 #define SYSCFG_SWITCH_PC3_OPEN SYSCFG_PMCR_PC3SO /*!< PC3 analog switch opened */ 00180 #define SYSCFG_SWITCH_PC3_CLOSE ((uint32_t)0x00000000) /*!< PC3 analog switch closed */ 00181 00182 /** 00183 * @} 00184 */ 00185 00186 #define IS_SYSCFG_ANALOG_SWITCH(SWITCH) ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \ 00187 (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \ 00188 (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \ 00189 (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3)) 00190 00191 00192 #define IS_SYSCFG_SWITCH_STATE(STATE) ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN) || \ 00193 (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE) || \ 00194 (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN) || \ 00195 (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE) || \ 00196 (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN) || \ 00197 (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE) || \ 00198 (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN) || \ 00199 (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE)) 00200 00201 00202 /** @defgroup SYSCFG_Boot_Config Boot Config 00203 * @{ 00204 */ 00205 #define SYSCFG_BOOT_ADDR0 ((uint32_t)0x00000000) /*!< Select Boot address0 */ 00206 #define SYSCFG_BOOT_ADDR1 ((uint32_t)0x00000001) /*!< Select Boot address1 */ 00207 00208 #define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \ 00209 ((REGISTER) == SYSCFG_BOOT_ADDR1)) 00210 00211 #define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE) 00212 00213 /** 00214 * @} 00215 */ 00216 00217 00218 /** @defgroup SYSCFG_IOCompenstionCell_Config IOCompenstionCell Config 00219 * @{ 00220 */ 00221 #define SYSCFG_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */ 00222 #define SYSCFG_REGISTER_CODE SYSCFG_CCCSR_CS /*!< Code from the SYSCFG compensation cell code register */ 00223 00224 #define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \ 00225 ((SELECT) == SYSCFG_REGISTER_CODE)) 00226 00227 #define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL)) 00228 00229 /** 00230 * @} 00231 */ 00232 00233 00234 00235 00236 /** @defgroup EXTI_Event_Input_Config Event Input Config 00237 * @{ 00238 */ 00239 00240 #define EXTI_MODE_IT ((uint32_t)0x00010000) 00241 #define EXTI_MODE_EVT ((uint32_t)0x00020000) 00242 #define EXTI_RISING_EDGE ((uint32_t)0x00100000) 00243 #define EXTI_FALLING_EDGE ((uint32_t)0x00200000) 00244 00245 #define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE)) 00246 #define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT)) 00247 00248 #define EXTI_LINE0 ((uint32_t)0x00) /*!< External interrupt LINE 0 */ 00249 #define EXTI_LINE1 ((uint32_t)0x01) /*!< External interrupt LINE 1 */ 00250 #define EXTI_LINE2 ((uint32_t)0x02) /*!< External interrupt LINE 2 */ 00251 #define EXTI_LINE3 ((uint32_t)0x03) /*!< External interrupt LINE 3 */ 00252 #define EXTI_LINE4 ((uint32_t)0x04) /*!< External interrupt LINE 4 */ 00253 #define EXTI_LINE5 ((uint32_t)0x05) /*!< External interrupt LINE 5 */ 00254 #define EXTI_LINE6 ((uint32_t)0x06) /*!< External interrupt LINE 6 */ 00255 #define EXTI_LINE7 ((uint32_t)0x07) /*!< External interrupt LINE 7 */ 00256 #define EXTI_LINE8 ((uint32_t)0x08) /*!< External interrupt LINE 8 */ 00257 #define EXTI_LINE9 ((uint32_t)0x09) /*!< External interrupt LINE 9 */ 00258 #define EXTI_LINE10 ((uint32_t)0x0A) /*!< External interrupt LINE 10 */ 00259 #define EXTI_LINE11 ((uint32_t)0x0B) /*!< External interrupt LINE 11 */ 00260 #define EXTI_LINE12 ((uint32_t)0x0C) /*!< External interrupt LINE 12 */ 00261 #define EXTI_LINE13 ((uint32_t)0x0D) /*!< External interrupt LINE 13 */ 00262 #define EXTI_LINE14 ((uint32_t)0x0E) /*!< External interrupt LINE 14 */ 00263 #define EXTI_LINE15 ((uint32_t)0x0F) /*!< External interrupt LINE 15 */ 00264 #define EXTI_LINE16 ((uint32_t)0x10) 00265 #define EXTI_LINE17 ((uint32_t)0x11) 00266 #define EXTI_LINE18 ((uint32_t)0x12) 00267 #define EXTI_LINE19 ((uint32_t)0x13) 00268 #define EXTI_LINE20 ((uint32_t)0x14) 00269 #define EXTI_LINE21 ((uint32_t)0x15) 00270 #define EXTI_LINE22 ((uint32_t)0x16) 00271 #define EXTI_LINE23 ((uint32_t)0x17) 00272 #define EXTI_LINE24 ((uint32_t)0x18) 00273 #define EXTI_LINE25 ((uint32_t)0x19) 00274 #define EXTI_LINE26 ((uint32_t)0x1A) 00275 #define EXTI_LINE27 ((uint32_t)0x1B) 00276 #define EXTI_LINE28 ((uint32_t)0x1C) 00277 #define EXTI_LINE29 ((uint32_t)0x1D) 00278 #define EXTI_LINE30 ((uint32_t)0x1E) 00279 #define EXTI_LINE31 ((uint32_t)0x1F) 00280 #define EXTI_LINE32 ((uint32_t)0x20) 00281 #define EXTI_LINE33 ((uint32_t)0x21) 00282 #define EXTI_LINE34 ((uint32_t)0x22) 00283 #define EXTI_LINE35 ((uint32_t)0x23) 00284 #define EXTI_LINE36 ((uint32_t)0x24) 00285 #define EXTI_LINE37 ((uint32_t)0x25) 00286 #define EXTI_LINE38 ((uint32_t)0x26) 00287 #define EXTI_LINE39 ((uint32_t)0x27) 00288 00289 #define EXTI_LINE40 ((uint32_t)0x28) 00290 #define EXTI_LINE41 ((uint32_t)0x29) 00291 #define EXTI_LINE42 ((uint32_t)0x2A) 00292 #define EXTI_LINE43 ((uint32_t)0x2B) 00293 #define EXTI_LINE44 ((uint32_t)0x2C) /* Not available in all family lines */ 00294 /* EXTI_LINE45 Reserved */ 00295 #if defined(DUAL_CORE) 00296 #define EXTI_LINE46 ((uint32_t)0x2E) 00297 #else 00298 /* EXTI_LINE46 Reserved */ 00299 #endif /* DUAL_CORE */ 00300 #define EXTI_LINE47 ((uint32_t)0x2F) 00301 #define EXTI_LINE48 ((uint32_t)0x30) 00302 #define EXTI_LINE49 ((uint32_t)0x31) 00303 #define EXTI_LINE50 ((uint32_t)0x32) 00304 #define EXTI_LINE51 ((uint32_t)0x33) 00305 #define EXTI_LINE52 ((uint32_t)0x34) 00306 #define EXTI_LINE53 ((uint32_t)0x35) 00307 #define EXTI_LINE54 ((uint32_t)0x36) 00308 #define EXTI_LINE55 ((uint32_t)0x37) 00309 #define EXTI_LINE56 ((uint32_t)0x38) 00310 #define EXTI_LINE57 ((uint32_t)0x39) 00311 #define EXTI_LINE58 ((uint32_t)0x3A) 00312 #define EXTI_LINE59 ((uint32_t)0x3B) 00313 #define EXTI_LINE60 ((uint32_t)0x3C) 00314 #define EXTI_LINE61 ((uint32_t)0x3D) 00315 #define EXTI_LINE62 ((uint32_t)0x3E) 00316 #define EXTI_LINE63 ((uint32_t)0x3F) 00317 #define EXTI_LINE64 ((uint32_t)0x40) 00318 #define EXTI_LINE65 ((uint32_t)0x41) 00319 #define EXTI_LINE66 ((uint32_t)0x42) 00320 #define EXTI_LINE67 ((uint32_t)0x43) 00321 #define EXTI_LINE68 ((uint32_t)0x44) 00322 #define EXTI_LINE69 ((uint32_t)0x45) 00323 #define EXTI_LINE70 ((uint32_t)0x46) 00324 #define EXTI_LINE71 ((uint32_t)0x47) 00325 #define EXTI_LINE72 ((uint32_t)0x48) 00326 #define EXTI_LINE73 ((uint32_t)0x49) 00327 #define EXTI_LINE74 ((uint32_t)0x4A) 00328 #define EXTI_LINE75 ((uint32_t)0x4B) /* Not available in all family lines */ 00329 #define EXTI_LINE76 ((uint32_t)0x4C) /* Not available in all family lines */ 00330 #if defined(DUAL_CORE) 00331 #define EXTI_LINE77 ((uint32_t)0x4D) 00332 #define EXTI_LINE78 ((uint32_t)0x4E) 00333 #define EXTI_LINE79 ((uint32_t)0x4F) 00334 #define EXTI_LINE80 ((uint32_t)0x50) 00335 #else 00336 /* EXTI_LINE77 Reserved */ 00337 /* EXTI_LINE78 Reserved */ 00338 /* EXTI_LINE79 Reserved */ 00339 /* EXTI_LINE80 Reserved */ 00340 #endif /* DUAL_CORE */ 00341 /* EXTI_LINE81 Reserved */ 00342 #if defined(DUAL_CORE) 00343 #define EXTI_LINE82 ((uint32_t)0x52) 00344 #else 00345 /* EXTI_LINE82 Reserved */ 00346 #endif /* DUAL_CORE */ 00347 /* EXTI_LINE83 Reserved */ 00348 #if defined(DUAL_CORE) 00349 #define EXTI_LINE84 ((uint32_t)0x54) 00350 #else 00351 /* EXTI_LINE84 Reserved */ 00352 #endif /* DUAL_CORE */ 00353 #define EXTI_LINE85 ((uint32_t)0x55) 00354 #define EXTI_LINE86 ((uint32_t)0x56) /* Not available in all family lines */ 00355 #define EXTI_LINE87 ((uint32_t)0x57) 00356 #define EXTI_LINE88 ((uint32_t)0x58) /* Not available in all family lines */ 00357 #define EXTI_LINE89 ((uint32_t)0x59) /* Not available in all family lines */ 00358 #define EXTI_LINE90 ((uint32_t)0x5A) /* Not available in all family lines */ 00359 #define EXTI_LINE91 ((uint32_t)0x5B) /* Not available in all family lines */ 00360 00361 #if defined(DUAL_CORE) 00362 #define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00363 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00364 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00365 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00366 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00367 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00368 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00369 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00370 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ 00371 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ 00372 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ 00373 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \ 00374 ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84) || \ 00375 ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) 00376 #else 00377 #define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \ 00378 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00379 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00380 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00381 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00382 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00383 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00384 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00385 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ 00386 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ 00387 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ 00388 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \ 00389 ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86)) 00390 #endif /* DUAL_CORE */ 00391 00392 #if defined(DUAL_CORE) 00393 #define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00394 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00395 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00396 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00397 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00398 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00399 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00400 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00401 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ 00402 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ 00403 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ 00404 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ 00405 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ 00406 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ 00407 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ 00408 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ 00409 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ 00410 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ 00411 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ 00412 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ 00413 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ 00414 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ 00415 ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ 00416 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ 00417 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ 00418 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ 00419 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ 00420 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ 00421 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ 00422 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ 00423 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ 00424 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ 00425 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ 00426 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ 00427 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ 00428 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ 00429 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ 00430 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ 00431 ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \ 00432 ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \ 00433 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ 00434 ((LINE) == EXTI_LINE78) || \ 00435 ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82)) 00436 #else 00437 #define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00438 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00439 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00440 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00441 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00442 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00443 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00444 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00445 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ 00446 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ 00447 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ 00448 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ 00449 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ 00450 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ 00451 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ 00452 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ 00453 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ 00454 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ 00455 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ 00456 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ 00457 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ 00458 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ 00459 ((LINE) == EXTI_LINE44) || \ 00460 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ 00461 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ 00462 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ 00463 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ 00464 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ 00465 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ 00466 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ 00467 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ 00468 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ 00469 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ 00470 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ 00471 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ 00472 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ 00473 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ 00474 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ 00475 ((LINE) == EXTI_LINE85) || \ 00476 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ 00477 ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \ 00478 ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) 00479 #endif /*DUAL_CORE*/ 00480 00481 #if defined(DUAL_CORE) 00482 #define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00483 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00484 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00485 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00486 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00487 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00488 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00489 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00490 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ 00491 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ 00492 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ 00493 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ 00494 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ 00495 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ 00496 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ 00497 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ 00498 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ 00499 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ 00500 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ 00501 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ 00502 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ 00503 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ 00504 ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ 00505 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ 00506 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ 00507 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ 00508 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ 00509 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ 00510 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ 00511 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ 00512 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ 00513 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ 00514 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ 00515 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ 00516 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ 00517 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ 00518 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ 00519 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ 00520 ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \ 00521 ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \ 00522 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87)) 00523 #else 00524 #define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00525 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00526 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00527 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00528 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00529 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00530 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00531 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00532 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ 00533 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ 00534 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ 00535 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ 00536 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ 00537 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ 00538 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ 00539 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ 00540 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ 00541 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ 00542 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ 00543 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ 00544 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ 00545 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ 00546 ((LINE) == EXTI_LINE44) || \ 00547 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ 00548 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ 00549 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ 00550 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ 00551 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ 00552 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ 00553 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ 00554 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ 00555 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ 00556 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ 00557 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ 00558 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ 00559 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ 00560 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ 00561 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ 00562 ((LINE) == EXTI_LINE85) || \ 00563 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \ 00564 ((LINE) == EXTI_LINE88) || ((LINE) == EXTI_LINE89) || \ 00565 ((LINE) == EXTI_LINE90) || ((LINE) == EXTI_LINE91)) 00566 #endif /*DUAL_CORE*/ 00567 00568 #if defined(DUAL_CORE) 00569 #define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00570 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00571 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00572 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00573 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00574 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00575 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00576 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00577 ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \ 00578 ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \ 00579 ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \ 00580 ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \ 00581 ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \ 00582 ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \ 00583 ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \ 00584 ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \ 00585 ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \ 00586 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ 00587 ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \ 00588 ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \ 00589 ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \ 00590 ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \ 00591 ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \ 00592 ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \ 00593 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ 00594 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ 00595 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \ 00596 ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \ 00597 ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \ 00598 ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \ 00599 ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \ 00600 ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \ 00601 ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \ 00602 ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \ 00603 ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \ 00604 ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \ 00605 ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \ 00606 ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \ 00607 ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \ 00608 ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \ 00609 ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87)) 00610 #endif /*DUAL_CORE*/ 00611 00612 #if defined(DUAL_CORE) 00613 #define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00614 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00615 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00616 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00617 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00618 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00619 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00620 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00621 ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ 00622 ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ 00623 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ 00624 ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ 00625 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ 00626 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ 00627 ((LINE) == EXTI_LINE53)) 00628 #elif (POWER_DOMAINS_NUMBER == 3U) 00629 #define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00630 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00631 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00632 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00633 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00634 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00635 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00636 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00637 ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ 00638 ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ 00639 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ 00640 ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ 00641 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ 00642 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \ 00643 ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE88)) 00644 #else 00645 #define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \ 00646 ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3) || \ 00647 ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5) || \ 00648 ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7) || \ 00649 ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9) || \ 00650 ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \ 00651 ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \ 00652 ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \ 00653 ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \ 00654 ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \ 00655 ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \ 00656 ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \ 00657 ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \ 00658 ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88)) 00659 #endif /*DUAL_CORE*/ 00660 00661 00662 #define BDMA_CH6_CLEAR ((uint32_t)0x00000000) /*!< BDMA ch6 event selected as D3 domain pendclear source*/ 00663 #define BDMA_CH7_CLEAR ((uint32_t)0x00000001) /*!< BDMA ch7 event selected as D3 domain pendclear source*/ 00664 #if defined (LPTIM4) 00665 #define LPTIM4_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM4 out selected as D3 domain pendclear source*/ 00666 #else 00667 #define LPTIM2_OUT_CLEAR ((uint32_t)0x00000002) /*!< LPTIM2 out selected as D3 domain pendclear source*/ 00668 #endif /* LPTIM4 */ 00669 #if defined (LPTIM5) 00670 #define LPTIM5_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM5 out selected as D3 domain pendclear source*/ 00671 #else 00672 #define LPTIM3_OUT_CLEAR ((uint32_t)0x00000003) /*!< LPTIM3 out selected as D3 domain pendclear source*/ 00673 #endif /* LPTIM5 */ 00674 #if defined (LPTIM4) && defined (LPTIM5) 00675 #define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \ 00676 ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR)) 00677 #else 00678 #define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR) || \ 00679 ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR)) 00680 #endif /* LPTIM4 LPTIM5 */ 00681 /** 00682 * @} 00683 */ 00684 00685 00686 /** @defgroup FMC_SwapBankMapping_Config SwapBankMapping Config 00687 * @{ 00688 */ 00689 #define FMC_SWAPBMAP_DISABLE (0x00000000U) 00690 #define FMC_SWAPBMAP_SDRAM_SRAM FMC_BCR1_BMAP_0 00691 #define FMC_SWAPBMAP_SDRAMB2 FMC_BCR1_BMAP_1 00692 00693 #define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE) || \ 00694 ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \ 00695 ((__MODE__) == FMC_SWAPBMAP_SDRAMB2)) 00696 /** 00697 * @} 00698 */ 00699 00700 00701 /* Exported macro ------------------------------------------------------------*/ 00702 #if defined(DUAL_CORE) 00703 /** @defgroup ART_Exported_Macros ART Exported Macros 00704 * @{ 00705 */ 00706 00707 /** @brief ART Enable Macro. 00708 * Enable the Cortex-M4 ART cache. 00709 */ 00710 #define __HAL_ART_ENABLE() SET_BIT(ART->CTR, ART_CTR_EN) 00711 00712 /** @brief ART Disable Macro. 00713 * Disable the Cortex-M4 ART cache. 00714 */ 00715 #define __HAL_ART_DISABLE() CLEAR_BIT(ART->CTR, ART_CTR_EN) 00716 00717 /** @brief ART Cache BaseAddress Config. 00718 * Configure the Cortex-M4 ART cache Base Address. 00719 */ 00720 #define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__) MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL)) 00721 00722 /** 00723 * @} 00724 */ 00725 #endif /* DUAL_CORE */ 00726 00727 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 00728 * @{ 00729 */ 00730 00731 /** @brief SYSCFG Break AXIRAM double ECC lock. 00732 * Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. 00733 * @note The selected configuration is locked and can be unlocked only by system reset. 00734 This feature is available on STM32H7 rev.B and above. 00735 */ 00736 #define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML) 00737 00738 /** @brief SYSCFG Break ITCM double ECC lock. 00739 * Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. 00740 * @note The selected configuration is locked and can be unlocked only by system reset. 00741 This feature is available on STM32H7 rev.B and above. 00742 */ 00743 #define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML) 00744 00745 /** @brief SYSCFG Break DTCM double ECC lock. 00746 * Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. 00747 * @note The selected configuration is locked and can be unlocked only by system reset. 00748 This feature is available on STM32H7 rev.B and above. 00749 */ 00750 #define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML) 00751 00752 /** @brief SYSCFG Break SRAM1 double ECC lock. 00753 * Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. 00754 * @note The selected configuration is locked and can be unlocked only by system reset. 00755 This feature is available on STM32H7 rev.B and above. 00756 */ 00757 #define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L) 00758 00759 /** @brief SYSCFG Break SRAM2 double ECC lock. 00760 * Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. 00761 * @note The selected configuration is locked and can be unlocked only by system reset. 00762 This feature is available on STM32H7 rev.B and above. 00763 */ 00764 #define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L) 00765 00766 /** @brief SYSCFG Break SRAM3 double ECC lock. 00767 * Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. 00768 * @note The selected configuration is locked and can be unlocked only by system reset. 00769 This feature is available on STM32H7 rev.B and above. 00770 */ 00771 #define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L) 00772 00773 /** @brief SYSCFG Break SRAM4 double ECC lock. 00774 * Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. 00775 * @note The selected configuration is locked and can be unlocked only by system reset. 00776 This feature is available on STM32H7 rev.B and above. 00777 */ 00778 #define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L) 00779 00780 /** @brief SYSCFG Break Backup SRAM double ECC lock. 00781 * Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input. 00782 * @note The selected configuration is locked and can be unlocked only by system reset. 00783 This feature is available on STM32H7 rev.B and above. 00784 */ 00785 #define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML) 00786 00787 /** @brief SYSCFG Break Cortex-M7 Lockup lock. 00788 * Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. 00789 * @note The selected configuration is locked and can be unlocked only by system reset. 00790 This feature is available on STM32H7 rev.B and above. 00791 */ 00792 #define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L) 00793 00794 /** @brief SYSCFG Break FLASH double ECC lock. 00795 * Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input. 00796 * @note The selected configuration is locked and can be unlocked only by system reset. 00797 This feature is available on STM32H7 rev.B and above. 00798 */ 00799 #define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL) 00800 00801 /** @brief SYSCFG Break PVD lock. 00802 * Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register. 00803 * @note The selected configuration is locked and can be unlocked only by system reset. 00804 This feature is available on STM32H7 rev.B and above. 00805 */ 00806 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL) 00807 00808 #if defined(DUAL_CORE) 00809 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 00810 * Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input. 00811 * @note The selected configuration is locked and can be unlocked only by system reset. 00812 This feature is available on STM32H7 rev.B and above. 00813 */ 00814 #define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L) 00815 #endif /* DUAL_CORE */ 00816 00817 #if !defined(SYSCFG_PMCR_BOOSTEN) 00818 /** @brief Fast-mode Plus driving capability enable/disable macros 00819 * @param __FASTMODEPLUS__ This parameter can be a value of : 00820 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 00821 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 00822 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 00823 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 00824 */ 00825 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 00826 SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ 00827 }while(0) 00828 00829 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 00830 CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\ 00831 }while(0) 00832 00833 #endif /* !SYSCFG_PMCR_BOOSTEN */ 00834 /** 00835 * @} 00836 */ 00837 00838 /** @brief Freeze/Unfreeze Peripherals in Debug mode 00839 */ 00840 #define __HAL_DBGMCU_FREEZE_WWDG1() (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1)) 00841 00842 #define __HAL_DBGMCU_FREEZE_TIM2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2)) 00843 #define __HAL_DBGMCU_FREEZE_TIM3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3)) 00844 #define __HAL_DBGMCU_FREEZE_TIM4() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4)) 00845 #define __HAL_DBGMCU_FREEZE_TIM5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5)) 00846 #define __HAL_DBGMCU_FREEZE_TIM6() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6)) 00847 #define __HAL_DBGMCU_FREEZE_TIM7() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7)) 00848 #define __HAL_DBGMCU_FREEZE_TIM12() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12)) 00849 #define __HAL_DBGMCU_FREEZE_TIM13() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13)) 00850 #define __HAL_DBGMCU_FREEZE_TIM14() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14)) 00851 #define __HAL_DBGMCU_FREEZE_LPTIM1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1)) 00852 #define __HAL_DBGMCU_FREEZE_I2C1() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1)) 00853 #define __HAL_DBGMCU_FREEZE_I2C2() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2)) 00854 #define __HAL_DBGMCU_FREEZE_I2C3() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3)) 00855 #if defined(I2C5) 00856 #define __HAL_DBGMCU_FREEZE_I2C5() (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C5)) 00857 #endif /*I2C5*/ 00858 #if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) 00859 #define __HAL_DBGMCU_FREEZE_FDCAN() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN)) 00860 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ 00861 00862 #if defined(TIM23) 00863 #define __HAL_DBGMCU_FREEZE_TIM23() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM23)) 00864 #endif /*TIM23*/ 00865 #if defined(TIM24) 00866 #define __HAL_DBGMCU_FREEZE_TIM24() (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_TIM24)) 00867 #endif /*TIM24*/ 00868 00869 #define __HAL_DBGMCU_FREEZE_TIM1() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1)) 00870 #define __HAL_DBGMCU_FREEZE_TIM8() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8)) 00871 #define __HAL_DBGMCU_FREEZE_TIM15() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15)) 00872 #define __HAL_DBGMCU_FREEZE_TIM16() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16)) 00873 #define __HAL_DBGMCU_FREEZE_TIM17() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17)) 00874 #define __HAL_DBGMCU_FREEZE_HRTIM() (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM)) 00875 00876 #define __HAL_DBGMCU_FREEZE_I2C4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4)) 00877 #define __HAL_DBGMCU_FREEZE_LPTIM2() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2)) 00878 #define __HAL_DBGMCU_FREEZE_LPTIM3() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3)) 00879 #define __HAL_DBGMCU_FREEZE_LPTIM4() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4)) 00880 #define __HAL_DBGMCU_FREEZE_LPTIM5() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5)) 00881 #define __HAL_DBGMCU_FREEZE_RTC() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC)) 00882 #define __HAL_DBGMCU_FREEZE_IWDG1() (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1)) 00883 00884 00885 #define __HAL_DBGMCU_UnFreeze_WWDG1() (DBGMCU->APB3FZ1 &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1)) 00886 00887 #define __HAL_DBGMCU_UnFreeze_TIM2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2)) 00888 #define __HAL_DBGMCU_UnFreeze_TIM3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3)) 00889 #define __HAL_DBGMCU_UnFreeze_TIM4() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4)) 00890 #define __HAL_DBGMCU_UnFreeze_TIM5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5)) 00891 #define __HAL_DBGMCU_UnFreeze_TIM6() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6)) 00892 #define __HAL_DBGMCU_UnFreeze_TIM7() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7)) 00893 #define __HAL_DBGMCU_UnFreeze_TIM12() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12)) 00894 #define __HAL_DBGMCU_UnFreeze_TIM13() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13)) 00895 #define __HAL_DBGMCU_UnFreeze_TIM14() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14)) 00896 #define __HAL_DBGMCU_UnFreeze_LPTIM1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1)) 00897 #define __HAL_DBGMCU_UnFreeze_I2C1() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1)) 00898 #define __HAL_DBGMCU_UnFreeze_I2C2() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2)) 00899 #define __HAL_DBGMCU_UnFreeze_I2C3() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3)) 00900 #if defined(I2C5) 00901 #define __HAL_DBGMCU_UnFreeze_I2C5() (DBGMCU->APB1LFZ1 &= ~ (DBGMCU_APB1LFZ1_DBG_I2C5)) 00902 #endif /*I2C5*/ 00903 #if defined(DBGMCU_APB1HFZ1_DBG_FDCAN) 00904 #define __HAL_DBGMCU_UnFreeze_FDCAN() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN)) 00905 #endif /*DBGMCU_APB1HFZ1_DBG_FDCAN*/ 00906 00907 #if defined(TIM23) 00908 #define __HAL_DBGMCU_UnFreeze_TIM23() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM23)) 00909 #endif /*TIM23*/ 00910 #if defined(TIM24) 00911 #define __HAL_DBGMCU_UnFreeze_TIM24() (DBGMCU->APB1HFZ1 &= ~ (DBGMCU_APB1HFZ1_DBG_TIM24)) 00912 #endif /*TIM24*/ 00913 00914 #define __HAL_DBGMCU_UnFreeze_TIM1() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM1)) 00915 #define __HAL_DBGMCU_UnFreeze_TIM8() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM8)) 00916 #define __HAL_DBGMCU_UnFreeze_TIM15() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM15)) 00917 #define __HAL_DBGMCU_UnFreeze_TIM16() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM16)) 00918 #define __HAL_DBGMCU_UnFreeze_TIM17() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_TIM17)) 00919 #define __HAL_DBGMCU_UnFreeze_HRTIM() (DBGMCU->APB2FZ1 &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM)) 00920 00921 #define __HAL_DBGMCU_UnFreeze_I2C4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_I2C4)) 00922 #define __HAL_DBGMCU_UnFreeze_LPTIM2() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2)) 00923 #define __HAL_DBGMCU_UnFreeze_LPTIM3() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3)) 00924 #define __HAL_DBGMCU_UnFreeze_LPTIM4() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4)) 00925 #define __HAL_DBGMCU_UnFreeze_LPTIM5() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5)) 00926 #define __HAL_DBGMCU_UnFreeze_RTC() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_RTC)) 00927 #define __HAL_DBGMCU_UnFreeze_IWDG1() (DBGMCU->APB4FZ1 &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1)) 00928 00929 00930 #if defined(DUAL_CORE) 00931 #define __HAL_DBGMCU_FREEZE2_IWDG2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG2)) 00932 #define __HAL_DBGMCU_FREEZE2_WWDG2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2)) 00933 00934 #define __HAL_DBGMCU_UnFreeze2_IWDG2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2)) 00935 #define __HAL_DBGMCU_UnFreeze2_WWDG2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2)) 00936 00937 00938 #define __HAL_DBGMCU_FREEZE2_WWDG1() (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1)) 00939 00940 #define __HAL_DBGMCU_FREEZE2_TIM2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2)) 00941 #define __HAL_DBGMCU_FREEZE2_TIM3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3)) 00942 #define __HAL_DBGMCU_FREEZE2_TIM4() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4)) 00943 #define __HAL_DBGMCU_FREEZE2_TIM5() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5)) 00944 #define __HAL_DBGMCU_FREEZE2_TIM6() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6)) 00945 #define __HAL_DBGMCU_FREEZE2_TIM7() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7)) 00946 #define __HAL_DBGMCU_FREEZE2_TIM12() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12)) 00947 #define __HAL_DBGMCU_FREEZE2_TIM13() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13)) 00948 #define __HAL_DBGMCU_FREEZE2_TIM14() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14)) 00949 #define __HAL_DBGMCU_FREEZE2_LPTIM1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1)) 00950 #define __HAL_DBGMCU_FREEZE2_I2C1() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1)) 00951 #define __HAL_DBGMCU_FREEZE2_I2C2() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2)) 00952 #define __HAL_DBGMCU_FREEZE2_I2C3() (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3)) 00953 #define __HAL_DBGMCU_FREEZE2_FDCAN() (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN)) 00954 00955 00956 #define __HAL_DBGMCU_FREEZE2_TIM1() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1)) 00957 #define __HAL_DBGMCU_FREEZE2_TIM8() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8)) 00958 #define __HAL_DBGMCU_FREEZE2_TIM15() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15)) 00959 #define __HAL_DBGMCU_FREEZE2_TIM16() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16)) 00960 #define __HAL_DBGMCU_FREEZE2_TIM17() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17)) 00961 #define __HAL_DBGMCU_FREEZE2_HRTIM() (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM)) 00962 00963 #define __HAL_DBGMCU_FREEZE2_I2C4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4)) 00964 #define __HAL_DBGMCU_FREEZE2_LPTIM2() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2)) 00965 #define __HAL_DBGMCU_FREEZE2_LPTIM3() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3)) 00966 #define __HAL_DBGMCU_FREEZE2_LPTIM4() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4)) 00967 #define __HAL_DBGMCU_FREEZE2_LPTIM5() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5)) 00968 #define __HAL_DBGMCU_FREEZE2_RTC() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC)) 00969 #define __HAL_DBGMCU_FREEZE2_IWDG1() (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1)) 00970 00971 #define __HAL_DBGMCU_UnFreeze2_WWDG1() (DBGMCU->APB3FZ2 &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1)) 00972 00973 #define __HAL_DBGMCU_UnFreeze2_TIM2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2)) 00974 #define __HAL_DBGMCU_UnFreeze2_TIM3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3)) 00975 #define __HAL_DBGMCU_UnFreeze2_TIM4() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4)) 00976 #define __HAL_DBGMCU_UnFreeze2_TIM5() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5)) 00977 #define __HAL_DBGMCU_UnFreeze2_TIM6() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6)) 00978 #define __HAL_DBGMCU_UnFreeze2_TIM7() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7)) 00979 #define __HAL_DBGMCU_UnFreeze2_TIM12() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12)) 00980 #define __HAL_DBGMCU_UnFreeze2_TIM13() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13)) 00981 #define __HAL_DBGMCU_UnFreeze2_TIM14() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14)) 00982 #define __HAL_DBGMCU_UnFreeze2_LPTIM1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1)) 00983 #define __HAL_DBGMCU_UnFreeze2_I2C1() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1)) 00984 #define __HAL_DBGMCU_UnFreeze2_I2C2() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2)) 00985 #define __HAL_DBGMCU_UnFreeze2_I2C3() (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3)) 00986 #define __HAL_DBGMCU_UnFreeze2_FDCAN() (DBGMCU->APB1HFZ2 &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN)) 00987 00988 00989 #define __HAL_DBGMCU_UnFreeze2_TIM1() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM1)) 00990 #define __HAL_DBGMCU_UnFreeze2_TIM8() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM8)) 00991 #define __HAL_DBGMCU_UnFreeze2_TIM15() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM15)) 00992 #define __HAL_DBGMCU_UnFreeze2_TIM16() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM16)) 00993 #define __HAL_DBGMCU_UnFreeze2_TIM17() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_TIM17)) 00994 #define __HAL_DBGMCU_UnFreeze2_HRTIM() (DBGMCU->APB2FZ2 &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM)) 00995 00996 #define __HAL_DBGMCU_UnFreeze2_I2C4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_I2C4)) 00997 #define __HAL_DBGMCU_UnFreeze2_LPTIM2() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2)) 00998 #define __HAL_DBGMCU_UnFreeze2_LPTIM3() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3)) 00999 #define __HAL_DBGMCU_UnFreeze2_LPTIM4() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4)) 01000 #define __HAL_DBGMCU_UnFreeze2_LPTIM5() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5)) 01001 #define __HAL_DBGMCU_UnFreeze2_RTC() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_RTC)) 01002 #define __HAL_DBGMCU_UnFreeze2_IWDG1() (DBGMCU->APB4FZ2 &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1)) 01003 01004 #endif /*DUAL_CORE*/ 01005 01006 /** @defgroup HAL_Private_Macros HAL Private Macros 01007 * @{ 01008 */ 01009 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 01010 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 01011 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 01012 /** 01013 * @} 01014 */ 01015 01016 /* Exported variables --------------------------------------------------------*/ 01017 01018 /** @addtogroup HAL_Exported_Variables 01019 * @{ 01020 */ 01021 extern __IO uint32_t uwTick; 01022 extern uint32_t uwTickPrio; 01023 extern HAL_TickFreqTypeDef uwTickFreq; 01024 /** 01025 * @} 01026 */ 01027 01028 /* Exported functions --------------------------------------------------------*/ 01029 01030 /* Initialization and de-initialization functions ******************************/ 01031 HAL_StatusTypeDef HAL_Init(void); 01032 HAL_StatusTypeDef HAL_DeInit(void); 01033 void HAL_MspInit(void); 01034 void HAL_MspDeInit(void); 01035 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 01036 01037 /* Peripheral Control functions ************************************************/ 01038 void HAL_IncTick(void); 01039 void HAL_Delay(uint32_t Delay); 01040 uint32_t HAL_GetTick(void); 01041 uint32_t HAL_GetTickPrio(void); 01042 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 01043 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 01044 void HAL_SuspendTick(void); 01045 void HAL_ResumeTick(void); 01046 uint32_t HAL_GetHalVersion(void); 01047 uint32_t HAL_GetREVID(void); 01048 uint32_t HAL_GetDEVID(void); 01049 uint32_t HAL_GetUIDw0(void); 01050 uint32_t HAL_GetUIDw1(void); 01051 uint32_t HAL_GetUIDw2(void); 01052 #if defined(SYSCFG_PMCR_EPIS_SEL) 01053 void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface); 01054 #endif /* SYSCFG_PMCR_EPIS_SEL */ 01055 void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState ); 01056 #if defined(SYSCFG_PMCR_BOOSTEN) 01057 void HAL_SYSCFG_EnableBOOST(void); 01058 void HAL_SYSCFG_DisableBOOST(void); 01059 #endif /* SYSCFG_PMCR_BOOSTEN */ 01060 01061 #if defined (SYSCFG_UR2_BOOT_ADD0) || defined (SYSCFG_UR2_BCM7_ADD0) 01062 void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); 01063 #endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/ 01064 01065 #if defined(DUAL_CORE) 01066 void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress); 01067 void HAL_SYSCFG_EnableCM7BOOT(void); 01068 void HAL_SYSCFG_DisableCM7BOOT(void); 01069 void HAL_SYSCFG_EnableCM4BOOT(void); 01070 void HAL_SYSCFG_DisableCM4BOOT(void); 01071 #endif /*DUAL_CORE*/ 01072 void HAL_EnableCompensationCell(void); 01073 void HAL_DisableCompensationCell(void); 01074 void HAL_SYSCFG_EnableIOSpeedOptimize(void); 01075 void HAL_SYSCFG_DisableIOSpeedOptimize(void); 01076 void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode); 01077 void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); 01078 #if defined(SYSCFG_CCCR_NCC_MMC) 01079 void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode); 01080 #endif /* SYSCFG_CCCR_NCC_MMC */ 01081 void HAL_DBGMCU_EnableDBGSleepMode(void); 01082 void HAL_DBGMCU_DisableDBGSleepMode(void); 01083 void HAL_DBGMCU_EnableDBGStopMode(void); 01084 void HAL_DBGMCU_DisableDBGStopMode(void); 01085 void HAL_DBGMCU_EnableDBGStandbyMode(void); 01086 void HAL_DBGMCU_DisableDBGStandbyMode(void); 01087 #if defined(DUAL_CORE) 01088 void HAL_EnableDomain2DBGSleepMode(void); 01089 void HAL_DisableDomain2DBGSleepMode(void); 01090 void HAL_EnableDomain2DBGStopMode(void); 01091 void HAL_DisableDomain2DBGStopMode(void); 01092 void HAL_EnableDomain2DBGStandbyMode(void); 01093 void HAL_DisableDomain2DBGStandbyMode(void); 01094 #endif /*DUAL_CORE*/ 01095 #if defined(DBGMCU_CR_DBG_STOPD3) 01096 void HAL_EnableDomain3DBGStopMode(void); 01097 void HAL_DisableDomain3DBGStopMode(void); 01098 #endif /*DBGMCU_CR_DBG_STOPD3*/ 01099 #if defined(DBGMCU_CR_DBG_STANDBYD3) 01100 void HAL_EnableDomain3DBGStandbyMode(void); 01101 void HAL_DisableDomain3DBGStandbyMode(void); 01102 #endif /*DBGMCU_CR_DBG_STANDBYD3*/ 01103 void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge ); 01104 void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 01105 #if defined(DUAL_CORE) 01106 void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line); 01107 #endif /*DUAL_CORE*/ 01108 void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line); 01109 void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd); 01110 #if defined(DUAL_CORE) 01111 void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode, uint32_t EXTI_LineCmd); 01112 #endif /*DUAL_CORE*/ 01113 void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc); 01114 void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig); 01115 uint32_t HAL_GetFMCMemorySwappingConfig(void); 01116 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 01117 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 01118 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 01119 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 01120 void HAL_SYSCFG_DisableVREFBUF(void); 01121 #if defined(SYSCFG_ADC2ALT_ADC2_ROUT0) 01122 void HAL_SYSCFG_ADC2ALT_Rout0Config(uint32_t Adc2AltRout0); 01123 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT0*/ 01124 #if defined(SYSCFG_ADC2ALT_ADC2_ROUT1) 01125 void HAL_SYSCFG_ADC2ALT_Rout1Config(uint32_t Adc2AltRout1); 01126 #endif /*SYSCFG_ADC2ALT_ADC2_ROUT1*/ 01127 01128 /** 01129 * @} 01130 */ 01131 01132 /** 01133 * @} 01134 */ 01135 01136 #ifdef __cplusplus 01137 } 01138 #endif 01139 01140 #endif /* STM32H7xx_HAL_H */ 01141 01142
1.7.6.1