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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_adc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC HAL extended module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_ADC_EX_H 00021 #define STM32H7xx_HAL_ADC_EX_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 /** @addtogroup STM32H7xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup ADCEx 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 00040 * @{ 00041 */ 00042 00043 /** 00044 * @brief ADC Injected Conversion Oversampling structure definition 00045 */ 00046 typedef struct 00047 { 00048 uint32_t Ratio; /*!< Configures the oversampling ratio. */ 00049 #if defined(ADC_VER_V5_V90) 00050 /* On devices STM32H72xx and STM32H73xx this parameter can be a value from 1 to 1023 for ADC1/2 and value of @ref ADC_HAL_EC_OVS_RATIO for ADC3*/ 00051 #else 00052 /* This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 00053 #endif 00054 00055 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 00056 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 00057 } ADC_InjOversamplingTypeDef; 00058 00059 /** 00060 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 00061 * @note Parameters of this structure are shared within 2 scopes: 00062 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 00063 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 00064 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 00065 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 00066 * ADC state can be either: 00067 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 00068 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 00069 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 00070 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 00071 * on ADC groups regular and injected. 00072 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00073 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 00074 */ 00075 typedef struct 00076 { 00077 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 00078 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 00079 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 00080 00081 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 00082 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 00083 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 00084 the new channel setting (or parameter number of conversions adjusted) */ 00085 00086 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 00087 Unit: ADC clock cycles. 00088 Conversion time is the addition of sampling time and processing time 00089 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 00090 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 00091 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00092 It overwrites the last setting. 00093 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00094 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 00095 Refer to device datasheet for timings values. */ 00096 00097 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 00098 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 00099 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 00100 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 00101 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00102 It overwrites the last setting. 00103 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 00104 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 00105 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00106 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 00107 of another parameter update on the fly) */ 00108 00109 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 00110 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 00111 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 00112 00113 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 00114 Offset value must be a positive number. 00115 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 00116 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 00117 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00118 without continuous mode or external trigger that could launch a conversion). */ 00119 00120 uint32_t InjectedOffsetRightShift; /*!< Specifies whether the 1 bit Right-shift feature is used or not. 00121 This parameter is applied only for 16-bit or 8-bit resolution. 00122 This parameter can be set to ENABLE or DISABLE. */ 00123 #if defined(ADC_VER_V5_V90) 00124 uint32_t InjectedOffsetSign; /*!< Define if the offset should be subtracted (negative sign) or added (positive sign) from or to the raw converted data. 00125 This parameter can be a value of @ref ADCEx_OffsetSign. 00126 Note: 00127 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 00128 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 00129 FunctionalState InjectedOffsetSaturation; /*!< Define if the offset should be saturated upon under or over flow. 00130 This parameter value can be ENABLE or DISABLE. 00131 Note: 00132 - This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). 00133 - On devices STM32H72xx and STM32H73xx, this parameter is specific to ADC3 only. */ 00134 00135 #endif 00136 00137 FunctionalState InjectedOffsetSignedSaturation; /*!< Specifies whether the Signed saturation feature is used or not. 00138 This parameter is applied only for 16-bit or 8-bit resolution. 00139 This parameter can be set to ENABLE or DISABLE. */ 00140 00141 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 00142 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00143 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 00144 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00145 configure a channel on injected group can impact the configuration of other channels previously set. */ 00146 00147 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 00148 (main sequence subdivided in successive parts). 00149 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00150 Discontinuous mode can be enabled only if continuous mode is disabled. 00151 This parameter can be set to ENABLE or DISABLE. 00152 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00153 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 00154 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00155 configure a channel on injected group can impact the configuration of other channels previously set. */ 00156 00157 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 00158 This parameter can be set to ENABLE or DISABLE. 00159 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 00160 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 00161 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 00162 To maintain JAUTO always enabled, DMA must be configured in circular mode. 00163 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00164 configure a channel on injected group can impact the configuration of other channels previously set. */ 00165 00166 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 00167 This parameter can be set to ENABLE or DISABLE. 00168 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 00169 new injected context is set when queue is full, error is triggered by interruption and through function 00170 'HAL_ADCEx_InjectedQueueOverflowCallback'. 00171 Caution: This feature request that the sequence is fully configured before injected conversion start. 00172 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 00173 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00174 configure a channel on injected group can impact the configuration of other channels previously set. 00175 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 00176 00177 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 00178 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 00179 This parameter can be a value of @ref ADC_injected_external_trigger_source. 00180 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00181 configure a channel on injected group can impact the configuration of other channels previously set. */ 00182 00183 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 00184 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 00185 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 00186 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00187 configure a channel on injected group can impact the configuration of other channels previously set. */ 00188 00189 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 00190 This parameter can be set to ENABLE or DISABLE. 00191 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00192 00193 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 00194 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 00195 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00196 } ADC_InjectionConfTypeDef; 00197 00198 /** 00199 * @brief Structure definition of ADC multimode 00200 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 00201 * Both Master and Slave ADCs must be disabled. 00202 */ 00203 typedef struct 00204 { 00205 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 00206 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 00207 00208 uint32_t DualModeData; /*!< Configures the Dual ADC Mode Data Format: 00209 This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */ 00210 00211 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 00212 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 00213 Delay range depends on selected resolution: 00214 from 1 to 9 clock cycles for 16 bits, 00215 from 1 to 9 clock cycles for 14 bits 00216 from 1 to 8 clock cycles for 12 bits 00217 from 1 to 6 clock cycles for 10 bits 00218 from 1 to 6 clock cycles for 8 bits */ 00219 } ADC_MultiModeTypeDef; 00220 00221 /** 00222 * @} 00223 */ 00224 00225 /* Exported constants --------------------------------------------------------*/ 00226 00227 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 00228 * @{ 00229 */ 00230 00231 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 00232 * @{ 00233 */ 00234 /* ADC group regular trigger sources for all ADC instances */ 00235 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 00236 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */ 00237 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00238 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */ 00239 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00240 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00241 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */ 00242 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 00243 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00244 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */ 00245 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */ 00246 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */ 00247 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00248 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */ 00249 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00250 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */ 00251 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */ 00252 #if defined(HRTIM1) 00253 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */ 00254 #define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4 (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */ 00255 #endif /* HRTIM1 */ 00256 #define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */ 00257 #define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */ 00258 #define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT) /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */ 00259 /** 00260 * @} 00261 */ 00262 00263 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 00264 * @{ 00265 */ 00266 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 00267 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 00268 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 00269 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 00270 /** 00271 * @} 00272 */ 00273 00274 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 00275 * @{ 00276 */ 00277 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 00278 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 00284 * @{ 00285 */ 00286 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 00287 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00288 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00289 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00290 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00291 /** 00292 * @} 00293 */ 00294 00295 #if defined(ADC_VER_V5_V90) 00296 /** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign 00297 * @{ 00298 */ 00299 #define ADC3_OFFSET_SIGN_NEGATIVE (0x00000000UL) /*!< Offset sign negative, offset is subtracted */ 00300 #define ADC3_OFFSET_SIGN_POSITIVE (ADC3_OFR1_OFFSETPOS) /*!< Offset sign positive, offset is added */ 00301 /** 00302 * @} 00303 */ 00304 #endif 00305 00306 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 00307 * @{ 00308 */ 00309 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 00310 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 00311 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 00312 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 00313 /** 00314 * @} 00315 */ 00316 00317 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 00318 * @{ 00319 */ 00320 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 00321 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 00322 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 00323 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 00324 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 00325 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 00326 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 00327 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 00328 00329 /** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting 00330 * @{ 00331 */ 00332 #define ADC_DUALMODEDATAFORMAT_DISABLED (0x00000000UL) /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */ 00333 #define ADC_DUALMODEDATAFORMAT_32_10_BITS (ADC_CCR_DAMDF_1) /*!< Data formatting mode for 32 down to 10-bit resolution */ 00334 #define ADC_DUALMODEDATAFORMAT_8_BITS ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */ 00335 /** 00336 * @} 00337 */ 00338 00339 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 00340 * @{ 00341 */ 00342 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 00343 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 00344 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 00345 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 00346 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 00347 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 00348 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 00349 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 00350 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 00351 /** 00352 * @} 00353 */ 00354 00355 /** 00356 * @} 00357 */ 00358 00359 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 00360 * @{ 00361 */ 00362 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 00363 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 00364 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 00365 /** 00366 * @} 00367 */ 00368 00369 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 00370 * @{ 00371 */ 00372 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 00373 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 00374 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 00375 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 00376 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 00377 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 00378 /** 00379 * @} 00380 */ 00381 00382 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 00383 * @{ 00384 */ 00385 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 00386 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 00387 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 00388 ADC_SMPR1_SMP0) 00389 /** 00390 * @} 00391 */ 00392 00393 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 00394 * @{ 00395 */ 00396 /* ADC_CFGR fields of parameters that can be updated when no conversion 00397 (neither regular nor injected) is on-going */ 00398 #define ADC_CFGR_FIELDS_2 ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY)) 00399 /** 00400 * @} 00401 */ 00402 #if defined(ADC_VER_V5_V90) 00403 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 00404 * @{ 00405 */ 00406 /* ADC_CFGR fields of parameters that can be updated when no conversion 00407 (neither regular nor injected) is on-going */ 00408 #define ADC3_CFGR_FIELDS_2 ((ADC3_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 00409 /** 00410 * @} 00411 */ 00412 #endif 00413 00414 #if defined(DFSDM1_Channel0) 00415 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 00416 * @{ 00417 */ 00418 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ 00419 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 00420 /** 00421 * @} 00422 */ 00423 #endif 00424 00425 /** 00426 * @} 00427 */ 00428 00429 /* Exported macros -----------------------------------------------------------*/ 00430 00431 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 00432 * @{ 00433 */ 00434 00435 /** @brief Force ADC instance in multimode mode independent (multimode disable). 00436 * @note This macro must be used only in case of transition from multimode 00437 * to mode independent and in case of unknown previous state, 00438 * to ensure ADC configuration is in mode independent. 00439 * @note Standard way of multimode configuration change is done from 00440 * HAL ADC handle of ADC master using function 00441 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 00442 * Usage of this macro is not the Standard way of multimode 00443 * configuration and can lead to have HAL ADC handles status 00444 * misaligned. Usage of this macro must be limited to cases 00445 * mentioned above. 00446 * @param __HANDLE__ ADC handle. 00447 * @retval None 00448 */ 00449 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 00450 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 00451 00452 /** 00453 * @} 00454 */ 00455 00456 /* Private macros ------------------------------------------------------------*/ 00457 00458 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 00459 * @{ 00460 */ 00461 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 00462 /* code of final user. */ 00463 00464 /** 00465 * @brief Test if conversion trigger of injected group is software start 00466 * or external trigger. 00467 * @param __HANDLE__ ADC handle. 00468 * @retval SET (software start) or RESET (external trigger). 00469 */ 00470 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 00471 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 00472 00473 /** 00474 * @brief Check if conversion is on going on regular or injected groups. 00475 * @param __HANDLE__ ADC handle. 00476 * @retval SET (conversion is on going) or RESET (no conversion is on going). 00477 */ 00478 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 00479 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 00480 ) ? RESET : SET) 00481 00482 /** 00483 * @brief Check if conversion is on going on injected group. 00484 * @param __HANDLE__ ADC handle. 00485 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 00486 */ 00487 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 00488 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 00489 00490 00491 #if defined (ADC3) 00492 /** 00493 * @brief Check whether or not ADC is independent. 00494 * @param __HANDLE__ ADC handle. 00495 * @note When multimode feature is not available, the macro always returns SET. 00496 * @retval SET (ADC is independent) or RESET (ADC is not). 00497 */ 00498 00499 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 00500 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 00501 )? \ 00502 SET \ 00503 : \ 00504 RESET \ 00505 ) 00506 #endif 00507 00508 /** 00509 * @brief Set the selected injected Channel rank. 00510 * @param __CHANNELNB__ Channel number. 00511 * @param __RANKNB__ Rank number. 00512 * @retval None 00513 */ 00514 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 00515 00516 /** 00517 * @brief Configure ADC injected context queue 00518 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 00519 * @retval None 00520 */ 00521 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 00522 00523 /** 00524 * @brief Configure ADC discontinuous conversion mode for injected group 00525 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 00526 * @retval None 00527 */ 00528 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 00529 00530 /** 00531 * @brief Configure ADC discontinuous conversion mode for regular group 00532 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 00533 * @retval None 00534 */ 00535 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 00536 00537 /** 00538 * @brief Configure the number of discontinuous conversions for regular group. 00539 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 00540 * @retval None 00541 */ 00542 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 00543 00544 /** 00545 * @brief Configure the ADC auto delay mode. 00546 * @param __AUTOWAIT__ Auto delay bit enable or disable. 00547 * @retval None 00548 */ 00549 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 00550 00551 /** 00552 * @brief Configure ADC continuous conversion mode. 00553 * @param __CONTINUOUS_MODE__ Continuous mode. 00554 * @retval None 00555 */ 00556 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 00557 00558 /** 00559 * @brief Enable the ADC DMA continuous request. 00560 * @param __DMACONTREQ_MODE__: DMA continuous request mode. 00561 * @retval None 00562 */ 00563 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__)) 00564 00565 #if defined(ADC_VER_V5_V90) 00566 /** 00567 * @brief Configure the ADC DMA continuous request. 00568 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 00569 * @retval None 00570 */ 00571 #define ADC3_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC3_CFGR_DMACFG_Pos) 00572 #endif 00573 /** 00574 * @brief Configure the channel number into offset OFRx register. 00575 * @param __CHANNEL__ ADC Channel. 00576 * @retval None 00577 */ 00578 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 00579 00580 /** 00581 * @brief Configure the channel number into differential mode selection register. 00582 * @param __CHANNEL__ ADC Channel. 00583 * @retval None 00584 */ 00585 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 00586 00587 /** 00588 * @brief Configure calibration factor in differential mode to be set into calibration register. 00589 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00590 * @retval None 00591 */ 00592 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 00593 00594 /** 00595 * @brief Calibration factor in differential mode to be retrieved from calibration register. 00596 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00597 * @retval None 00598 */ 00599 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 00600 00601 /** 00602 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 00603 * @param __THRESHOLD__ Threshold value. 00604 * @retval None 00605 */ 00606 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 00607 00608 /** 00609 * @brief Configure the ADC DMA continuous request for ADC multimode. 00610 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 00611 * @retval None 00612 */ 00613 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 00614 00615 /** 00616 * @brief Shift the offset in function of the selected ADC resolution. 00617 * @note Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0 00618 * If resolution 16 bits, no shift. 00619 * If resolution 14 bits, shift of 2 ranks on the left. 00620 * If resolution 12 bits, shift of 4 ranks on the left. 00621 * If resolution 10 bits, shift of 6 ranks on the left. 00622 * If resolution 8 bits, shift of 8 ranks on the left. 00623 * therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2)) 00624 * @param __HANDLE__: ADC handle 00625 * @param __OFFSET__: Value to be shifted 00626 * @retval None 00627 */ 00628 #if defined(ADC_VER_V5_3) 00629 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 00630 ( \ 00631 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 00632 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00633 : \ 00634 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 00635 ) 00636 #else 00637 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 00638 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 00639 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00640 : \ 00641 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 00642 ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00643 : \ 00644 ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 00645 ) 00646 #endif /* ADC_VER_V5_3 */ 00647 00648 #if defined(ADC_VER_V5_V90) 00649 #define ADC3_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 00650 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC3_CFGR_RES) >> 3UL) * 2UL)) 00651 00652 #endif /* ADC_VER_V5_V90 */ 00653 00654 /** 00655 * @brief Shift the AWD1 threshold in function of the selected ADC resolution. 00656 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 00657 * If resolution 16 bits, no shift. 00658 * If resolution 14 bits, shift of 2 ranks on the left. 00659 * If resolution 12 bits, shift of 4 ranks on the left. 00660 * If resolution 10 bits, shift of 6 ranks on the left. 00661 * If resolution 8 bits, shift of 8 ranks on the left. 00662 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 00663 * @param __HANDLE__: ADC handle 00664 * @param __THRESHOLD__: Value to be shifted 00665 * @retval None 00666 */ 00667 #if defined(ADC_VER_V5_3) 00668 #if defined(ADC_VER_V5_V90) 00669 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00670 ( ((__HANDLE__)->Instance == ADC3) \ 00671 ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC3_CFGR_RES)>> 3UL)*2UL)) \ 00672 : \ 00673 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 00674 ?((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00675 : \ 00676 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 00677 ) 00678 #else 00679 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00680 ( \ 00681 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 00682 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00683 : \ 00684 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 00685 ) 00686 #endif 00687 00688 #else 00689 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00690 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 00691 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00692 : \ 00693 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 00694 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00695 : \ 00696 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 00697 ) 00698 #endif /* ADC_VER_V5_3 */ 00699 00700 /** 00701 * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution. 00702 * @note Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0. 00703 * If resolution 16 bits, no shift. 00704 * If resolution 14 bits, shift of 2 ranks on the left. 00705 * If resolution 12 bits, shift of 4 ranks on the left. 00706 * If resolution 10 bits, shift of 6 ranks on the left. 00707 * If resolution 8 bits, shift of 8 ranks on the left. 00708 * therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2)) 00709 * @param __HANDLE__: ADC handle 00710 * @param __THRESHOLD__: Value to be shifted 00711 * @retval None 00712 */ 00713 #if defined(ADC_VER_V5_3) || defined(ADC_VER_V5_V90) 00714 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00715 ( \ 00716 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 00717 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00718 : \ 00719 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 00720 ) 00721 #else 00722 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00723 (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL) \ 00724 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00725 : \ 00726 ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL) \ 00727 ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL)) \ 00728 : \ 00729 ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL)) \ 00730 ) 00731 #endif /* ADC_VER_V5_3 */ 00732 /** 00733 * @brief Clear Common Control Register. 00734 * @param __HANDLE__ ADC handle. 00735 * @retval None 00736 */ 00737 /** 00738 * @brief Report common register to ADC1 and ADC2 00739 * @param __HANDLE__: ADC handle 00740 * @retval Common control register 00741 */ 00742 #define ADC12_COMMON_REGISTER(__HANDLE__) (ADC12_COMMON) 00743 #if defined (ADC3) 00744 /** 00745 * @brief Report common register to ADC3 00746 * @param __HANDLE__: ADC handle 00747 * @retval Common control register 00748 */ 00749 #define ADC3_COMMON_REGISTER(__HANDLE__) (ADC3_COMMON) 00750 #endif 00751 /** 00752 * @brief Report Master Instance 00753 * @param __HANDLE__: ADC handle 00754 * @note return same instance if ADC of input handle is independent ADC 00755 * @retval Master Instance 00756 */ 00757 #if defined (ADC3) 00758 #define ADC_MASTER_REGISTER(__HANDLE__) \ 00759 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \ 00760 )? \ 00761 ((__HANDLE__)->Instance) \ 00762 : \ 00763 (ADC1) \ 00764 ) 00765 #else 00766 #define ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1)) 00767 #endif 00768 00769 /** 00770 * @brief Check whether or not dual regular conversions are enabled 00771 * @param __HANDLE__: ADC handle 00772 * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled) 00773 */ 00774 #define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \ 00775 ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \ 00776 )? \ 00777 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \ 00778 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \ 00779 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \ 00780 : \ 00781 RESET \ 00782 ) 00783 00784 /** 00785 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master 00786 * @param __HANDLE__: ADC handle 00787 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 00788 */ 00789 #define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 00790 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2) \ 00791 )? \ 00792 SET \ 00793 : \ 00794 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 00795 ) 00796 #if defined (ADC3) 00797 /** 00798 * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master 00799 * @param __HANDLE__: ADC handle 00800 * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode) 00801 */ 00802 #define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \ 00803 ( ( ((__HANDLE__)->Instance == ADC3) \ 00804 )? \ 00805 SET \ 00806 : \ 00807 ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET) \ 00808 ) 00809 #endif 00810 /** 00811 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled 00812 * @param __HANDLE__: ADC handle 00813 * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled) 00814 */ 00815 #if defined (ADC3) 00816 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 00817 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 00818 )? \ 00819 SET \ 00820 : \ 00821 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 00822 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 00823 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 00824 #else 00825 #define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \ 00826 ( ( ((__HANDLE__)->Instance == ADC1) \ 00827 )? \ 00828 SET \ 00829 : \ 00830 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 00831 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \ 00832 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) )) 00833 #endif 00834 00835 /** 00836 * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled 00837 * @param __HANDLE__: ADC handle 00838 * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled) 00839 */ 00840 #if defined (ADC3) 00841 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 00842 ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \ 00843 )? \ 00844 SET \ 00845 : \ 00846 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 00847 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 00848 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 00849 #else 00850 #define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \ 00851 ( ( ((__HANDLE__)->Instance == ADC1) \ 00852 )? \ 00853 SET \ 00854 : \ 00855 ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) || \ 00856 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) || \ 00857 ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) )) 00858 #endif 00859 00860 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE | \ 00861 ADC_CCR_PRESC | \ 00862 ADC_CCR_VBATEN | \ 00863 ADC_CCR_TSEN | \ 00864 ADC_CCR_VREFEN | \ 00865 ADC_CCR_DAMDF | \ 00866 ADC_CCR_DELAY | \ 00867 ADC_CCR_DUAL ) 00868 00869 /** 00870 * @brief Set handle instance of the ADC slave associated to the ADC master. 00871 * @param __HANDLE_MASTER__ ADC master handle. 00872 * @param __HANDLE_SLAVE__ ADC slave handle. 00873 * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 00874 * @retval None 00875 */ 00876 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 00877 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 00878 00879 00880 /** 00881 * @brief Verify the ADC instance connected to the temperature sensor. 00882 * @param __HANDLE__ ADC handle. 00883 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00884 */ 00885 #if defined(ADC3) 00886 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 00887 #else 00888 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 00889 #endif 00890 00891 /** 00892 * @brief Verify the ADC instance connected to the battery voltage VBAT. 00893 * @param __HANDLE__ ADC handle. 00894 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00895 */ 00896 #if defined(ADC3) 00897 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 00898 #else 00899 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 00900 #endif 00901 00902 /** 00903 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 00904 * @param __HANDLE__ ADC handle. 00905 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00906 */ 00907 #if defined(ADC3) 00908 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC3) 00909 #else 00910 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC2) 00911 #endif 00912 00913 /** 00914 * @brief Verify the length of scheduled injected conversions group. 00915 * @param __LENGTH__ number of programmed conversions. 00916 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 00917 */ 00918 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 00919 00920 /** 00921 * @brief Calibration factor size verification (7 bits maximum). 00922 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00923 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 00924 */ 00925 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 00926 00927 00928 /** 00929 * @brief Verify the ADC channel setting. 00930 * @param __CHANNEL__ programmed ADC channel. 00931 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00932 */ 00933 #define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0) || \ 00934 ((__CHANNEL__) == ADC_CHANNEL_1) || \ 00935 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00936 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00937 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00938 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00939 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00940 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00941 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00942 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00943 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00944 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00945 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00946 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00947 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00948 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00949 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00950 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 00951 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 00952 ((__CHANNEL__) == ADC_CHANNEL_19) || \ 00953 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 00954 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 00955 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \ 00956 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \ 00957 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) ) 00958 00959 /** 00960 * @brief Verify the ADC channel setting in differential mode for ADC1. 00961 * @param __CHANNEL__: programmed ADC channel. 00962 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00963 */ 00964 #define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00965 ((__CHANNEL__) == ADC_CHANNEL_2) ||\ 00966 ((__CHANNEL__) == ADC_CHANNEL_3) ||\ 00967 ((__CHANNEL__) == ADC_CHANNEL_4) ||\ 00968 ((__CHANNEL__) == ADC_CHANNEL_5) ||\ 00969 ((__CHANNEL__) == ADC_CHANNEL_10) ||\ 00970 ((__CHANNEL__) == ADC_CHANNEL_11) ||\ 00971 ((__CHANNEL__) == ADC_CHANNEL_12) ||\ 00972 ((__CHANNEL__) == ADC_CHANNEL_16) ||\ 00973 ((__CHANNEL__) == ADC_CHANNEL_18) ) 00974 00975 /** 00976 * @brief Verify the ADC channel setting in differential mode for ADC2. 00977 * @param __CHANNEL__: programmed ADC channel. 00978 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00979 */ 00980 #define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00981 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00982 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00983 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00984 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00985 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00986 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00987 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00988 ((__CHANNEL__) == ADC_CHANNEL_18) ) 00989 00990 /** 00991 * @brief Verify the ADC channel setting in differential mode for ADC3. 00992 * @param __CHANNEL__: programmed ADC channel. 00993 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00994 */ 00995 #define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00996 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00997 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00998 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00999 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 01000 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 01001 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 01002 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 01003 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 01004 ((__CHANNEL__) == ADC_CHANNEL_15) ) 01005 01006 /** 01007 * @brief Verify the ADC single-ended input or differential mode setting. 01008 * @param __SING_DIFF__ programmed channel setting. 01009 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 01010 */ 01011 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 01012 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 01013 01014 /** 01015 * @brief Verify the ADC offset management setting. 01016 * @param __OFFSET_NUMBER__ ADC offset management. 01017 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 01018 */ 01019 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 01020 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 01021 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 01022 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 01023 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 01024 #if defined(ADC_VER_V5_V90) 01025 /** 01026 * @brief Verify the ADC offset sign setting. 01027 * @param __OFFSET_SIGN__ ADC offset sign. 01028 * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid) 01029 */ 01030 #define IS_ADC3_OFFSET_SIGN(__OFFSET_SIGN__) (((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_NEGATIVE) || \ 01031 ((__OFFSET_SIGN__) == ADC3_OFFSET_SIGN_POSITIVE) ) 01032 #endif /* ADC_VER_V5_V90 */ 01033 /** 01034 * @brief Verify the ADC injected channel setting. 01035 * @param __CHANNEL__ programmed ADC injected channel. 01036 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01037 */ 01038 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 01039 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 01040 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 01041 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 01042 01043 /** 01044 * @brief Verify the ADC injected conversions external trigger. 01045 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 01046 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 01047 */ 01048 #if defined (HRTIM1) 01049 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 01050 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 01051 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 01052 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 01053 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 01054 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 01055 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 01056 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 01057 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 01058 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 01059 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 01060 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 01061 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 01062 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 01063 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 01064 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 01065 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2) || \ 01066 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4) || \ 01067 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ 01068 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ 01069 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ 01070 \ 01071 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 01072 #else 01073 #define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 01074 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 01075 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 01076 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 01077 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 01078 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 01079 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 01080 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 01081 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 01082 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 01083 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 01084 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 01085 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 01086 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 01087 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 01088 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 01089 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM1_OUT) || \ 01090 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM2_OUT) || \ 01091 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM3_OUT) || \ 01092 \ 01093 ((__INJTRIG__) == ADC_SOFTWARE_START) ) 01094 #endif /* HRTIM */ 01095 /** 01096 * @brief Verify the ADC edge trigger setting for injected group. 01097 * @param __EDGE__ programmed ADC edge trigger setting. 01098 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 01099 */ 01100 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 01101 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 01102 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 01103 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 01104 01105 /** 01106 * @brief Verify the ADC multimode setting. 01107 * @param __MODE__ programmed ADC multimode setting. 01108 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01109 */ 01110 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 01111 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 01112 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 01113 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 01114 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 01115 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 01116 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 01117 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 01118 01119 /** 01120 * @brief Verify the ADC dual data mode setting. 01121 * @param MODE: programmed ADC dual mode setting. 01122 * @retval SET (MODE is valid) or RESET (MODE is invalid) 01123 */ 01124 #define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED) || \ 01125 ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \ 01126 ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS) ) 01127 01128 /** 01129 * @brief Verify the ADC multimode delay setting. 01130 * @param __DELAY__ programmed ADC multimode delay setting. 01131 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 01132 */ 01133 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 01134 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 01135 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 01136 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 01137 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 01138 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 01139 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 01140 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 01141 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) ) 01142 01143 /** 01144 * @brief Verify the ADC analog watchdog setting. 01145 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 01146 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 01147 */ 01148 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 01149 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 01150 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 01151 01152 /** 01153 * @brief Verify the ADC analog watchdog mode setting. 01154 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 01155 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 01156 */ 01157 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 01158 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 01159 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 01160 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 01161 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 01162 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 01163 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 01164 01165 #if defined(ADC_VER_V5_V90) 01166 /** 01167 * @brief Verify the ADC analog watchdog filtering setting. 01168 * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting. 01169 * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid) 01170 */ 01171 #define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE_ADC3(__FILTERING_MODE__) (((__FILTERING_MODE__) == ADC3_AWD_FILTERING_NONE) || \ 01172 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_2SAMPLES) || \ 01173 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_3SAMPLES) || \ 01174 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_4SAMPLES) || \ 01175 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_5SAMPLES) || \ 01176 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_6SAMPLES) || \ 01177 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_7SAMPLES) || \ 01178 ((__FILTERING_MODE__) == ADC3_AWD_FILTERING_8SAMPLES) ) 01179 01180 #endif /* ADC_VER_V5_V90 */ 01181 01182 /** 01183 * @brief Verify the ADC conversion (regular or injected or both). 01184 * @param __CONVERSION__ ADC conversion group. 01185 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 01186 */ 01187 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 01188 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 01189 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 01190 01191 /** 01192 * @brief Verify the ADC event type. 01193 * @param __EVENT__ ADC event. 01194 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 01195 */ 01196 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 01197 ((__EVENT__) == ADC_AWD_EVENT) || \ 01198 ((__EVENT__) == ADC_AWD2_EVENT) || \ 01199 ((__EVENT__) == ADC_AWD3_EVENT) || \ 01200 ((__EVENT__) == ADC_OVR_EVENT) || \ 01201 ((__EVENT__) == ADC_JQOVF_EVENT) ) 01202 01203 /** 01204 * @brief Verify the ADC oversampling ratio. 01205 * @param RATIO: programmed ADC oversampling ratio. 01206 * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid) 01207 */ 01208 #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) >= 1UL) && ((RATIO) <= 1024UL)) 01209 01210 #if defined(ADC_VER_V5_V90) 01211 /** 01212 * @brief Verify the ADC3 oversampling ratio. 01213 * @param __RATIO__ programmed ADC oversampling ratio. 01214 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 01215 */ 01216 #define IS_ADC_OVERSAMPLING_RATIO_ADC3(__RATIO__) (((__RATIO__) == ADC3_OVERSAMPLING_RATIO_2 ) || \ 01217 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_4 ) || \ 01218 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_8 ) || \ 01219 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_16 ) || \ 01220 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_32 ) || \ 01221 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_64 ) || \ 01222 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_128 ) || \ 01223 ((__RATIO__) == ADC3_OVERSAMPLING_RATIO_256 )) 01224 #endif /* ADC_VER_V5_V90 */ 01225 01226 /** 01227 * @brief Verify the ADC oversampling shift. 01228 * @param __SHIFT__ programmed ADC oversampling shift. 01229 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 01230 */ 01231 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 01232 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 01233 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 01234 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 01235 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 01236 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 01237 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 01238 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 01239 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ) || \ 01240 ((__SHIFT__) == ADC_RIGHTBITSHIFT_9 ) || \ 01241 ((__SHIFT__) == ADC_RIGHTBITSHIFT_10 ) || \ 01242 ((__SHIFT__) == ADC_RIGHTBITSHIFT_11 )) 01243 01244 /** 01245 * @brief Verify the ADC oversampling triggered mode. 01246 * @param __MODE__ programmed ADC oversampling triggered mode. 01247 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01248 */ 01249 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 01250 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 01251 01252 /** 01253 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 01254 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 01255 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01256 */ 01257 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 01258 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 01259 01260 /** 01261 * @brief Verify the DFSDM mode configuration. 01262 * @param __HANDLE__ ADC handle. 01263 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 01264 * this reason, the input parameter is the ADC handle and not the configuration parameter 01265 * directly. 01266 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 01267 */ 01268 #if defined(DFSDM1_Channel0) 01269 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 01270 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 01271 #else 01272 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 01273 #endif 01274 01275 /** 01276 * @brief Return the DFSDM configuration mode. 01277 * @param __HANDLE__ ADC handle. 01278 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 01279 * For this reason, the input parameter is the ADC handle and not the configuration parameter 01280 * directly. 01281 * @retval DFSDM configuration mode 01282 */ 01283 #if defined(DFSDM1_Channel0) 01284 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 01285 #else 01286 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 01287 #endif 01288 01289 /** 01290 * @} 01291 */ 01292 01293 01294 /* Exported functions --------------------------------------------------------*/ 01295 /** @addtogroup ADCEx_Exported_Functions 01296 * @{ 01297 */ 01298 01299 /** @addtogroup ADCEx_Exported_Functions_Group1 01300 * @{ 01301 */ 01302 /* IO operation functions *****************************************************/ 01303 01304 /* ADC calibration */ 01305 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff); 01306 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 01307 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); 01308 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); 01309 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t *LinearCalib_Buffer); 01310 HAL_StatusTypeDef HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc); 01311 01312 01313 /* Blocking mode: Polling */ 01314 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 01315 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 01316 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 01317 01318 /* Non-blocking mode: Interruption */ 01319 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 01320 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 01321 01322 /* ADC multimode */ 01323 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 01324 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 01325 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 01326 01327 /* ADC retrieve conversion value intended to be used with polling or interruption */ 01328 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 01329 01330 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 01331 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 01332 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 01333 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 01334 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 01335 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 01336 01337 /* ADC group regular conversions stop */ 01338 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 01339 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 01340 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 01341 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 01342 01343 /** 01344 * @} 01345 */ 01346 01347 /** @addtogroup ADCEx_Exported_Functions_Group2 01348 * @{ 01349 */ 01350 /* Peripheral Control functions ***********************************************/ 01351 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, ADC_InjectionConfTypeDef *sConfigInjected); 01352 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 01353 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 01354 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 01355 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 01356 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 01357 01358 /** 01359 * @} 01360 */ 01361 01362 /** 01363 * @} 01364 */ 01365 01366 /** 01367 * @} 01368 */ 01369 01370 /** 01371 * @} 01372 */ 01373 01374 #ifdef __cplusplus 01375 } 01376 #endif 01377 01378 #endif /* STM32H7xx_HAL_ADC_EX_H */ 01379 01380
1.7.6.1