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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_CORTEX_H 00021 #define STM32H7xx_HAL_CORTEX_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 /** @addtogroup STM32H7xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup CORTEX 00035 * @{ 00036 */ 00037 /* Exported types ------------------------------------------------------------*/ 00038 /** @defgroup CORTEX_Exported_Types Cortex Exported Types 00039 * @{ 00040 */ 00041 00042 #if (__MPU_PRESENT == 1) 00043 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 00044 * @brief MPU Region initialization structure 00045 * @{ 00046 */ 00047 typedef struct 00048 { 00049 uint8_t Enable; /*!< Specifies the status of the region. 00050 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 00051 uint8_t Number; /*!< Specifies the number of the region to protect. 00052 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 00053 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 00054 uint8_t Size; /*!< Specifies the size of the region to protect. 00055 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 00056 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 00057 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00058 uint8_t TypeExtField; /*!< Specifies the TEX field level. 00059 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 00060 uint8_t AccessPermission; /*!< Specifies the region access permission type. 00061 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 00062 uint8_t DisableExec; /*!< Specifies the instruction access status. 00063 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 00064 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 00065 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 00066 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 00067 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 00068 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 00069 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 00070 }MPU_Region_InitTypeDef; 00071 /** 00072 * @} 00073 */ 00074 #endif /* __MPU_PRESENT */ 00075 00076 /** 00077 * @} 00078 */ 00079 00080 /* Exported constants --------------------------------------------------------*/ 00081 00082 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 00083 * @{ 00084 */ 00085 00086 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 00087 * @{ 00088 */ 00089 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority 00090 4 bits for subpriority */ 00091 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority 00092 3 bits for subpriority */ 00093 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority 00094 2 bits for subpriority */ 00095 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority 00096 1 bits for subpriority */ 00097 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority 00098 0 bits for subpriority */ 00099 /** 00100 * @} 00101 */ 00102 00103 /** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source 00104 * @{ 00105 */ 00106 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) 00107 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) 00108 00109 /** 00110 * @} 00111 */ 00112 00113 #if (__MPU_PRESENT == 1) 00114 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control 00115 * @{ 00116 */ 00117 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) 00118 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) 00119 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) 00120 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) 00121 /** 00122 * @} 00123 */ 00124 00125 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 00126 * @{ 00127 */ 00128 #define MPU_REGION_ENABLE ((uint8_t)0x01) 00129 #define MPU_REGION_DISABLE ((uint8_t)0x00) 00130 /** 00131 * @} 00132 */ 00133 00134 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 00135 * @{ 00136 */ 00137 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 00138 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 00139 /** 00140 * @} 00141 */ 00142 00143 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 00144 * @{ 00145 */ 00146 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 00147 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 00148 /** 00149 * @} 00150 */ 00151 00152 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 00153 * @{ 00154 */ 00155 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 00156 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 00157 /** 00158 * @} 00159 */ 00160 00161 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 00162 * @{ 00163 */ 00164 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 00165 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 00166 /** 00167 * @} 00168 */ 00169 00170 /** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels 00171 * @{ 00172 */ 00173 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 00174 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 00175 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 00176 /** 00177 * @} 00178 */ 00179 00180 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 00181 * @{ 00182 */ 00183 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 00184 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 00185 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 00186 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 00187 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 00188 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 00189 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 00190 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 00191 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 00192 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 00193 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 00194 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 00195 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 00196 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 00197 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 00198 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 00199 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 00200 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 00201 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 00202 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 00203 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 00204 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 00205 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 00206 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 00207 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 00208 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 00209 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 00210 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 00211 /** 00212 * @} 00213 */ 00214 00215 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 00216 * @{ 00217 */ 00218 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 00219 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 00220 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 00221 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 00222 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 00223 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 00224 /** 00225 * @} 00226 */ 00227 00228 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 00229 * @{ 00230 */ 00231 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 00232 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 00233 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 00234 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 00235 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 00236 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 00237 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 00238 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 00239 #if !defined(CORE_CM4) 00240 #define MPU_REGION_NUMBER8 ((uint8_t)0x08) 00241 #define MPU_REGION_NUMBER9 ((uint8_t)0x09) 00242 #define MPU_REGION_NUMBER10 ((uint8_t)0x0A) 00243 #define MPU_REGION_NUMBER11 ((uint8_t)0x0B) 00244 #define MPU_REGION_NUMBER12 ((uint8_t)0x0C) 00245 #define MPU_REGION_NUMBER13 ((uint8_t)0x0D) 00246 #define MPU_REGION_NUMBER14 ((uint8_t)0x0E) 00247 #define MPU_REGION_NUMBER15 ((uint8_t)0x0F) 00248 #endif /* !defined(CORE_CM4) */ 00249 00250 /** 00251 * @} 00252 */ 00253 #endif /* __MPU_PRESENT */ 00254 00255 /** 00256 * @} 00257 */ 00258 00259 00260 /* Exported Macros -----------------------------------------------------------*/ 00261 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 00262 * @{ 00263 */ 00264 00265 /** 00266 * @} 00267 */ 00268 00269 00270 00271 /** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier 00272 * @{ 00273 */ 00274 #define CM7_CPUID ((uint32_t)0x00000003) 00275 00276 #if defined(DUAL_CORE) 00277 #define CM4_CPUID ((uint32_t)0x00000001) 00278 #endif /*DUAL_CORE*/ 00279 /** 00280 * @} 00281 */ 00282 00283 00284 /* Exported functions --------------------------------------------------------*/ 00285 /** @addtogroup CORTEX_Exported_Functions 00286 * @{ 00287 */ 00288 00289 /** @addtogroup CORTEX_Exported_Functions_Group1 00290 * @{ 00291 */ 00292 /* Initialization and de-initialization functions *****************************/ 00293 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 00294 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 00295 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 00296 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 00297 void HAL_NVIC_SystemReset(void); 00298 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 00299 /** 00300 * @} 00301 */ 00302 00303 /** @addtogroup CORTEX_Exported_Functions_Group2 00304 * @{ 00305 */ 00306 /* Peripheral Control functions ***********************************************/ 00307 #if (__MPU_PRESENT == 1) 00308 void HAL_MPU_Enable(uint32_t MPU_Control); 00309 void HAL_MPU_Disable(void); 00310 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 00311 #endif /* __MPU_PRESENT */ 00312 uint32_t HAL_NVIC_GetPriorityGrouping(void); 00313 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 00314 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 00315 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 00316 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 00317 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 00318 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 00319 void HAL_SYSTICK_IRQHandler(void); 00320 void HAL_SYSTICK_Callback(void); 00321 uint32_t HAL_GetCurrentCPUID(void); 00322 00323 00324 /** 00325 * @} 00326 */ 00327 00328 /** 00329 * @} 00330 */ 00331 00332 /* Private types -------------------------------------------------------------*/ 00333 /* Private variables ---------------------------------------------------------*/ 00334 /* Private constants ---------------------------------------------------------*/ 00335 /* Private macros ------------------------------------------------------------*/ 00336 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 00337 * @{ 00338 */ 00339 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 00340 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 00341 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 00342 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 00343 ((GROUP) == NVIC_PRIORITYGROUP_4)) 00344 00345 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) 00346 00347 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10UL) 00348 00349 #define IS_NVIC_DEVICE_IRQ(IRQ) (((int32_t)IRQ) >= 0x00) 00350 00351 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 00352 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 00353 00354 #if (__MPU_PRESENT == 1) 00355 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 00356 ((STATE) == MPU_REGION_DISABLE)) 00357 00358 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 00359 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 00360 00361 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 00362 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 00363 00364 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 00365 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 00366 00367 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 00368 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 00369 00370 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 00371 ((TYPE) == MPU_TEX_LEVEL1) || \ 00372 ((TYPE) == MPU_TEX_LEVEL2)) 00373 00374 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 00375 ((TYPE) == MPU_REGION_PRIV_RW) || \ 00376 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 00377 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 00378 ((TYPE) == MPU_REGION_PRIV_RO) || \ 00379 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 00380 00381 #if !defined(CORE_CM4) 00382 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 00383 ((NUMBER) == MPU_REGION_NUMBER1) || \ 00384 ((NUMBER) == MPU_REGION_NUMBER2) || \ 00385 ((NUMBER) == MPU_REGION_NUMBER3) || \ 00386 ((NUMBER) == MPU_REGION_NUMBER4) || \ 00387 ((NUMBER) == MPU_REGION_NUMBER5) || \ 00388 ((NUMBER) == MPU_REGION_NUMBER6) || \ 00389 ((NUMBER) == MPU_REGION_NUMBER7) || \ 00390 ((NUMBER) == MPU_REGION_NUMBER8) || \ 00391 ((NUMBER) == MPU_REGION_NUMBER9) || \ 00392 ((NUMBER) == MPU_REGION_NUMBER10) || \ 00393 ((NUMBER) == MPU_REGION_NUMBER11) || \ 00394 ((NUMBER) == MPU_REGION_NUMBER12) || \ 00395 ((NUMBER) == MPU_REGION_NUMBER13) || \ 00396 ((NUMBER) == MPU_REGION_NUMBER14) || \ 00397 ((NUMBER) == MPU_REGION_NUMBER15)) 00398 #else 00399 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 00400 ((NUMBER) == MPU_REGION_NUMBER1) || \ 00401 ((NUMBER) == MPU_REGION_NUMBER2) || \ 00402 ((NUMBER) == MPU_REGION_NUMBER3) || \ 00403 ((NUMBER) == MPU_REGION_NUMBER4) || \ 00404 ((NUMBER) == MPU_REGION_NUMBER5) || \ 00405 ((NUMBER) == MPU_REGION_NUMBER6) || \ 00406 ((NUMBER) == MPU_REGION_NUMBER7)) 00407 #endif /* !defined(CORE_CM4) */ 00408 00409 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 00410 ((SIZE) == MPU_REGION_SIZE_64B) || \ 00411 ((SIZE) == MPU_REGION_SIZE_128B) || \ 00412 ((SIZE) == MPU_REGION_SIZE_256B) || \ 00413 ((SIZE) == MPU_REGION_SIZE_512B) || \ 00414 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 00415 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 00416 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 00417 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 00418 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 00419 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 00420 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 00421 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 00422 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 00423 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 00424 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 00425 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 00426 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 00427 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 00428 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 00429 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 00430 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 00431 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 00432 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 00433 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 00434 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 00435 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 00436 ((SIZE) == MPU_REGION_SIZE_4GB)) 00437 00438 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 00439 #endif /* __MPU_PRESENT */ 00440 00441 /** 00442 * @} 00443 */ 00444 00445 /** 00446 * @} 00447 */ 00448 00449 /** 00450 * @} 00451 */ 00452 00453 #ifdef __cplusplus 00454 } 00455 #endif 00456 00457 #endif /* STM32H7xx_HAL_CORTEX_H */ 00458 00459
1.7.6.1