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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_dac.h 00004 * @author MCD Application Team 00005 * @brief Header file of DAC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_DAC_H 00021 #define STM32H7xx_HAL_DAC_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /** @addtogroup STM32H7xx_HAL_Driver 00028 * @{ 00029 */ 00030 00031 /* Includes ------------------------------------------------------------------*/ 00032 #include "stm32h7xx_hal_def.h" 00033 00034 #if defined(DAC1) || defined(DAC2) 00035 00036 /** @addtogroup DAC 00037 * @{ 00038 */ 00039 00040 /* Exported types ------------------------------------------------------------*/ 00041 00042 /** @defgroup DAC_Exported_Types DAC Exported Types 00043 * @{ 00044 */ 00045 00046 /** 00047 * @brief HAL State structures definition 00048 */ 00049 typedef enum 00050 { 00051 HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */ 00052 HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */ 00053 HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */ 00054 HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */ 00055 HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */ 00056 00057 } HAL_DAC_StateTypeDef; 00058 00059 /** 00060 * @brief DAC handle Structure definition 00061 */ 00062 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00063 typedef struct __DAC_HandleTypeDef 00064 #else 00065 typedef struct 00066 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00067 { 00068 DAC_TypeDef *Instance; /*!< Register base address */ 00069 00070 __IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */ 00071 00072 HAL_LockTypeDef Lock; /*!< DAC locking object */ 00073 00074 DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ 00075 00076 DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ 00077 00078 __IO uint32_t ErrorCode; /*!< DAC Error code */ 00079 00080 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00081 void (* ConvCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 00082 void (* ConvHalfCpltCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 00083 void (* ErrorCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 00084 void (* DMAUnderrunCallbackCh1) (struct __DAC_HandleTypeDef *hdac); 00085 00086 void (* ConvCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 00087 void (* ConvHalfCpltCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 00088 void (* ErrorCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 00089 void (* DMAUnderrunCallbackCh2) (struct __DAC_HandleTypeDef *hdac); 00090 00091 00092 void (* MspInitCallback) (struct __DAC_HandleTypeDef *hdac); 00093 void (* MspDeInitCallback) (struct __DAC_HandleTypeDef *hdac); 00094 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00095 00096 } DAC_HandleTypeDef; 00097 00098 /** 00099 * @brief DAC Configuration sample and hold Channel structure definition 00100 */ 00101 typedef struct 00102 { 00103 uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel. 00104 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 00105 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 00106 00107 uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel 00108 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 00109 This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */ 00110 00111 uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel 00112 This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE. 00113 This parameter must be a number between Min_Data = 0 and Max_Data = 255 */ 00114 } DAC_SampleAndHoldConfTypeDef; 00115 00116 /** 00117 * @brief DAC Configuration regular Channel structure definition 00118 */ 00119 typedef struct 00120 { 00121 uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode. 00122 This parameter can be a value of @ref DAC_SampleAndHold */ 00123 00124 uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. 00125 This parameter can be a value of @ref DAC_trigger_selection */ 00126 00127 uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. 00128 This parameter can be a value of @ref DAC_output_buffer */ 00129 00130 uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral . 00131 This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */ 00132 00133 uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode 00134 This parameter must be a value of @ref DAC_UserTrimming 00135 DAC_UserTrimming is either factory or user trimming */ 00136 00137 uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value 00138 i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER. 00139 This parameter must be a number between Min_Data = 1 and Max_Data = 31 */ 00140 DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */ 00141 } DAC_ChannelConfTypeDef; 00142 00143 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00144 /** 00145 * @brief HAL DAC Callback ID enumeration definition 00146 */ 00147 typedef enum 00148 { 00149 HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */ 00150 HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */ 00151 HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */ 00152 HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */ 00153 00154 HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */ 00155 HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */ 00156 HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */ 00157 HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */ 00158 00159 HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */ 00160 HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */ 00161 HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */ 00162 } HAL_DAC_CallbackIDTypeDef; 00163 00164 /** 00165 * @brief HAL DAC Callback pointer definition 00166 */ 00167 typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); 00168 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00169 00170 /** 00171 * @} 00172 */ 00173 00174 /* Exported constants --------------------------------------------------------*/ 00175 00176 /** @defgroup DAC_Exported_Constants DAC Exported Constants 00177 * @{ 00178 */ 00179 00180 /** @defgroup DAC_Error_Code DAC Error Code 00181 * @{ 00182 */ 00183 #define HAL_DAC_ERROR_NONE 0x00U /*!< No error */ 00184 #define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */ 00185 #define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */ 00186 #define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */ 00187 #define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */ 00188 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00189 #define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */ 00190 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00191 00192 /** 00193 * @} 00194 */ 00195 00196 /** @defgroup DAC_trigger_selection DAC trigger selection 00197 * @{ 00198 */ 00199 #define DAC_TRIGGER_NONE 0x00000000U /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */ 00200 #define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */ 00201 #define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */ 00202 #define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ 00203 #define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ 00204 #define DAC_TRIGGER_T5_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ 00205 #define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ 00206 #define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ 00207 #define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */ 00208 #define DAC_TRIGGER_T15_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */ 00209 #if defined(HRTIM1) 00210 #define DAC_TRIGGER_HR1_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */ 00211 #define DAC_TRIGGER_HR1_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */ 00212 #endif 00213 #define DAC_TRIGGER_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */ 00214 #define DAC_TRIGGER_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */ 00215 #define DAC_TRIGGER_EXT_IT9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ 00216 #if defined(TIM23) 00217 #define DAC_TRIGGER_T23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */ 00218 #endif 00219 #if defined(TIM24) 00220 #define DAC_TRIGGER_T24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */ 00221 #endif 00222 #if defined(DAC2) 00223 #define DAC_TRIGGER_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */ 00224 #endif 00225 00226 /** 00227 * @} 00228 */ 00229 00230 /** @defgroup DAC_output_buffer DAC output buffer 00231 * @{ 00232 */ 00233 #define DAC_OUTPUTBUFFER_ENABLE 0x00000000U 00234 #define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1) 00235 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup DAC_Channel_selection DAC Channel selection 00241 * @{ 00242 */ 00243 #define DAC_CHANNEL_1 0x00000000U 00244 00245 #define DAC_CHANNEL_2 0x00000010U 00246 00247 /** 00248 * @} 00249 */ 00250 00251 /** @defgroup DAC_data_alignment DAC data alignment 00252 * @{ 00253 */ 00254 #define DAC_ALIGN_12B_R 0x00000000U 00255 #define DAC_ALIGN_12B_L 0x00000004U 00256 #define DAC_ALIGN_8B_R 0x00000008U 00257 00258 /** 00259 * @} 00260 */ 00261 00262 /** @defgroup DAC_flags_definition DAC flags definition 00263 * @{ 00264 */ 00265 #define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) 00266 00267 #define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) 00268 00269 00270 /** 00271 * @} 00272 */ 00273 00274 /** @defgroup DAC_IT_definition DAC IT definition 00275 * @{ 00276 */ 00277 #define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1) 00278 00279 #define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2) 00280 00281 00282 /** 00283 * @} 00284 */ 00285 00286 /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral 00287 * @{ 00288 */ 00289 #define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) 00290 #define DAC_CHIPCONNECT_INTERNAL (1UL << 1) 00291 #define DAC_CHIPCONNECT_BOTH (1UL << 2) 00292 00293 /** 00294 * @} 00295 */ 00296 00297 /** @defgroup DAC_UserTrimming DAC User Trimming 00298 * @{ 00299 */ 00300 #define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */ 00301 #define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */ 00302 /** 00303 * @} 00304 */ 00305 00306 /** @defgroup DAC_SampleAndHold DAC power mode 00307 * @{ 00308 */ 00309 #define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL) 00310 #define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2) 00311 00312 /** 00313 * @} 00314 */ 00315 /** 00316 * @} 00317 */ 00318 00319 /* Exported macro ------------------------------------------------------------*/ 00320 00321 /** @defgroup DAC_Exported_Macros DAC Exported Macros 00322 * @{ 00323 */ 00324 00325 /** @brief Reset DAC handle state. 00326 * @param __HANDLE__ specifies the DAC handle. 00327 * @retval None 00328 */ 00329 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00330 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \ 00331 (__HANDLE__)->State = HAL_DAC_STATE_RESET; \ 00332 (__HANDLE__)->MspInitCallback = NULL; \ 00333 (__HANDLE__)->MspDeInitCallback = NULL; \ 00334 } while(0) 00335 #else 00336 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) 00337 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00338 00339 /** @brief Enable the DAC channel. 00340 * @param __HANDLE__ specifies the DAC handle. 00341 * @param __DAC_Channel__ specifies the DAC channel 00342 * @retval None 00343 */ 00344 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ 00345 ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 00346 00347 /** @brief Disable the DAC channel. 00348 * @param __HANDLE__ specifies the DAC handle 00349 * @param __DAC_Channel__ specifies the DAC channel. 00350 * @retval None 00351 */ 00352 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ 00353 ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL))) 00354 00355 /** @brief Set DHR12R1 alignment. 00356 * @param __ALIGNMENT__ specifies the DAC alignment 00357 * @retval None 00358 */ 00359 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__)) 00360 00361 00362 /** @brief Set DHR12R2 alignment. 00363 * @param __ALIGNMENT__ specifies the DAC alignment 00364 * @retval None 00365 */ 00366 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__)) 00367 00368 00369 /** @brief Set DHR12RD alignment. 00370 * @param __ALIGNMENT__ specifies the DAC alignment 00371 * @retval None 00372 */ 00373 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__)) 00374 00375 /** @brief Enable the DAC interrupt. 00376 * @param __HANDLE__ specifies the DAC handle 00377 * @param __INTERRUPT__ specifies the DAC interrupt. 00378 * This parameter can be any combination of the following values: 00379 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 00380 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 00381 * @retval None 00382 */ 00383 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) 00384 00385 /** @brief Disable the DAC interrupt. 00386 * @param __HANDLE__ specifies the DAC handle 00387 * @param __INTERRUPT__ specifies the DAC interrupt. 00388 * This parameter can be any combination of the following values: 00389 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 00390 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 00391 * @retval None 00392 */ 00393 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) 00394 00395 /** @brief Check whether the specified DAC interrupt source is enabled or not. 00396 * @param __HANDLE__ DAC handle 00397 * @param __INTERRUPT__ DAC interrupt source to check 00398 * This parameter can be any combination of the following values: 00399 * @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt 00400 * @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt 00401 * @retval State of interruption (SET or RESET) 00402 */ 00403 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\ 00404 & (__INTERRUPT__)) == (__INTERRUPT__)) 00405 00406 /** @brief Get the selected DAC's flag status. 00407 * @param __HANDLE__ specifies the DAC handle. 00408 * @param __FLAG__ specifies the DAC flag to get. 00409 * This parameter can be any combination of the following values: 00410 * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag 00411 * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag 00412 * @retval None 00413 */ 00414 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 00415 00416 /** @brief Clear the DAC's flag. 00417 * @param __HANDLE__ specifies the DAC handle. 00418 * @param __FLAG__ specifies the DAC flag to clear. 00419 * This parameter can be any combination of the following values: 00420 * @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag 00421 * @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag 00422 * @retval None 00423 */ 00424 #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) 00425 00426 /** 00427 * @} 00428 */ 00429 00430 /* Private macro -------------------------------------------------------------*/ 00431 00432 /** @defgroup DAC_Private_Macros DAC Private Macros 00433 * @{ 00434 */ 00435 #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \ 00436 ((STATE) == DAC_OUTPUTBUFFER_DISABLE)) 00437 00438 #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ 00439 ((CHANNEL) == DAC_CHANNEL_2)) 00440 00441 #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \ 00442 ((ALIGN) == DAC_ALIGN_12B_L) || \ 00443 ((ALIGN) == DAC_ALIGN_8B_R)) 00444 00445 #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL) 00446 00447 #define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL) 00448 00449 /** 00450 * @} 00451 */ 00452 00453 /* Include DAC HAL Extended module */ 00454 #include "stm32h7xx_hal_dac_ex.h" 00455 00456 /* Exported functions --------------------------------------------------------*/ 00457 00458 /** @addtogroup DAC_Exported_Functions 00459 * @{ 00460 */ 00461 00462 /** @addtogroup DAC_Exported_Functions_Group1 00463 * @{ 00464 */ 00465 /* Initialization and de-initialization functions *****************************/ 00466 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac); 00467 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac); 00468 void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac); 00469 void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac); 00470 00471 /** 00472 * @} 00473 */ 00474 00475 /** @addtogroup DAC_Exported_Functions_Group2 00476 * @{ 00477 */ 00478 /* IO operation functions *****************************************************/ 00479 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel); 00480 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel); 00481 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length, 00482 uint32_t Alignment); 00483 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel); 00484 void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac); 00485 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); 00486 00487 void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac); 00488 void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac); 00489 void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); 00490 void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); 00491 00492 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00493 /* DAC callback registering/unregistering */ 00494 HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, 00495 pDAC_CallbackTypeDef pCallback); 00496 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID); 00497 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00498 00499 /** 00500 * @} 00501 */ 00502 00503 /** @addtogroup DAC_Exported_Functions_Group3 00504 * @{ 00505 */ 00506 /* Peripheral Control functions ***********************************************/ 00507 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel); 00508 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel); 00509 /** 00510 * @} 00511 */ 00512 00513 /** @addtogroup DAC_Exported_Functions_Group4 00514 * @{ 00515 */ 00516 /* Peripheral State and Error functions ***************************************/ 00517 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac); 00518 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); 00519 00520 /** 00521 * @} 00522 */ 00523 00524 /** 00525 * @} 00526 */ 00527 00528 /** @defgroup DAC_Private_Functions DAC Private Functions 00529 * @{ 00530 */ 00531 void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); 00532 void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); 00533 void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 00534 /** 00535 * @} 00536 */ 00537 00538 /** 00539 * @} 00540 */ 00541 00542 #endif /* DAC1 || DAC2 */ 00543 00544 /** 00545 * @} 00546 */ 00547 00548 #ifdef __cplusplus 00549 } 00550 #endif 00551 00552 00553 #endif /* STM32H7xx_HAL_DAC_H */ 00554
1.7.6.1