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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_dma2d.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA2D HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_DMA2D_H 00021 #define STM32H7xx_HAL_DMA2D_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 /** @addtogroup STM32H7xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (DMA2D) 00035 00036 /** @addtogroup DMA2D DMA2D 00037 * @brief DMA2D HAL module driver 00038 * @{ 00039 */ 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 00043 * @{ 00044 */ 00045 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 00046 00047 /** 00048 * @brief DMA2D CLUT Structure definition 00049 */ 00050 typedef struct 00051 { 00052 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 00053 00054 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 00055 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 00056 00057 uint32_t Size; /*!< Configures the DMA2D CLUT size. 00058 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 00059 } DMA2D_CLUTCfgTypeDef; 00060 00061 /** 00062 * @brief DMA2D Init structure definition 00063 */ 00064 typedef struct 00065 { 00066 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 00067 This parameter can be one value of @ref DMA2D_Mode. */ 00068 00069 uint32_t ColorMode; /*!< Configures the color format of the output image. 00070 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 00071 00072 uint32_t OutputOffset; /*!< Specifies the Offset value. 00073 This parameter must be a number between 00074 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00075 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 00076 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 00077 00078 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 00079 for the output pixel format converter. 00080 This parameter can be one value of @ref DMA2D_RB_Swap. */ 00081 00082 00083 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 00084 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 00085 00086 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. 00087 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 00088 00089 } DMA2D_InitTypeDef; 00090 00091 00092 /** 00093 * @brief DMA2D Layer structure definition 00094 */ 00095 typedef struct 00096 { 00097 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 00098 This parameter must be a number between 00099 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00100 00101 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 00102 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 00103 00104 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 00105 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 00106 00107 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 00108 in case of A8 or A4 color mode. 00109 This parameter must be a number between Min_Data = 0x00 00110 and Max_Data = 0xFF except for the color modes detailed below. 00111 @note In case of A8 or A4 color mode (ARGB), 00112 this parameter must be a number between 00113 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 00114 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 00115 - InputAlpha[16:23] is the red value RED[0:7] 00116 - InputAlpha[8:15] is the green value GREEN[0:7] 00117 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 00118 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 00119 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 00120 00121 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 00122 This parameter can be one value of @ref DMA2D_RB_Swap. */ 00123 00124 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode 00125 This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */ 00126 00127 } DMA2D_LayerCfgTypeDef; 00128 00129 /** 00130 * @brief HAL DMA2D State structures definition 00131 */ 00132 typedef enum 00133 { 00134 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 00135 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00136 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00137 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00138 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 00139 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 00140 } HAL_DMA2D_StateTypeDef; 00141 00142 /** 00143 * @brief DMA2D handle Structure definition 00144 */ 00145 typedef struct __DMA2D_HandleTypeDef 00146 { 00147 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 00148 00149 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 00150 00151 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 00152 00153 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 00154 00155 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00156 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 00157 00158 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 00159 00160 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 00161 00162 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 00163 00164 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 00165 00166 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 00167 00168 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 00169 00170 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 00171 00172 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 00173 } DMA2D_HandleTypeDef; 00174 00175 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00176 /** 00177 * @brief HAL DMA2D Callback pointer definition 00178 */ 00179 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 00180 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00181 /** 00182 * @} 00183 */ 00184 00185 /* Exported constants --------------------------------------------------------*/ 00186 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 00187 * @{ 00188 */ 00189 00190 /** @defgroup DMA2D_Error_Code DMA2D Error Code 00191 * @{ 00192 */ 00193 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 00194 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 00195 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 00196 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 00197 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00198 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00199 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 00200 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 00201 00202 /** 00203 * @} 00204 */ 00205 00206 /** @defgroup DMA2D_Mode DMA2D Mode 00207 * @{ 00208 */ 00209 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 00210 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 00211 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 00212 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 00213 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 00214 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 00215 /** 00216 * @} 00217 */ 00218 00219 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 00220 * @{ 00221 */ 00222 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 00223 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 00224 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 00225 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 00226 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 00232 * @{ 00233 */ 00234 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 00235 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 00236 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 00237 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 00238 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 00239 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 00240 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 00241 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 00242 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 00243 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 00244 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 00245 #define DMA2D_INPUT_YCBCR 0x0000000BU /*!< YCbCr color mode */ 00246 /** 00247 * @} 00248 */ 00249 00250 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 00251 * @{ 00252 */ 00253 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 00254 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 00255 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 00256 with original alpha channel value */ 00257 /** 00258 * @} 00259 */ 00260 00261 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 00262 * @{ 00263 */ 00264 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 00265 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 00266 /** 00267 * @} 00268 */ 00269 00270 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 00271 * @{ 00272 */ 00273 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 00274 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 00275 /** 00276 * @} 00277 */ 00278 00279 00280 00281 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 00282 * @{ 00283 */ 00284 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 00285 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 00286 /** 00287 * @} 00288 */ 00289 00290 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 00291 * @{ 00292 */ 00293 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 00294 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 00295 /** 00296 * @} 00297 */ 00298 00299 /** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling 00300 * @{ 00301 */ 00302 #define DMA2D_NO_CSS 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ 00303 #define DMA2D_CSS_422 0x00000001U /*!< chroma sub-sampling 4:2:2 */ 00304 #define DMA2D_CSS_420 0x00000002U /*!< chroma sub-sampling 4:2:0 */ 00305 /** 00306 * @} 00307 */ 00308 00309 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 00310 * @{ 00311 */ 00312 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 00313 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 00314 /** 00315 * @} 00316 */ 00317 00318 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 00319 * @{ 00320 */ 00321 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 00322 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 00323 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 00324 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 00325 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 00326 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 00327 /** 00328 * @} 00329 */ 00330 00331 /** @defgroup DMA2D_Flags DMA2D Flags 00332 * @{ 00333 */ 00334 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 00335 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 00336 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 00337 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 00338 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 00339 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 00340 /** 00341 * @} 00342 */ 00343 00344 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00345 /** 00346 * @brief HAL DMA2D common Callback ID enumeration definition 00347 */ 00348 typedef enum 00349 { 00350 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 00351 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 00352 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 00353 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 00354 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 00355 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 00356 } HAL_DMA2D_CallbackIDTypeDef; 00357 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00358 00359 00360 /** 00361 * @} 00362 */ 00363 /* Exported macros ------------------------------------------------------------*/ 00364 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 00365 * @{ 00366 */ 00367 00368 /** @brief Reset DMA2D handle state 00369 * @param __HANDLE__ specifies the DMA2D handle. 00370 * @retval None 00371 */ 00372 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00373 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00374 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 00375 (__HANDLE__)->MspInitCallback = NULL; \ 00376 (__HANDLE__)->MspDeInitCallback = NULL; \ 00377 }while(0) 00378 #else 00379 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 00380 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00381 00382 00383 /** 00384 * @brief Enable the DMA2D. 00385 * @param __HANDLE__ DMA2D handle 00386 * @retval None. 00387 */ 00388 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 00389 00390 00391 /* Interrupt & Flag management */ 00392 /** 00393 * @brief Get the DMA2D pending flags. 00394 * @param __HANDLE__ DMA2D handle 00395 * @param __FLAG__ flag to check. 00396 * This parameter can be any combination of the following values: 00397 * @arg DMA2D_FLAG_CE: Configuration error flag 00398 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00399 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00400 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00401 * @arg DMA2D_FLAG_TC: Transfer complete flag 00402 * @arg DMA2D_FLAG_TE: Transfer error flag 00403 * @retval The state of FLAG. 00404 */ 00405 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 00406 00407 /** 00408 * @brief Clear the DMA2D pending flags. 00409 * @param __HANDLE__ DMA2D handle 00410 * @param __FLAG__ specifies the flag to clear. 00411 * This parameter can be any combination of the following values: 00412 * @arg DMA2D_FLAG_CE: Configuration error flag 00413 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00414 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00415 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00416 * @arg DMA2D_FLAG_TC: Transfer complete flag 00417 * @arg DMA2D_FLAG_TE: Transfer error flag 00418 * @retval None 00419 */ 00420 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 00421 00422 /** 00423 * @brief Enable the specified DMA2D interrupts. 00424 * @param __HANDLE__ DMA2D handle 00425 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 00426 * This parameter can be any combination of the following values: 00427 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00428 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00429 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00430 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00431 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00432 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00433 * @retval None 00434 */ 00435 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 00436 00437 /** 00438 * @brief Disable the specified DMA2D interrupts. 00439 * @param __HANDLE__ DMA2D handle 00440 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 00441 * This parameter can be any combination of the following values: 00442 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00443 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00444 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00445 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00446 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00447 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00448 * @retval None 00449 */ 00450 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 00451 00452 /** 00453 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 00454 * @param __HANDLE__ DMA2D handle 00455 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 00456 * This parameter can be one of the following values: 00457 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00458 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00459 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00460 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00461 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00462 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00463 * @retval The state of INTERRUPT source. 00464 */ 00465 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 00466 00467 /** 00468 * @} 00469 */ 00470 00471 /* Exported functions --------------------------------------------------------*/ 00472 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 00473 * @{ 00474 */ 00475 00476 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 00477 * @{ 00478 */ 00479 00480 /* Initialization and de-initialization functions *******************************/ 00481 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 00482 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 00483 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 00484 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 00485 /* Callbacks Register/UnRegister functions ***********************************/ 00486 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00487 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 00488 pDMA2D_CallbackTypeDef pCallback); 00489 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 00490 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00491 00492 /** 00493 * @} 00494 */ 00495 00496 00497 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 00498 * @{ 00499 */ 00500 00501 /* IO operation functions *******************************************************/ 00502 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 00503 uint32_t Height); 00504 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 00505 uint32_t DstAddress, uint32_t Width, uint32_t Height); 00506 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 00507 uint32_t Height); 00508 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 00509 uint32_t DstAddress, uint32_t Width, uint32_t Height); 00510 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 00511 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 00512 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 00513 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00514 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 00515 uint32_t LayerIdx); 00516 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 00517 uint32_t LayerIdx); 00518 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00519 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00520 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00521 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00522 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00523 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 00524 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 00525 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 00526 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 00527 00528 /** 00529 * @} 00530 */ 00531 00532 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 00533 * @{ 00534 */ 00535 00536 /* Peripheral Control functions *************************************************/ 00537 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00538 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00539 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 00540 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00541 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00542 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 00543 00544 /** 00545 * @} 00546 */ 00547 00548 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 00549 * @{ 00550 */ 00551 00552 /* Peripheral State functions ***************************************************/ 00553 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 00554 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 00555 00556 /** 00557 * @} 00558 */ 00559 00560 /** 00561 * @} 00562 */ 00563 00564 /* Private constants ---------------------------------------------------------*/ 00565 00566 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 00567 * @{ 00568 */ 00569 00570 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 00571 * @{ 00572 */ 00573 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 00574 /** 00575 * @} 00576 */ 00577 00578 /** @defgroup DMA2D_Color_Value DMA2D Color Value 00579 * @{ 00580 */ 00581 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 00582 /** 00583 * @} 00584 */ 00585 00586 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 00587 * @{ 00588 */ 00589 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 00590 /** 00591 * @} 00592 */ 00593 00594 /** @defgroup DMA2D_Layers DMA2D Layers 00595 * @{ 00596 */ 00597 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 00598 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 00599 /** 00600 * @} 00601 */ 00602 00603 /** @defgroup DMA2D_Offset DMA2D Offset 00604 * @{ 00605 */ 00606 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 00607 /** 00608 * @} 00609 */ 00610 00611 /** @defgroup DMA2D_Size DMA2D Size 00612 * @{ 00613 */ 00614 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 00615 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 00616 /** 00617 * @} 00618 */ 00619 00620 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 00621 * @{ 00622 */ 00623 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 00624 /** 00625 * @} 00626 */ 00627 00628 /** 00629 * @} 00630 */ 00631 00632 00633 /* Private macros ------------------------------------------------------------*/ 00634 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 00635 * @{ 00636 */ 00637 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 00638 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 00639 00640 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 00641 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 00642 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 00643 00644 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 00645 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 00646 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 00647 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 00648 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 00649 00650 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 00651 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 00652 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 00653 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 00654 00655 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 00656 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 00657 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 00658 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 00659 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 00660 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 00661 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 00662 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 00663 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 00664 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 00665 ((INPUT_CM) == DMA2D_INPUT_A4) || \ 00666 ((INPUT_CM) == DMA2D_INPUT_YCBCR)) 00667 00668 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 00669 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 00670 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 00671 00672 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 00673 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 00674 00675 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 00676 ((RB_Swap) == DMA2D_RB_SWAP)) 00677 00678 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 00679 ((LOM) == DMA2D_LOM_BYTES)) 00680 00681 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 00682 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 00683 00684 #define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS) || \ 00685 ((CSS) == DMA2D_CSS_422) || \ 00686 ((CSS) == DMA2D_CSS_420)) 00687 00688 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 00689 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 00690 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 00691 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 00692 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 00693 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 00694 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 00695 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 00696 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 00697 /** 00698 * @} 00699 */ 00700 00701 /** 00702 * @} 00703 */ 00704 00705 #endif /* defined (DMA2D) */ 00706 00707 /** 00708 * @} 00709 */ 00710 00711 #ifdef __cplusplus 00712 } 00713 #endif 00714 00715 #endif /* STM32H7xx_HAL_DMA2D_H */
1.7.6.1