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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_hrtim.h 00004 * @author MCD Application Team 00005 * @brief Header file of HRTIM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_HRTIM_H 00021 #define STM32H7xx_HAL_HRTIM_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 #if defined(HRTIM1) 00031 /** @addtogroup STM32H7xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup HRTIM HRTIM 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants 00041 * @{ 00042 */ 00043 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer 00044 * @{ 00045 */ 00046 #define MAX_HRTIM_TIMER 6U 00047 /** 00048 * @} 00049 */ 00050 /** 00051 * @} 00052 */ 00053 00054 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types 00055 * @{ 00056 */ 00057 00058 /** 00059 * @brief HRTIM Configuration Structure definition - Time base related parameters 00060 */ 00061 typedef struct 00062 { 00063 uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance. 00064 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */ 00065 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals. 00066 The HRTIM instance can be configured to act as a slave (waiting for a trigger 00067 to be synchronized) or a master (generating a synchronization signal) or both. 00068 This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/ 00069 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when 00070 the HRTIM instance is configured as a slave). 00071 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */ 00072 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs 00073 (significant only when the HRTIM instance is configured as a master). 00074 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */ 00075 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization 00076 outputs (significant only when the HRTIM instance is configured as a master). 00077 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */ 00078 } HRTIM_InitTypeDef; 00079 00080 /** 00081 * @brief HAL State structures definition 00082 */ 00083 typedef enum 00084 { 00085 HAL_HRTIM_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ 00086 HAL_HRTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00087 HAL_HRTIM_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 00088 HAL_HRTIM_STATE_TIMEOUT = 0x06U, /*!< Timeout state */ 00089 HAL_HRTIM_STATE_ERROR = 0x07U, /*!< Error state */ 00090 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 00091 HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U /*!< Invalid Callback error */ 00092 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 00093 } HAL_HRTIM_StateTypeDef; 00094 00095 /** 00096 * @brief HRTIM Timer Structure definition 00097 */ 00098 typedef struct 00099 { 00100 uint32_t CaptureTrigger1; /*!< Event(s) triggering capture unit 1. 00101 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 00102 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 00103 uint32_t CaptureTrigger2; /*!< Event(s) triggering capture unit 2. 00104 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels. 00105 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */ 00106 uint32_t InterruptRequests; /*!< Interrupts requests enabled for the timer. */ 00107 uint32_t DMARequests; /*!< DMA requests enabled for the timer. */ 00108 uint32_t DMASrcAddress; /*!< Address of the source address of the DMA transfer. */ 00109 uint32_t DMADstAddress; /*!< Address of the destination address of the DMA transfer. */ 00110 uint32_t DMASize; /*!< Size of the DMA transfer */ 00111 } HRTIM_TimerParamTypeDef; 00112 00113 /** 00114 * @brief HRTIM Handle Structure definition 00115 */ 00116 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 00117 typedef struct __HRTIM_HandleTypeDef 00118 #else 00119 typedef struct 00120 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 00121 { 00122 HRTIM_TypeDef * Instance; /*!< Register base address */ 00123 00124 HRTIM_InitTypeDef Init; /*!< HRTIM required parameters */ 00125 00126 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */ 00127 00128 HAL_LockTypeDef Lock; /*!< Locking object */ 00129 00130 __IO HAL_HRTIM_StateTypeDef State; /*!< HRTIM communication state */ 00131 00132 DMA_HandleTypeDef * hdmaMaster; /*!< Master timer DMA handle parameters */ 00133 DMA_HandleTypeDef * hdmaTimerA; /*!< Timer A DMA handle parameters */ 00134 DMA_HandleTypeDef * hdmaTimerB; /*!< Timer B DMA handle parameters */ 00135 DMA_HandleTypeDef * hdmaTimerC; /*!< Timer C DMA handle parameters */ 00136 DMA_HandleTypeDef * hdmaTimerD; /*!< Timer D DMA handle parameters */ 00137 DMA_HandleTypeDef * hdmaTimerE; /*!< Timer E DMA handle parameters */ 00138 00139 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 00140 void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 1 interrupt callback function pointer */ 00141 void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 2 interrupt callback function pointer */ 00142 void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 3 interrupt callback function pointer */ 00143 void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 4 interrupt callback function pointer */ 00144 void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Fault 5 interrupt callback function pointer */ 00145 void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< System fault interrupt callback function pointer */ 00146 void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Burst mode period interrupt callback function pointer */ 00147 void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< Sync Input interrupt callback function pointer */ 00148 void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< DMA error callback function pointer */ 00149 00150 void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Update interrupt callback function pointer */ 00151 void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Repetition interrupt callback function pointer */ 00152 void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 1 match interrupt callback function pointer */ 00153 void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 2 match interrupt callback function pointer */ 00154 void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 3 match interrupt callback function pointer */ 00155 void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Compare 4 match interrupt callback function pointer */ 00156 void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 1 interrupts callback function pointer */ 00157 void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Capture 2 interrupts callback function pointer */ 00158 void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer */ 00159 void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x counter reset/roll-over interrupt callback function pointer */ 00160 void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 set interrupt callback function pointer */ 00161 void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 1 reset interrupt callback function pointer */ 00162 void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 set interrupt callback function pointer */ 00163 void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x output 2 reset interrupt callback function pointer */ 00164 void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Burst DMA completed interrupt callback function pointer */ 00165 00166 void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 00167 void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM MspInit callback function pointer */ 00168 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 00169 } HRTIM_HandleTypeDef; 00170 00171 /** 00172 * @brief Simple output compare mode configuration definition 00173 */ 00174 typedef struct 00175 { 00176 uint32_t Period; /*!< Specifies the timer period. 00177 The period value must be above 3 periods of the fHRTIM clock. 00178 Maximum value is = 0xFFDFU */ 00179 uint32_t RepetitionCounter; /*!< Specifies the timer repetition period. 00180 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 00181 uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio. 00182 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */ 00183 uint32_t Mode; /*!< Specifies the counter operating mode. 00184 This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */ 00185 } HRTIM_TimeBaseCfgTypeDef; 00186 00187 /** 00188 * @brief Simple output compare mode configuration definition 00189 */ 00190 typedef struct 00191 { 00192 uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive). 00193 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */ 00194 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 00195 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 00196 uint32_t Polarity; /*!< Specifies the output polarity. 00197 This parameter can be any value of @ref HRTIM_Output_Polarity */ 00198 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 00199 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 00200 } HRTIM_SimpleOCChannelCfgTypeDef; 00201 00202 /** 00203 * @brief Simple PWM output mode configuration definition 00204 */ 00205 typedef struct 00206 { 00207 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 00208 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 00209 uint32_t Polarity; /*!< Specifies the output polarity. 00210 This parameter can be any value of @ref HRTIM_Output_Polarity */ 00211 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 00212 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 00213 } HRTIM_SimplePWMChannelCfgTypeDef; 00214 00215 /** 00216 * @brief Simple capture mode configuration definition 00217 */ 00218 typedef struct 00219 { 00220 uint32_t Event; /*!< Specifies the external event triggering the capture. 00221 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 00222 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 00223 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 00224 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 00225 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 00226 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 00227 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 00228 } HRTIM_SimpleCaptureChannelCfgTypeDef; 00229 00230 /** 00231 * @brief Simple One Pulse mode configuration definition 00232 */ 00233 typedef struct 00234 { 00235 uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register. 00236 The compare value must be above or equal to 3 periods of the fHRTIM clock */ 00237 uint32_t OutputPolarity; /*!< Specifies the output polarity. 00238 This parameter can be any value of @ref HRTIM_Output_Polarity */ 00239 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 00240 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 00241 uint32_t Event; /*!< Specifies the external event triggering the pulse generation. 00242 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */ 00243 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 00244 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 00245 uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event. 00246 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */ 00247 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 00248 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 00249 } HRTIM_SimpleOnePulseChannelCfgTypeDef; 00250 00251 /** 00252 * @brief Timer configuration definition 00253 */ 00254 typedef struct 00255 { 00256 uint32_t InterruptRequests; /*!< Relevant for all HRTIM timers, including the master. 00257 Specifies which interrupts requests must enabled for the timer. 00258 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable 00259 or @ref HRTIM_Timing_Unit_Interrupt_Enable */ 00260 uint32_t DMARequests; /*!< Relevant for all HRTIM timers, including the master. 00261 Specifies which DMA requests must be enabled for the timer. 00262 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable 00263 or @ref HRTIM_Timing_Unit_DMA_Request_Enable */ 00264 uint32_t DMASrcAddress; /*!< Relevant for all HRTIM timers, including the master. 00265 Specifies the address of the source address of the DMA transfer */ 00266 uint32_t DMADstAddress; /*!< Relevant for all HRTIM timers, including the master. 00267 Specifies the address of the destination address of the DMA transfer */ 00268 uint32_t DMASize; /*!< Relevant for all HRTIM timers, including the master. 00269 Specifies the size of the DMA transfer */ 00270 uint32_t HalfModeEnable; /*!< Relevant for all HRTIM timers, including the master. 00271 Specifies whether or not half mode is enabled 00272 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */ 00273 uint32_t StartOnSync; /*!< Relevant for all HRTIM timers, including the master. 00274 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 00275 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */ 00276 uint32_t ResetOnSync; /*!< Relevant for all HRTIM timers, including the master. 00277 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled). 00278 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */ 00279 uint32_t DACSynchro; /*!< Relevant for all HRTIM timers, including the master. 00280 Indicates whether or not the a DAC synchronization event is generated. 00281 This parameter can be any value of @ref HRTIM_DAC_Synchronization */ 00282 uint32_t PreloadEnable; /*!< Relevant for all HRTIM timers, including the master. 00283 Specifies whether or not register preload is enabled. 00284 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */ 00285 uint32_t UpdateGating; /*!< Relevant for all HRTIM timers, including the master. 00286 Specifies how the update occurs with respect to a burst DMA transaction or 00287 update enable inputs (Slave timers only). 00288 This parameter can be any value of @ref HRTIM_Update_Gating */ 00289 uint32_t BurstMode; /*!< Relevant for all HRTIM timers, including the master. 00290 Specifies how the timer behaves during a burst mode operation. 00291 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */ 00292 uint32_t RepetitionUpdate; /*!< Relevant for all HRTIM timers, including the master. 00293 Specifies whether or not registers update is triggered by the repetition event. 00294 This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */ 00295 uint32_t PushPull; /*!< Relevant for Timer A to Timer E. 00296 Specifies whether or not the push-pull mode is enabled. 00297 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */ 00298 uint32_t FaultEnable; /*!< Relevant for Timer A to Timer E. 00299 Specifies which fault channels are enabled for the timer. 00300 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */ 00301 uint32_t FaultLock; /*!< Relevant for Timer A to Timer E. 00302 Specifies whether or not fault enabling status is write protected. 00303 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */ 00304 uint32_t DeadTimeInsertion; /*!< Relevant for Timer A to Timer E. 00305 Specifies whether or not dead-time insertion is enabled for the timer. 00306 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */ 00307 uint32_t DelayedProtectionMode; /*!< Relevant for Timer A to Timer E. 00308 Specifies the delayed protection mode. 00309 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */ 00310 uint32_t UpdateTrigger; /*!< Relevant for Timer A to Timer E. 00311 Specifies source(s) triggering the timer registers update. 00312 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */ 00313 uint32_t ResetTrigger; /*!< Relevant for Timer A to Timer E. 00314 Specifies source(s) triggering the timer counter reset. 00315 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */ 00316 uint32_t ResetUpdate; /*!< Relevant for Timer A to Timer E. 00317 Specifies whether or not registers update is triggered when the timer counter is reset. 00318 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */ 00319 } HRTIM_TimerCfgTypeDef; 00320 00321 /** 00322 * @brief Compare unit configuration definition 00323 */ 00324 typedef struct 00325 { 00326 uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit. 00327 The minimum value must be greater than or equal to 3 periods of the fHRTIM clock. 00328 The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */ 00329 uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4. 00330 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */ 00331 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected. 00332 CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */ 00333 } HRTIM_CompareCfgTypeDef; 00334 00335 /** 00336 * @brief Capture unit configuration definition 00337 */ 00338 typedef struct 00339 { 00340 uint32_t Trigger; /*!< Specifies source(s) triggering the capture. 00341 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */ 00342 } HRTIM_CaptureCfgTypeDef; 00343 00344 /** 00345 * @brief Output configuration definition 00346 */ 00347 typedef struct 00348 { 00349 uint32_t Polarity; /*!< Specifies the output polarity. 00350 This parameter can be any value of @ref HRTIM_Output_Polarity */ 00351 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level. 00352 This parameter can be a combination of @ref HRTIM_Output_Set_Source */ 00353 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level. 00354 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */ 00355 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation. 00356 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */ 00357 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state. 00358 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */ 00359 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state. 00360 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */ 00361 uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled 00362 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */ 00363 uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation. 00364 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */ 00365 } HRTIM_OutputCfgTypeDef; 00366 00367 /** 00368 * @brief External event filtering in timing units configuration definition 00369 */ 00370 typedef struct 00371 { 00372 uint32_t Filter; /*!< Specifies the type of event filtering within the timing unit. 00373 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */ 00374 uint32_t Latch; /*!< Specifies whether or not the signal is latched. 00375 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */ 00376 } HRTIM_TimerEventFilteringCfgTypeDef; 00377 00378 /** 00379 * @brief Dead time feature configuration definition 00380 */ 00381 typedef struct 00382 { 00383 uint32_t Prescaler; /*!< Specifies the dead-time prescaler. 00384 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */ 00385 uint32_t RisingValue; /*!< Specifies the dead-time following a rising edge. 00386 This parameter can be a number between 0x0 and 0x1FFU */ 00387 uint32_t RisingSign; /*!< Specifies whether the dead-time is positive or negative on rising edge. 00388 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */ 00389 uint32_t RisingLock; /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected. 00390 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */ 00391 uint32_t RisingSignLock; /*!< Specifies whether or not dead-time rising sign is write protected. 00392 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */ 00393 uint32_t FallingValue; /*!< Specifies the dead-time following a falling edge. 00394 This parameter can be a number between 0x0 and 0x1FFU */ 00395 uint32_t FallingSign; /*!< Specifies whether the dead-time is positive or negative on falling edge. 00396 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */ 00397 uint32_t FallingLock; /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected. 00398 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */ 00399 uint32_t FallingSignLock; /*!< Specifies whether or not dead-time falling sign is write protected. 00400 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */ 00401 } HRTIM_DeadTimeCfgTypeDef; 00402 00403 /** 00404 * @brief Chopper mode configuration definition 00405 */ 00406 typedef struct 00407 { 00408 uint32_t CarrierFreq; /*!< Specifies the Timer carrier frequency value. 00409 This parameter can be a value of @ref HRTIM_Chopper_Frequency */ 00410 uint32_t DutyCycle; /*!< Specifies the Timer chopper duty cycle value. 00411 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */ 00412 uint32_t StartPulse; /*!< Specifies the Timer pulse width value. 00413 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */ 00414 } HRTIM_ChopperModeCfgTypeDef; 00415 00416 /** 00417 * @brief External event channel configuration definition 00418 */ 00419 typedef struct 00420 { 00421 uint32_t Source; /*!< Identifies the source of the external event. 00422 This parameter can be a value of @ref HRTIM_External_Event_Sources */ 00423 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity). 00424 This parameter can be a value of @ref HRTIM_External_Event_Polarity */ 00425 uint32_t Sensitivity; /*!< Specifies the sensitivity of the external event. 00426 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */ 00427 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter. 00428 This parameter can be a value of @ref HRTIM_External_Event_Filter */ 00429 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event. 00430 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */ 00431 } HRTIM_EventCfgTypeDef; 00432 00433 /** 00434 * @brief Fault channel configuration definition 00435 */ 00436 typedef struct 00437 { 00438 uint32_t Source; /*!< Identifies the source of the fault. 00439 This parameter can be a value of @ref HRTIM_Fault_Sources */ 00440 uint32_t Polarity; /*!< Specifies the polarity of the fault event. 00441 This parameter can be a value of @ref HRTIM_Fault_Polarity */ 00442 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter. 00443 This parameter can be a value of @ref HRTIM_Fault_Filter */ 00444 uint32_t Lock; /*!< Indicates whether or not fault programming bits are write protected. 00445 This parameter can be a value of @ref HRTIM_Fault_Lock */ 00446 } HRTIM_FaultCfgTypeDef; 00447 00448 /** 00449 * @brief Burst mode configuration definition 00450 */ 00451 typedef struct 00452 { 00453 uint32_t Mode; /*!< Specifies the burst mode operating mode. 00454 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */ 00455 uint32_t ClockSource; /*!< Specifies the burst mode clock source. 00456 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */ 00457 uint32_t Prescaler; /*!< Specifies the burst mode prescaler. 00458 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */ 00459 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER). 00460 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */ 00461 uint32_t Trigger; /*!< Specifies the event(s) triggering the burst operation. 00462 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */ 00463 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state. 00464 This parameter can be a number between 0x0 and 0xFFFF */ 00465 uint32_t Period; /*!< Specifies burst mode repetition period. 00466 This parameter can be a number between 0x1 and 0xFFFF */ 00467 } HRTIM_BurstModeCfgTypeDef; 00468 00469 /** 00470 * @brief ADC trigger configuration definition 00471 */ 00472 typedef struct 00473 { 00474 uint32_t UpdateSource; /*!< Specifies the ADC trigger update source. 00475 This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source */ 00476 uint32_t Trigger; /*!< Specifies the event(s) triggering the ADC conversion. 00477 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event */ 00478 } HRTIM_ADCTriggerCfgTypeDef; 00479 00480 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 00481 /** 00482 * @brief HAL HRTIM Callback ID enumeration definition 00483 */ 00484 typedef enum { 00485 HAL_HRTIM_FAULT1CALLBACK_CB_ID = 0x00U, /*!< Fault 1 interrupt callback ID */ 00486 HAL_HRTIM_FAULT2CALLBACK_CB_ID = 0x01U, /*!< Fault 2 interrupt callback ID */ 00487 HAL_HRTIM_FAULT3CALLBACK_CB_ID = 0x02U, /*!< Fault 3 interrupt callback ID */ 00488 HAL_HRTIM_FAULT4CALLBACK_CB_ID = 0x03U, /*!< Fault 4 interrupt callback ID */ 00489 HAL_HRTIM_FAULT5CALLBACK_CB_ID = 0x04U, /*!< Fault 5 interrupt callback ID */ 00490 HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID = 0x05U, /*!< System fault interrupt callback ID */ 00491 HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID = 0x07U, /*!< Burst mode period interrupt callback ID */ 00492 HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID */ 00493 HAL_HRTIM_ERRORCALLBACK_CB_ID = 0x09U, /*!< DMA error callback ID */ 00494 00495 HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID = 0x10U, /*!< Timer x Update interrupt callback ID */ 00496 HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID = 0x11U, /*!< Timer x Repetition interrupt callback ID */ 00497 HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID */ 00498 HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID */ 00499 HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID */ 00500 HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID */ 00501 HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID = 0x16U, /*!< Timer x Capture 1 interrupts callback ID */ 00502 HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID = 0x17U, /*!< Timer x Capture 2 interrupts callback ID */ 00503 HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID = 0x18U, /*!< Timer x Delayed protection interrupt callback ID */ 00504 HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */ 00505 HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID = 0x1AU, /*!< Timer x output 1 set interrupt callback ID */ 00506 HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID */ 00507 HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID = 0x1CU, /*!< Timer x output 2 set interrupt callback ID */ 00508 HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID */ 00509 HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID */ 00510 00511 HAL_HRTIM_MSPINIT_CB_ID = 0x20U, /*!< HRTIM MspInit callback ID */ 00512 HAL_HRTIM_MSPDEINIT_CB_ID = 0x21U, /*!< HRTIM MspInit callback ID */ 00513 }HAL_HRTIM_CallbackIDTypeDef; 00514 00515 /** 00516 * @brief HAL HRTIM Callback function pointer definitions 00517 */ 00518 typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim); /*!< HRTIM related callback function pointer */ 00519 00520 typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim, /*!< HRTIM Timer x related callback function pointer */ 00521 uint32_t TimerIdx); 00522 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 00523 00524 /** 00525 * @} 00526 */ 00527 00528 /* Exported constants --------------------------------------------------------*/ 00529 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants 00530 * @{ 00531 */ 00532 00533 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index 00534 * @{ 00535 * @brief Constants defining the timer indexes 00536 */ 00537 #define HRTIM_TIMERINDEX_TIMER_A 0x0U /*!< Index used to access timer A registers */ 00538 #define HRTIM_TIMERINDEX_TIMER_B 0x1U /*!< Index used to access timer B registers */ 00539 #define HRTIM_TIMERINDEX_TIMER_C 0x2U /*!< Index used to access timer C registers */ 00540 #define HRTIM_TIMERINDEX_TIMER_D 0x3U /*!< Index used to access timer D registers */ 00541 #define HRTIM_TIMERINDEX_TIMER_E 0x4U /*!< Index used to access timer E registers */ 00542 #define HRTIM_TIMERINDEX_MASTER 0x5U /*!< Index used to access master registers */ 00543 #define HRTIM_TIMERINDEX_COMMON 0xFFU /*!< Index used to access HRTIM common registers */ 00544 /** 00545 * @} 00546 */ 00547 00548 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier 00549 * @{ 00550 * @brief Constants defining timer identifiers 00551 */ 00552 #define HRTIM_TIMERID_MASTER (HRTIM_MCR_MCEN) /*!< Master identifier */ 00553 #define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN) /*!< Timer A identifier */ 00554 #define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN) /*!< Timer B identifier */ 00555 #define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN) /*!< Timer C identifier */ 00556 #define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN) /*!< Timer D identifier */ 00557 #define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN) /*!< Timer E identifier */ 00558 /** 00559 * @} 00560 */ 00561 00562 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit 00563 * @{ 00564 * @brief Constants defining compare unit identifiers 00565 */ 00566 #define HRTIM_COMPAREUNIT_1 0x00000001U /*!< Compare unit 1 identifier */ 00567 #define HRTIM_COMPAREUNIT_2 0x00000002U /*!< Compare unit 2 identifier */ 00568 #define HRTIM_COMPAREUNIT_3 0x00000004U /*!< Compare unit 3 identifier */ 00569 #define HRTIM_COMPAREUNIT_4 0x00000008U /*!< Compare unit 4 identifier */ 00570 /** 00571 * @} 00572 */ 00573 00574 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit 00575 * @{ 00576 * @brief Constants defining capture unit identifiers 00577 */ 00578 #define HRTIM_CAPTUREUNIT_1 0x00000001U /*!< Capture unit 1 identifier */ 00579 #define HRTIM_CAPTUREUNIT_2 0x00000002U /*!< Capture unit 2 identifier */ 00580 /** 00581 * @} 00582 */ 00583 00584 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output 00585 * @{ 00586 * @brief Constants defining timer output identifiers 00587 */ 00588 #define HRTIM_OUTPUT_TA1 0x00000001U /*!< Timer A - Output 1 identifier */ 00589 #define HRTIM_OUTPUT_TA2 0x00000002U /*!< Timer A - Output 2 identifier */ 00590 #define HRTIM_OUTPUT_TB1 0x00000004U /*!< Timer B - Output 1 identifier */ 00591 #define HRTIM_OUTPUT_TB2 0x00000008U /*!< Timer B - Output 2 identifier */ 00592 #define HRTIM_OUTPUT_TC1 0x00000010U /*!< Timer C - Output 1 identifier */ 00593 #define HRTIM_OUTPUT_TC2 0x00000020U /*!< Timer C - Output 2 identifier */ 00594 #define HRTIM_OUTPUT_TD1 0x00000040U /*!< Timer D - Output 1 identifier */ 00595 #define HRTIM_OUTPUT_TD2 0x00000080U /*!< Timer D - Output 2 identifier */ 00596 #define HRTIM_OUTPUT_TE1 0x00000100U /*!< Timer E - Output 1 identifier */ 00597 #define HRTIM_OUTPUT_TE2 0x00000200U /*!< Timer E - Output 2 identifier */ 00598 /** 00599 * @} 00600 */ 00601 00602 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger 00603 * @{ 00604 * @brief Constants defining ADC triggers identifiers 00605 */ 00606 #define HRTIM_ADCTRIGGER_1 0x00000001U /*!< ADC trigger 1 identifier */ 00607 #define HRTIM_ADCTRIGGER_2 0x00000002U /*!< ADC trigger 2 identifier */ 00608 #define HRTIM_ADCTRIGGER_3 0x00000004U /*!< ADC trigger 3 identifier */ 00609 #define HRTIM_ADCTRIGGER_4 0x00000008U /*!< ADC trigger 4 identifier */ 00610 00611 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\ 00612 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \ 00613 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \ 00614 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \ 00615 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)) 00616 /** 00617 * @} 00618 */ 00619 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels 00620 * @{ 00621 * @brief Constants defining external event channel identifiers 00622 */ 00623 #define HRTIM_EVENT_NONE (0x00000000U) /*!< Undefined event channel */ 00624 #define HRTIM_EVENT_1 (0x00000001U) /*!< External event channel 1 identifier */ 00625 #define HRTIM_EVENT_2 (0x00000002U) /*!< External event channel 2 identifier */ 00626 #define HRTIM_EVENT_3 (0x00000003U) /*!< External event channel 3 identifier */ 00627 #define HRTIM_EVENT_4 (0x00000004U) /*!< External event channel 4 identifier */ 00628 #define HRTIM_EVENT_5 (0x00000005U) /*!< External event channel 5 identifier */ 00629 #define HRTIM_EVENT_6 (0x00000006U) /*!< External event channel 6 identifier */ 00630 #define HRTIM_EVENT_7 (0x00000007U) /*!< External event channel 7 identifier */ 00631 #define HRTIM_EVENT_8 (0x00000008U) /*!< External event channel 8 identifier */ 00632 #define HRTIM_EVENT_9 (0x00000009U) /*!< External event channel 9 identifier */ 00633 #define HRTIM_EVENT_10 (0x0000000AU) /*!< External event channel 10 identifier */ 00634 /** 00635 * @} 00636 */ 00637 00638 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel 00639 * @{ 00640 * @brief Constants defining fault channel identifiers 00641 */ 00642 #define HRTIM_FAULT_1 (0x01U) /*!< Fault channel 1 identifier */ 00643 #define HRTIM_FAULT_2 (0x02U) /*!< Fault channel 2 identifier */ 00644 #define HRTIM_FAULT_3 (0x04U) /*!< Fault channel 3 identifier */ 00645 #define HRTIM_FAULT_4 (0x08U) /*!< Fault channel 4 identifier */ 00646 #define HRTIM_FAULT_5 (0x10U) /*!< Fault channel 5 identifier */ 00647 /** 00648 * @} 00649 */ 00650 00651 00652 /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio 00653 * @{ 00654 * @brief Constants defining timer high-resolution clock prescaler ratio. 00655 */ 00656 #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ 00657 #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ 00658 #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ 00659 /** 00660 * @} 00661 */ 00662 00663 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode 00664 * @{ 00665 * @brief Constants defining timer counter operating mode. 00666 */ 00667 #define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */ 00668 #define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */ 00669 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */ 00670 /** 00671 * @} 00672 */ 00673 00674 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable 00675 * @{ 00676 * @brief Constants defining half mode enabling status. 00677 */ 00678 #define HRTIM_HALFMODE_DISABLED (0x00000000U) /*!< Half mode is disabled */ 00679 #define HRTIM_HALFMODE_ENABLED (0x00000020U) /*!< Half mode is enabled */ 00680 /** 00681 * @} 00682 */ 00683 00684 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event 00685 * @{ 00686 * @brief Constants defining the timer behavior following the synchronization event 00687 */ 00688 #define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 00689 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */ 00690 /** 00691 * @} 00692 */ 00693 00694 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event 00695 * @{ 00696 * @brief Constants defining the timer behavior following the synchronization event 00697 */ 00698 #define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */ 00699 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */ 00700 /** 00701 * @} 00702 */ 00703 00704 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization 00705 * @{ 00706 * @brief Constants defining on which output the DAC synchronization event is sent 00707 */ 00708 #define HRTIM_DACSYNC_NONE 0x00000000U /*!< No DAC synchronization event generated */ 00709 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */ 00710 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */ 00711 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */ 00712 /** 00713 * @} 00714 */ 00715 00716 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable 00717 * @{ 00718 * @brief Constants defining whether a write access into a preloadable 00719 * register is done into the active or the preload register. 00720 */ 00721 #define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */ 00722 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */ 00723 /** 00724 * @} 00725 */ 00726 00727 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating 00728 * @{ 00729 * @brief Constants defining how the update occurs relatively to the burst DMA 00730 * transaction and the external update request on update enable inputs 1 to 3. 00731 */ 00732 #define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */ 00733 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */ 00734 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/ 00735 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */ 00736 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */ 00737 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */ 00738 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */ 00739 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */ 00740 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */ 00741 /** 00742 * @} 00743 */ 00744 00745 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode 00746 * @{ 00747 * @brief Constants defining how the timer behaves during a burst 00748 mode operation. 00749 */ 00750 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U /*!< Timer counter clock is maintained and the timer operates normally */ 00751 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */ 00752 /** 00753 * @} 00754 */ 00755 00756 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update 00757 * @{ 00758 * @brief Constants defining whether registers are updated when the timer 00759 * repetition period is completed (either due to roll-over or 00760 * reset events) 00761 */ 00762 #define HRTIM_UPDATEONREPETITION_DISABLED 0x00000000U /*!< Update on repetition disabled */ 00763 #define HRTIM_UPDATEONREPETITION_ENABLED (HRTIM_MCR_MREPU) /*!< Update on repetition enabled */ 00764 /** 00765 * @} 00766 */ 00767 00768 00769 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode 00770 * @{ 00771 * @brief Constants defining whether or not the push-pull mode is enabled for 00772 * a timer. 00773 */ 00774 #define HRTIM_TIMPUSHPULLMODE_DISABLED 0x00000000U /*!< Push-Pull mode disabled */ 00775 #define HRTIM_TIMPUSHPULLMODE_ENABLED (HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */ 00776 /** 00777 * @} 00778 */ 00779 00780 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling 00781 * @{ 00782 * @brief Constants defining whether a fault channel is enabled for a timer 00783 */ 00784 #define HRTIM_TIMFAULTENABLE_NONE 0x00000000U /*!< No fault enabled */ 00785 #define HRTIM_TIMFAULTENABLE_FAULT1 (HRTIM_FLTR_FLT1EN) /*!< Fault 1 enabled */ 00786 #define HRTIM_TIMFAULTENABLE_FAULT2 (HRTIM_FLTR_FLT2EN) /*!< Fault 2 enabled */ 00787 #define HRTIM_TIMFAULTENABLE_FAULT3 (HRTIM_FLTR_FLT3EN) /*!< Fault 3 enabled */ 00788 #define HRTIM_TIMFAULTENABLE_FAULT4 (HRTIM_FLTR_FLT4EN) /*!< Fault 4 enabled */ 00789 #define HRTIM_TIMFAULTENABLE_FAULT5 (HRTIM_FLTR_FLT5EN) /*!< Fault 5 enabled */ 00790 /** 00791 * @} 00792 */ 00793 00794 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock 00795 * @{ 00796 * @brief Constants defining whether or not fault enabling bits are write 00797 * protected for a timer 00798 */ 00799 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */ 00800 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */ 00801 /** 00802 * @} 00803 */ 00804 00805 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion 00806 * @{ 00807 * @brief Constants defining whether or not fault the dead time insertion 00808 * feature is enabled for a timer 00809 */ 00810 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */ 00811 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Dead-time is inserted between output 1 and output 2U */ 00812 /** 00813 * @} 00814 */ 00815 00816 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode 00817 * @{ 00818 * @brief Constants defining all possible delayed protection modes 00819 * for a timer. Also define the source and outputs on which the delayed 00820 * protection schemes are applied 00821 */ 00822 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 00823 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */ 00824 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */ 00825 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */ 00826 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */ 00827 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */ 00828 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */ 00829 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */ 00830 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */ 00831 00832 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED (0x00000000U) /*!< No action */ 00833 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */ 00834 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */ 00835 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */ 00836 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */ 00837 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */ 00838 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */ 00839 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */ 00840 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */ 00841 /** 00842 * @} 00843 */ 00844 00845 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger 00846 * @{ 00847 * @brief Constants defining whether the registers update is done synchronously 00848 * with any other timer or master update 00849 */ 00850 #define HRTIM_TIMUPDATETRIGGER_NONE 0x00000000U /*!< Register update is disabled */ 00851 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */ 00852 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */ 00853 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */ 00854 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/ 00855 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */ 00856 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */ 00857 /** 00858 * @} 00859 */ 00860 00861 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger 00862 * @{ 00863 * @brief Constants defining the events that can be selected to trigger the reset 00864 * of the timer counter 00865 */ 00866 #define HRTIM_TIMRESETTRIGGER_NONE 0x00000000U /*!< No counter reset trigger */ 00867 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */ 00868 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */ 00869 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */ 00870 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */ 00871 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */ 00872 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */ 00873 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */ 00874 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */ 00875 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */ 00876 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */ 00877 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */ 00878 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */ 00879 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */ 00880 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */ 00881 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */ 00882 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */ 00883 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */ 00884 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */ 00885 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 00886 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 00887 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 00888 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 00889 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 00890 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 00891 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 00892 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 00893 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 00894 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */ 00895 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */ 00896 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */ 00897 /** 00898 * @} 00899 */ 00900 00901 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update 00902 * @{ 00903 * @brief Constants defining whether the register are updated upon Timerx 00904 * counter reset or roll-over to 0 after reaching the period value 00905 * in continuous mode 00906 */ 00907 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */ 00908 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */ 00909 /** 00910 * @} 00911 */ 00912 00913 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode 00914 * @{ 00915 * @brief Constants defining whether the compare register is behaving in 00916 * regular mode (compare match issued as soon as counter equal compare), 00917 * or in auto-delayed mode 00918 */ 00919 #define HRTIM_AUTODELAYEDMODE_REGULAR (0x00000000U) /*!< standard compare mode */ 00920 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */ 00921 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ 00922 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ 00923 /** 00924 * @} 00925 */ 00926 00927 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode 00928 * @{ 00929 * @brief Constants defining the behavior of the output signal when the timer 00930 operates in basic output compare mode 00931 */ 00932 #define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */ 00933 #define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */ 00934 #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */ 00935 00936 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\ 00937 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \ 00938 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \ 00939 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE)) 00940 /** 00941 * @} 00942 */ 00943 00944 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity 00945 * @{ 00946 * @brief Constants defining the polarity of a timer output 00947 */ 00948 #define HRTIM_OUTPUTPOLARITY_HIGH (0x00000000U) /*!< Output is active HIGH */ 00949 #define HRTIM_OUTPUTPOLARITY_LOW (HRTIM_OUTR_POL1) /*!< Output is active LOW */ 00950 /** 00951 * @} 00952 */ 00953 00954 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source 00955 * @{ 00956 * @brief Constants defining the events that can be selected to configure the 00957 * set crossbar of a timer output 00958 */ 00959 #define HRTIM_OUTPUTSET_NONE 0x00000000U /*!< Reset the output set crossbar */ 00960 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */ 00961 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */ 00962 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */ 00963 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */ 00964 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */ 00965 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */ 00966 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */ 00967 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */ 00968 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */ 00969 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */ 00970 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */ 00971 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 00972 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 00973 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 00974 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 00975 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 00976 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 00977 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 00978 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 00979 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 00980 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */ 00981 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */ 00982 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */ 00983 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */ 00984 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */ 00985 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */ 00986 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */ 00987 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */ 00988 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */ 00989 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */ 00990 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */ 00991 /** 00992 * @} 00993 */ 00994 00995 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source 00996 * @{ 00997 * @brief Constants defining the events that can be selected to configure the 00998 * reset crossbar of a timer output 00999 */ 01000 #define HRTIM_OUTPUTRESET_NONE 0x00000000U /*!< Reset the output reset crossbar */ 01001 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */ 01002 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */ 01003 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */ 01004 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */ 01005 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */ 01006 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */ 01007 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */ 01008 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */ 01009 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */ 01010 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */ 01011 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */ 01012 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */ 01013 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */ 01014 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */ 01015 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */ 01016 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */ 01017 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */ 01018 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */ 01019 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */ 01020 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */ 01021 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */ 01022 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */ 01023 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */ 01024 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */ 01025 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */ 01026 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */ 01027 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */ 01028 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */ 01029 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */ 01030 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */ 01031 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */ 01032 /** 01033 * @} 01034 */ 01035 01036 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode 01037 * @{ 01038 * @brief Constants defining whether or not the timer output transition to its 01039 IDLE state when burst mode is entered 01040 */ 01041 #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */ 01042 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ 01043 /** 01044 * @} 01045 */ 01046 01047 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level 01048 * @{ 01049 * @brief Constants defining the output level when output is in IDLE state 01050 */ 01051 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ 01052 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ 01053 /** 01054 * @} 01055 */ 01056 01057 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level 01058 * @{ 01059 * @brief Constants defining the output level when output is in FAULT state 01060 */ 01061 #define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */ 01062 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ 01063 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ 01064 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ 01065 /** 01066 * @} 01067 */ 01068 01069 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable 01070 * @{ 01071 * @brief Constants defining whether or not chopper mode is enabled for a timer 01072 output 01073 */ 01074 #define HRTIM_OUTPUTCHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ 01075 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */ 01076 /** 01077 * @} 01078 */ 01079 01080 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed 01081 * @{ 01082 * @brief Constants defining the idle mode entry is delayed by forcing a 01083 dead-time insertion before switching the outputs to their idle state 01084 */ 01085 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ 01086 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Dead-time is inserted on output before entering the idle mode */ 01087 /** 01088 * @} 01089 */ 01090 01091 01092 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger 01093 * @{ 01094 * @brief Constants defining the events that can be selected to trigger the 01095 * capture of the timing unit counter 01096 */ 01097 #define HRTIM_CAPTURETRIGGER_NONE 0x00000000U /*!< Capture trigger is disabled */ 01098 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */ 01099 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */ 01100 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */ 01101 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */ 01102 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */ 01103 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */ 01104 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */ 01105 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */ 01106 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */ 01107 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */ 01108 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */ 01109 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */ 01110 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */ 01111 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */ 01112 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */ 01113 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */ 01114 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */ 01115 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */ 01116 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */ 01117 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */ 01118 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */ 01119 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */ 01120 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */ 01121 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */ 01122 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */ 01123 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */ 01124 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */ 01125 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */ 01126 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */ 01127 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */ 01128 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */ 01129 /** 01130 * @} 01131 */ 01132 01133 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter 01134 * @{ 01135 * @brief Constants defining the event filtering applied to external events 01136 * by a timer 01137 */ 01138 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U) 01139 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */ 01140 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */ 01141 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */ 01142 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */ 01143 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 01144 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 01145 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 01146 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 01147 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 01148 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 01149 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 01150 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 01151 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */ 01152 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */ 01153 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ 01154 /** 01155 * @} 01156 */ 01157 01158 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch 01159 * @{ 01160 * @brief Constants defining whether or not the external event is 01161 * memorized (latched) and generated as soon as the blanking period 01162 * is completed or the window ends 01163 */ 01164 #define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */ 01165 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */ 01166 /** 01167 * @} 01168 */ 01169 01170 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio 01171 * @{ 01172 * @brief Constants defining division ratio between the timer clock frequency 01173 * (fHRTIM) and the dead-time generator clock (fDTG) 01174 */ 01175 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8 (0x00000000U) /*!< fDTG = fHRTIM * 8U */ 01176 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4U */ 01177 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2U */ 01178 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ 01179 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2U */ 01180 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */ 01181 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */ 01182 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */ 01183 /** 01184 * @} 01185 */ 01186 01187 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign 01188 * @{ 01189 * @brief Constants defining whether the dead-time is positive or negative 01190 * (overlapping signal) on rising edge 01191 */ 01192 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on rising edge */ 01193 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative dead-time on rising edge */ 01194 /** 01195 * @} 01196 */ 01197 01198 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock 01199 * @{ 01200 * @brief Constants defining whether or not the dead-time (rising sign and 01201 * value) is write protected 01202 */ 01203 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Dead-time rising value and sign is writeable */ 01204 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Dead-time rising value and sign is read-only */ 01205 /** 01206 * @} 01207 */ 01208 01209 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock 01210 * @{ 01211 * @brief Constants defining whether or not the dead-time rising sign is write 01212 * protected 01213 */ 01214 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time rising sign is writeable */ 01215 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Dead-time rising sign is read-only */ 01216 /** 01217 * @} 01218 */ 01219 01220 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign 01221 * @{ 01222 * @brief Constants defining whether the dead-time is positive or negative 01223 * (overlapping signal) on falling edge 01224 */ 01225 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive dead-time on falling edge */ 01226 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative dead-time on falling edge */ 01227 /** 01228 * @} 01229 */ 01230 01231 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock 01232 * @{ 01233 * @brief Constants defining whether or not the dead-time (falling sign and 01234 * value) is write protected 01235 */ 01236 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Dead-time falling value and sign is writeable */ 01237 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Dead-time falling value and sign is read-only */ 01238 /** 01239 * @} 01240 */ 01241 01242 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock 01243 * @{ 01244 * @brief Constants defining whether or not the dead-time falling sign is write 01245 * protected 01246 */ 01247 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Dead-time falling sign is writeable */ 01248 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Dead-time falling sign is read-only */ 01249 /** 01250 * @} 01251 */ 01252 01253 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency 01254 * @{ 01255 * @brief Constants defining the frequency of the generated high frequency carrier 01256 */ 01257 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV16 (0x000000U) /*!< fCHPFRQ = fHRTIM / 16 */ 01258 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */ 01259 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */ 01260 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */ 01261 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */ 01262 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */ 01263 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */ 01264 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */ 01265 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */ 01266 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */ 01267 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */ 01268 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */ 01269 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */ 01270 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ 01271 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ 01272 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ 01273 /** 01274 * @} 01275 */ 01276 01277 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle 01278 * @{ 01279 * @brief Constants defining the duty cycle of the generated high frequency carrier 01280 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) 01281 */ 01282 #define HRTIM_CHOPPER_DUTYCYCLE_0 (0x000000U) /*!< Only 1st pulse is present */ 01283 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */ 01284 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */ 01285 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */ 01286 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */ 01287 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */ 01288 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */ 01289 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */ 01290 /** 01291 * @} 01292 */ 01293 01294 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width 01295 * @{ 01296 * @brief Constants defining the pulse width of the first pulse of the generated 01297 * high frequency carrier 01298 */ 01299 #define HRTIM_CHOPPER_PULSEWIDTH_16 (0x000000U) /*!< tSTPW = tHRTIM x 16 */ 01300 #define HRTIM_CHOPPER_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */ 01301 #define HRTIM_CHOPPER_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */ 01302 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */ 01303 #define HRTIM_CHOPPER_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */ 01304 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */ 01305 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */ 01306 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */ 01307 #define HRTIM_CHOPPER_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */ 01308 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */ 01309 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */ 01310 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */ 01311 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */ 01312 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */ 01313 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */ 01314 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */ 01315 /** 01316 * @} 01317 */ 01318 01319 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options 01320 * @{ 01321 * @brief Constants defining the options for synchronizing multiple HRTIM 01322 * instances, as a master unit (generating a synchronization signal) 01323 * or as a slave (waiting for a trigger to be synchronized) 01324 */ 01325 #define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */ 01326 #define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/ 01327 #define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */ 01328 /** 01329 * @} 01330 */ 01331 01332 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source 01333 * @{ 01334 * @brief Constants defining defining the synchronization input source 01335 */ 01336 #define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */ 01337 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */ 01338 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ 01339 /** 01340 * @} 01341 */ 01342 01343 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source 01344 * @{ 01345 * @brief Constants defining the source and event to be sent on the 01346 * synchronization outputs 01347 */ 01348 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ 01349 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ 01350 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ 01351 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ 01352 /** 01353 * @} 01354 */ 01355 01356 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity 01357 * @{ 01358 * @brief Constants defining the routing and conditioning of the synchronization output event 01359 */ 01360 #define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */ 01361 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */ 01362 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */ 01363 /** 01364 * @} 01365 */ 01366 01367 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources 01368 * @{ 01369 * @brief Constants defining available sources associated to external events 01370 */ 01371 #define HRTIM_EVENTSRC_1 (0x00000000U) /*!< External event source 1U */ 01372 #define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2U */ 01373 #define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3U */ 01374 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U */ 01375 /** 01376 * @} 01377 */ 01378 01379 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity 01380 * @{ 01381 * @brief Constants defining the polarity of an external event 01382 */ 01383 #define HRTIM_EVENTPOLARITY_HIGH (0x00000000U) /*!< External event is active high */ 01384 #define HRTIM_EVENTPOLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */ 01385 /** 01386 * @} 01387 */ 01388 01389 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity 01390 * @{ 01391 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) 01392 * of an external event 01393 */ 01394 #define HRTIM_EVENTSENSITIVITY_LEVEL (0x00000000U) /*!< External event is active on level */ 01395 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */ 01396 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */ 01397 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */ 01398 /** 01399 * @} 01400 */ 01401 01402 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode 01403 * @{ 01404 * @brief Constants defining whether or not an external event is programmed in 01405 fast mode 01406 */ 01407 #define HRTIM_EVENTFASTMODE_DISABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ 01408 #define HRTIM_EVENTFASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ 01409 /** 01410 * @} 01411 */ 01412 01413 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter 01414 * @{ 01415 * @brief Constants defining the frequency used to sample an external event 6 01416 * input and the length (N) of the digital filter applied 01417 */ 01418 #define HRTIM_EVENTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 01419 #define HRTIM_EVENTFILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 01420 #define HRTIM_EVENTFILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 01421 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 01422 #define HRTIM_EVENTFILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/2U, N=6U */ 01423 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */ 01424 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */ 01425 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */ 01426 #define HRTIM_EVENTFILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING= fEEVS/8U, N=6U */ 01427 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */ 01428 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */ 01429 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */ 01430 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */ 01431 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */ 01432 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */ 01433 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */ 01434 /** 01435 * @} 01436 */ 01437 01438 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler 01439 * @{ 01440 * @brief Constants defining division ratio between the timer clock frequency 01441 * fHRTIM) and the external event signal sampling clock (fEEVS) 01442 * used by the digital filters 01443 */ 01444 #define HRTIM_EVENTPRESCALER_DIV1 (0x00000000U) /*!< fEEVS=fHRTIM */ 01445 #define HRTIM_EVENTPRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 2U */ 01446 #define HRTIM_EVENTPRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS=fHRTIM / 4U */ 01447 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */ 01448 /** 01449 * @} 01450 */ 01451 01452 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources 01453 * @{ 01454 * @brief Constants defining whether a fault is triggered by any external 01455 * or internal fault source 01456 */ 01457 #define HRTIM_FAULTSOURCE_DIGITALINPUT (0x00000000U) /*!< Fault input is FLT input pin */ 01458 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ 01459 /** 01460 * @} 01461 */ 01462 01463 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity 01464 * @{ 01465 * @brief Constants defining the polarity of a fault event 01466 */ 01467 #define HRTIM_FAULTPOLARITY_LOW (0x00000000U) /*!< Fault input is active low */ 01468 #define HRTIM_FAULTPOLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ 01469 /** 01470 * @} 01471 */ 01472 01473 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter 01474 * @{ 01475 * @ brief Constants defining the frequency used to sample the fault input and 01476 * the length (N) of the digital filter applied 01477 */ 01478 #define HRTIM_FAULTFILTER_NONE (0x00000000U) /*!< Filter disabled */ 01479 #define HRTIM_FAULTFILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2U */ 01480 #define HRTIM_FAULTFILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4U */ 01481 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */ 01482 #define HRTIM_FAULTFILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2U, N=6U */ 01483 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */ 01484 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */ 01485 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */ 01486 #define HRTIM_FAULTFILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8U, N=6U */ 01487 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */ 01488 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */ 01489 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */ 01490 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */ 01491 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */ 01492 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */ 01493 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */ 01494 /** 01495 * @} 01496 */ 01497 01498 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock 01499 * @{ 01500 * @brief Constants defining whether or not the fault programming bits are 01501 write protected 01502 */ 01503 #define HRTIM_FAULTLOCK_READWRITE (0x00000000U) /*!< Fault settings bits are read/write */ 01504 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */ 01505 /** 01506 * @} 01507 */ 01508 01509 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler 01510 * @{ 01511 * @brief Constants defining the division ratio between the timer clock 01512 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used 01513 * by the digital filters. 01514 */ 01515 #define HRTIM_FAULTPRESCALER_DIV1 (0x00000000U) /*!< fFLTS=fHRTIM */ 01516 #define HRTIM_FAULTPRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 2U */ 01517 #define HRTIM_FAULTPRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS=fHRTIM / 4U */ 01518 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */ 01519 /** 01520 * @} 01521 */ 01522 01523 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode 01524 * @{ 01525 * @brief Constants defining if the burst mode is entered once or if it is 01526 * continuously operating 01527 */ 01528 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */ 01529 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ 01530 /** 01531 * @} 01532 */ 01533 01534 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source 01535 * @{ 01536 * @brief Constants defining the clock source for the burst mode counter 01537 */ 01538 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */ 01539 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */ 01540 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */ 01541 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */ 01542 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */ 01543 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */ 01544 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ 01545 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ 01546 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ 01547 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */ 01548 /** 01549 * @} 01550 */ 01551 01552 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler 01553 * @{ 01554 * @brief Constants defining the prescaling ratio of the fHRTIM clock 01555 * for the burst mode controller 01556 */ 01557 #define HRTIM_BURSTMODEPRESCALER_DIV1 (0x00000000U) /*!< fBRST = fHRTIM */ 01558 #define HRTIM_BURSTMODEPRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2U */ 01559 #define HRTIM_BURSTMODEPRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4U */ 01560 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */ 01561 #define HRTIM_BURSTMODEPRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16U */ 01562 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */ 01563 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */ 01564 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */ 01565 #define HRTIM_BURSTMODEPRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256U */ 01566 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */ 01567 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */ 01568 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/ 01569 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */ 01570 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */ 01571 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */ 01572 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */ 01573 /** 01574 * @} 01575 */ 01576 01577 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable 01578 * @{ 01579 * @brief Constants defining whether or not burst mode registers preload 01580 mechanism is enabled, i.e. a write access into a preloadable register 01581 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register 01582 */ 01583 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */ 01584 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */ 01585 /** 01586 * @} 01587 */ 01588 01589 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger 01590 * @{ 01591 * @brief Constants defining the events that can be used to trig the burst 01592 * mode operation 01593 */ 01594 #define HRTIM_BURSTMODETRIGGER_NONE 0x00000000U /*!< No trigger */ 01595 #define HRTIM_BURSTMODETRIGGER_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master reset */ 01596 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */ 01597 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master compare 1U */ 01598 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master compare 2U */ 01599 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master compare 3U */ 01600 #define HRTIM_BURSTMODETRIGGER_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master compare 4U */ 01601 #define HRTIM_BURSTMODETRIGGER_TIMERA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset */ 01602 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */ 01603 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 */ 01604 #define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 */ 01605 #define HRTIM_BURSTMODETRIGGER_TIMERB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset */ 01606 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */ 01607 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 */ 01608 #define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 */ 01609 #define HRTIM_BURSTMODETRIGGER_TIMERC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C reset */ 01610 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */ 01611 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 */ 01612 #define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 */ 01613 #define HRTIM_BURSTMODETRIGGER_TIMERD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset */ 01614 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */ 01615 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 */ 01616 #define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 */ 01617 #define HRTIM_BURSTMODETRIGGER_TIMERE_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset */ 01618 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */ 01619 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 */ 01620 #define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 */ 01621 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */ 01622 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */ 01623 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */ 01624 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/ 01625 #define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< On-chip Event */ 01626 /** 01627 * @} 01628 */ 01629 01630 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source 01631 * @{ 01632 * @brief constants defining the source triggering the update of the 01633 HRTIM_ADCxR register (transfer from preload to active register). 01634 */ 01635 #define HRTIM_ADCTRIGGERUPDATE_MASTER 0x00000000U /*!< Master timer */ 01636 #define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< Timer A */ 01637 #define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< Timer B */ 01638 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */ 01639 #define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< Timer D */ 01640 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */ 01641 /** 01642 * @} 01643 */ 01644 01645 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event 01646 * @{ 01647 * @brief constants defining the events triggering ADC conversion. 01648 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3 01649 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4 01650 */ 01651 #define HRTIM_ADCTRIGGEREVENT13_NONE 0x00000000U /*!< No ADC trigger event */ 01652 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */ 01653 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */ 01654 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */ 01655 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */ 01656 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */ 01657 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */ 01658 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */ 01659 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */ 01660 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */ 01661 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */ 01662 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2U */ 01663 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */ 01664 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */ 01665 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */ 01666 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */ 01667 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2U */ 01668 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */ 01669 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */ 01670 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */ 01671 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */ 01672 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2U */ 01673 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */ 01674 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */ 01675 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */ 01676 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2U */ 01677 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */ 01678 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */ 01679 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */ 01680 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2U */ 01681 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */ 01682 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */ 01683 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */ 01684 01685 #define HRTIM_ADCTRIGGEREVENT24_NONE 0x00000000U /*!< No ADC trigger event */ 01686 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */ 01687 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */ 01688 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */ 01689 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */ 01690 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */ 01691 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */ 01692 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */ 01693 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */ 01694 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */ 01695 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */ 01696 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */ 01697 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3U */ 01698 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */ 01699 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */ 01700 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */ 01701 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3U */ 01702 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */ 01703 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */ 01704 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */ 01705 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3U */ 01706 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */ 01707 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */ 01708 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */ 01709 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */ 01710 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3U */ 01711 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */ 01712 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */ 01713 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */ 01714 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */ 01715 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */ 01716 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */ 01717 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */ 01718 01719 /** 01720 * @} 01721 */ 01722 01723 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update 01724 * @{ 01725 * @brief Constants defining the registers that can be written during a burst 01726 * DMA operation 01727 */ 01728 #define HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ 01729 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */ 01730 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */ 01731 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */ 01732 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */ 01733 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */ 01734 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */ 01735 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */ 01736 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */ 01737 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */ 01738 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */ 01739 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */ 01740 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */ 01741 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */ 01742 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */ 01743 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */ 01744 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */ 01745 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */ 01746 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */ 01747 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */ 01748 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */ 01749 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */ 01750 /** 01751 * @} 01752 */ 01753 01754 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control 01755 * @{ 01756 * @brief Constants used to enable or disable the burst mode controller 01757 */ 01758 #define HRTIM_BURSTMODECTL_DISABLED 0x00000000U /*!< Burst mode disabled */ 01759 #define HRTIM_BURSTMODECTL_ENABLED (HRTIM_BMCR_BME) /*!< Burst mode enabled */ 01760 /** 01761 * @} 01762 */ 01763 01764 /** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control 01765 * @{ 01766 * @brief Constants used to enable or disable a fault channel 01767 */ 01768 #define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */ 01769 #define HRTIM_FAULTMODECTL_ENABLED 0x00000001U /*!< Fault channel is enabled */ 01770 /** 01771 * @} 01772 */ 01773 01774 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update 01775 * @{ 01776 * @brief Constants used to force timer registers update 01777 */ 01778 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Force an immediate transfer from the preload to the active register in the master timer */ 01779 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Force an immediate transfer from the preload to the active register in the timer A */ 01780 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Force an immediate transfer from the preload to the active register in the timer B */ 01781 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Force an immediate transfer from the preload to the active register in the timer C */ 01782 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Force an immediate transfer from the preload to the active register in the timer D */ 01783 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Force an immediate transfer from the preload to the active register in the timer E */ 01784 /** 01785 * @} 01786 */ 01787 01788 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset 01789 * @{ 01790 * @brief Constants used to force timer counter reset 01791 */ 01792 #define HRTIM_TIMERRESET_MASTER (HRTIM_CR2_MRST) /*!< Reset the master timer counter */ 01793 #define HRTIM_TIMERRESET_TIMER_A (HRTIM_CR2_TARST) /*!< Reset the timer A counter */ 01794 #define HRTIM_TIMERRESET_TIMER_B (HRTIM_CR2_TBRST) /*!< Reset the timer B counter */ 01795 #define HRTIM_TIMERRESET_TIMER_C (HRTIM_CR2_TCRST) /*!< Reset the timer C counter */ 01796 #define HRTIM_TIMERRESET_TIMER_D (HRTIM_CR2_TDRST) /*!< Reset the timer D counter */ 01797 #define HRTIM_TIMERRESET_TIMER_E (HRTIM_CR2_TERST) /*!< Reset the timer E counter */ 01798 /** 01799 * @} 01800 */ 01801 01802 /** @defgroup HRTIM_Output_Level HRTIM Output Level 01803 * @{ 01804 * @brief Constants defining the level of a timer output 01805 */ 01806 #define HRTIM_OUTPUTLEVEL_ACTIVE (0x00000001U) /*!< Force the output to its active state */ 01807 #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Force the output to its inactive state */ 01808 01809 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\ 01810 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \ 01811 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE)) 01812 /** 01813 * @} 01814 */ 01815 01816 /** @defgroup HRTIM_Output_State HRTIM Output State 01817 * @{ 01818 * @brief Constants defining the state of a timer output 01819 */ 01820 #define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or 01821 inactive level as programmed in the crossbar unit */ 01822 #define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the 01823 outputs are disabled by software or during a burst mode operation */ 01824 #define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on 01825 FAULTx inputs */ 01826 /** 01827 * @} 01828 */ 01829 01830 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status 01831 * @{ 01832 * @brief Constants defining the operating state of the burst mode controller 01833 */ 01834 #define HRTIM_BURSTMODESTATUS_NORMAL 0x00000000U /*!< Normal operation */ 01835 #define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT) /*!< Burst operation on-going */ 01836 /** 01837 * @} 01838 */ 01839 01840 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status 01841 * @{ 01842 * @brief Constants defining on which output the signal is currently applied 01843 * in push-pull mode 01844 */ 01845 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */ 01846 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ 01847 /** 01848 * @} 01849 */ 01850 01851 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status 01852 * @{ 01853 * @brief Constants defining on which output the signal was applied, in 01854 * push-pull mode balanced fault mode or delayed idle mode, when the 01855 * protection was triggered 01856 */ 01857 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ 01858 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ 01859 /** 01860 * @} 01861 */ 01862 01863 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable 01864 * @{ 01865 */ 01866 #define HRTIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 01867 #define HRTIM_IT_FLT1 HRTIM_IER_FLT1 /*!< Fault 1 interrupt enable */ 01868 #define HRTIM_IT_FLT2 HRTIM_IER_FLT2 /*!< Fault 2 interrupt enable */ 01869 #define HRTIM_IT_FLT3 HRTIM_IER_FLT3 /*!< Fault 3 interrupt enable */ 01870 #define HRTIM_IT_FLT4 HRTIM_IER_FLT4 /*!< Fault 4 interrupt enable */ 01871 #define HRTIM_IT_FLT5 HRTIM_IER_FLT5 /*!< Fault 5 interrupt enable */ 01872 #define HRTIM_IT_SYSFLT HRTIM_IER_SYSFLT /*!< System Fault interrupt enable */ 01873 #define HRTIM_IT_BMPER HRTIM_IER_BMPER /*!< Burst mode period interrupt enable */ 01874 /** 01875 * @} 01876 */ 01877 01878 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable 01879 * @{ 01880 */ 01881 #define HRTIM_MASTER_IT_NONE 0x00000000U /*!< No interrupt enabled */ 01882 #define HRTIM_MASTER_IT_MCMP1 HRTIM_MDIER_MCMP1IE /*!< Master compare 1 interrupt enable */ 01883 #define HRTIM_MASTER_IT_MCMP2 HRTIM_MDIER_MCMP2IE /*!< Master compare 2 interrupt enable */ 01884 #define HRTIM_MASTER_IT_MCMP3 HRTIM_MDIER_MCMP3IE /*!< Master compare 3 interrupt enable */ 01885 #define HRTIM_MASTER_IT_MCMP4 HRTIM_MDIER_MCMP4IE /*!< Master compare 4 interrupt enable */ 01886 #define HRTIM_MASTER_IT_MREP HRTIM_MDIER_MREPIE /*!< Master Repetition interrupt enable */ 01887 #define HRTIM_MASTER_IT_SYNC HRTIM_MDIER_SYNCIE /*!< Synchronization input interrupt enable */ 01888 #define HRTIM_MASTER_IT_MUPD HRTIM_MDIER_MUPDIE /*!< Master update interrupt enable */ 01889 /** 01890 * @} 01891 */ 01892 01893 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable 01894 * @{ 01895 */ 01896 #define HRTIM_TIM_IT_NONE 0x00000000U /*!< No interrupt enabled */ 01897 #define HRTIM_TIM_IT_CMP1 HRTIM_TIMDIER_CMP1IE /*!< Timer compare 1 interrupt enable */ 01898 #define HRTIM_TIM_IT_CMP2 HRTIM_TIMDIER_CMP2IE /*!< Timer compare 2 interrupt enable */ 01899 #define HRTIM_TIM_IT_CMP3 HRTIM_TIMDIER_CMP3IE /*!< Timer compare 3 interrupt enable */ 01900 #define HRTIM_TIM_IT_CMP4 HRTIM_TIMDIER_CMP4IE /*!< Timer compare 4 interrupt enable */ 01901 #define HRTIM_TIM_IT_REP HRTIM_TIMDIER_REPIE /*!< Timer repetition interrupt enable */ 01902 #define HRTIM_TIM_IT_UPD HRTIM_TIMDIER_UPDIE /*!< Timer update interrupt enable */ 01903 #define HRTIM_TIM_IT_CPT1 HRTIM_TIMDIER_CPT1IE /*!< Timer capture 1 interrupt enable */ 01904 #define HRTIM_TIM_IT_CPT2 HRTIM_TIMDIER_CPT2IE /*!< Timer capture 2 interrupt enable */ 01905 #define HRTIM_TIM_IT_SET1 HRTIM_TIMDIER_SET1IE /*!< Timer output 1 set interrupt enable */ 01906 #define HRTIM_TIM_IT_RST1 HRTIM_TIMDIER_RST1IE /*!< Timer output 1 reset interrupt enable */ 01907 #define HRTIM_TIM_IT_SET2 HRTIM_TIMDIER_SET2IE /*!< Timer output 2 set interrupt enable */ 01908 #define HRTIM_TIM_IT_RST2 HRTIM_TIMDIER_RST2IE /*!< Timer output 2 reset interrupt enable */ 01909 #define HRTIM_TIM_IT_RST HRTIM_TIMDIER_RSTIE /*!< Timer reset interrupt enable */ 01910 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */ 01911 /** 01912 * @} 01913 */ 01914 01915 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag 01916 * @{ 01917 */ 01918 #define HRTIM_FLAG_FLT1 HRTIM_ISR_FLT1 /*!< Fault 1 interrupt flag */ 01919 #define HRTIM_FLAG_FLT2 HRTIM_ISR_FLT2 /*!< Fault 2 interrupt flag */ 01920 #define HRTIM_FLAG_FLT3 HRTIM_ISR_FLT3 /*!< Fault 3 interrupt flag */ 01921 #define HRTIM_FLAG_FLT4 HRTIM_ISR_FLT4 /*!< Fault 4 interrupt flag */ 01922 #define HRTIM_FLAG_FLT5 HRTIM_ISR_FLT5 /*!< Fault 5 interrupt flag */ 01923 #define HRTIM_FLAG_SYSFLT HRTIM_ISR_SYSFLT /*!< System Fault interrupt flag */ 01924 #define HRTIM_FLAG_BMPER HRTIM_ISR_BMPER /*!< Burst mode period interrupt flag */ 01925 /** 01926 * @} 01927 */ 01928 01929 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag 01930 * @{ 01931 */ 01932 #define HRTIM_MASTER_FLAG_MCMP1 HRTIM_MISR_MCMP1 /*!< Master compare 1 interrupt flag */ 01933 #define HRTIM_MASTER_FLAG_MCMP2 HRTIM_MISR_MCMP2 /*!< Master compare 2 interrupt flag */ 01934 #define HRTIM_MASTER_FLAG_MCMP3 HRTIM_MISR_MCMP3 /*!< Master compare 3 interrupt flag */ 01935 #define HRTIM_MASTER_FLAG_MCMP4 HRTIM_MISR_MCMP4 /*!< Master compare 4 interrupt flag */ 01936 #define HRTIM_MASTER_FLAG_MREP HRTIM_MISR_MREP /*!< Master Repetition interrupt flag */ 01937 #define HRTIM_MASTER_FLAG_SYNC HRTIM_MISR_SYNC /*!< Synchronization input interrupt flag */ 01938 #define HRTIM_MASTER_FLAG_MUPD HRTIM_MISR_MUPD /*!< Master update interrupt flag */ 01939 /** 01940 * @} 01941 */ 01942 01943 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag 01944 * @{ 01945 */ 01946 #define HRTIM_TIM_FLAG_CMP1 HRTIM_TIMISR_CMP1 /*!< Timer compare 1 interrupt flag */ 01947 #define HRTIM_TIM_FLAG_CMP2 HRTIM_TIMISR_CMP2 /*!< Timer compare 2 interrupt flag */ 01948 #define HRTIM_TIM_FLAG_CMP3 HRTIM_TIMISR_CMP3 /*!< Timer compare 3 interrupt flag */ 01949 #define HRTIM_TIM_FLAG_CMP4 HRTIM_TIMISR_CMP4 /*!< Timer compare 4 interrupt flag */ 01950 #define HRTIM_TIM_FLAG_REP HRTIM_TIMISR_REP /*!< Timer repetition interrupt flag */ 01951 #define HRTIM_TIM_FLAG_UPD HRTIM_TIMISR_UPD /*!< Timer update interrupt flag */ 01952 #define HRTIM_TIM_FLAG_CPT1 HRTIM_TIMISR_CPT1 /*!< Timer capture 1 interrupt flag */ 01953 #define HRTIM_TIM_FLAG_CPT2 HRTIM_TIMISR_CPT2 /*!< Timer capture 2 interrupt flag */ 01954 #define HRTIM_TIM_FLAG_SET1 HRTIM_TIMISR_SET1 /*!< Timer output 1 set interrupt flag */ 01955 #define HRTIM_TIM_FLAG_RST1 HRTIM_TIMISR_RST1 /*!< Timer output 1 reset interrupt flag */ 01956 #define HRTIM_TIM_FLAG_SET2 HRTIM_TIMISR_SET2 /*!< Timer output 2 set interrupt flag */ 01957 #define HRTIM_TIM_FLAG_RST2 HRTIM_TIMISR_RST2 /*!< Timer output 2 reset interrupt flag */ 01958 #define HRTIM_TIM_FLAG_RST HRTIM_TIMISR_RST /*!< Timer reset interrupt flag */ 01959 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */ 01960 /** 01961 * @} 01962 */ 01963 01964 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable 01965 * @{ 01966 */ 01967 #define HRTIM_MASTER_DMA_NONE 0x00000000U /*!< No DMA request enable */ 01968 #define HRTIM_MASTER_DMA_MCMP1 HRTIM_MDIER_MCMP1DE /*!< Master compare 1 DMA request enable */ 01969 #define HRTIM_MASTER_DMA_MCMP2 HRTIM_MDIER_MCMP2DE /*!< Master compare 2 DMA request enable */ 01970 #define HRTIM_MASTER_DMA_MCMP3 HRTIM_MDIER_MCMP3DE /*!< Master compare 3 DMA request enable */ 01971 #define HRTIM_MASTER_DMA_MCMP4 HRTIM_MDIER_MCMP4DE /*!< Master compare 4 DMA request enable */ 01972 #define HRTIM_MASTER_DMA_MREP HRTIM_MDIER_MREPDE /*!< Master Repetition DMA request enable */ 01973 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */ 01974 #define HRTIM_MASTER_DMA_MUPD HRTIM_MDIER_MUPDDE /*!< Master update DMA request enable */ 01975 /** 01976 * @} 01977 */ 01978 01979 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable 01980 * @{ 01981 */ 01982 #define HRTIM_TIM_DMA_NONE 0x00000000U /*!< No DMA request enable */ 01983 #define HRTIM_TIM_DMA_CMP1 HRTIM_TIMDIER_CMP1DE /*!< Timer compare 1 DMA request enable */ 01984 #define HRTIM_TIM_DMA_CMP2 HRTIM_TIMDIER_CMP2DE /*!< Timer compare 2 DMA request enable */ 01985 #define HRTIM_TIM_DMA_CMP3 HRTIM_TIMDIER_CMP3DE /*!< Timer compare 3 DMA request enable */ 01986 #define HRTIM_TIM_DMA_CMP4 HRTIM_TIMDIER_CMP4DE /*!< Timer compare 4 DMA request enable */ 01987 #define HRTIM_TIM_DMA_REP HRTIM_TIMDIER_REPDE /*!< Timer repetition DMA request enable */ 01988 #define HRTIM_TIM_DMA_UPD HRTIM_TIMDIER_UPDDE /*!< Timer update DMA request enable */ 01989 #define HRTIM_TIM_DMA_CPT1 HRTIM_TIMDIER_CPT1DE /*!< Timer capture 1 DMA request enable */ 01990 #define HRTIM_TIM_DMA_CPT2 HRTIM_TIMDIER_CPT2DE /*!< Timer capture 2 DMA request enable */ 01991 #define HRTIM_TIM_DMA_SET1 HRTIM_TIMDIER_SET1DE /*!< Timer output 1 set DMA request enable */ 01992 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */ 01993 #define HRTIM_TIM_DMA_SET2 HRTIM_TIMDIER_SET2DE /*!< Timer output 2 set DMA request enable */ 01994 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */ 01995 #define HRTIM_TIM_DMA_RST HRTIM_TIMDIER_RSTDE /*!< Timer reset DMA request enable */ 01996 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */ 01997 /** 01998 * @} 01999 */ 02000 02001 /** 02002 * @} 02003 */ 02004 02005 /* Private macros --------------------------------------------------------*/ 02006 /** @addtogroup HRTIM_Private_Macros 02007 * @{ 02008 */ 02009 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\ 02010 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \ 02011 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 02012 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 02013 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 02014 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 02015 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) 02016 02017 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\ 02018 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \ 02019 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \ 02020 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \ 02021 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \ 02022 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)) 02023 02024 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U) 02025 02026 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\ 02027 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \ 02028 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \ 02029 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \ 02030 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4)) 02031 02032 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\ 02033 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \ 02034 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2)) 02035 02036 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U) 02037 02038 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\ 02039 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 02040 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \ 02041 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \ 02042 || \ 02043 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 02044 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \ 02045 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \ 02046 || \ 02047 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 02048 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \ 02049 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \ 02050 || \ 02051 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 02052 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \ 02053 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \ 02054 || \ 02055 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 02056 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \ 02057 ((OUTPUT) == HRTIM_OUTPUT_TE2)))) 02058 02059 #define IS_HRTIM_EVENT(EVENT)\ 02060 (((EVENT) == HRTIM_EVENT_NONE)|| \ 02061 ((EVENT) == HRTIM_EVENT_1) || \ 02062 ((EVENT) == HRTIM_EVENT_2) || \ 02063 ((EVENT) == HRTIM_EVENT_3) || \ 02064 ((EVENT) == HRTIM_EVENT_4) || \ 02065 ((EVENT) == HRTIM_EVENT_5) || \ 02066 ((EVENT) == HRTIM_EVENT_6) || \ 02067 ((EVENT) == HRTIM_EVENT_7) || \ 02068 ((EVENT) == HRTIM_EVENT_8) || \ 02069 ((EVENT) == HRTIM_EVENT_9) || \ 02070 ((EVENT) == HRTIM_EVENT_10)) 02071 02072 #define IS_HRTIM_FAULT(FAULT)\ 02073 (((FAULT) == HRTIM_FAULT_1) || \ 02074 ((FAULT) == HRTIM_FAULT_2) || \ 02075 ((FAULT) == HRTIM_FAULT_3) || \ 02076 ((FAULT) == HRTIM_FAULT_4) || \ 02077 ((FAULT) == HRTIM_FAULT_5)) 02078 02079 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\ 02080 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \ 02081 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \ 02082 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4)) 02083 02084 #define IS_HRTIM_MODE(MODE)\ 02085 (((MODE) == HRTIM_MODE_CONTINUOUS) || \ 02086 ((MODE) == HRTIM_MODE_SINGLESHOT) || \ 02087 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 02088 02089 #define IS_HRTIM_MODE_ONEPULSE(MODE)\ 02090 (((MODE) == HRTIM_MODE_SINGLESHOT) || \ 02091 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE)) 02092 02093 02094 #define IS_HRTIM_HALFMODE(HALFMODE)\ 02095 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \ 02096 ((HALFMODE) == HRTIM_HALFMODE_ENABLED)) 02097 02098 #define IS_HRTIM_SYNCSTART(SYNCSTART)\ 02099 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \ 02100 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED)) 02101 02102 #define IS_HRTIM_SYNCRESET(SYNCRESET)\ 02103 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \ 02104 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED)) 02105 02106 #define IS_HRTIM_DACSYNC(DACSYNC)\ 02107 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \ 02108 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \ 02109 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \ 02110 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3)) 02111 02112 #define IS_HRTIM_PRELOAD(PRELOAD)\ 02113 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \ 02114 ((PRELOAD) == HRTIM_PRELOAD_ENABLED)) 02115 02116 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\ 02117 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 02118 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 02119 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)) 02120 02121 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\ 02122 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \ 02123 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \ 02124 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \ 02125 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \ 02126 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \ 02127 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \ 02128 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \ 02129 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \ 02130 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE)) 02131 02132 #define IS_HRTIM_TIMERBURSTMODE(MODE) \ 02133 (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \ 02134 ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER)) 02135 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \ 02136 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \ 02137 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED)) 02138 02139 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\ 02140 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \ 02141 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED)) 02142 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U) 02143 02144 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\ 02145 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \ 02146 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY)) 02147 02148 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\ 02149 ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \ 02150 ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \ 02151 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \ 02152 || \ 02153 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ 02154 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED))) 02155 02156 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\ 02157 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \ 02158 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \ 02159 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \ 02160 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \ 02161 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \ 02162 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \ 02163 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \ 02164 || \ 02165 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \ 02166 (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \ 02167 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7)))) 02168 02169 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U) 02170 02171 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U) 02172 02173 02174 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \ 02175 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \ 02176 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED)) 02177 02178 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\ 02179 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 02180 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 02181 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 02182 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)) 02183 02184 /* Auto delayed mode is only available for compare units 2 and 4U */ 02185 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \ 02186 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \ 02187 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 02188 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 02189 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 02190 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \ 02191 || \ 02192 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \ 02193 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \ 02194 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \ 02195 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \ 02196 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))) 02197 02198 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\ 02199 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \ 02200 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW)) 02201 02202 #define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU) 02203 02204 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\ 02205 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \ 02206 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \ 02207 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \ 02208 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \ 02209 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \ 02210 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \ 02211 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \ 02212 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \ 02213 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \ 02214 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \ 02215 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \ 02216 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \ 02217 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \ 02218 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \ 02219 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \ 02220 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \ 02221 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \ 02222 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \ 02223 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \ 02224 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \ 02225 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \ 02226 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \ 02227 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \ 02228 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \ 02229 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \ 02230 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \ 02231 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \ 02232 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \ 02233 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \ 02234 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \ 02235 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \ 02236 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE)) 02237 02238 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\ 02239 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \ 02240 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \ 02241 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \ 02242 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \ 02243 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \ 02244 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \ 02245 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \ 02246 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \ 02247 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \ 02248 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \ 02249 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \ 02250 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \ 02251 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \ 02252 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \ 02253 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \ 02254 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \ 02255 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \ 02256 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \ 02257 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \ 02258 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \ 02259 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \ 02260 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \ 02261 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \ 02262 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \ 02263 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \ 02264 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \ 02265 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \ 02266 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \ 02267 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \ 02268 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \ 02269 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \ 02270 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE)) 02271 02272 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\ 02273 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \ 02274 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE)) 02275 02276 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\ 02277 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \ 02278 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE)) 02279 02280 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\ 02281 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \ 02282 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \ 02283 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \ 02284 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ)) 02285 02286 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\ 02287 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \ 02288 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED)) 02289 02290 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\ 02291 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \ 02292 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED)) 02293 02294 02295 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \ 02296 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \ 02297 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \ 02298 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \ 02299 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \ 02300 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \ 02301 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \ 02302 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \ 02303 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \ 02304 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \ 02305 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \ 02306 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \ 02307 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \ 02308 || \ 02309 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \ 02310 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 02311 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 02312 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 02313 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 02314 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 02315 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 02316 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 02317 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 02318 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 02319 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 02320 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 02321 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 02322 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 02323 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 02324 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 02325 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 02326 || \ 02327 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \ 02328 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 02329 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 02330 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 02331 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 02332 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 02333 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 02334 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 02335 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 02336 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 02337 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 02338 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 02339 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 02340 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 02341 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 02342 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 02343 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 02344 || \ 02345 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \ 02346 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 02347 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 02348 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 02349 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 02350 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 02351 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 02352 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 02353 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 02354 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 02355 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 02356 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 02357 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \ 02358 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 02359 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 02360 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 02361 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 02362 || \ 02363 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \ 02364 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 02365 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 02366 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 02367 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 02368 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 02369 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 02370 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 02371 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 02372 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 02373 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 02374 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 02375 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 02376 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \ 02377 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \ 02378 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \ 02379 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \ 02380 || \ 02381 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \ 02382 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \ 02383 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \ 02384 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \ 02385 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \ 02386 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \ 02387 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \ 02388 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \ 02389 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \ 02390 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \ 02391 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \ 02392 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \ 02393 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \ 02394 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \ 02395 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \ 02396 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \ 02397 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))) 02398 02399 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\ 02400 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \ 02401 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \ 02402 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \ 02403 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \ 02404 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \ 02405 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \ 02406 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \ 02407 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \ 02408 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \ 02409 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \ 02410 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \ 02411 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \ 02412 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \ 02413 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \ 02414 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \ 02415 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM)) 02416 02417 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\ 02418 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \ 02419 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED)) 02420 02421 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\ 02422 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \ 02423 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \ 02424 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \ 02425 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \ 02426 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \ 02427 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \ 02428 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \ 02429 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16)) 02430 02431 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\ 02432 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \ 02433 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE)) 02434 02435 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\ 02436 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \ 02437 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY)) 02438 02439 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\ 02440 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \ 02441 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY)) 02442 02443 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\ 02444 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \ 02445 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE)) 02446 02447 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\ 02448 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \ 02449 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY)) 02450 02451 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\ 02452 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \ 02453 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY)) 02454 02455 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\ 02456 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \ 02457 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \ 02458 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \ 02459 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \ 02460 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \ 02461 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \ 02462 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \ 02463 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \ 02464 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \ 02465 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \ 02466 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \ 02467 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \ 02468 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \ 02469 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \ 02470 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \ 02471 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256)) 02472 02473 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\ 02474 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \ 02475 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \ 02476 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \ 02477 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \ 02478 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \ 02479 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \ 02480 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \ 02481 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875)) 02482 02483 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\ 02484 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \ 02485 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \ 02486 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \ 02487 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \ 02488 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \ 02489 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \ 02490 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \ 02491 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \ 02492 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \ 02493 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \ 02494 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \ 02495 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \ 02496 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \ 02497 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \ 02498 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \ 02499 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256)) 02500 02501 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\ 02502 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \ 02503 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \ 02504 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT)) 02505 02506 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\ 02507 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \ 02508 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \ 02509 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \ 02510 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1)) 02511 02512 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\ 02513 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \ 02514 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \ 02515 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE)) 02516 02517 #define IS_HRTIM_EVENTSRC(EVENTSRC)\ 02518 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \ 02519 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \ 02520 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \ 02521 ((EVENTSRC) == HRTIM_EVENTSRC_4)) 02522 02523 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\ 02524 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \ 02525 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \ 02526 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \ 02527 || \ 02528 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 02529 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \ 02530 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))) 02531 02532 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\ 02533 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \ 02534 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \ 02535 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \ 02536 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)) 02537 02538 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\ 02539 (((((EVENT) == HRTIM_EVENT_1) || \ 02540 ((EVENT) == HRTIM_EVENT_2) || \ 02541 ((EVENT) == HRTIM_EVENT_3) || \ 02542 ((EVENT) == HRTIM_EVENT_4) || \ 02543 ((EVENT) == HRTIM_EVENT_5)) && \ 02544 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \ 02545 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \ 02546 || \ 02547 (((EVENT) == HRTIM_EVENT_6) || \ 02548 ((EVENT) == HRTIM_EVENT_7) || \ 02549 ((EVENT) == HRTIM_EVENT_8) || \ 02550 ((EVENT) == HRTIM_EVENT_9) || \ 02551 ((EVENT) == HRTIM_EVENT_10))) 02552 02553 02554 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\ 02555 ((((EVENT) == HRTIM_EVENT_1) || \ 02556 ((EVENT) == HRTIM_EVENT_2) || \ 02557 ((EVENT) == HRTIM_EVENT_3) || \ 02558 ((EVENT) == HRTIM_EVENT_4) || \ 02559 ((EVENT) == HRTIM_EVENT_5)) \ 02560 || \ 02561 ((((EVENT) == HRTIM_EVENT_6) || \ 02562 ((EVENT) == HRTIM_EVENT_7) || \ 02563 ((EVENT) == HRTIM_EVENT_8) || \ 02564 ((EVENT) == HRTIM_EVENT_9) || \ 02565 ((EVENT) == HRTIM_EVENT_10)) && \ 02566 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \ 02567 ((FILTER) == HRTIM_EVENTFILTER_1) || \ 02568 ((FILTER) == HRTIM_EVENTFILTER_2) || \ 02569 ((FILTER) == HRTIM_EVENTFILTER_3) || \ 02570 ((FILTER) == HRTIM_EVENTFILTER_4) || \ 02571 ((FILTER) == HRTIM_EVENTFILTER_5) || \ 02572 ((FILTER) == HRTIM_EVENTFILTER_6) || \ 02573 ((FILTER) == HRTIM_EVENTFILTER_7) || \ 02574 ((FILTER) == HRTIM_EVENTFILTER_8) || \ 02575 ((FILTER) == HRTIM_EVENTFILTER_9) || \ 02576 ((FILTER) == HRTIM_EVENTFILTER_10) || \ 02577 ((FILTER) == HRTIM_EVENTFILTER_11) || \ 02578 ((FILTER) == HRTIM_EVENTFILTER_12) || \ 02579 ((FILTER) == HRTIM_EVENTFILTER_13) || \ 02580 ((FILTER) == HRTIM_EVENTFILTER_14) || \ 02581 ((FILTER) == HRTIM_EVENTFILTER_15)))) 02582 02583 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\ 02584 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \ 02585 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \ 02586 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \ 02587 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8)) 02588 02589 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\ 02590 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \ 02591 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL)) 02592 02593 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\ 02594 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \ 02595 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH)) 02596 02597 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\ 02598 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \ 02599 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED)) 02600 02601 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\ 02602 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \ 02603 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \ 02604 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \ 02605 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \ 02606 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \ 02607 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \ 02608 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \ 02609 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \ 02610 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \ 02611 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \ 02612 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \ 02613 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \ 02614 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \ 02615 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \ 02616 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \ 02617 ((FAULTFILTER) == HRTIM_FAULTFILTER_15)) 02618 02619 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\ 02620 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \ 02621 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY)) 02622 02623 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\ 02624 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \ 02625 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \ 02626 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \ 02627 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8)) 02628 02629 #define IS_HRTIM_BURSTMODE(BURSTMODE)\ 02630 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \ 02631 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS)) 02632 02633 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\ 02634 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \ 02635 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \ 02636 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \ 02637 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \ 02638 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \ 02639 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \ 02640 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \ 02641 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \ 02642 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \ 02643 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM)) 02644 02645 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\ 02646 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \ 02647 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \ 02648 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \ 02649 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \ 02650 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \ 02651 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \ 02652 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \ 02653 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \ 02654 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \ 02655 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \ 02656 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \ 02657 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \ 02658 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \ 02659 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \ 02660 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \ 02661 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768)) 02662 02663 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\ 02664 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \ 02665 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED)) 02666 02667 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\ 02668 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \ 02669 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \ 02670 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \ 02671 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \ 02672 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \ 02673 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \ 02674 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \ 02675 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \ 02676 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \ 02677 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \ 02678 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \ 02679 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \ 02680 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \ 02681 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \ 02682 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \ 02683 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \ 02684 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \ 02685 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \ 02686 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \ 02687 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \ 02688 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \ 02689 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \ 02690 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \ 02691 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \ 02692 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \ 02693 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \ 02694 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \ 02695 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \ 02696 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \ 02697 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \ 02698 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \ 02699 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP)) 02700 02701 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\ 02702 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \ 02703 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \ 02704 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \ 02705 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \ 02706 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \ 02707 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)) 02708 02709 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\ 02710 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \ 02711 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \ 02712 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \ 02713 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \ 02714 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14)) 02715 02716 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \ 02717 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \ 02718 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 02719 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 02720 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 02721 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \ 02722 || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U))) 02723 02724 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\ 02725 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \ 02726 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED)) 02727 02728 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U) 02729 02730 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U) 02731 02732 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U) 02733 02734 02735 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U) 02736 02737 02738 #define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U) 02739 02740 02741 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U) 02742 02743 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U) 02744 /** 02745 * @} 02746 */ 02747 02748 /* Exported macros -----------------------------------------------------------*/ 02749 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros 02750 * @{ 02751 */ 02752 02753 /** @brief Reset HRTIM handle state 02754 * @param __HANDLE__ HRTIM handle. 02755 * @retval None 02756 */ 02757 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 02758 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) do{ \ 02759 (__HANDLE__)->State = HAL_HRTIM_STATE_RESET; \ 02760 (__HANDLE__)->MspInitCallback = NULL; \ 02761 (__HANDLE__)->MspDeInitCallback = NULL; \ 02762 } while(0) 02763 #else 02764 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET) 02765 #endif 02766 02767 /** @brief Enables or disables the timer counter(s) 02768 * @param __HANDLE__ specifies the HRTIM Handle. 02769 * @param __TIMERS__ timers to enable/disable 02770 * This parameter can be any combinations of the following values: 02771 * @arg HRTIM_TIMERID_MASTER: Master timer identifier 02772 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier 02773 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier 02774 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier 02775 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier 02776 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier 02777 * @retval None 02778 */ 02779 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__)) 02780 02781 /* The counter of a timing unit is disabled only if all the timer outputs */ 02782 /* are disabled and no capture is configured */ 02783 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN) 02784 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN) 02785 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN) 02786 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN) 02787 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN) 02788 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\ 02789 do {\ 02790 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\ 02791 {\ 02792 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\ 02793 }\ 02794 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\ 02795 {\ 02796 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\ 02797 {\ 02798 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\ 02799 }\ 02800 }\ 02801 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\ 02802 {\ 02803 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\ 02804 {\ 02805 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\ 02806 }\ 02807 }\ 02808 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\ 02809 {\ 02810 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\ 02811 {\ 02812 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\ 02813 }\ 02814 }\ 02815 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\ 02816 {\ 02817 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\ 02818 {\ 02819 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\ 02820 }\ 02821 }\ 02822 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\ 02823 {\ 02824 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\ 02825 {\ 02826 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\ 02827 }\ 02828 }\ 02829 } while(0U) 02830 02831 02832 /** @brief Enables or disables the specified HRTIM common interrupts. 02833 * @param __HANDLE__ specifies the HRTIM Handle. 02834 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 02835 * This parameter can be one of the following values: 02836 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 02837 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 02838 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable 02839 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable 02840 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable 02841 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 02842 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 02843 * @retval None 02844 */ 02845 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__)) 02846 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__)) 02847 02848 /** @brief Enables or disables the specified HRTIM Master timer interrupts. 02849 * @param __HANDLE__ specifies the HRTIM Handle. 02850 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 02851 * This parameter can be one of the following values: 02852 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 02853 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 02854 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 02855 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 02856 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 02857 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 02858 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 02859 * @retval None 02860 */ 02861 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__)) 02862 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__)) 02863 02864 /** @brief Enables or disables the specified HRTIM Timerx interrupts. 02865 * @param __HANDLE__ specifies the HRTIM Handle. 02866 * @param __TIMER__ specified the timing unit (Timer A to E) 02867 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 02868 * This parameter can be one of the following values: 02869 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 02870 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 02871 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 02872 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 02873 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 02874 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 02875 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 02876 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 02877 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 02878 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 02879 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 02880 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 02881 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 02882 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 02883 * @retval None 02884 */ 02885 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__)) 02886 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__)) 02887 02888 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled. 02889 * @param __HANDLE__ specifies the HRTIM Handle. 02890 * @param __INTERRUPT__ specifies the interrupt source to check. 02891 * This parameter can be one of the following values: 02892 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable 02893 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable 02894 * @arg HRTIM_IT_FLT3: Fault 3 enable 02895 * @arg HRTIM_IT_FLT4: Fault 4 enable 02896 * @arg HRTIM_IT_FLT5: Fault 5 enable 02897 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable 02898 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable 02899 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 02900 */ 02901 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 02902 02903 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled. 02904 * @param __HANDLE__ specifies the HRTIM Handle. 02905 * @param __INTERRUPT__ specifies the interrupt source to check. 02906 * This parameter can be one of the following values: 02907 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 02908 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 02909 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 02910 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 02911 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 02912 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 02913 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 02914 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 02915 */ 02916 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 02917 02918 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled. 02919 * @param __HANDLE__ specifies the HRTIM Handle. 02920 * @param __TIMER__ specified the timing unit (Timer A to E) 02921 * @param __INTERRUPT__ specifies the interrupt source to check. 02922 * This parameter can be one of the following values: 02923 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable 02924 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable 02925 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable 02926 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable 02927 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable 02928 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable 02929 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable 02930 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable 02931 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable 02932 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable 02933 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable 02934 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable 02935 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable 02936 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable 02937 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable 02938 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable 02939 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable 02940 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable 02941 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable 02942 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable 02943 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable 02944 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 02945 */ 02946 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 02947 02948 /** @brief Clears the specified HRTIM common pending flag. 02949 * @param __HANDLE__ specifies the HRTIM Handle. 02950 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 02951 * This parameter can be one of the following values: 02952 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag 02953 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag 02954 * @arg HRTIM_IT_FLT3: Fault 3 clear flag 02955 * @arg HRTIM_IT_FLT4: Fault 4 clear flag 02956 * @arg HRTIM_IT_FLT5: Fault 5 clear flag 02957 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag 02958 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag 02959 * @retval None 02960 */ 02961 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__)) 02962 02963 /** @brief Clears the specified HRTIM Master pending flag. 02964 * @param __HANDLE__ specifies the HRTIM Handle. 02965 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 02966 * This parameter can be one of the following values: 02967 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag 02968 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag 02969 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag 02970 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag 02971 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag 02972 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag 02973 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag 02974 * @retval None 02975 */ 02976 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) 02977 02978 /** @brief Clears the specified HRTIM Timerx pending flag. 02979 * @param __HANDLE__ specifies the HRTIM Handle. 02980 * @param __TIMER__ specified the timing unit (Timer A to E) 02981 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. 02982 * This parameter can be one of the following values: 02983 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag 02984 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag 02985 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag 02986 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag 02987 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag 02988 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag 02989 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag 02990 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag 02991 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag 02992 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag 02993 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag 02994 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag 02995 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag 02996 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag 02997 * @retval None 02998 */ 02999 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__)) 03000 03001 /* DMA HANDLING */ 03002 /** @brief Enables or disables the specified HRTIM Master timer DMA requests. 03003 * @param __HANDLE__ specifies the HRTIM Handle. 03004 * @param __DMA__ specifies the DMA request to enable or disable. 03005 * This parameter can be one of the following values: 03006 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable 03007 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable 03008 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable 03009 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable 03010 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable 03011 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable 03012 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable 03013 * @retval None 03014 */ 03015 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__)) 03016 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__)) 03017 03018 /** @brief Enables or disables the specified HRTIM Timerx DMA requests. 03019 * @param __HANDLE__ specifies the HRTIM Handle. 03020 * @param __TIMER__ specified the timing unit (Timer A to E) 03021 * @param __DMA__ specifies the DMA request to enable or disable. 03022 * This parameter can be one of the following values: 03023 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable 03024 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable 03025 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable 03026 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable 03027 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable 03028 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable 03029 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable 03030 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable 03031 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable 03032 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable 03033 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable 03034 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable 03035 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable 03036 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable 03037 * @retval None 03038 */ 03039 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__)) 03040 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__)) 03041 03042 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__)) 03043 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__)) 03044 03045 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__)) 03046 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__)) 03047 03048 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__)) 03049 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__)) 03050 03051 /** @brief Sets the HRTIM timer Counter Register value on runtime 03052 * @param __HANDLE__ HRTIM Handle. 03053 * @param __TIMER__ HRTIM timer 03054 * This parameter can be one of the following values: 03055 * @arg 0x5 for master timer 03056 * @arg 0x0 to 0x4 for timers A to E 03057 * @param __COUNTER__ specifies the Counter Register new value. 03058 * @retval None 03059 */ 03060 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \ 03061 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\ 03062 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__))) 03063 03064 /** @brief Gets the HRTIM timer Counter Register value on runtime 03065 * @param __HANDLE__ HRTIM Handle. 03066 * @param __TIMER__ HRTIM timer 03067 * This parameter can be one of the following values: 03068 * @arg 0x5 for master timer 03069 * @arg 0x0 to 0x4 for timers A to E 03070 * @retval HRTIM timer Counter Register value 03071 */ 03072 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \ 03073 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\ 03074 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR)) 03075 03076 /** @brief Sets the HRTIM timer Period value on runtime 03077 * @param __HANDLE__ HRTIM Handle. 03078 * @param __TIMER__ HRTIM timer 03079 * This parameter can be one of the following values: 03080 * @arg 0x5 for master timer 03081 * @arg 0x0 to 0x4 for timers A to E 03082 * @param __PERIOD__ specifies the Period Register new value. 03083 * @retval None 03084 */ 03085 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \ 03086 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\ 03087 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__))) 03088 03089 /** @brief Gets the HRTIM timer Period Register value on runtime 03090 * @param __HANDLE__ HRTIM Handle. 03091 * @param __TIMER__ HRTIM timer 03092 * This parameter can be one of the following values: 03093 * @arg 0x5 for master timer 03094 * @arg 0x0 to 0x4 for timers A to E 03095 * @retval timer Period Register 03096 */ 03097 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \ 03098 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\ 03099 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR)) 03100 03101 /** @brief Sets the HRTIM timer clock prescaler value on runtime 03102 * @param __HANDLE__ HRTIM Handle. 03103 * @param __TIMER__ HRTIM timer 03104 * This parameter can be one of the following values: 03105 * @arg 0x5 for master timer 03106 * @arg 0x0 to 0x4 for timers A to E 03107 * @param __PRESCALER__ specifies the clock prescaler new value. 03108 * This parameter can be one of the following values: 03109 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) 03110 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) 03111 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) 03112 * @retval None 03113 */ 03114 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \ 03115 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\ 03116 (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__)))) 03117 03118 /** @brief Gets the HRTIM timer clock prescaler value on runtime 03119 * @param __HANDLE__ HRTIM Handle. 03120 * @param __TIMER__ HRTIM timer 03121 * This parameter can be one of the following values: 03122 * @arg 0x5 for master timer 03123 * @arg 0x0 to 0x4 for timers A to E 03124 * @retval timer clock prescaler value 03125 */ 03126 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \ 03127 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\ 03128 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC)) 03129 03130 /** @brief Sets the HRTIM timer Compare Register value on runtime 03131 * @param __HANDLE__ HRTIM Handle. 03132 * @param __TIMER__ HRTIM timer 03133 * This parameter can be one of the following values: 03134 * @arg 0x0 to 0x4 for timers A to E 03135 * @param __COMPAREUNIT__ timer compare unit 03136 * This parameter can be one of the following values: 03137 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 03138 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 03139 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 03140 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 03141 * @param __COMPARE__ specifies the Compare new value. 03142 * @retval None 03143 */ 03144 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \ 03145 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 03146 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\ 03147 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\ 03148 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\ 03149 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \ 03150 : \ 03151 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\ 03152 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\ 03153 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\ 03154 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__)))) 03155 03156 /** @brief Gets the HRTIM timer Compare Register value on runtime 03157 * @param __HANDLE__ HRTIM Handle. 03158 * @param __TIMER__ HRTIM timer 03159 * This parameter can be one of the following values: 03160 * @arg 0x0 to 0x4 for timers A to E 03161 * @param __COMPAREUNIT__ timer compare unit 03162 * This parameter can be one of the following values: 03163 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1 03164 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2 03165 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3 03166 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4 03167 * @retval Compare value 03168 */ 03169 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \ 03170 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \ 03171 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\ 03172 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\ 03173 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\ 03174 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \ 03175 : \ 03176 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\ 03177 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\ 03178 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\ 03179 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR))) 03180 03181 /** 03182 * @} 03183 */ 03184 03185 /* Exported functions --------------------------------------------------------*/ 03186 /** @addtogroup HRTIM_Exported_Functions 03187 * @{ 03188 */ 03189 03190 /** @addtogroup HRTIM_Exported_Functions_Group1 03191 * @{ 03192 */ 03193 03194 /* Initialization and Configuration functions ********************************/ 03195 HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim); 03196 03197 HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim); 03198 03199 void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim); 03200 03201 void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim); 03202 03203 HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim, 03204 uint32_t TimerIdx, 03205 HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg); 03206 /** 03207 * @} 03208 */ 03209 03210 /** @addtogroup HRTIM_Exported_Functions_Group2 03211 * @{ 03212 */ 03213 03214 /* Simple time base related functions *****************************************/ 03215 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim, 03216 uint32_t TimerIdx); 03217 03218 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim, 03219 uint32_t TimerIdx); 03220 03221 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim, 03222 uint32_t TimerIdx); 03223 03224 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim, 03225 uint32_t TimerIdx); 03226 03227 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim, 03228 uint32_t TimerIdx, 03229 uint32_t SrcAddr, 03230 uint32_t DestAddr, 03231 uint32_t Length); 03232 03233 HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim, 03234 uint32_t TimerIdx); 03235 03236 /** 03237 * @} 03238 */ 03239 03240 /** @addtogroup HRTIM_Exported_Functions_Group3 03241 * @{ 03242 */ 03243 /* Simple output compare related functions ************************************/ 03244 HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim, 03245 uint32_t TimerIdx, 03246 uint32_t OCChannel, 03247 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg); 03248 03249 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim, 03250 uint32_t TimerIdx, 03251 uint32_t OCChannel); 03252 03253 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim, 03254 uint32_t TimerIdx, 03255 uint32_t OCChannel); 03256 03257 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim, 03258 uint32_t TimerIdx, 03259 uint32_t OCChannel); 03260 03261 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim, 03262 uint32_t TimerIdx, 03263 uint32_t OCChannel); 03264 03265 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim, 03266 uint32_t TimerIdx, 03267 uint32_t OCChannel, 03268 uint32_t SrcAddr, 03269 uint32_t DestAddr, 03270 uint32_t Length); 03271 03272 HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim, 03273 uint32_t TimerIdx, 03274 uint32_t OCChannel); 03275 03276 /** 03277 * @} 03278 */ 03279 03280 /** @addtogroup HRTIM_Exported_Functions_Group4 03281 * @{ 03282 */ 03283 /* Simple PWM output related functions ****************************************/ 03284 HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim, 03285 uint32_t TimerIdx, 03286 uint32_t PWMChannel, 03287 HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg); 03288 03289 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim, 03290 uint32_t TimerIdx, 03291 uint32_t PWMChannel); 03292 03293 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim, 03294 uint32_t TimerIdx, 03295 uint32_t PWMChannel); 03296 03297 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim, 03298 uint32_t TimerIdx, 03299 uint32_t PWMChannel); 03300 03301 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim, 03302 uint32_t TimerIdx, 03303 uint32_t PWMChannel); 03304 03305 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim, 03306 uint32_t TimerIdx, 03307 uint32_t PWMChannel, 03308 uint32_t SrcAddr, 03309 uint32_t DestAddr, 03310 uint32_t Length); 03311 03312 HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim, 03313 uint32_t TimerIdx, 03314 uint32_t PWMChannel); 03315 03316 /** 03317 * @} 03318 */ 03319 03320 /** @addtogroup HRTIM_Exported_Functions_Group5 03321 * @{ 03322 */ 03323 /* Simple capture related functions *******************************************/ 03324 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim, 03325 uint32_t TimerIdx, 03326 uint32_t CaptureChannel, 03327 HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg); 03328 03329 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim, 03330 uint32_t TimerIdx, 03331 uint32_t CaptureChannel); 03332 03333 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim, 03334 uint32_t TimerIdx, 03335 uint32_t CaptureChannel); 03336 03337 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim, 03338 uint32_t TimerIdx, 03339 uint32_t CaptureChannel); 03340 03341 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim, 03342 uint32_t TimerIdx, 03343 uint32_t CaptureChannel); 03344 03345 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim, 03346 uint32_t TimerIdx, 03347 uint32_t CaptureChannel, 03348 uint32_t SrcAddr, 03349 uint32_t DestAddr, 03350 uint32_t Length); 03351 03352 HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim, 03353 uint32_t TimerIdx, 03354 uint32_t CaptureChannel); 03355 03356 /** 03357 * @} 03358 */ 03359 03360 /** @addtogroup HRTIM_Exported_Functions_Group6 03361 * @{ 03362 */ 03363 /* Simple one pulse related functions *****************************************/ 03364 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim, 03365 uint32_t TimerIdx, 03366 uint32_t OnePulseChannel, 03367 HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg); 03368 03369 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim, 03370 uint32_t TimerIdx, 03371 uint32_t OnePulseChannel); 03372 03373 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim, 03374 uint32_t TimerIdx, 03375 uint32_t OnePulseChannel); 03376 03377 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim, 03378 uint32_t TimerIdx, 03379 uint32_t OnePulseChannel); 03380 03381 HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim, 03382 uint32_t TimerIdx, 03383 uint32_t OnePulseChannel); 03384 03385 /** 03386 * @} 03387 */ 03388 03389 /** @addtogroup HRTIM_Exported_Functions_Group7 03390 * @{ 03391 */ 03392 HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim, 03393 HRTIM_BurstModeCfgTypeDef* pBurstModeCfg); 03394 03395 HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim, 03396 uint32_t Event, 03397 HRTIM_EventCfgTypeDef* pEventCfg); 03398 03399 HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 03400 uint32_t Prescaler); 03401 03402 HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim, 03403 uint32_t Fault, 03404 HRTIM_FaultCfgTypeDef* pFaultCfg); 03405 03406 HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim, 03407 uint32_t Prescaler); 03408 03409 void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim, 03410 uint32_t Faults, 03411 uint32_t Enable); 03412 03413 HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim, 03414 uint32_t ADCTrigger, 03415 HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg); 03416 03417 /** 03418 * @} 03419 */ 03420 03421 /** @addtogroup HRTIM_Exported_Functions_Group8 03422 * @{ 03423 */ 03424 /* Waveform related functions *************************************************/ 03425 HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim, 03426 uint32_t TimerIdx, 03427 HRTIM_TimerCfgTypeDef * pTimerCfg); 03428 03429 HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim, 03430 uint32_t TimerIdx, 03431 uint32_t CompareUnit, 03432 HRTIM_CompareCfgTypeDef* pCompareCfg); 03433 03434 HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim, 03435 uint32_t TimerIdx, 03436 uint32_t CaptureUnit, 03437 HRTIM_CaptureCfgTypeDef* pCaptureCfg); 03438 03439 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim, 03440 uint32_t TimerIdx, 03441 uint32_t Output, 03442 HRTIM_OutputCfgTypeDef * pOutputCfg); 03443 03444 HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim, 03445 uint32_t TimerIdx, 03446 uint32_t Output, 03447 uint32_t OutputLevel); 03448 03449 HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim, 03450 uint32_t TimerIdx, 03451 uint32_t Event, 03452 HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg); 03453 03454 HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim, 03455 uint32_t TimerIdx, 03456 HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg); 03457 03458 HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim, 03459 uint32_t TimerIdx, 03460 HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg); 03461 03462 HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim, 03463 uint32_t TimerIdx, 03464 uint32_t RegistersToUpdate); 03465 03466 03467 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim, 03468 uint32_t Timers); 03469 03470 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim, 03471 uint32_t Timers); 03472 03473 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim, 03474 uint32_t Timers); 03475 03476 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim, 03477 uint32_t Timers); 03478 03479 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim, 03480 uint32_t Timers); 03481 03482 HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim, 03483 uint32_t Timers); 03484 03485 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim, 03486 uint32_t OutputsToStart); 03487 03488 HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim, 03489 uint32_t OutputsToStop); 03490 03491 HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim, 03492 uint32_t Enable); 03493 03494 HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim); 03495 03496 HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim, 03497 uint32_t TimerIdx, 03498 uint32_t CaptureUnit); 03499 03500 HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim, 03501 uint32_t Timers); 03502 03503 HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim, 03504 uint32_t Timers); 03505 03506 HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim, 03507 uint32_t TimerIdx, 03508 uint32_t BurstBufferAddress, 03509 uint32_t BurstBufferLength); 03510 03511 HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim, 03512 uint32_t Timers); 03513 03514 HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim, 03515 uint32_t Timers); 03516 03517 /** 03518 * @} 03519 */ 03520 03521 /** @addtogroup HRTIM_Exported_Functions_Group9 03522 * @{ 03523 */ 03524 /* HRTIM peripheral state functions */ 03525 HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim); 03526 03527 uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim, 03528 uint32_t TimerIdx, 03529 uint32_t CaptureUnit); 03530 03531 uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim, 03532 uint32_t TimerIdx, 03533 uint32_t Output); 03534 03535 uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim, 03536 uint32_t TimerIdx, 03537 uint32_t Output); 03538 03539 uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim, 03540 uint32_t TimerIdx, 03541 uint32_t Output); 03542 03543 uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim); 03544 03545 uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim, 03546 uint32_t TimerIdx); 03547 03548 uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim, 03549 uint32_t TimerIdx); 03550 03551 /** 03552 * @} 03553 */ 03554 03555 /** @addtogroup HRTIM_Exported_Functions_Group10 03556 * @{ 03557 */ 03558 /* IRQ handler */ 03559 void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim, 03560 uint32_t TimerIdx); 03561 03562 /* HRTIM events related callback functions */ 03563 void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim); 03564 void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim); 03565 void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim); 03566 void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim); 03567 void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim); 03568 void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim); 03569 void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim); 03570 void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim); 03571 03572 /* Timer events related callback functions */ 03573 void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim, 03574 uint32_t TimerIdx); 03575 void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim, 03576 uint32_t TimerIdx); 03577 void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim, 03578 uint32_t TimerIdx); 03579 void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim, 03580 uint32_t TimerIdx); 03581 void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim, 03582 uint32_t TimerIdx); 03583 void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim, 03584 uint32_t TimerIdx); 03585 void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim, 03586 uint32_t TimerIdx); 03587 void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim, 03588 uint32_t TimerIdx); 03589 void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim, 03590 uint32_t TimerIdx); 03591 void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim, 03592 uint32_t TimerIdx); 03593 void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim, 03594 uint32_t TimerIdx); 03595 void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim, 03596 uint32_t TimerIdx); 03597 void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim, 03598 uint32_t TimerIdx); 03599 void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim, 03600 uint32_t TimerIdx); 03601 void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim, 03602 uint32_t TimerIdx); 03603 void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim); 03604 03605 #if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1) 03606 HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef * hhrtim, 03607 HAL_HRTIM_CallbackIDTypeDef CallbackID, 03608 pHRTIM_CallbackTypeDef pCallback); 03609 03610 HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 03611 HAL_HRTIM_CallbackIDTypeDef CallbackID); 03612 03613 HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 03614 HAL_HRTIM_CallbackIDTypeDef CallbackID, 03615 pHRTIM_TIMxCallbackTypeDef pCallback); 03616 03617 HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef * hhrtim, 03618 HAL_HRTIM_CallbackIDTypeDef CallbackID); 03619 #endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */ 03620 03621 /** 03622 * @} 03623 */ 03624 03625 /** 03626 * @} 03627 */ 03628 03629 /** 03630 * @} 03631 */ 03632 03633 /** 03634 * @} 03635 */ 03636 03637 #endif /* HRTIM1 */ 03638 03639 #ifdef __cplusplus 03640 } 03641 #endif 03642 03643 #endif /* STM32H7xx_HAL_HRTIM_H */
1.7.6.1