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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_nand.h 00004 * @author MCD Application Team 00005 * @brief Header file of NAND HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_NAND_H 00021 #define STM32H7xx_HAL_NAND_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 00028 /* Includes ------------------------------------------------------------------*/ 00029 #include "stm32h7xx_ll_fmc.h" 00030 00031 /** @addtogroup STM32H7xx_HAL_Driver 00032 * @{ 00033 */ 00034 00035 /** @addtogroup NAND 00036 * @{ 00037 */ 00038 00039 /* Exported typedef ----------------------------------------------------------*/ 00040 /* Exported types ------------------------------------------------------------*/ 00041 /** @defgroup NAND_Exported_Types NAND Exported Types 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief HAL NAND State structures definition 00047 */ 00048 typedef enum 00049 { 00050 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 00051 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 00052 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 00053 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 00054 } HAL_NAND_StateTypeDef; 00055 00056 /** 00057 * @brief NAND Memory electronic signature Structure definition 00058 */ 00059 typedef struct 00060 { 00061 /*<! NAND memory electronic signature maker and device IDs */ 00062 00063 uint8_t Maker_Id; 00064 00065 uint8_t Device_Id; 00066 00067 uint8_t Third_Id; 00068 00069 uint8_t Fourth_Id; 00070 } NAND_IDTypeDef; 00071 00072 /** 00073 * @brief NAND Memory address Structure definition 00074 */ 00075 typedef struct 00076 { 00077 uint16_t Page; /*!< NAND memory Page address */ 00078 00079 uint16_t Plane; /*!< NAND memory Zone address */ 00080 00081 uint16_t Block; /*!< NAND memory Block address */ 00082 00083 } NAND_AddressTypeDef; 00084 00085 /** 00086 * @brief NAND Memory info Structure definition 00087 */ 00088 typedef struct 00089 { 00090 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 00091 for 8 bits addressing or words for 16 bits addressing */ 00092 00093 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 00094 for 8 bits addressing or words for 16 bits addressing */ 00095 00096 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 00097 00098 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 00099 00100 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 00101 00102 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 00103 00104 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 00105 parameter is mandatory for some NAND parts after the read 00106 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 00107 Example: Toshiba THTH58BYG3S0HBAI6. 00108 This parameter could be ENABLE or DISABLE 00109 Please check the Read Mode sequnece in the NAND device datasheet */ 00110 } NAND_DeviceConfigTypeDef; 00111 00112 /** 00113 * @brief NAND handle Structure definition 00114 */ 00115 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00116 typedef struct __NAND_HandleTypeDef 00117 #else 00118 typedef struct 00119 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00120 { 00121 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 00122 00123 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 00124 00125 HAL_LockTypeDef Lock; /*!< NAND locking object */ 00126 00127 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 00128 00129 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ 00130 00131 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00132 void (* MspInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp Init callback */ 00133 void (* MspDeInitCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND Msp DeInit callback */ 00134 void (* ItCallback)(struct __NAND_HandleTypeDef *hnand); /*!< NAND IT callback */ 00135 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00136 } NAND_HandleTypeDef; 00137 00138 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00139 /** 00140 * @brief HAL NAND Callback ID enumeration definition 00141 */ 00142 typedef enum 00143 { 00144 HAL_NAND_MSP_INIT_CB_ID = 0x00U, /*!< NAND MspInit Callback ID */ 00145 HAL_NAND_MSP_DEINIT_CB_ID = 0x01U, /*!< NAND MspDeInit Callback ID */ 00146 HAL_NAND_IT_CB_ID = 0x02U /*!< NAND IT Callback ID */ 00147 } HAL_NAND_CallbackIDTypeDef; 00148 00149 /** 00150 * @brief HAL NAND Callback pointer definition 00151 */ 00152 typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand); 00153 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00154 00155 /** 00156 * @} 00157 */ 00158 00159 /* Exported constants --------------------------------------------------------*/ 00160 /* Exported macro ------------------------------------------------------------*/ 00161 /** @defgroup NAND_Exported_Macros NAND Exported Macros 00162 * @{ 00163 */ 00164 00165 /** @brief Reset NAND handle state 00166 * @param __HANDLE__ specifies the NAND handle. 00167 * @retval None 00168 */ 00169 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00170 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) do { \ 00171 (__HANDLE__)->State = HAL_NAND_STATE_RESET; \ 00172 (__HANDLE__)->MspInitCallback = NULL; \ 00173 (__HANDLE__)->MspDeInitCallback = NULL; \ 00174 } while(0) 00175 #else 00176 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 00177 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00178 00179 /** 00180 * @} 00181 */ 00182 00183 /* Exported functions --------------------------------------------------------*/ 00184 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 00185 * @{ 00186 */ 00187 00188 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 00189 * @{ 00190 */ 00191 00192 /* Initialization/de-initialization functions ********************************/ 00193 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, 00194 FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 00195 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 00196 00197 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 00198 00199 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 00200 00201 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 00202 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 00203 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 00204 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 00205 00206 /** 00207 * @} 00208 */ 00209 00210 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 00211 * @{ 00212 */ 00213 00214 /* IO operation functions ****************************************************/ 00215 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 00216 00217 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 00218 uint32_t NumPageToRead); 00219 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, 00220 uint32_t NumPageToWrite); 00221 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00222 uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 00223 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00224 uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 00225 00226 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 00227 uint32_t NumPageToRead); 00228 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, 00229 uint32_t NumPageToWrite); 00230 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00231 uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 00232 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, 00233 uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 00234 00235 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00236 00237 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00238 00239 #if (USE_HAL_NAND_REGISTER_CALLBACKS == 1) 00240 /* NAND callback registering/unregistering */ 00241 HAL_StatusTypeDef HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, 00242 pNAND_CallbackTypeDef pCallback); 00243 HAL_StatusTypeDef HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId); 00244 #endif /* USE_HAL_NAND_REGISTER_CALLBACKS */ 00245 00246 /** 00247 * @} 00248 */ 00249 00250 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 00251 * @{ 00252 */ 00253 00254 /* NAND Control functions ****************************************************/ 00255 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 00256 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 00257 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 00258 00259 /** 00260 * @} 00261 */ 00262 00263 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 00264 * @{ 00265 */ 00266 /* NAND State functions *******************************************************/ 00267 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); 00268 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); 00269 /** 00270 * @} 00271 */ 00272 00273 /** 00274 * @} 00275 */ 00276 00277 /* Private types -------------------------------------------------------------*/ 00278 /* Private variables ---------------------------------------------------------*/ 00279 /* Private constants ---------------------------------------------------------*/ 00280 /** @defgroup NAND_Private_Constants NAND Private Constants 00281 * @{ 00282 */ 00283 #define NAND_DEVICE 0x80000000UL 00284 #define NAND_WRITE_TIMEOUT 0x01000000UL 00285 00286 #define CMD_AREA (1UL<<16U) /* A16 = CLE high */ 00287 #define ADDR_AREA (1UL<<17U) /* A17 = ALE high */ 00288 00289 #define NAND_CMD_AREA_A ((uint8_t)0x00) 00290 #define NAND_CMD_AREA_B ((uint8_t)0x01) 00291 #define NAND_CMD_AREA_C ((uint8_t)0x50) 00292 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30) 00293 00294 #define NAND_CMD_WRITE0 ((uint8_t)0x80) 00295 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10) 00296 #define NAND_CMD_ERASE0 ((uint8_t)0x60) 00297 #define NAND_CMD_ERASE1 ((uint8_t)0xD0) 00298 #define NAND_CMD_READID ((uint8_t)0x90) 00299 #define NAND_CMD_STATUS ((uint8_t)0x70) 00300 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A) 00301 #define NAND_CMD_RESET ((uint8_t)0xFF) 00302 00303 /* NAND memory status */ 00304 #define NAND_VALID_ADDRESS 0x00000100UL 00305 #define NAND_INVALID_ADDRESS 0x00000200UL 00306 #define NAND_TIMEOUT_ERROR 0x00000400UL 00307 #define NAND_BUSY 0x00000000UL 00308 #define NAND_ERROR 0x00000001UL 00309 #define NAND_READY 0x00000040UL 00310 /** 00311 * @} 00312 */ 00313 00314 /* Private macros ------------------------------------------------------------*/ 00315 /** @defgroup NAND_Private_Macros NAND Private Macros 00316 * @{ 00317 */ 00318 00319 /** 00320 * @brief NAND memory address computation. 00321 * @param __ADDRESS__ NAND memory address. 00322 * @param __HANDLE__ NAND handle. 00323 * @retval NAND Raw address value 00324 */ 00325 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ 00326 (((__ADDRESS__)->Block + \ 00327 (((__ADDRESS__)->Plane) * \ 00328 ((__HANDLE__)->Config.PlaneSize))) * \ 00329 ((__HANDLE__)->Config.BlockSize))) 00330 00331 /** 00332 * @brief NAND memory Column address computation. 00333 * @param __HANDLE__ NAND handle. 00334 * @retval NAND Raw address value 00335 */ 00336 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 00337 00338 /** 00339 * @brief NAND memory address cycling. 00340 * @param __ADDRESS__ NAND memory address. 00341 * @retval NAND address cycling value. 00342 */ 00343 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 00344 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 00345 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 00346 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 00347 00348 /** 00349 * @brief NAND memory Columns cycling. 00350 * @param __ADDRESS__ NAND memory address. 00351 * @retval NAND Column address cycling value. 00352 */ 00353 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) & 0xFFU) /* 1st Column addressing cycle */ 00354 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 00355 00356 /** 00357 * @} 00358 */ 00359 00360 /** 00361 * @} 00362 */ 00363 00364 /** 00365 * @} 00366 */ 00367 00368 /** 00369 * @} 00370 */ 00371 00372 00373 #ifdef __cplusplus 00374 } 00375 #endif 00376 00377 #endif /* STM32H7xx_HAL_NAND_H */
1.7.6.1