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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_pwr.h 00004 * @author MCD Application Team 00005 * @brief Header file of PWR HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_PWR_H 00021 #define STM32H7xx_HAL_PWR_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif /* __cplusplus */ 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 /** @addtogroup STM32H7xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup PWR 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 00040 /** @defgroup PWR_Exported_Types PWR Exported Types 00041 * @{ 00042 */ 00043 00044 /** 00045 * @brief PWR PVD configuration structure definition 00046 */ 00047 typedef struct 00048 { 00049 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This 00050 parameter can be a value of @ref 00051 PWR_PVD_detection_level. 00052 */ 00053 00054 uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the PVD 00055 event. This parameter can be a value of @ref 00056 PWR_PVD_Mode. 00057 */ 00058 }PWR_PVDTypeDef; 00059 00060 /** 00061 * @} 00062 */ 00063 00064 /* Exported constants --------------------------------------------------------*/ 00065 /** @defgroup PWR_Exported_Constants PWR Exported Constants 00066 * @{ 00067 */ 00068 00069 /** @defgroup PWR_PVD_detection_level PWR PVD detection level 00070 * @{ 00071 */ 00072 #define PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Programmable voltage detector 00073 level 0 selection : 1V95 */ 00074 #define PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Programmable voltage detector 00075 level 1 selection : 2V1 */ 00076 #define PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Programmable voltage detector 00077 level 2 selection : 2V25 */ 00078 #define PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Programmable voltage detector 00079 level 3 selection : 2V4 */ 00080 #define PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Programmable voltage detector 00081 level 4 selection : 2V55 */ 00082 #define PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Programmable voltage detector 00083 level 5 selection : 2V7 */ 00084 #define PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Programmable voltage detector 00085 level 6 selection : 2V85 */ 00086 #define PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External input analog voltage 00087 (Compare internally to VREF) */ 00088 /** 00089 * @} 00090 */ 00091 00092 /** @defgroup PWR_PVD_Mode PWR PVD Mode 00093 * @{ 00094 */ 00095 #define PWR_PVD_MODE_NORMAL (0x00000000U) /*!< Basic mode is used */ 00096 #define PWR_PVD_MODE_IT_RISING (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection */ 00097 #define PWR_PVD_MODE_IT_FALLING (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection */ 00098 #define PWR_PVD_MODE_IT_RISING_FALLING (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */ 00099 #define PWR_PVD_MODE_EVENT_RISING (0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 00100 #define PWR_PVD_MODE_EVENT_FALLING (0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 00101 #define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 00102 /** 00103 * @} 00104 */ 00105 00106 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode 00107 * @{ 00108 */ 00109 #define PWR_MAINREGULATOR_ON (0U) 00110 #define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS 00111 /** 00112 * @} 00113 */ 00114 00115 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 00116 * @{ 00117 */ 00118 #define PWR_SLEEPENTRY_WFI (0x01U) 00119 #define PWR_SLEEPENTRY_WFE (0x02U) 00120 /** 00121 * @} 00122 */ 00123 00124 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 00125 * @{ 00126 */ 00127 #define PWR_STOPENTRY_WFI (0x01U) 00128 #define PWR_STOPENTRY_WFE (0x02U) 00129 /** 00130 * @} 00131 */ 00132 00133 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale 00134 * @{ 00135 */ 00136 #if defined(PWR_SRDCR_VOS) 00137 #define PWR_REGULATOR_VOLTAGE_SCALE0 (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0) 00138 #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_SRDCR_VOS_1) 00139 #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_SRDCR_VOS_0) 00140 #define PWR_REGULATOR_VOLTAGE_SCALE3 (0U) 00141 #else 00142 #define PWR_REGULATOR_VOLTAGE_SCALE0 (0U) 00143 #define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0) 00144 #define PWR_REGULATOR_VOLTAGE_SCALE2 (PWR_D3CR_VOS_1) 00145 #define PWR_REGULATOR_VOLTAGE_SCALE3 (PWR_D3CR_VOS_0) 00146 #endif /* PWR_SRDCR_VOS */ 00147 /** 00148 * @} 00149 */ 00150 00151 /** @defgroup PWR_Flag PWR Flag 00152 * @{ 00153 */ 00154 /* PWR CPU flag */ 00155 #define PWR_FLAG_STOP (0x01U) 00156 #if defined (PWR_CPUCR_SBF_D2) 00157 #define PWR_FLAG_SB_D1 (0x02U) 00158 #define PWR_FLAG_SB_D2 (0x03U) 00159 #endif /* defined (PWR_CPUCR_SBF_D2) */ 00160 #define PWR_FLAG_SB (0x04U) 00161 #if defined (DUAL_CORE) 00162 #define PWR_FLAG_CPU_HOLD (0x05U) 00163 #define PWR_FLAG_CPU2_HOLD (0x06U) 00164 #define PWR_FLAG2_STOP (0x07U) 00165 #define PWR_FLAG2_SB_D1 (0x08U) 00166 #define PWR_FLAG2_SB_D2 (0x09U) 00167 #define PWR_FLAG2_SB (0x0AU) 00168 #endif /* defined (DUAL_CORE) */ 00169 #define PWR_FLAG_PVDO (0x0BU) 00170 #define PWR_FLAG_AVDO (0x0CU) 00171 #define PWR_FLAG_ACTVOSRDY (0x0DU) 00172 #define PWR_FLAG_ACTVOS (0x0EU) 00173 #define PWR_FLAG_BRR (0x0FU) 00174 #define PWR_FLAG_VOSRDY (0x10U) 00175 #if defined (SMPS) 00176 #define PWR_FLAG_SMPSEXTRDY (0x11U) 00177 #else 00178 #define PWR_FLAG_SCUEN (0x11U) 00179 #endif /* defined (SMPS) */ 00180 #if defined (PWR_CSR1_MMCVDO) 00181 #define PWR_FLAG_MMCVDO (0x12U) 00182 #endif /* defined (PWR_CSR1_MMCVDO) */ 00183 #define PWR_FLAG_USB33RDY (0x13U) 00184 #define PWR_FLAG_TEMPH (0x14U) 00185 #define PWR_FLAG_TEMPL (0x15U) 00186 #define PWR_FLAG_VBATH (0x16U) 00187 #define PWR_FLAG_VBATL (0x17U) 00188 00189 /* PWR Wake up flag */ 00190 #define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1 00191 #define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2 00192 #define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3 00193 #define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4 00194 #define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5 00195 #define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6 00196 /** 00197 * @} 00198 */ 00199 00200 /** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask 00201 * @{ 00202 */ 00203 #define PWR_EWUP_MASK (0x0FFF3F3FU) 00204 /** 00205 * @} 00206 */ 00207 00208 /** 00209 * @} 00210 */ 00211 /* Exported macro ------------------------------------------------------------*/ 00212 /** @defgroup PWR_Exported_Macro PWR Exported Macro 00213 * @{ 00214 */ 00215 00216 /** @brief Configure the main internal regulator output voltage. 00217 * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a 00218 * trade-off between performance and power consumption 00219 * when the device does not operate at the maximum 00220 * frequency (refer to the datasheet for more details). 00221 * This parameter can be one of the following values: 00222 * @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output 00223 * Scale 0 mode. 00224 * @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output 00225 * Scale 1 mode. 00226 * @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output 00227 * Scale 2 mode. 00228 * @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output 00229 * Scale 3 mode. 00230 * @note For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is 00231 * only possible when Vcore is supplied from LDO (Low DropOut). The 00232 * SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() 00233 * macro before configuring Voltage Scale 0 using 00234 * __HAL_PWR_VOLTAGESCALING_CONFIG(). 00235 * Transition to Voltage Scale 0 is only possible when the system is 00236 * already in Voltage Scale 1. 00237 * Transition from Voltage Scale 0 is only possible to Voltage Scale 1 00238 * then once in Voltage Scale 1 it is possible to switch to another 00239 * voltage scale. 00240 * After each regulator voltage setting, wait on VOSRDY flag to be set 00241 * using macro __HAL_PWR_GET_FLAG(). 00242 * To enter low power mode , and if current regulator voltage is 00243 * Voltage Scale 0 then first switch to Voltage Scale 1 before entering 00244 * low power mode. 00245 * @retval None. 00246 */ 00247 #if defined (PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */ 00248 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 00249 do { \ 00250 __IO uint32_t tmpreg = 0x00; \ 00251 /* Configure the Voltage Scaling */ \ 00252 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__)); \ 00253 /* Delay after setting the voltage scaling */ \ 00254 tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS); \ 00255 UNUSED(tmpreg); \ 00256 } while(0) 00257 #else /* 3 power domains devices */ 00258 #if defined(SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ 00259 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 00260 do { \ 00261 __IO uint32_t tmpreg = 0x00; \ 00262 /* Check the voltage scaling to be configured */ \ 00263 if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0) \ 00264 { \ 00265 /* Configure the Voltage Scaling 1 */ \ 00266 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); \ 00267 /* Delay after setting the voltage scaling */ \ 00268 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ 00269 /* Enable the PWR overdrive */ \ 00270 SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ 00271 /* Delay after setting the syscfg boost setting */ \ 00272 tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ 00273 } \ 00274 else \ 00275 { \ 00276 /* Disable the PWR overdrive */ \ 00277 CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ 00278 /* Delay after setting the syscfg boost setting */ \ 00279 tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN); \ 00280 /* Configure the Voltage Scaling x */ \ 00281 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ 00282 /* Delay after setting the voltage scaling */ \ 00283 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ 00284 } \ 00285 UNUSED(tmpreg); \ 00286 } while(0) 00287 #else /* STM32H72xxx and STM32H73xxx lines */ 00288 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ 00289 do { \ 00290 __IO uint32_t tmpreg = 0x00; \ 00291 /* Configure the Voltage Scaling */ \ 00292 MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__)); \ 00293 /* Delay after setting the voltage scaling */ \ 00294 tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS); \ 00295 UNUSED(tmpreg); \ 00296 } while(0) 00297 #endif /* defined(SYSCFG_PWRCR_ODEN) */ 00298 #endif /* defined (PWR_SRDCR_VOS) */ 00299 00300 /** @brief Check PWR flags are set or not. 00301 * @param __FLAG__ : Specifies the flag to check. 00302 * This parameter can be one of the following values: 00303 * @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD 00304 * is enabled by the HAL_PWR_EnablePVD() 00305 * function. 00306 * The PVD is stopped by STANDBY mode. For this 00307 * reason, this bit is equal to 0 after STANDBY 00308 * or reset until the PVDE bit is set. 00309 * @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD 00310 * is enabled by the HAL_PWREx_EnableAVD() 00311 * function. The AVD is stopped by STANDBY mode. 00312 * For this reason, this bit is equal to 0 00313 * after STANDBY or reset until the AVDE bit 00314 * is set. 00315 * @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator 00316 * voltage scaling output selection is 00317 * ready. 00318 * @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not 00319 * reset when the device wakes up from STANDBY 00320 * mode or by a system reset or power-on reset. 00321 * @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator 00322 * voltage scaling output selection is ready. 00323 * mode or by a system reset or power-on reset. 00324 * @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply 00325 * from regulator is ready. 00326 * @arg PWR_FLAG_TEMPH : This flag indicates that the temperature 00327 * equal or above high threshold level. 00328 * @arg PWR_FLAG_TEMPL : This flag indicates that the temperature 00329 * equal or below low threshold level. 00330 * @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal 00331 * or above high threshold level. 00332 * @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal 00333 * or below low threshold level. 00334 * @arg PWR_FLAG_STOP : This flag indicates that the system entered 00335 * in STOP mode. 00336 * @arg PWR_FLAG_SB : This flag indicates that the system entered in 00337 * STANDBY mode. 00338 * @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain 00339 * entered in STANDBY mode. 00340 * @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain 00341 * entered in STANDBY mode. 00342 * @arg PWR_FLAG2_STOP : This flag indicates that the system entered 00343 * in STOP mode. 00344 * @arg PWR_FLAG2_SB : This flag indicates that the system entered 00345 * in STANDBY mode. 00346 * @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain 00347 * entered in STANDBY mode. 00348 * @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain 00349 * entered in STANDBY mode. 00350 * @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes 00351 * up with hold. 00352 * @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes 00353 * up with hold. 00354 * @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS 00355 * External supply is sready. 00356 * @arg PWR_FLAG_SCUEN : This flag indicates that the supply 00357 * configuration update is enabled. 00358 * @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is 00359 * above or equal to 1.2 V. 00360 * @note The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR, 00361 * PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL, 00362 * PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags 00363 * are used for all H7 family lines. 00364 * The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2, 00365 * PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7 00366 * dual core lines. 00367 * The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7 00368 * family except STM32H7Axxx and STM32H7Bxxx lines. 00369 * The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and 00370 * STM32H7Bxxx lines. 00371 * The PWR_FLAG_SCUEN flag is used for devices that support only LDO 00372 * regulator. 00373 * The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO 00374 * and SMPS regulators. 00375 * @retval The (__FLAG__) state (TRUE or FALSE). 00376 */ 00377 #if defined (DUAL_CORE) /* Dual core lines */ 00378 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 00379 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 00380 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 00381 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 00382 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ 00383 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ 00384 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 00385 ((__FLAG__) == PWR_FLAG_CPU_HOLD) ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F) :\ 00386 ((__FLAG__) == PWR_FLAG_CPU2_HOLD) ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F) == PWR_CPUCR_HOLD2F) :\ 00387 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 00388 ((__FLAG__) == PWR_FLAG2_SB) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF) == PWR_CPU2CR_SBF) :\ 00389 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 00390 ((__FLAG__) == PWR_FLAG2_STOP) ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF) == PWR_CPU2CR_STOPF) :\ 00391 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ 00392 ((__FLAG__) == PWR_FLAG2_SB_D1) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1) :\ 00393 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ 00394 ((__FLAG__) == PWR_FLAG2_SB_D2) ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2) :\ 00395 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 00396 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 00397 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 00398 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 00399 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 00400 #else /* Single core lines */ 00401 #if defined (PWR_CPUCR_SBF_D2) /* STM32H72x, STM32H73x, STM32H74x and STM32H75x lines */ 00402 #if defined (SMPS) /* STM32H725 and STM32H735 lines */ 00403 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 00404 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 00405 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 00406 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 00407 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ 00408 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_FLAG_SMPSEXTRDY) == PWR_FLAG_SMPSEXTRDY) :\ 00409 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 00410 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 00411 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 00412 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ 00413 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ 00414 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 00415 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 00416 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 00417 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 00418 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 00419 #else /* STM32H723, STM32H733, STM32H742, STM32H743, STM32H750 and STM32H753 lines */ 00420 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 00421 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 00422 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 00423 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 00424 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->D3CR & PWR_D3CR_VOSRDY) == PWR_D3CR_VOSRDY) :\ 00425 ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ 00426 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 00427 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 00428 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 00429 ((__FLAG__) == PWR_FLAG_SB_D1) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1) == PWR_CPUCR_SBF_D1) :\ 00430 ((__FLAG__) == PWR_FLAG_SB_D2) ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2) == PWR_CPUCR_SBF_D2) :\ 00431 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 00432 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 00433 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 00434 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 00435 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 00436 #endif /* defined (SMPS) */ 00437 #else /* STM32H7Axxx and STM32H7Bxxx lines */ 00438 #if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ lines */ 00439 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 00440 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 00441 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 00442 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 00443 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 00444 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ 00445 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 00446 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 00447 ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ 00448 ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY) == PWR_CR3_SMPSEXTRDY) :\ 00449 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 00450 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 00451 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 00452 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 00453 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 00454 #else /* STM32H7Axx and STM32H7Bxx lines */ 00455 #define __HAL_PWR_GET_FLAG(__FLAG__) \ 00456 (((__FLAG__) == PWR_FLAG_PVDO) ? ((PWR->CSR1 & PWR_CSR1_PVDO) == PWR_CSR1_PVDO) :\ 00457 ((__FLAG__) == PWR_FLAG_AVDO) ? ((PWR->CSR1 & PWR_CSR1_AVDO) == PWR_CSR1_AVDO) :\ 00458 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\ 00459 ((__FLAG__) == PWR_FLAG_BRR) ? ((PWR->CR2 & PWR_CR2_BRRDY) == PWR_CR2_BRRDY) :\ 00460 ((__FLAG__) == PWR_FLAG_VOSRDY) ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY) == PWR_SRDCR_VOSRDY) :\ 00461 ((__FLAG__) == PWR_FLAG_SCUEN) ? ((PWR->CR3 & PWR_CR3_SCUEN) == PWR_CR3_SCUEN) :\ 00462 ((__FLAG__) == PWR_FLAG_STOP) ? ((PWR->CPUCR & PWR_CPUCR_STOPF) == PWR_CPUCR_STOPF) :\ 00463 ((__FLAG__) == PWR_FLAG_SB) ? ((PWR->CPUCR & PWR_CPUCR_SBF) == PWR_CPUCR_SBF) :\ 00464 ((__FLAG__) == PWR_FLAG_MMCVDO) ? ((PWR->CSR1 & PWR_CSR1_MMCVDO) == PWR_CSR1_MMCVDO) :\ 00465 ((__FLAG__) == PWR_FLAG_USB33RDY) ? ((PWR->CR3 & PWR_CR3_USB33RDY) == PWR_CR3_USB33RDY) :\ 00466 ((__FLAG__) == PWR_FLAG_TEMPH) ? ((PWR->CR2 & PWR_CR2_TEMPH) == PWR_CR2_TEMPH) :\ 00467 ((__FLAG__) == PWR_FLAG_TEMPL) ? ((PWR->CR2 & PWR_CR2_TEMPL) == PWR_CR2_TEMPL) :\ 00468 ((__FLAG__) == PWR_FLAG_VBATH) ? ((PWR->CR2 & PWR_CR2_VBATH) == PWR_CR2_VBATH) :\ 00469 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL)) 00470 #endif /* SMPS */ 00471 #endif /* PWR_CPUCR_SBF_D2 */ 00472 #endif /* DUAL_CORE */ 00473 00474 /** @brief Check PWR wake up flags are set or not. 00475 * @param __FLAG__: specifies the wake up flag to check. 00476 * This parameter can be one of the following values: 00477 * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. 00478 * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. 00479 * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. 00480 * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. 00481 * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. 00482 * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. 00483 * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices 00484 * that support GPIOI port. 00485 * @retval The (__FLAG__) state (TRUE or FALSE). 00486 */ 00487 #define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1) 00488 00489 #if defined (DUAL_CORE) 00490 /** @brief Clear CPU PWR flags. 00491 * @param __FLAG__ : Specifies the flag to clear. 00492 * @note This parameter is not used for the STM32H7 family and is kept as 00493 * parameter just to maintain compatibility with other families. 00494 * @note This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2. 00495 * This parameter can be one of the following values : 00496 * @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2 00497 * CPU flags. 00498 * @retval None. 00499 */ 00500 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ 00501 do { \ 00502 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); \ 00503 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \ 00504 } while(0) 00505 #else 00506 /** @brief Clear CPU PWR flags. 00507 * @param __FLAG__ : Specifies the flag to clear. 00508 * @note This parameter is not used for the STM32H7 family and is kept as 00509 * parameter just to maintain compatibility with other families. 00510 * @note This macro clear all CPU flags. 00511 * For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU 00512 * flags are STOPF, SBF, SBF_D1 and SBF_D2. 00513 * For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF. 00514 * @retval None. 00515 */ 00516 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF) 00517 #endif /* defined (DUAL_CORE) */ 00518 00519 /** @brief Clear PWR wake up flags. 00520 * @param __FLAG__ : Specifies the wake up flag to be cleared. 00521 * This parameter can be one of the following values : 00522 * @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. 00523 * @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. 00524 * @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. 00525 * @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. 00526 * @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. 00527 * @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag. 00528 * @note The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices 00529 * that support GPIOI port. 00530 * @retval None. 00531 */ 00532 #define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__)) 00533 00534 /** 00535 * @brief Enable the PVD EXTI Line 16. 00536 * @retval None. 00537 */ 00538 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 00539 00540 #if defined (DUAL_CORE) 00541 /** 00542 * @brief Enable the PVD EXTI D2 Line 16. 00543 * @retval None. 00544 */ 00545 #define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) 00546 #endif /* defined (DUAL_CORE) */ 00547 00548 /** 00549 * @brief Disable the PVD EXTI Line 16. 00550 * @retval None. 00551 */ 00552 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) 00553 00554 #if defined (DUAL_CORE) 00555 /** 00556 * @brief Disable the PVD EXTI D2 Line 16. 00557 * @retval None. 00558 */ 00559 #define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD) 00560 #endif /* defined (DUAL_CORE) */ 00561 00562 /** 00563 * @brief Enable event on PVD EXTI Line 16. 00564 * @retval None. 00565 */ 00566 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) 00567 00568 #if defined (DUAL_CORE) 00569 /** 00570 * @brief Enable event on PVD EXTI D2 Line. 00571 * @retval None. 00572 */ 00573 #define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) 00574 #endif /* defined (DUAL_CORE) */ 00575 00576 /** 00577 * @brief Disable event on PVD EXTI Line 16. 00578 * @retval None. 00579 */ 00580 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) 00581 00582 #if defined (DUAL_CORE) 00583 /** 00584 * @brief Disable event on PVD EXTI D2 Line. 00585 * @retval None. 00586 */ 00587 #define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD) 00588 #endif /* defined (DUAL_CORE) */ 00589 00590 /** 00591 * @brief Enable the PVD Rising Interrupt Trigger. 00592 * @retval None. 00593 */ 00594 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 00595 00596 /** 00597 * @brief Disable the PVD Rising Interrupt Trigger. 00598 * @retval None. 00599 */ 00600 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) 00601 00602 /** 00603 * @brief Enable the PVD Falling Interrupt Trigger. 00604 * @retval None. 00605 */ 00606 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 00607 00608 /** 00609 * @brief Disable the PVD Falling Interrupt Trigger. 00610 * @retval None. 00611 */ 00612 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) 00613 00614 /** 00615 * @brief Enable the PVD Rising & Falling Interrupt Trigger. 00616 * @retval None. 00617 */ 00618 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ 00619 do { \ 00620 __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ 00621 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ 00622 } while(0); 00623 00624 /** 00625 * @brief Disable the PVD Rising & Falling Interrupt Trigger. 00626 * @retval None. 00627 */ 00628 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ 00629 do { \ 00630 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ 00631 __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ 00632 } while(0); 00633 00634 /** 00635 * @brief Check whether the specified PVD EXTI interrupt flag is set or not. 00636 * @retval EXTI PVD Line Status. 00637 */ 00638 #define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) 00639 00640 #if defined (DUAL_CORE) 00641 /** 00642 * @brief Checks whether the specified PVD EXTI interrupt flag is set or not. 00643 * @retval EXTI D2 PVD Line Status. 00644 */ 00645 #define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL) 00646 #endif /* defined (DUAL_CORE) */ 00647 00648 /** 00649 * @brief Clear the PVD EXTI flag. 00650 * @retval None. 00651 */ 00652 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) 00653 00654 #if defined (DUAL_CORE) 00655 /** 00656 * @brief Clear the PVD EXTI D2 flag. 00657 * @retval None. 00658 */ 00659 #define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) 00660 #endif /* defined (DUAL_CORE) */ 00661 00662 /** 00663 * @brief Generates a Software interrupt on PVD EXTI line. 00664 * @retval None. 00665 */ 00666 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) 00667 /** 00668 * @} 00669 */ 00670 00671 /* Include PWR HAL Extension module */ 00672 #include "stm32h7xx_hal_pwr_ex.h" 00673 00674 /* Exported functions --------------------------------------------------------*/ 00675 /** @addtogroup PWR_Exported_Functions PWR Exported Functions 00676 * @{ 00677 */ 00678 00679 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions 00680 * @{ 00681 */ 00682 /* Initialization and de-initialization functions *****************************/ 00683 void HAL_PWR_DeInit (void); 00684 void HAL_PWR_EnableBkUpAccess (void); 00685 void HAL_PWR_DisableBkUpAccess (void); 00686 /** 00687 * @} 00688 */ 00689 00690 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control Functions 00691 * @{ 00692 */ 00693 /* Peripheral Control functions **********************************************/ 00694 /* PVD configuration */ 00695 void HAL_PWR_ConfigPVD (PWR_PVDTypeDef *sConfigPVD); 00696 void HAL_PWR_EnablePVD (void); 00697 void HAL_PWR_DisablePVD (void); 00698 00699 /* WakeUp pins configuration */ 00700 void HAL_PWR_EnableWakeUpPin (uint32_t WakeUpPinPolarity); 00701 void HAL_PWR_DisableWakeUpPin (uint32_t WakeUpPinx); 00702 00703 /* Low Power modes entry */ 00704 void HAL_PWR_EnterSTOPMode (uint32_t Regulator, uint8_t STOPEntry); 00705 void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry); 00706 void HAL_PWR_EnterSTANDBYMode (void); 00707 00708 /* Power PVD IRQ Handler */ 00709 void HAL_PWR_PVD_IRQHandler (void); 00710 void HAL_PWR_PVDCallback (void); 00711 00712 /* Cortex System Control functions *******************************************/ 00713 void HAL_PWR_EnableSleepOnExit (void); 00714 void HAL_PWR_DisableSleepOnExit (void); 00715 void HAL_PWR_EnableSEVOnPend (void); 00716 void HAL_PWR_DisableSEVOnPend (void); 00717 /** 00718 * @} 00719 */ 00720 00721 /** 00722 * @} 00723 */ 00724 00725 /* Private types -------------------------------------------------------------*/ 00726 /* Private variables ---------------------------------------------------------*/ 00727 /* Private constants ---------------------------------------------------------*/ 00728 /** @defgroup PWR_Private_Constants PWR Private Constants 00729 * @{ 00730 */ 00731 00732 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line 00733 * @{ 00734 */ 00735 #define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< External interrupt line 16 00736 Connected to the PVD EXTI Line */ 00737 /** 00738 * @} 00739 */ 00740 00741 /** 00742 * @} 00743 */ 00744 /* Private macros ------------------------------------------------------------*/ 00745 /** @defgroup PWR_Private_Macros PWR Private Macros 00746 * @{ 00747 */ 00748 00749 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters 00750 * @{ 00751 */ 00752 /* Check PVD level parameter */ 00753 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\ 00754 ((LEVEL) == PWR_PVDLEVEL_1) ||\ 00755 ((LEVEL) == PWR_PVDLEVEL_2) ||\ 00756 ((LEVEL) == PWR_PVDLEVEL_3) ||\ 00757 ((LEVEL) == PWR_PVDLEVEL_4) ||\ 00758 ((LEVEL) == PWR_PVDLEVEL_5) ||\ 00759 ((LEVEL) == PWR_PVDLEVEL_6) ||\ 00760 ((LEVEL) == PWR_PVDLEVEL_7)) 00761 00762 /* Check PVD mode parameter */ 00763 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING) ||\ 00764 ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ 00765 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ 00766 ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ 00767 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ 00768 ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\ 00769 ((MODE) == PWR_PVD_MODE_NORMAL)) 00770 00771 /* Check low power regulator parameter */ 00772 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) ||\ 00773 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 00774 00775 /* Check low power mode entry parameter */ 00776 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ 00777 ((ENTRY) == PWR_SLEEPENTRY_WFE)) 00778 00779 /* Check low power mode entry parameter */ 00780 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ 00781 ((ENTRY) == PWR_STOPENTRY_WFE)) 00782 00783 /* Check voltage scale level parameter */ 00784 #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \ 00785 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 00786 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ 00787 ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) 00788 /** 00789 * @} 00790 */ 00791 00792 /** 00793 * @} 00794 */ 00795 00796 /** 00797 * @} 00798 */ 00799 00800 /** 00801 * @} 00802 */ 00803 00804 #ifdef __cplusplus 00805 } 00806 #endif /* __cplusplus */ 00807 00808 #endif /* STM32H7xx_HAL_PWR_H */ 00809
1.7.6.1