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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_qspi.h 00004 * @author MCD Application Team 00005 * @brief Header file of QSPI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_QSPI_H 00021 #define STM32H7xx_HAL_QSPI_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 #if defined(QUADSPI) 00031 00032 /** @addtogroup STM32H7xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @addtogroup QSPI 00037 * @{ 00038 */ 00039 00040 /* Exported types ------------------------------------------------------------*/ 00041 /** @defgroup QSPI_Exported_Types QSPI Exported Types 00042 * @{ 00043 */ 00044 00045 /** 00046 * @brief QSPI Init structure definition 00047 */ 00048 typedef struct 00049 { 00050 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 00051 This parameter can be a number between 0 and 255 */ 00052 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 00053 This parameter can be a value between 1 and 32 */ 00054 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 00055 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 00056 This parameter can be a value of @ref QSPI_SampleShifting */ 00057 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 00058 required to address the flash memory. The flash capacity can be up to 4GB 00059 (addressed using 32 bits) in indirect mode, but the addressable space in 00060 memory-mapped mode is limited to 256MB 00061 This parameter can be a number between 0 and 31 */ 00062 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 00063 of clock cycles which the chip select must remain high between commands. 00064 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 00065 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 00066 This parameter can be a value of @ref QSPI_ClockMode */ 00067 uint32_t FlashID; /* Specifies the Flash which will be used, 00068 This parameter can be a value of @ref QSPI_Flash_Select */ 00069 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 00070 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 00071 }QSPI_InitTypeDef; 00072 00073 /** 00074 * @brief HAL QSPI State structures definition 00075 */ 00076 typedef enum 00077 { 00078 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 00079 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 00080 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 00081 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 00082 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 00083 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 00084 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 00085 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 00086 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 00087 }HAL_QSPI_StateTypeDef; 00088 00089 /** 00090 * @brief QSPI Handle Structure definition 00091 */ 00092 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00093 typedef struct __QSPI_HandleTypeDef 00094 #else 00095 typedef struct 00096 #endif 00097 { 00098 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 00099 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 00100 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 00101 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 00102 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 00103 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 00104 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 00105 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 00106 MDMA_HandleTypeDef *hmdma; /* QSPI Rx/Tx MDMA Handle parameters */ 00107 __IO HAL_LockTypeDef Lock; /* Locking object */ 00108 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 00109 __IO uint32_t ErrorCode; /* QSPI Error code */ 00110 uint32_t Timeout; /* Timeout for the QSPI memory access */ 00111 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00112 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 00113 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00114 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 00115 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00116 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00117 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00118 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 00119 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 00120 00121 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 00122 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 00123 #endif 00124 }QSPI_HandleTypeDef; 00125 00126 /** 00127 * @brief QSPI Command structure definition 00128 */ 00129 typedef struct 00130 { 00131 uint32_t Instruction; /* Specifies the Instruction to be sent 00132 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 00133 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 00134 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 00135 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 00136 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 00137 uint32_t AddressSize; /* Specifies the Address Size 00138 This parameter can be a value of @ref QSPI_AddressSize */ 00139 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 00140 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 00141 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 00142 This parameter can be a number between 0 and 31 */ 00143 uint32_t InstructionMode; /* Specifies the Instruction Mode 00144 This parameter can be a value of @ref QSPI_InstructionMode */ 00145 uint32_t AddressMode; /* Specifies the Address Mode 00146 This parameter can be a value of @ref QSPI_AddressMode */ 00147 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 00148 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 00149 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 00150 This parameter can be a value of @ref QSPI_DataMode */ 00151 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 00152 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 00153 until end of memory)*/ 00154 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 00155 This parameter can be a value of @ref QSPI_DdrMode */ 00156 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 00157 output by one half of system clock in DDR mode. 00158 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 00159 uint32_t SIOOMode; /* Specifies the send instruction only once mode 00160 This parameter can be a value of @ref QSPI_SIOOMode */ 00161 }QSPI_CommandTypeDef; 00162 00163 /** 00164 * @brief QSPI Auto Polling mode configuration structure definition 00165 */ 00166 typedef struct 00167 { 00168 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 00169 This parameter can be any value between 0 and 0xFFFFFFFF */ 00170 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 00171 This parameter can be any value between 0 and 0xFFFFFFFF */ 00172 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 00173 This parameter can be any value between 0 and 0xFFFF */ 00174 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 00175 This parameter can be any value between 1 and 4 */ 00176 uint32_t MatchMode; /* Specifies the method used for determining a match. 00177 This parameter can be a value of @ref QSPI_MatchMode */ 00178 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 00179 This parameter can be a value of @ref QSPI_AutomaticStop */ 00180 }QSPI_AutoPollingTypeDef; 00181 00182 /** 00183 * @brief QSPI Memory Mapped mode configuration structure definition 00184 */ 00185 typedef struct 00186 { 00187 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 00188 This parameter can be any value between 0 and 0xFFFF */ 00189 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 00190 This parameter can be a value of @ref QSPI_TimeOutActivation */ 00191 }QSPI_MemoryMappedTypeDef; 00192 00193 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00194 /** 00195 * @brief HAL QSPI Callback ID enumeration definition 00196 */ 00197 typedef enum 00198 { 00199 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 00200 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 00201 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 00202 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 00203 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 00204 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 00205 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 00206 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 00207 00208 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 00209 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 00210 }HAL_QSPI_CallbackIDTypeDef; 00211 00212 /** 00213 * @brief HAL QSPI Callback pointer definition 00214 */ 00215 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 00216 #endif 00217 /** 00218 * @} 00219 */ 00220 00221 /* Exported constants --------------------------------------------------------*/ 00222 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 00223 * @{ 00224 */ 00225 00226 /** @defgroup QSPI_ErrorCode QSPI Error Code 00227 * @{ 00228 */ 00229 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 00230 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 00231 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 00232 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 00233 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 00234 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00235 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 00236 #endif 00237 /** 00238 * @} 00239 */ 00240 00241 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 00242 * @{ 00243 */ 00244 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 00245 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 00246 /** 00247 * @} 00248 */ 00249 00250 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 00251 * @{ 00252 */ 00253 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 00254 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 00255 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 00256 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 00257 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 00258 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 00259 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 00260 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 00261 /** 00262 * @} 00263 */ 00264 00265 /** @defgroup QSPI_ClockMode QSPI Clock Mode 00266 * @{ 00267 */ 00268 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 00269 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 00270 /** 00271 * @} 00272 */ 00273 00274 /** @defgroup QSPI_Flash_Select QSPI Flash Select 00275 * @{ 00276 */ 00277 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 00278 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 00284 * @{ 00285 */ 00286 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 00287 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 00288 /** 00289 * @} 00290 */ 00291 00292 /** @defgroup QSPI_AddressSize QSPI Address Size 00293 * @{ 00294 */ 00295 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 00296 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 00297 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 00298 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 00299 /** 00300 * @} 00301 */ 00302 00303 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 00304 * @{ 00305 */ 00306 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 00307 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 00308 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 00309 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 00310 /** 00311 * @} 00312 */ 00313 00314 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 00315 * @{ 00316 */ 00317 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 00318 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 00319 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 00320 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 00321 /** 00322 * @} 00323 */ 00324 00325 /** @defgroup QSPI_AddressMode QSPI Address Mode 00326 * @{ 00327 */ 00328 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 00329 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 00330 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 00331 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 00332 /** 00333 * @} 00334 */ 00335 00336 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 00337 * @{ 00338 */ 00339 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 00340 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 00341 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 00342 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 00343 /** 00344 * @} 00345 */ 00346 00347 /** @defgroup QSPI_DataMode QSPI Data Mode 00348 * @{ 00349 */ 00350 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 00351 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 00352 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 00353 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup QSPI_DdrMode QSPI DDR Mode 00359 * @{ 00360 */ 00361 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 00362 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 00363 /** 00364 * @} 00365 */ 00366 00367 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 00368 * @{ 00369 */ 00370 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 00371 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 00372 /** 00373 * @} 00374 */ 00375 00376 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 00377 * @{ 00378 */ 00379 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 00380 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 00381 /** 00382 * @} 00383 */ 00384 00385 /** @defgroup QSPI_MatchMode QSPI Match Mode 00386 * @{ 00387 */ 00388 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 00389 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 00390 /** 00391 * @} 00392 */ 00393 00394 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 00395 * @{ 00396 */ 00397 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 00398 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 00399 /** 00400 * @} 00401 */ 00402 00403 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 00404 * @{ 00405 */ 00406 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 00407 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 00408 /** 00409 * @} 00410 */ 00411 00412 /** @defgroup QSPI_Flags QSPI Flags 00413 * @{ 00414 */ 00415 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 00416 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 00417 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 00418 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 00419 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 00420 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 00421 /** 00422 * @} 00423 */ 00424 00425 /** @defgroup QSPI_Interrupts QSPI Interrupts 00426 * @{ 00427 */ 00428 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 00429 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 00430 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 00431 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 00432 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 00433 /** 00434 * @} 00435 */ 00436 00437 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 00438 * @brief QSPI Timeout definition 00439 * @{ 00440 */ 00441 #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 00442 /** 00443 * @} 00444 */ 00445 00446 /** 00447 * @} 00448 */ 00449 00450 /* Exported macros -----------------------------------------------------------*/ 00451 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 00452 * @{ 00453 */ 00454 /** @brief Reset QSPI handle state. 00455 * @param __HANDLE__ QSPI handle. 00456 * @retval None 00457 */ 00458 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00459 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 00460 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 00461 (__HANDLE__)->MspInitCallback = NULL; \ 00462 (__HANDLE__)->MspDeInitCallback = NULL; \ 00463 } while(0) 00464 #else 00465 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 00466 #endif 00467 00468 /** @brief Enable the QSPI peripheral. 00469 * @param __HANDLE__ specifies the QSPI Handle. 00470 * @retval None 00471 */ 00472 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00473 00474 /** @brief Disable the QSPI peripheral. 00475 * @param __HANDLE__ specifies the QSPI Handle. 00476 * @retval None 00477 */ 00478 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00479 00480 /** @brief Enable the specified QSPI interrupt. 00481 * @param __HANDLE__ specifies the QSPI Handle. 00482 * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. 00483 * This parameter can be one of the following values: 00484 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00485 * @arg QSPI_IT_SM: QSPI Status match interrupt 00486 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00487 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00488 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00489 * @retval None 00490 */ 00491 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00492 00493 00494 /** @brief Disable the specified QSPI interrupt. 00495 * @param __HANDLE__ specifies the QSPI Handle. 00496 * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. 00497 * This parameter can be one of the following values: 00498 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00499 * @arg QSPI_IT_SM: QSPI Status match interrupt 00500 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00501 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00502 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00503 * @retval None 00504 */ 00505 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00506 00507 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 00508 * @param __HANDLE__ specifies the QSPI Handle. 00509 * @param __INTERRUPT__ specifies the QSPI interrupt source to check. 00510 * This parameter can be one of the following values: 00511 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00512 * @arg QSPI_IT_SM: QSPI Status match interrupt 00513 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00514 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00515 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00516 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 00517 */ 00518 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 00519 00520 /** 00521 * @brief Check whether the selected QSPI flag is set or not. 00522 * @param __HANDLE__ specifies the QSPI Handle. 00523 * @param __FLAG__ specifies the QSPI flag to check. 00524 * This parameter can be one of the following values: 00525 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 00526 * @arg QSPI_FLAG_TO: QSPI Timeout flag 00527 * @arg QSPI_FLAG_SM: QSPI Status match flag 00528 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 00529 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00530 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00531 * @retval None 00532 */ 00533 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 00534 00535 /** @brief Clears the specified QSPI's flag status. 00536 * @param __HANDLE__ specifies the QSPI Handle. 00537 * @param __FLAG__ specifies the QSPI clear register flag that needs to be set 00538 * This parameter can be one of the following values: 00539 * @arg QSPI_FLAG_TO: QSPI Timeout flag 00540 * @arg QSPI_FLAG_SM: QSPI Status match flag 00541 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00542 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00543 * @retval None 00544 */ 00545 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 00546 /** 00547 * @} 00548 */ 00549 00550 /* Exported functions --------------------------------------------------------*/ 00551 /** @addtogroup QSPI_Exported_Functions 00552 * @{ 00553 */ 00554 00555 /** @addtogroup QSPI_Exported_Functions_Group1 00556 * @{ 00557 */ 00558 /* Initialization/de-initialization functions ********************************/ 00559 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 00560 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 00561 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 00562 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 00563 /** 00564 * @} 00565 */ 00566 00567 /** @addtogroup QSPI_Exported_Functions_Group2 00568 * @{ 00569 */ 00570 /* IO operation functions *****************************************************/ 00571 /* QSPI IRQ handler method */ 00572 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 00573 00574 /* QSPI indirect mode */ 00575 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 00576 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00577 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00578 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 00579 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00580 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00581 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00582 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00583 00584 /* QSPI status flag polling mode */ 00585 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 00586 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 00587 00588 /* QSPI memory-mapped mode */ 00589 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 00590 00591 /* Callback functions in non-blocking modes ***********************************/ 00592 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 00593 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 00594 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 00595 00596 /* QSPI indirect mode */ 00597 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 00598 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 00599 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 00600 00601 /* QSPI status flag polling mode */ 00602 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 00603 00604 /* QSPI memory-mapped mode */ 00605 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 00606 00607 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00608 /* QSPI callback registering/unregistering */ 00609 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback); 00610 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId); 00611 #endif 00612 /** 00613 * @} 00614 */ 00615 00616 /** @addtogroup QSPI_Exported_Functions_Group3 00617 * @{ 00618 */ 00619 /* Peripheral Control and State functions ************************************/ 00620 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 00621 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 00622 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 00623 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 00624 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 00625 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 00626 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 00627 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 00628 /** 00629 * @} 00630 */ 00631 00632 /** 00633 * @} 00634 */ 00635 /* End of exported functions -------------------------------------------------*/ 00636 00637 /* Private macros ------------------------------------------------------------*/ 00638 /** @defgroup QSPI_Private_Macros QSPI Private Macros 00639 * @{ 00640 */ 00641 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 00642 00643 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 32U)) 00644 00645 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 00646 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 00647 00648 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 00649 00650 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 00651 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 00652 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 00653 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 00654 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 00655 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 00656 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 00657 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 00658 00659 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 00660 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 00661 00662 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 00663 ((FLASH_ID) == QSPI_FLASH_ID_2)) 00664 00665 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 00666 ((MODE) == QSPI_DUALFLASH_DISABLE)) 00667 00668 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 00669 00670 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 00671 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 00672 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 00673 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 00674 00675 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 00676 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 00677 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 00678 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 00679 00680 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 00681 00682 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 00683 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 00684 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 00685 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 00686 00687 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 00688 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 00689 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 00690 ((MODE) == QSPI_ADDRESS_4_LINES)) 00691 00692 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 00693 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 00694 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 00695 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 00696 00697 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 00698 ((MODE) == QSPI_DATA_1_LINE) || \ 00699 ((MODE) == QSPI_DATA_2_LINES) || \ 00700 ((MODE) == QSPI_DATA_4_LINES)) 00701 00702 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 00703 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 00704 00705 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 00706 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 00707 00708 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 00709 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 00710 00711 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 00712 00713 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 00714 00715 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 00716 ((MODE) == QSPI_MATCH_MODE_OR)) 00717 00718 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 00719 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 00720 00721 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 00722 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 00723 00724 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 00725 /** 00726 * @} 00727 */ 00728 /* End of private macros -----------------------------------------------------*/ 00729 00730 /** 00731 * @} 00732 */ 00733 00734 /** 00735 * @} 00736 */ 00737 00738 #endif /* defined(QUADSPI) */ 00739 00740 #ifdef __cplusplus 00741 } 00742 #endif 00743 00744 #endif /* STM32H7xx_HAL_QSPI_H */
1.7.6.1