STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_sdram.c 00004 * @author MCD Application Team 00005 * @brief SDRAM HAL module driver. 00006 * This file provides a generic firmware to drive SDRAM memories mounted 00007 * as external device. 00008 * 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * Copyright (c) 2017 STMicroelectronics. 00013 * All rights reserved. 00014 * 00015 * This software is licensed under terms that can be found in the LICENSE file 00016 * in the root directory of this software component. 00017 * If no LICENSE file comes with this software, it is provided AS-IS. 00018 * 00019 ****************************************************************************** 00020 @verbatim 00021 ============================================================================== 00022 ##### How to use this driver ##### 00023 ============================================================================== 00024 [..] 00025 This driver is a generic layered driver which contains a set of APIs used to 00026 control SDRAM memories. It uses the FMC layer functions to interface 00027 with SDRAM devices. 00028 The following sequence should be followed to configure the FMC to interface 00029 with SDRAM memories: 00030 00031 (#) Declare a SDRAM_HandleTypeDef handle structure, for example: 00032 SDRAM_HandleTypeDef hsdram 00033 00034 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed 00035 values of the structure member. 00036 00037 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined 00038 base register instance for NOR or SDRAM device 00039 00040 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: 00041 FMC_SDRAM_TimingTypeDef Timing; 00042 and fill its fields with the allowed values of the structure member. 00043 00044 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function 00045 performs the following sequence: 00046 00047 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() 00048 (##) Control register configuration using the FMC SDRAM interface function 00049 FMC_SDRAM_Init() 00050 (##) Timing register configuration using the FMC SDRAM interface function 00051 FMC_SDRAM_Timing_Init() 00052 (##) Program the SDRAM external device by applying its initialization sequence 00053 according to the device plugged in your hardware. This step is mandatory 00054 for accessing the SDRAM device. 00055 00056 (#) At this stage you can perform read/write accesses from/to the memory connected 00057 to the SDRAM Bank. You can perform either polling or DMA transfer using the 00058 following APIs: 00059 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access 00060 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer 00061 00062 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ 00063 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or 00064 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM 00065 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef 00066 structure. 00067 00068 (#) You can continuously monitor the SDRAM device HAL state by calling the function 00069 HAL_SDRAM_GetState() 00070 00071 *** Callback registration *** 00072 ============================================= 00073 [..] 00074 The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS when set to 1 00075 allows the user to configure dynamically the driver callbacks. 00076 00077 Use Functions HAL_SDRAM_RegisterCallback() to register a user callback, 00078 it allows to register following callbacks: 00079 (+) MspInitCallback : SDRAM MspInit. 00080 (+) MspDeInitCallback : SDRAM MspDeInit. 00081 This function takes as parameters the HAL peripheral handle, the Callback ID 00082 and a pointer to the user callback function. 00083 00084 Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default 00085 weak (surcharged) function. It allows to reset following callbacks: 00086 (+) MspInitCallback : SDRAM MspInit. 00087 (+) MspDeInitCallback : SDRAM MspDeInit. 00088 This function) takes as parameters the HAL peripheral handle and the Callback ID. 00089 00090 By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET 00091 all callbacks are reset to the corresponding legacy weak (surcharged) functions. 00092 Exception done for MspInit and MspDeInit callbacks that are respectively 00093 reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init 00094 and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand). 00095 If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit 00096 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) 00097 00098 Callbacks can be registered/unregistered in READY state only. 00099 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered 00100 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used 00101 during the Init/DeInit. 00102 In that case first register the MspInit/MspDeInit user callbacks 00103 using HAL_SDRAM_RegisterCallback before calling HAL_SDRAM_DeInit 00104 or HAL_SDRAM_Init function. 00105 00106 When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or 00107 not defined, the callback registering feature is not available 00108 and weak (surcharged) callbacks are used. 00109 00110 @endverbatim 00111 ****************************************************************************** 00112 */ 00113 00114 /* Includes ------------------------------------------------------------------*/ 00115 #include "stm32h7xx_hal.h" 00116 00117 00118 /** @addtogroup STM32H7xx_HAL_Driver 00119 * @{ 00120 */ 00121 00122 #ifdef HAL_SDRAM_MODULE_ENABLED 00123 00124 /** @defgroup SDRAM SDRAM 00125 * @brief SDRAM driver modules 00126 * @{ 00127 */ 00128 00129 /* Private typedef -----------------------------------------------------------*/ 00130 /* Private define ------------------------------------------------------------*/ 00131 /* Private macro -------------------------------------------------------------*/ 00132 /* Private variables ---------------------------------------------------------*/ 00133 /* Private function prototypes -----------------------------------------------*/ 00134 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma); 00135 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma); 00136 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma); 00137 00138 /* Exported functions --------------------------------------------------------*/ 00139 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions 00140 * @{ 00141 */ 00142 00143 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions 00144 * @brief Initialization and Configuration functions 00145 * 00146 @verbatim 00147 ============================================================================== 00148 ##### SDRAM Initialization and de_initialization functions ##### 00149 ============================================================================== 00150 [..] 00151 This section provides functions allowing to initialize/de-initialize 00152 the SDRAM memory 00153 00154 @endverbatim 00155 * @{ 00156 */ 00157 00158 /** 00159 * @brief Performs the SDRAM device initialization sequence. 00160 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00161 * the configuration information for SDRAM module. 00162 * @param Timing Pointer to SDRAM control timing structure 00163 * @retval HAL status 00164 */ 00165 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) 00166 { 00167 /* Check the SDRAM handle parameter */ 00168 if (hsdram == NULL) 00169 { 00170 return HAL_ERROR; 00171 } 00172 00173 if (hsdram->State == HAL_SDRAM_STATE_RESET) 00174 { 00175 /* Allocate lock resource and initialize it */ 00176 hsdram->Lock = HAL_UNLOCKED; 00177 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00178 if (hsdram->MspInitCallback == NULL) 00179 { 00180 hsdram->MspInitCallback = HAL_SDRAM_MspInit; 00181 } 00182 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; 00183 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; 00184 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; 00185 00186 /* Init the low level hardware */ 00187 hsdram->MspInitCallback(hsdram); 00188 #else 00189 /* Initialize the low level hardware (MSP) */ 00190 HAL_SDRAM_MspInit(hsdram); 00191 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00192 } 00193 00194 /* Initialize the SDRAM controller state */ 00195 hsdram->State = HAL_SDRAM_STATE_BUSY; 00196 00197 /* Initialize SDRAM control Interface */ 00198 (void)FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); 00199 00200 /* Initialize SDRAM timing Interface */ 00201 (void)FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); 00202 00203 /* Enable FMC Peripheral */ 00204 __FMC_ENABLE(); 00205 /* Update the SDRAM controller state */ 00206 hsdram->State = HAL_SDRAM_STATE_READY; 00207 00208 return HAL_OK; 00209 } 00210 00211 /** 00212 * @brief Perform the SDRAM device initialization sequence. 00213 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00214 * the configuration information for SDRAM module. 00215 * @retval HAL status 00216 */ 00217 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) 00218 { 00219 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00220 if (hsdram->MspDeInitCallback == NULL) 00221 { 00222 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; 00223 } 00224 00225 /* DeInit the low level hardware */ 00226 hsdram->MspDeInitCallback(hsdram); 00227 #else 00228 /* Initialize the low level hardware (MSP) */ 00229 HAL_SDRAM_MspDeInit(hsdram); 00230 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00231 00232 /* Configure the SDRAM registers with their reset values */ 00233 (void)FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); 00234 00235 /* Reset the SDRAM controller state */ 00236 hsdram->State = HAL_SDRAM_STATE_RESET; 00237 00238 /* Release Lock */ 00239 __HAL_UNLOCK(hsdram); 00240 00241 return HAL_OK; 00242 } 00243 00244 /** 00245 * @brief SDRAM MSP Init. 00246 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00247 * the configuration information for SDRAM module. 00248 * @retval None 00249 */ 00250 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) 00251 { 00252 /* Prevent unused argument(s) compilation warning */ 00253 UNUSED(hsdram); 00254 00255 /* NOTE: This function Should not be modified, when the callback is needed, 00256 the HAL_SDRAM_MspInit could be implemented in the user file 00257 */ 00258 } 00259 00260 /** 00261 * @brief SDRAM MSP DeInit. 00262 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00263 * the configuration information for SDRAM module. 00264 * @retval None 00265 */ 00266 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) 00267 { 00268 /* Prevent unused argument(s) compilation warning */ 00269 UNUSED(hsdram); 00270 00271 /* NOTE: This function Should not be modified, when the callback is needed, 00272 the HAL_SDRAM_MspDeInit could be implemented in the user file 00273 */ 00274 } 00275 00276 /** 00277 * @brief This function handles SDRAM refresh error interrupt request. 00278 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00279 * the configuration information for SDRAM module. 00280 * @retval HAL status 00281 */ 00282 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) 00283 { 00284 /* Check SDRAM interrupt Rising edge flag */ 00285 if (__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) 00286 { 00287 /* SDRAM refresh error interrupt callback */ 00288 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00289 hsdram->RefreshErrorCallback(hsdram); 00290 #else 00291 HAL_SDRAM_RefreshErrorCallback(hsdram); 00292 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00293 00294 /* Clear SDRAM refresh error interrupt pending bit */ 00295 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); 00296 } 00297 } 00298 00299 /** 00300 * @brief SDRAM Refresh error callback. 00301 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00302 * the configuration information for SDRAM module. 00303 * @retval None 00304 */ 00305 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) 00306 { 00307 /* Prevent unused argument(s) compilation warning */ 00308 UNUSED(hsdram); 00309 00310 /* NOTE: This function Should not be modified, when the callback is needed, 00311 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file 00312 */ 00313 } 00314 00315 /** 00316 * @brief DMA transfer complete callback. 00317 * @param hmdma pointer to a DMA_HandleTypeDef structure that contains 00318 * the configuration information for the specified DMA module. 00319 * @retval None 00320 */ 00321 __weak void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma) 00322 { 00323 /* Prevent unused argument(s) compilation warning */ 00324 UNUSED(hmdma); 00325 00326 /* NOTE: This function Should not be modified, when the callback is needed, 00327 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file 00328 */ 00329 } 00330 00331 /** 00332 * @brief DMA transfer complete error callback. 00333 * @param hmdma DMA handle 00334 * @retval None 00335 */ 00336 __weak void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma) 00337 { 00338 /* Prevent unused argument(s) compilation warning */ 00339 UNUSED(hmdma); 00340 00341 /* NOTE: This function Should not be modified, when the callback is needed, 00342 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file 00343 */ 00344 } 00345 00346 /** 00347 * @} 00348 */ 00349 00350 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions 00351 * @brief Input Output and memory control functions 00352 * 00353 @verbatim 00354 ============================================================================== 00355 ##### SDRAM Input and Output functions ##### 00356 ============================================================================== 00357 [..] 00358 This section provides functions allowing to use and control the SDRAM memory 00359 00360 @endverbatim 00361 * @{ 00362 */ 00363 00364 /** 00365 * @brief Reads 8-bit data buffer from the SDRAM memory. 00366 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00367 * the configuration information for SDRAM module. 00368 * @param pAddress Pointer to read start address 00369 * @param pDstBuffer Pointer to destination buffer 00370 * @param BufferSize Size of the buffer to read from memory 00371 * @retval HAL status 00372 */ 00373 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, 00374 uint32_t BufferSize) 00375 { 00376 uint32_t size; 00377 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; 00378 uint8_t *pdestbuff = pDstBuffer; 00379 HAL_SDRAM_StateTypeDef state = hsdram->State; 00380 00381 /* Check the SDRAM controller state */ 00382 if (state == HAL_SDRAM_STATE_BUSY) 00383 { 00384 return HAL_BUSY; 00385 } 00386 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00387 { 00388 /* Process Locked */ 00389 __HAL_LOCK(hsdram); 00390 00391 /* Update the SDRAM controller state */ 00392 hsdram->State = HAL_SDRAM_STATE_BUSY; 00393 00394 /* Read data from source */ 00395 for (size = BufferSize; size != 0U; size--) 00396 { 00397 *pdestbuff = *(__IO uint8_t *)pSdramAddress; 00398 pdestbuff++; 00399 pSdramAddress++; 00400 } 00401 00402 /* Update the SDRAM controller state */ 00403 hsdram->State = state; 00404 00405 /* Process Unlocked */ 00406 __HAL_UNLOCK(hsdram); 00407 } 00408 else 00409 { 00410 return HAL_ERROR; 00411 } 00412 00413 return HAL_OK; 00414 } 00415 00416 /** 00417 * @brief Writes 8-bit data buffer to SDRAM memory. 00418 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00419 * the configuration information for SDRAM module. 00420 * @param pAddress Pointer to write start address 00421 * @param pSrcBuffer Pointer to source buffer to write 00422 * @param BufferSize Size of the buffer to write to memory 00423 * @retval HAL status 00424 */ 00425 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, 00426 uint32_t BufferSize) 00427 { 00428 uint32_t size; 00429 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; 00430 uint8_t *psrcbuff = pSrcBuffer; 00431 00432 /* Check the SDRAM controller state */ 00433 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 00434 { 00435 return HAL_BUSY; 00436 } 00437 else if (hsdram->State == HAL_SDRAM_STATE_READY) 00438 { 00439 /* Process Locked */ 00440 __HAL_LOCK(hsdram); 00441 00442 /* Update the SDRAM controller state */ 00443 hsdram->State = HAL_SDRAM_STATE_BUSY; 00444 00445 /* Write data to memory */ 00446 for (size = BufferSize; size != 0U; size--) 00447 { 00448 *(__IO uint8_t *)pSdramAddress = *psrcbuff; 00449 psrcbuff++; 00450 pSdramAddress++; 00451 } 00452 00453 /* Update the SDRAM controller state */ 00454 hsdram->State = HAL_SDRAM_STATE_READY; 00455 00456 /* Process Unlocked */ 00457 __HAL_UNLOCK(hsdram); 00458 } 00459 else 00460 { 00461 return HAL_ERROR; 00462 } 00463 00464 return HAL_OK; 00465 } 00466 00467 /** 00468 * @brief Reads 16-bit data buffer from the SDRAM memory. 00469 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00470 * the configuration information for SDRAM module. 00471 * @param pAddress Pointer to read start address 00472 * @param pDstBuffer Pointer to destination buffer 00473 * @param BufferSize Size of the buffer to read from memory 00474 * @retval HAL status 00475 */ 00476 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, 00477 uint32_t BufferSize) 00478 { 00479 uint32_t size; 00480 __IO uint32_t *pSdramAddress = pAddress; 00481 uint16_t *pdestbuff = pDstBuffer; 00482 HAL_SDRAM_StateTypeDef state = hsdram->State; 00483 00484 /* Check the SDRAM controller state */ 00485 if (state == HAL_SDRAM_STATE_BUSY) 00486 { 00487 return HAL_BUSY; 00488 } 00489 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00490 { 00491 /* Process Locked */ 00492 __HAL_LOCK(hsdram); 00493 00494 /* Update the SDRAM controller state */ 00495 hsdram->State = HAL_SDRAM_STATE_BUSY; 00496 00497 /* Read data from memory */ 00498 for (size = BufferSize; size >= 2U ; size -= 2U) 00499 { 00500 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); 00501 pdestbuff++; 00502 *pdestbuff = (uint16_t)(((*pSdramAddress) & 0xFFFF0000U) >> 16U); 00503 pdestbuff++; 00504 pSdramAddress++; 00505 } 00506 00507 /* Read last 16-bits if size is not 32-bits multiple */ 00508 if ((BufferSize % 2U) != 0U) 00509 { 00510 *pdestbuff = (uint16_t)((*pSdramAddress) & 0x0000FFFFU); 00511 } 00512 00513 /* Update the SDRAM controller state */ 00514 hsdram->State = state; 00515 00516 /* Process Unlocked */ 00517 __HAL_UNLOCK(hsdram); 00518 } 00519 else 00520 { 00521 return HAL_ERROR; 00522 } 00523 00524 return HAL_OK; 00525 } 00526 00527 /** 00528 * @brief Writes 16-bit data buffer to SDRAM memory. 00529 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00530 * the configuration information for SDRAM module. 00531 * @param pAddress Pointer to write start address 00532 * @param pSrcBuffer Pointer to source buffer to write 00533 * @param BufferSize Size of the buffer to write to memory 00534 * @retval HAL status 00535 */ 00536 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, 00537 uint32_t BufferSize) 00538 { 00539 uint32_t size; 00540 __IO uint32_t *psdramaddress = pAddress; 00541 uint16_t *psrcbuff = pSrcBuffer; 00542 00543 /* Check the SDRAM controller state */ 00544 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 00545 { 00546 return HAL_BUSY; 00547 } 00548 else if (hsdram->State == HAL_SDRAM_STATE_READY) 00549 { 00550 /* Process Locked */ 00551 __HAL_LOCK(hsdram); 00552 00553 /* Update the SDRAM controller state */ 00554 hsdram->State = HAL_SDRAM_STATE_BUSY; 00555 00556 /* Write data to memory */ 00557 for (size = BufferSize; size >= 2U ; size -= 2U) 00558 { 00559 *psdramaddress = (uint32_t)(*psrcbuff); 00560 psrcbuff++; 00561 *psdramaddress |= ((uint32_t)(*psrcbuff) << 16U); 00562 psrcbuff++; 00563 psdramaddress++; 00564 } 00565 00566 /* Write last 16-bits if size is not 32-bits multiple */ 00567 if ((BufferSize % 2U) != 0U) 00568 { 00569 *psdramaddress = ((uint32_t)(*psrcbuff) & 0x0000FFFFU) | ((*psdramaddress) & 0xFFFF0000U); 00570 } 00571 00572 /* Update the SDRAM controller state */ 00573 hsdram->State = HAL_SDRAM_STATE_READY; 00574 00575 /* Process Unlocked */ 00576 __HAL_UNLOCK(hsdram); 00577 } 00578 else 00579 { 00580 return HAL_ERROR; 00581 } 00582 00583 return HAL_OK; 00584 } 00585 00586 /** 00587 * @brief Reads 32-bit data buffer from the SDRAM memory. 00588 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00589 * the configuration information for SDRAM module. 00590 * @param pAddress Pointer to read start address 00591 * @param pDstBuffer Pointer to destination buffer 00592 * @param BufferSize Size of the buffer to read from memory 00593 * @retval HAL status 00594 */ 00595 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, 00596 uint32_t BufferSize) 00597 { 00598 uint32_t size; 00599 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; 00600 uint32_t *pdestbuff = pDstBuffer; 00601 HAL_SDRAM_StateTypeDef state = hsdram->State; 00602 00603 /* Check the SDRAM controller state */ 00604 if (state == HAL_SDRAM_STATE_BUSY) 00605 { 00606 return HAL_BUSY; 00607 } 00608 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00609 { 00610 /* Process Locked */ 00611 __HAL_LOCK(hsdram); 00612 00613 /* Update the SDRAM controller state */ 00614 hsdram->State = HAL_SDRAM_STATE_BUSY; 00615 00616 /* Read data from source */ 00617 for (size = BufferSize; size != 0U; size--) 00618 { 00619 *pdestbuff = *(__IO uint32_t *)pSdramAddress; 00620 pdestbuff++; 00621 pSdramAddress++; 00622 } 00623 00624 /* Update the SDRAM controller state */ 00625 hsdram->State = state; 00626 00627 /* Process Unlocked */ 00628 __HAL_UNLOCK(hsdram); 00629 } 00630 else 00631 { 00632 return HAL_ERROR; 00633 } 00634 00635 return HAL_OK; 00636 } 00637 00638 /** 00639 * @brief Writes 32-bit data buffer to SDRAM memory. 00640 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00641 * the configuration information for SDRAM module. 00642 * @param pAddress Pointer to write start address 00643 * @param pSrcBuffer Pointer to source buffer to write 00644 * @param BufferSize Size of the buffer to write to memory 00645 * @retval HAL status 00646 */ 00647 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, 00648 uint32_t BufferSize) 00649 { 00650 uint32_t size; 00651 __IO uint32_t *pSdramAddress = pAddress; 00652 uint32_t *psrcbuff = pSrcBuffer; 00653 00654 /* Check the SDRAM controller state */ 00655 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 00656 { 00657 return HAL_BUSY; 00658 } 00659 else if (hsdram->State == HAL_SDRAM_STATE_READY) 00660 { 00661 /* Process Locked */ 00662 __HAL_LOCK(hsdram); 00663 00664 /* Update the SDRAM controller state */ 00665 hsdram->State = HAL_SDRAM_STATE_BUSY; 00666 00667 /* Write data to memory */ 00668 for (size = BufferSize; size != 0U; size--) 00669 { 00670 *pSdramAddress = *psrcbuff; 00671 psrcbuff++; 00672 pSdramAddress++; 00673 } 00674 00675 /* Update the SDRAM controller state */ 00676 hsdram->State = HAL_SDRAM_STATE_READY; 00677 00678 /* Process Unlocked */ 00679 __HAL_UNLOCK(hsdram); 00680 } 00681 else 00682 { 00683 return HAL_ERROR; 00684 } 00685 00686 return HAL_OK; 00687 } 00688 00689 /** 00690 * @brief Reads a Words data from the SDRAM memory using DMA transfer. 00691 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00692 * the configuration information for SDRAM module. 00693 * @param pAddress Pointer to read start address 00694 * @param pDstBuffer Pointer to destination buffer 00695 * @param BufferSize Size of the buffer to read from memory 00696 * @retval HAL status 00697 */ 00698 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, 00699 uint32_t BufferSize) 00700 { 00701 HAL_StatusTypeDef status; 00702 HAL_SDRAM_StateTypeDef state = hsdram->State; 00703 00704 /* Check the SDRAM controller state */ 00705 if (state == HAL_SDRAM_STATE_BUSY) 00706 { 00707 status = HAL_BUSY; 00708 } 00709 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00710 { 00711 /* Process Locked */ 00712 __HAL_LOCK(hsdram); 00713 00714 /* Update the SDRAM controller state */ 00715 hsdram->State = HAL_SDRAM_STATE_BUSY; 00716 00717 /* Configure DMA user callbacks */ 00718 if (state == HAL_SDRAM_STATE_READY) 00719 { 00720 hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt; 00721 } 00722 else 00723 { 00724 hsdram->hmdma->XferCpltCallback = SDRAM_DMACpltProt; 00725 } 00726 hsdram->hmdma->XferErrorCallback = SDRAM_DMAError; 00727 00728 /* Enable the DMA Stream */ 00729 status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)(BufferSize * 4U), 1); 00730 00731 /* Process Unlocked */ 00732 __HAL_UNLOCK(hsdram); 00733 } 00734 else 00735 { 00736 status = HAL_ERROR; 00737 } 00738 00739 return status; 00740 } 00741 00742 /** 00743 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. 00744 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00745 * the configuration information for SDRAM module. 00746 * @param pAddress Pointer to write start address 00747 * @param pSrcBuffer Pointer to source buffer to write 00748 * @param BufferSize Size of the buffer to write to memory 00749 * @retval HAL status 00750 */ 00751 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, 00752 uint32_t BufferSize) 00753 { 00754 HAL_StatusTypeDef status; 00755 00756 /* Check the SDRAM controller state */ 00757 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 00758 { 00759 status = HAL_BUSY; 00760 } 00761 else if (hsdram->State == HAL_SDRAM_STATE_READY) 00762 { 00763 /* Process Locked */ 00764 __HAL_LOCK(hsdram); 00765 00766 /* Update the SDRAM controller state */ 00767 hsdram->State = HAL_SDRAM_STATE_BUSY; 00768 00769 /* Configure DMA user callbacks */ 00770 hsdram->hmdma->XferCpltCallback = SDRAM_DMACplt; 00771 hsdram->hmdma->XferErrorCallback = SDRAM_DMAError; 00772 00773 /* Enable the DMA Stream */ 00774 status = HAL_MDMA_Start_IT(hsdram->hmdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)(BufferSize * 4U), 1); 00775 00776 /* Process Unlocked */ 00777 __HAL_UNLOCK(hsdram); 00778 } 00779 else 00780 { 00781 status = HAL_ERROR; 00782 } 00783 00784 return status; 00785 } 00786 00787 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 00788 /** 00789 * @brief Register a User SDRAM Callback 00790 * To be used instead of the weak (surcharged) predefined callback 00791 * @param hsdram : SDRAM handle 00792 * @param CallbackId : ID of the callback to be registered 00793 * This parameter can be one of the following values: 00794 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID 00795 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID 00796 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID 00797 * @param pCallback : pointer to the Callback function 00798 * @retval status 00799 */ 00800 HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, 00801 pSDRAM_CallbackTypeDef pCallback) 00802 { 00803 HAL_StatusTypeDef status = HAL_OK; 00804 HAL_SDRAM_StateTypeDef state; 00805 00806 if (pCallback == NULL) 00807 { 00808 return HAL_ERROR; 00809 } 00810 00811 /* Process locked */ 00812 __HAL_LOCK(hsdram); 00813 00814 state = hsdram->State; 00815 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00816 { 00817 switch (CallbackId) 00818 { 00819 case HAL_SDRAM_MSP_INIT_CB_ID : 00820 hsdram->MspInitCallback = pCallback; 00821 break; 00822 case HAL_SDRAM_MSP_DEINIT_CB_ID : 00823 hsdram->MspDeInitCallback = pCallback; 00824 break; 00825 case HAL_SDRAM_REFRESH_ERR_CB_ID : 00826 hsdram->RefreshErrorCallback = pCallback; 00827 break; 00828 default : 00829 /* update return status */ 00830 status = HAL_ERROR; 00831 break; 00832 } 00833 } 00834 else if (hsdram->State == HAL_SDRAM_STATE_RESET) 00835 { 00836 switch (CallbackId) 00837 { 00838 case HAL_SDRAM_MSP_INIT_CB_ID : 00839 hsdram->MspInitCallback = pCallback; 00840 break; 00841 case HAL_SDRAM_MSP_DEINIT_CB_ID : 00842 hsdram->MspDeInitCallback = pCallback; 00843 break; 00844 default : 00845 /* update return status */ 00846 status = HAL_ERROR; 00847 break; 00848 } 00849 } 00850 else 00851 { 00852 /* update return status */ 00853 status = HAL_ERROR; 00854 } 00855 00856 /* Release Lock */ 00857 __HAL_UNLOCK(hsdram); 00858 return status; 00859 } 00860 00861 /** 00862 * @brief Unregister a User SDRAM Callback 00863 * SDRAM Callback is redirected to the weak (surcharged) predefined callback 00864 * @param hsdram : SDRAM handle 00865 * @param CallbackId : ID of the callback to be unregistered 00866 * This parameter can be one of the following values: 00867 * @arg @ref HAL_SDRAM_MSP_INIT_CB_ID SDRAM MspInit callback ID 00868 * @arg @ref HAL_SDRAM_MSP_DEINIT_CB_ID SDRAM MspDeInit callback ID 00869 * @arg @ref HAL_SDRAM_REFRESH_ERR_CB_ID SDRAM Refresh Error callback ID 00870 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID 00871 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID 00872 * @retval status 00873 */ 00874 HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId) 00875 { 00876 HAL_StatusTypeDef status = HAL_OK; 00877 HAL_SDRAM_StateTypeDef state; 00878 00879 /* Process locked */ 00880 __HAL_LOCK(hsdram); 00881 00882 state = hsdram->State; 00883 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00884 { 00885 switch (CallbackId) 00886 { 00887 case HAL_SDRAM_MSP_INIT_CB_ID : 00888 hsdram->MspInitCallback = HAL_SDRAM_MspInit; 00889 break; 00890 case HAL_SDRAM_MSP_DEINIT_CB_ID : 00891 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; 00892 break; 00893 case HAL_SDRAM_REFRESH_ERR_CB_ID : 00894 hsdram->RefreshErrorCallback = HAL_SDRAM_RefreshErrorCallback; 00895 break; 00896 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : 00897 hsdram->DmaXferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; 00898 break; 00899 case HAL_SDRAM_DMA_XFER_ERR_CB_ID : 00900 hsdram->DmaXferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; 00901 break; 00902 default : 00903 /* update return status */ 00904 status = HAL_ERROR; 00905 break; 00906 } 00907 } 00908 else if (hsdram->State == HAL_SDRAM_STATE_RESET) 00909 { 00910 switch (CallbackId) 00911 { 00912 case HAL_SDRAM_MSP_INIT_CB_ID : 00913 hsdram->MspInitCallback = HAL_SDRAM_MspInit; 00914 break; 00915 case HAL_SDRAM_MSP_DEINIT_CB_ID : 00916 hsdram->MspDeInitCallback = HAL_SDRAM_MspDeInit; 00917 break; 00918 default : 00919 /* update return status */ 00920 status = HAL_ERROR; 00921 break; 00922 } 00923 } 00924 else 00925 { 00926 /* update return status */ 00927 status = HAL_ERROR; 00928 } 00929 00930 /* Release Lock */ 00931 __HAL_UNLOCK(hsdram); 00932 return status; 00933 } 00934 00935 /** 00936 * @brief Register a User SDRAM Callback for DMA transfers 00937 * To be used instead of the weak (surcharged) predefined callback 00938 * @param hsdram : SDRAM handle 00939 * @param CallbackId : ID of the callback to be registered 00940 * This parameter can be one of the following values: 00941 * @arg @ref HAL_SDRAM_DMA_XFER_CPLT_CB_ID SDRAM DMA Xfer Complete callback ID 00942 * @arg @ref HAL_SDRAM_DMA_XFER_ERR_CB_ID SDRAM DMA Xfer Error callback ID 00943 * @param pCallback : pointer to the Callback function 00944 * @retval status 00945 */ 00946 HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, 00947 pSDRAM_DmaCallbackTypeDef pCallback) 00948 { 00949 HAL_StatusTypeDef status = HAL_OK; 00950 HAL_SDRAM_StateTypeDef state; 00951 00952 if (pCallback == NULL) 00953 { 00954 return HAL_ERROR; 00955 } 00956 00957 /* Process locked */ 00958 __HAL_LOCK(hsdram); 00959 00960 state = hsdram->State; 00961 if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00962 { 00963 switch (CallbackId) 00964 { 00965 case HAL_SDRAM_DMA_XFER_CPLT_CB_ID : 00966 hsdram->DmaXferCpltCallback = pCallback; 00967 break; 00968 case HAL_SDRAM_DMA_XFER_ERR_CB_ID : 00969 hsdram->DmaXferErrorCallback = pCallback; 00970 break; 00971 default : 00972 /* update return status */ 00973 status = HAL_ERROR; 00974 break; 00975 } 00976 } 00977 else 00978 { 00979 /* update return status */ 00980 status = HAL_ERROR; 00981 } 00982 00983 /* Release Lock */ 00984 __HAL_UNLOCK(hsdram); 00985 return status; 00986 } 00987 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 00988 00989 /** 00990 * @} 00991 */ 00992 00993 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions 00994 * @brief management functions 00995 * 00996 @verbatim 00997 ============================================================================== 00998 ##### SDRAM Control functions ##### 00999 ============================================================================== 01000 [..] 01001 This subsection provides a set of functions allowing to control dynamically 01002 the SDRAM interface. 01003 01004 @endverbatim 01005 * @{ 01006 */ 01007 01008 /** 01009 * @brief Enables dynamically SDRAM write protection. 01010 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01011 * the configuration information for SDRAM module. 01012 * @retval HAL status 01013 */ 01014 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) 01015 { 01016 /* Check the SDRAM controller state */ 01017 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 01018 { 01019 return HAL_BUSY; 01020 } 01021 else if (hsdram->State == HAL_SDRAM_STATE_READY) 01022 { 01023 /* Update the SDRAM state */ 01024 hsdram->State = HAL_SDRAM_STATE_BUSY; 01025 01026 /* Enable write protection */ 01027 (void)FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); 01028 01029 /* Update the SDRAM state */ 01030 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; 01031 } 01032 else 01033 { 01034 return HAL_ERROR; 01035 } 01036 01037 return HAL_OK; 01038 } 01039 01040 /** 01041 * @brief Disables dynamically SDRAM write protection. 01042 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01043 * the configuration information for SDRAM module. 01044 * @retval HAL status 01045 */ 01046 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) 01047 { 01048 HAL_SDRAM_StateTypeDef state = hsdram->State; 01049 01050 /* Check the SDRAM controller state */ 01051 if (state == HAL_SDRAM_STATE_BUSY) 01052 { 01053 return HAL_BUSY; 01054 } 01055 else if (state == HAL_SDRAM_STATE_WRITE_PROTECTED) 01056 { 01057 /* Update the SDRAM state */ 01058 hsdram->State = HAL_SDRAM_STATE_BUSY; 01059 01060 /* Disable write protection */ 01061 (void)FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); 01062 01063 /* Update the SDRAM state */ 01064 hsdram->State = HAL_SDRAM_STATE_READY; 01065 } 01066 else 01067 { 01068 return HAL_ERROR; 01069 } 01070 01071 return HAL_OK; 01072 } 01073 01074 /** 01075 * @brief Sends Command to the SDRAM bank. 01076 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01077 * the configuration information for SDRAM module. 01078 * @param Command SDRAM command structure 01079 * @param Timeout Timeout duration 01080 * @retval HAL status 01081 */ 01082 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, 01083 uint32_t Timeout) 01084 { 01085 HAL_SDRAM_StateTypeDef state = hsdram->State; 01086 01087 /* Check the SDRAM controller state */ 01088 if (state == HAL_SDRAM_STATE_BUSY) 01089 { 01090 return HAL_BUSY; 01091 } 01092 else if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_PRECHARGED)) 01093 { 01094 /* Update the SDRAM state */ 01095 hsdram->State = HAL_SDRAM_STATE_BUSY; 01096 01097 /* Send SDRAM command */ 01098 (void)FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); 01099 01100 /* Update the SDRAM controller state state */ 01101 if (Command->CommandMode == FMC_SDRAM_CMD_PALL) 01102 { 01103 hsdram->State = HAL_SDRAM_STATE_PRECHARGED; 01104 } 01105 else 01106 { 01107 hsdram->State = HAL_SDRAM_STATE_READY; 01108 } 01109 } 01110 else 01111 { 01112 return HAL_ERROR; 01113 } 01114 01115 return HAL_OK; 01116 } 01117 01118 /** 01119 * @brief Programs the SDRAM Memory Refresh rate. 01120 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01121 * the configuration information for SDRAM module. 01122 * @param RefreshRate The SDRAM refresh rate value 01123 * @retval HAL status 01124 */ 01125 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) 01126 { 01127 /* Check the SDRAM controller state */ 01128 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 01129 { 01130 return HAL_BUSY; 01131 } 01132 else if (hsdram->State == HAL_SDRAM_STATE_READY) 01133 { 01134 /* Update the SDRAM state */ 01135 hsdram->State = HAL_SDRAM_STATE_BUSY; 01136 01137 /* Program the refresh rate */ 01138 (void)FMC_SDRAM_ProgramRefreshRate(hsdram->Instance, RefreshRate); 01139 01140 /* Update the SDRAM state */ 01141 hsdram->State = HAL_SDRAM_STATE_READY; 01142 } 01143 else 01144 { 01145 return HAL_ERROR; 01146 } 01147 01148 return HAL_OK; 01149 } 01150 01151 /** 01152 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. 01153 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01154 * the configuration information for SDRAM module. 01155 * @param AutoRefreshNumber The SDRAM auto Refresh number 01156 * @retval HAL status 01157 */ 01158 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) 01159 { 01160 /* Check the SDRAM controller state */ 01161 if (hsdram->State == HAL_SDRAM_STATE_BUSY) 01162 { 01163 return HAL_BUSY; 01164 } 01165 else if (hsdram->State == HAL_SDRAM_STATE_READY) 01166 { 01167 /* Update the SDRAM state */ 01168 hsdram->State = HAL_SDRAM_STATE_BUSY; 01169 01170 /* Set the Auto-Refresh number */ 01171 (void)FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance, AutoRefreshNumber); 01172 01173 /* Update the SDRAM state */ 01174 hsdram->State = HAL_SDRAM_STATE_READY; 01175 } 01176 else 01177 { 01178 return HAL_ERROR; 01179 } 01180 01181 return HAL_OK; 01182 } 01183 01184 /** 01185 * @brief Returns the SDRAM memory current mode. 01186 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01187 * the configuration information for SDRAM module. 01188 * @retval The SDRAM memory mode. 01189 */ 01190 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) 01191 { 01192 /* Return the SDRAM memory current mode */ 01193 return (FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); 01194 } 01195 01196 /** 01197 * @} 01198 */ 01199 01200 /** @defgroup SDRAM_Exported_Functions_Group4 State functions 01201 * @brief Peripheral State functions 01202 * 01203 @verbatim 01204 ============================================================================== 01205 ##### SDRAM State functions ##### 01206 ============================================================================== 01207 [..] 01208 This subsection permits to get in run-time the status of the SDRAM controller 01209 and the data flow. 01210 01211 @endverbatim 01212 * @{ 01213 */ 01214 01215 /** 01216 * @brief Returns the SDRAM state. 01217 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 01218 * the configuration information for SDRAM module. 01219 * @retval HAL state 01220 */ 01221 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) 01222 { 01223 return hsdram->State; 01224 } 01225 01226 /** 01227 * @} 01228 */ 01229 01230 /** 01231 * @} 01232 */ 01233 01234 /** 01235 * @brief MDMA SDRAM process complete callback. 01236 * @param hmdma : MDMA handle 01237 * @retval None 01238 */ 01239 static void SDRAM_DMACplt(MDMA_HandleTypeDef *hmdma) 01240 { 01241 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); 01242 01243 /* Disable the MDMA channel */ 01244 __HAL_MDMA_DISABLE(hmdma); 01245 01246 /* Update the SDRAM controller state */ 01247 hsdram->State = HAL_SDRAM_STATE_READY; 01248 01249 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 01250 hsdram->DmaXferCpltCallback(hmdma); 01251 #else 01252 HAL_SDRAM_DMA_XferCpltCallback(hmdma); 01253 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 01254 } 01255 01256 /** 01257 * @brief MDMA SRAM process complete callback. 01258 * @param hmdma : MDMA handle 01259 * @retval None 01260 */ 01261 static void SDRAM_DMACpltProt(MDMA_HandleTypeDef *hmdma) 01262 { 01263 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); 01264 01265 /* Disable the MDMA channel */ 01266 __HAL_MDMA_DISABLE(hmdma); 01267 01268 /* Update the SDRAM controller state */ 01269 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; 01270 01271 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 01272 hsdram->DmaXferCpltCallback(hmdma); 01273 #else 01274 HAL_SDRAM_DMA_XferCpltCallback(hmdma); 01275 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 01276 } 01277 01278 /** 01279 * @brief MDMA SDRAM error callback. 01280 * @param hmdma : MDMA handle 01281 * @retval None 01282 */ 01283 static void SDRAM_DMAError(MDMA_HandleTypeDef *hmdma) 01284 { 01285 SDRAM_HandleTypeDef *hsdram = (SDRAM_HandleTypeDef *)(hmdma->Parent); 01286 01287 /* Disable the MDMA channel */ 01288 __HAL_MDMA_DISABLE(hmdma); 01289 01290 /* Update the SDRAM controller state */ 01291 hsdram->State = HAL_SDRAM_STATE_ERROR; 01292 01293 #if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1) 01294 hsdram->DmaXferErrorCallback(hmdma); 01295 #else 01296 HAL_SDRAM_DMA_XferErrorCallback(hmdma); 01297 #endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS */ 01298 } 01299 01300 /** 01301 * @} 01302 */ 01303 01304 #endif /* HAL_SDRAM_MODULE_ENABLED */ 01305 01306 /** 01307 * @} 01308 */ 01309