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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_smbus.h 00004 * @author MCD Application Team 00005 * @brief Header file of SMBUS HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_SMBUS_H 00021 #define STM32H7xx_HAL_SMBUS_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 /** @addtogroup STM32H7xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup SMBUS 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types 00040 * @{ 00041 */ 00042 00043 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition 00044 * @brief SMBUS Configuration Structure definition 00045 * @{ 00046 */ 00047 typedef struct 00048 { 00049 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. 00050 This parameter calculated by referring to SMBUS initialization section 00051 in Reference manual */ 00052 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 00053 This parameter can be a value of @ref SMBUS_Analog_Filter */ 00054 00055 uint32_t OwnAddress1; /*!< Specifies the first device own address. 00056 This parameter can be a 7-bit or 10-bit address. */ 00057 00058 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 00059 This parameter can be a value of @ref SMBUS_addressing_mode */ 00060 00061 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 00062 This parameter can be a value of @ref SMBUS_dual_addressing_mode */ 00063 00064 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 00065 This parameter can be a 7-bit address. */ 00066 00067 uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address 00068 if dual addressing mode is selected 00069 This parameter can be a value of @ref SMBUS_own_address2_masks. */ 00070 00071 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 00072 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ 00073 00074 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 00075 This parameter can be a value of @ref SMBUS_nostretch_mode */ 00076 00077 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 00078 This parameter can be a value of @ref SMBUS_packet_error_check_mode */ 00079 00080 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 00081 This parameter can be a value of @ref SMBUS_peripheral_mode */ 00082 00083 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. 00084 (Enable bits and different timeout values) 00085 This parameter calculated by referring to SMBUS initialization section 00086 in Reference manual */ 00087 } SMBUS_InitTypeDef; 00088 /** 00089 * @} 00090 */ 00091 00092 /** @defgroup HAL_state_definition HAL state definition 00093 * @brief HAL State definition 00094 * @{ 00095 */ 00096 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ 00097 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ 00098 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ 00099 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 00100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 00101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 00102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 00103 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 00104 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 00105 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 00106 /** 00107 * @} 00108 */ 00109 00110 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition 00111 * @brief SMBUS Error Code definition 00112 * @{ 00113 */ 00114 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 00115 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 00116 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 00117 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 00118 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 00119 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 00120 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 00121 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 00122 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 00123 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00124 #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 00125 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00126 #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 00127 /** 00128 * @} 00129 */ 00130 00131 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 00132 * @brief SMBUS handle Structure definition 00133 * @{ 00134 */ 00135 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00136 typedef struct __SMBUS_HandleTypeDef 00137 #else 00138 typedef struct 00139 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00140 { 00141 I2C_TypeDef *Instance; /*!< SMBUS registers base address */ 00142 00143 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ 00144 00145 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ 00146 00147 uint16_t XferSize; /*!< SMBUS transfer size */ 00148 00149 __IO uint16_t XferCount; /*!< SMBUS transfer counter */ 00150 00151 __IO uint32_t XferOptions; /*!< SMBUS transfer options */ 00152 00153 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ 00154 00155 HAL_LockTypeDef Lock; /*!< SMBUS locking object */ 00156 00157 __IO uint32_t State; /*!< SMBUS communication state */ 00158 00159 __IO uint32_t ErrorCode; /*!< SMBUS Error code */ 00160 00161 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00162 void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 00163 /*!< SMBUS Master Tx Transfer completed callback */ 00164 void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 00165 /*!< SMBUS Master Rx Transfer completed callback */ 00166 void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 00167 /*!< SMBUS Slave Tx Transfer completed callback */ 00168 void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 00169 /*!< SMBUS Slave Rx Transfer completed callback */ 00170 void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 00171 /*!< SMBUS Listen Complete callback */ 00172 void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 00173 /*!< SMBUS Error callback */ 00174 00175 void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 00176 /*!< SMBUS Slave Address Match callback */ 00177 00178 void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 00179 /*!< SMBUS Msp Init callback */ 00180 void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); 00181 /*!< SMBUS Msp DeInit callback */ 00182 00183 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00184 } SMBUS_HandleTypeDef; 00185 00186 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00187 /** 00188 * @brief HAL SMBUS Callback ID enumeration definition 00189 */ 00190 typedef enum 00191 { 00192 HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ 00193 HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ 00194 HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ 00195 HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ 00196 HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ 00197 HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ 00198 00199 HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ 00200 HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ 00201 00202 } HAL_SMBUS_CallbackIDTypeDef; 00203 00204 /** 00205 * @brief HAL SMBUS Callback pointer definition 00206 */ 00207 typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); 00208 /*!< pointer to an SMBUS callback function */ 00209 typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, 00210 uint16_t AddrMatchCode); 00211 /*!< pointer to an SMBUS Address Match callback function */ 00212 00213 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00214 /** 00215 * @} 00216 */ 00217 00218 /** 00219 * @} 00220 */ 00221 /* Exported constants --------------------------------------------------------*/ 00222 00223 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants 00224 * @{ 00225 */ 00226 00227 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter 00228 * @{ 00229 */ 00230 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) 00231 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 00232 /** 00233 * @} 00234 */ 00235 00236 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode 00237 * @{ 00238 */ 00239 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 00240 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 00241 /** 00242 * @} 00243 */ 00244 00245 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode 00246 * @{ 00247 */ 00248 00249 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) 00250 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 00251 /** 00252 * @} 00253 */ 00254 00255 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks 00256 * @{ 00257 */ 00258 00259 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) 00260 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) 00261 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) 00262 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) 00263 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) 00264 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) 00265 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) 00266 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) 00267 /** 00268 * @} 00269 */ 00270 00271 00272 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode 00273 * @{ 00274 */ 00275 #define SMBUS_GENERALCALL_DISABLE (0x00000000U) 00276 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN 00277 /** 00278 * @} 00279 */ 00280 00281 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode 00282 * @{ 00283 */ 00284 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) 00285 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 00286 /** 00287 * @} 00288 */ 00289 00290 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode 00291 * @{ 00292 */ 00293 #define SMBUS_PEC_DISABLE (0x00000000U) 00294 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN 00295 /** 00296 * @} 00297 */ 00298 00299 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode 00300 * @{ 00301 */ 00302 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN 00303 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) 00304 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN 00305 /** 00306 * @} 00307 */ 00308 00309 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition 00310 * @{ 00311 */ 00312 00313 #define SMBUS_SOFTEND_MODE (0x00000000U) 00314 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD 00315 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND 00316 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE 00317 /** 00318 * @} 00319 */ 00320 00321 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition 00322 * @{ 00323 */ 00324 00325 #define SMBUS_NO_STARTSTOP (0x00000000U) 00326 #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) 00327 #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 00328 #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 00329 /** 00330 * @} 00331 */ 00332 00333 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition 00334 * @{ 00335 */ 00336 00337 /* List of XferOptions in usage of : 00338 * 1- Restart condition when direction change 00339 * 2- No Restart condition in other use cases 00340 */ 00341 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE 00342 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) 00343 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 00344 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 00345 #define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) 00346 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 00347 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 00348 00349 /* List of XferOptions in usage of : 00350 * 1- Restart condition in all use cases (direction change or not) 00351 */ 00352 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 00353 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 00354 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 00355 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 00356 /** 00357 * @} 00358 */ 00359 00360 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition 00361 * @brief SMBUS Interrupt definition 00362 * Elements values convention: 0xXXXXXXXX 00363 * - XXXXXXXX : Interrupt control mask 00364 * @{ 00365 */ 00366 #define SMBUS_IT_ERRI I2C_CR1_ERRIE 00367 #define SMBUS_IT_TCI I2C_CR1_TCIE 00368 #define SMBUS_IT_STOPI I2C_CR1_STOPIE 00369 #define SMBUS_IT_NACKI I2C_CR1_NACKIE 00370 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE 00371 #define SMBUS_IT_RXI I2C_CR1_RXIE 00372 #define SMBUS_IT_TXI I2C_CR1_TXIE 00373 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ 00374 SMBUS_IT_NACKI | SMBUS_IT_TXI) 00375 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ 00376 SMBUS_IT_RXI) 00377 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) 00378 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) 00379 /** 00380 * @} 00381 */ 00382 00383 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition 00384 * @brief Flag definition 00385 * Elements values convention: 0xXXXXYYYY 00386 * - XXXXXXXX : Flag mask 00387 * @{ 00388 */ 00389 00390 #define SMBUS_FLAG_TXE I2C_ISR_TXE 00391 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS 00392 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE 00393 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR 00394 #define SMBUS_FLAG_AF I2C_ISR_NACKF 00395 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF 00396 #define SMBUS_FLAG_TC I2C_ISR_TC 00397 #define SMBUS_FLAG_TCR I2C_ISR_TCR 00398 #define SMBUS_FLAG_BERR I2C_ISR_BERR 00399 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO 00400 #define SMBUS_FLAG_OVR I2C_ISR_OVR 00401 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR 00402 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT 00403 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT 00404 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY 00405 #define SMBUS_FLAG_DIR I2C_ISR_DIR 00406 /** 00407 * @} 00408 */ 00409 00410 /** 00411 * @} 00412 */ 00413 00414 /* Exported macros ------------------------------------------------------------*/ 00415 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros 00416 * @{ 00417 */ 00418 00419 /** @brief Reset SMBUS handle state. 00420 * @param __HANDLE__ specifies the SMBUS Handle. 00421 * @retval None 00422 */ 00423 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00424 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00425 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ 00426 (__HANDLE__)->MspInitCallback = NULL; \ 00427 (__HANDLE__)->MspDeInitCallback = NULL; \ 00428 } while(0) 00429 #else 00430 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) 00431 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00432 00433 /** @brief Enable the specified SMBUS interrupts. 00434 * @param __HANDLE__ specifies the SMBUS Handle. 00435 * @param __INTERRUPT__ specifies the interrupt source to enable. 00436 * This parameter can be one of the following values: 00437 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 00438 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 00439 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 00440 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 00441 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 00442 * @arg @ref SMBUS_IT_RXI RX interrupt enable 00443 * @arg @ref SMBUS_IT_TXI TX interrupt enable 00444 * 00445 * @retval None 00446 */ 00447 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 00448 00449 /** @brief Disable the specified SMBUS interrupts. 00450 * @param __HANDLE__ specifies the SMBUS Handle. 00451 * @param __INTERRUPT__ specifies the interrupt source to disable. 00452 * This parameter can be one of the following values: 00453 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 00454 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 00455 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 00456 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 00457 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 00458 * @arg @ref SMBUS_IT_RXI RX interrupt enable 00459 * @arg @ref SMBUS_IT_TXI TX interrupt enable 00460 * 00461 * @retval None 00462 */ 00463 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 00464 00465 /** @brief Check whether the specified SMBUS interrupt source is enabled or not. 00466 * @param __HANDLE__ specifies the SMBUS Handle. 00467 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. 00468 * This parameter can be one of the following values: 00469 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 00470 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 00471 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 00472 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 00473 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 00474 * @arg @ref SMBUS_IT_RXI RX interrupt enable 00475 * @arg @ref SMBUS_IT_TXI TX interrupt enable 00476 * 00477 * @retval The new state of __IT__ (SET or RESET). 00478 */ 00479 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 00480 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00481 00482 /** @brief Check whether the specified SMBUS flag is set or not. 00483 * @param __HANDLE__ specifies the SMBUS Handle. 00484 * @param __FLAG__ specifies the flag to check. 00485 * This parameter can be one of the following values: 00486 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 00487 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status 00488 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty 00489 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 00490 * @arg @ref SMBUS_FLAG_AF NACK received flag 00491 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 00492 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) 00493 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload 00494 * @arg @ref SMBUS_FLAG_BERR Bus error 00495 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 00496 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 00497 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 00498 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 00499 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 00500 * @arg @ref SMBUS_FLAG_BUSY Bus busy 00501 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) 00502 * 00503 * @retval The new state of __FLAG__ (SET or RESET). 00504 */ 00505 #define SMBUS_FLAG_MASK (0x0001FFFFU) 00506 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ 00507 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ 00508 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 00509 00510 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. 00511 * @param __HANDLE__ specifies the SMBUS Handle. 00512 * @param __FLAG__ specifies the flag to clear. 00513 * This parameter can be any combination of the following values: 00514 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 00515 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 00516 * @arg @ref SMBUS_FLAG_AF NACK received flag 00517 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 00518 * @arg @ref SMBUS_FLAG_BERR Bus error 00519 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 00520 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 00521 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 00522 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 00523 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 00524 * 00525 * @retval None 00526 */ 00527 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \ 00528 ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ 00529 ((__HANDLE__)->Instance->ICR = (__FLAG__))) 00530 00531 /** @brief Enable the specified SMBUS peripheral. 00532 * @param __HANDLE__ specifies the SMBUS Handle. 00533 * @retval None 00534 */ 00535 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 00536 00537 /** @brief Disable the specified SMBUS peripheral. 00538 * @param __HANDLE__ specifies the SMBUS Handle. 00539 * @retval None 00540 */ 00541 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 00542 00543 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. 00544 * @param __HANDLE__ specifies the SMBUS Handle. 00545 * @retval None 00546 */ 00547 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 00548 00549 /** 00550 * @} 00551 */ 00552 00553 00554 /* Private constants ---------------------------------------------------------*/ 00555 00556 /* Private macros ------------------------------------------------------------*/ 00557 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros 00558 * @{ 00559 */ 00560 00561 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ 00562 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) 00563 00564 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 00565 00566 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ 00567 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) 00568 00569 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ 00570 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) 00571 00572 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ 00573 ((MASK) == SMBUS_OA2_MASK01) || \ 00574 ((MASK) == SMBUS_OA2_MASK02) || \ 00575 ((MASK) == SMBUS_OA2_MASK03) || \ 00576 ((MASK) == SMBUS_OA2_MASK04) || \ 00577 ((MASK) == SMBUS_OA2_MASK05) || \ 00578 ((MASK) == SMBUS_OA2_MASK06) || \ 00579 ((MASK) == SMBUS_OA2_MASK07)) 00580 00581 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ 00582 ((CALL) == SMBUS_GENERALCALL_ENABLE)) 00583 00584 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ 00585 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) 00586 00587 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ 00588 ((PEC) == SMBUS_PEC_ENABLE)) 00589 00590 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ 00591 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ 00592 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) 00593 00594 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ 00595 ((MODE) == SMBUS_AUTOEND_MODE) || \ 00596 ((MODE) == SMBUS_SOFTEND_MODE) || \ 00597 ((MODE) == SMBUS_SENDPEC_MODE) || \ 00598 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ 00599 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ 00600 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ 00601 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ 00602 SMBUS_RELOAD_MODE ))) 00603 00604 00605 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ 00606 ((REQUEST) == SMBUS_GENERATE_START_READ) || \ 00607 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ 00608 ((REQUEST) == SMBUS_NO_STARTSTOP)) 00609 00610 00611 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 00612 ((REQUEST) == SMBUS_FIRST_FRAME) || \ 00613 ((REQUEST) == SMBUS_NEXT_FRAME) || \ 00614 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 00615 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ 00616 ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ 00617 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 00618 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) 00619 00620 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ 00621 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 00622 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ 00623 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 00624 00625 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ 00626 (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ 00627 I2C_CR1_PECEN))) 00628 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ 00629 (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 00630 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 00631 I2C_CR2_RD_WRN))) 00632 00633 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ 00634 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ 00635 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ 00636 (~I2C_CR2_RD_WRN)) : \ 00637 (uint32_t)((((uint32_t)(__ADDRESS__) & \ 00638 (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ 00639 (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 00640 00641 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) 00642 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) 00643 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 00644 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) 00645 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) 00646 00647 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ 00648 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 00649 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 00650 00651 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 00652 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 00653 00654 /** 00655 * @} 00656 */ 00657 00658 /* Include SMBUS HAL Extended module */ 00659 #include "stm32h7xx_hal_smbus_ex.h" 00660 00661 /* Exported functions --------------------------------------------------------*/ 00662 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions 00663 * @{ 00664 */ 00665 00666 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 00667 * @{ 00668 */ 00669 00670 /* Initialization and de-initialization functions ****************************/ 00671 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); 00672 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); 00673 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); 00674 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); 00675 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); 00676 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); 00677 00678 /* Callbacks Register/UnRegister functions ***********************************/ 00679 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00680 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, 00681 HAL_SMBUS_CallbackIDTypeDef CallbackID, 00682 pSMBUS_CallbackTypeDef pCallback); 00683 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, 00684 HAL_SMBUS_CallbackIDTypeDef CallbackID); 00685 00686 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, 00687 pSMBUS_AddrCallbackTypeDef pCallback); 00688 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); 00689 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00690 /** 00691 * @} 00692 */ 00693 00694 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions 00695 * @{ 00696 */ 00697 00698 /* IO operation functions *****************************************************/ 00699 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 00700 * @{ 00701 */ 00702 /******* Blocking mode: Polling */ 00703 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, 00704 uint32_t Timeout); 00705 /** 00706 * @} 00707 */ 00708 00709 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 00710 * @{ 00711 */ 00712 /******* Non-Blocking mode: Interrupt */ 00713 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, 00714 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00715 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, 00716 uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00717 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); 00718 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, 00719 uint32_t XferOptions); 00720 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, 00721 uint32_t XferOptions); 00722 00723 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 00724 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 00725 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); 00726 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); 00727 /** 00728 * @} 00729 */ 00730 00731 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 00732 * @{ 00733 */ 00734 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 00735 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 00736 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 00737 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00738 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00739 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00740 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00741 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 00742 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00743 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); 00744 00745 /** 00746 * @} 00747 */ 00748 00749 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 00750 * @{ 00751 */ 00752 00753 /* Peripheral State and Errors functions **************************************************/ 00754 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); 00755 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); 00756 00757 /** 00758 * @} 00759 */ 00760 00761 /** 00762 * @} 00763 */ 00764 00765 /* Private Functions ---------------------------------------------------------*/ 00766 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions 00767 * @{ 00768 */ 00769 /* Private functions are defined in stm32h7xx_hal_smbus.c file */ 00770 /** 00771 * @} 00772 */ 00773 00774 /** 00775 * @} 00776 */ 00777 00778 /** 00779 * @} 00780 */ 00781 00782 /** 00783 * @} 00784 */ 00785 00786 #ifdef __cplusplus 00787 } 00788 #endif 00789 00790 00791 #endif /* STM32H7xx_HAL_SMBUS_H */
1.7.6.1