|
STM32H735xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_hal_spi.h 00004 * @author MCD Application Team 00005 * @brief Header file of SPI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_HAL_SPI_H 00021 #define STM32H7xx_HAL_SPI_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx_hal_def.h" 00029 00030 /** @addtogroup STM32H7xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup SPI 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup SPI_Exported_Types SPI Exported Types 00040 * @{ 00041 */ 00042 00043 /** 00044 * @brief SPI Configuration Structure definition 00045 */ 00046 typedef struct 00047 { 00048 uint32_t Mode; /*!< Specifies the SPI operating mode. 00049 This parameter can be a value of @ref SPI_Mode */ 00050 00051 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. 00052 This parameter can be a value of @ref SPI_Direction */ 00053 00054 uint32_t DataSize; /*!< Specifies the SPI data size. 00055 This parameter can be a value of @ref SPI_Data_Size */ 00056 00057 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. 00058 This parameter can be a value of @ref SPI_Clock_Polarity */ 00059 00060 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. 00061 This parameter can be a value of @ref SPI_Clock_Phase */ 00062 00063 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by 00064 hardware (NSS pin) or by software using the SSI bit. 00065 This parameter can be a value of 00066 @ref SPI_Slave_Select_Management */ 00067 00068 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 00069 used to configure the transmit and receive SCK clock. 00070 This parameter can be a value of @ref SPI_BaudRate_Prescaler 00071 @note The communication clock is derived from the master 00072 clock. The slave clock does not need to be set. */ 00073 00074 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 00075 This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ 00076 00077 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. 00078 This parameter can be a value of @ref SPI_TI_Mode */ 00079 00080 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 00081 This parameter can be a value of @ref SPI_CRC_Calculation */ 00082 00083 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. 00084 This parameter must be an odd number between 00085 Min_Data = 0 and Max_Data = 65535 */ 00086 00087 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. 00088 This parameter can be a value of @ref SPI_CRC_length */ 00089 00090 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . 00091 This parameter can be a value of @ref SPI_NSSP_Mode 00092 This mode is activated by the SSOM bit in the SPIx_CR2 register 00093 and it takes effect only if the SPI interface is configured 00094 as Motorola SPI master (FRF=0). */ 00095 00096 uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal 00097 (present on SS pin) is considered as active one. 00098 This parameter can be a value of @ref SPI_NSS_Polarity */ 00099 00100 uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. 00101 This parameter can be a value of @ref SPI_Fifo_Threshold */ 00102 00103 uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for 00104 the CRC calculation. This parameter can be a value of 00105 @ref SPI_CRC_Calculation_Initialization_Pattern */ 00106 00107 uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for 00108 the CRC calculation. This parameter can be a value of 00109 @ref SPI_CRC_Calculation_Initialization_Pattern */ 00110 00111 uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle 00112 periods, inserted additionally between active edge of SS 00113 and first data transaction start in master mode. 00114 This parameter can be a value of @ref SPI_Master_SS_Idleness */ 00115 00116 uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) 00117 inserted between two consecutive data frames in master mode. 00118 This parameter can be a value of 00119 @ref SPI_Master_InterData_Idleness */ 00120 00121 uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode 00122 and automatic management in order to avoid overrun condition. 00123 This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ 00124 00125 uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state 00126 This parameter can be a value of @ref SPI_Master_Keep_IO_State */ 00127 00128 uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions 00129 This parameter can be a value of @ref SPI_IO_Swap */ 00130 } SPI_InitTypeDef; 00131 00132 /** 00133 * @brief HAL SPI State structure definition 00134 */ 00135 typedef enum 00136 { 00137 HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ 00138 HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ 00139 HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ 00140 HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ 00141 HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ 00142 HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ 00143 HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ 00144 HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ 00145 } HAL_SPI_StateTypeDef; 00146 00147 #if defined(USE_SPI_RELOAD_TRANSFER) 00148 /** 00149 * @brief SPI Reload Structure definition 00150 */ 00151 typedef struct 00152 { 00153 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 00154 00155 uint16_t TxXferSize; /*!< SPI Tx Transfer size to reload */ 00156 00157 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 00158 00159 uint16_t RxXferSize; /*!< SPI Rx Transfer size to reload */ 00160 00161 uint32_t Requested; /*!< SPI reload request */ 00162 00163 } SPI_ReloadTypeDef; 00164 #endif /* USE_SPI_RELOAD_TRANSFER */ 00165 00166 /** 00167 * @brief SPI handle Structure definition 00168 */ 00169 typedef struct __SPI_HandleTypeDef 00170 { 00171 SPI_TypeDef *Instance; /*!< SPI registers base address */ 00172 00173 SPI_InitTypeDef Init; /*!< SPI communication parameters */ 00174 00175 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 00176 00177 uint16_t TxXferSize; /*!< SPI Tx Transfer size */ 00178 00179 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ 00180 00181 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 00182 00183 uint16_t RxXferSize; /*!< SPI Rx Transfer size */ 00184 00185 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ 00186 00187 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ 00188 00189 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ 00190 00191 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ 00192 00193 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ 00194 00195 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ 00196 00197 HAL_LockTypeDef Lock; /*!< Locking object */ 00198 00199 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ 00200 00201 __IO uint32_t ErrorCode; /*!< SPI Error code */ 00202 00203 #if defined(USE_SPI_RELOAD_TRANSFER) 00204 00205 SPI_ReloadTypeDef Reload; /*!< SPI reload parameters */ 00206 00207 #endif /* USE_SPI_RELOAD_TRANSFER */ 00208 00209 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 00210 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ 00211 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ 00212 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ 00213 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ 00214 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ 00215 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ 00216 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ 00217 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ 00218 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ 00219 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ 00220 00221 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00222 } SPI_HandleTypeDef; 00223 00224 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 00225 /** 00226 * @brief HAL SPI Callback ID enumeration definition 00227 */ 00228 typedef enum 00229 { 00230 HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ 00231 HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ 00232 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ 00233 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ 00234 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ 00235 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ 00236 HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ 00237 HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ 00238 HAL_SPI_MSPINIT_CB_ID = 0x08UL, /*!< SPI Msp Init callback ID */ 00239 HAL_SPI_MSPDEINIT_CB_ID = 0x09UL /*!< SPI Msp DeInit callback ID */ 00240 00241 } HAL_SPI_CallbackIDTypeDef; 00242 00243 /** 00244 * @brief HAL SPI Callback pointer definition 00245 */ 00246 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ 00247 00248 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00249 /** 00250 * @} 00251 */ 00252 00253 /* Exported constants --------------------------------------------------------*/ 00254 00255 /** @defgroup SPI_Exported_Constants SPI Exported Constants 00256 * @{ 00257 */ 00258 00259 /** @defgroup SPI_FIFO_Type SPI FIFO Type 00260 * @{ 00261 */ 00262 #define SPI_LOWEND_FIFO_SIZE 8UL 00263 #define SPI_HIGHEND_FIFO_SIZE 16UL 00264 /** 00265 * @} 00266 */ 00267 00268 /** @defgroup SPI_Error_Code SPI Error Codes 00269 * @{ 00270 */ 00271 #define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ 00272 #define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ 00273 #define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ 00274 #define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ 00275 #define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ 00276 #define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ 00277 #define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ 00278 #define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ 00279 #define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ 00280 #define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ 00281 #define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ 00282 #define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ 00283 #define HAL_SPI_ERROR_RELOAD (0x00000800UL) /*!< Reload error */ 00284 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 00285 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ 00286 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00287 /** 00288 * @} 00289 */ 00290 00291 /** @defgroup SPI_Mode SPI Mode 00292 * @{ 00293 */ 00294 #define SPI_MODE_SLAVE (0x00000000UL) 00295 #define SPI_MODE_MASTER SPI_CFG2_MASTER 00296 /** 00297 * @} 00298 */ 00299 00300 /** @defgroup SPI_Direction SPI Direction Mode 00301 * @{ 00302 */ 00303 #define SPI_DIRECTION_2LINES (0x00000000UL) 00304 #define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 00305 #define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 00306 #define SPI_DIRECTION_1LINE SPI_CFG2_COMM 00307 /** 00308 * @} 00309 */ 00310 00311 /** @defgroup SPI_Data_Size SPI Data Size 00312 * @{ 00313 */ 00314 #define SPI_DATASIZE_4BIT (0x00000003UL) 00315 #define SPI_DATASIZE_5BIT (0x00000004UL) 00316 #define SPI_DATASIZE_6BIT (0x00000005UL) 00317 #define SPI_DATASIZE_7BIT (0x00000006UL) 00318 #define SPI_DATASIZE_8BIT (0x00000007UL) 00319 #define SPI_DATASIZE_9BIT (0x00000008UL) 00320 #define SPI_DATASIZE_10BIT (0x00000009UL) 00321 #define SPI_DATASIZE_11BIT (0x0000000AUL) 00322 #define SPI_DATASIZE_12BIT (0x0000000BUL) 00323 #define SPI_DATASIZE_13BIT (0x0000000CUL) 00324 #define SPI_DATASIZE_14BIT (0x0000000DUL) 00325 #define SPI_DATASIZE_15BIT (0x0000000EUL) 00326 #define SPI_DATASIZE_16BIT (0x0000000FUL) 00327 #define SPI_DATASIZE_17BIT (0x00000010UL) 00328 #define SPI_DATASIZE_18BIT (0x00000011UL) 00329 #define SPI_DATASIZE_19BIT (0x00000012UL) 00330 #define SPI_DATASIZE_20BIT (0x00000013UL) 00331 #define SPI_DATASIZE_21BIT (0x00000014UL) 00332 #define SPI_DATASIZE_22BIT (0x00000015UL) 00333 #define SPI_DATASIZE_23BIT (0x00000016UL) 00334 #define SPI_DATASIZE_24BIT (0x00000017UL) 00335 #define SPI_DATASIZE_25BIT (0x00000018UL) 00336 #define SPI_DATASIZE_26BIT (0x00000019UL) 00337 #define SPI_DATASIZE_27BIT (0x0000001AUL) 00338 #define SPI_DATASIZE_28BIT (0x0000001BUL) 00339 #define SPI_DATASIZE_29BIT (0x0000001CUL) 00340 #define SPI_DATASIZE_30BIT (0x0000001DUL) 00341 #define SPI_DATASIZE_31BIT (0x0000001EUL) 00342 #define SPI_DATASIZE_32BIT (0x0000001FUL) 00343 /** 00344 * @} 00345 */ 00346 00347 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity 00348 * @{ 00349 */ 00350 #define SPI_POLARITY_LOW (0x00000000UL) 00351 #define SPI_POLARITY_HIGH SPI_CFG2_CPOL 00352 /** 00353 * @} 00354 */ 00355 00356 /** @defgroup SPI_Clock_Phase SPI Clock Phase 00357 * @{ 00358 */ 00359 #define SPI_PHASE_1EDGE (0x00000000UL) 00360 #define SPI_PHASE_2EDGE SPI_CFG2_CPHA 00361 /** 00362 * @} 00363 */ 00364 00365 /** @defgroup SPI_Slave_Select_Management SPI Slave Select Management 00366 * @{ 00367 */ 00368 #define SPI_NSS_SOFT SPI_CFG2_SSM 00369 #define SPI_NSS_HARD_INPUT (0x00000000UL) 00370 #define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE 00371 /** 00372 * @} 00373 */ 00374 00375 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode 00376 * @{ 00377 */ 00378 #define SPI_NSS_PULSE_DISABLE (0x00000000UL) 00379 #define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM 00380 /** 00381 * @} 00382 */ 00383 00384 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler 00385 * @{ 00386 */ 00387 #define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) 00388 #define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) 00389 #define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) 00390 #define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) 00391 #define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) 00392 #define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) 00393 #define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) 00394 #define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) 00395 /** 00396 * @} 00397 */ 00398 00399 /** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission 00400 * @{ 00401 */ 00402 #define SPI_FIRSTBIT_MSB (0x00000000UL) 00403 #define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST 00404 /** 00405 * @} 00406 */ 00407 00408 /** @defgroup SPI_TI_Mode SPI TI Mode 00409 * @{ 00410 */ 00411 #define SPI_TIMODE_DISABLE (0x00000000UL) 00412 #define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 00413 /** 00414 * @} 00415 */ 00416 00417 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation 00418 * @{ 00419 */ 00420 #define SPI_CRCCALCULATION_DISABLE (0x00000000UL) 00421 #define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN 00422 /** 00423 * @} 00424 */ 00425 00426 /** @defgroup SPI_CRC_length SPI CRC Length 00427 * @{ 00428 */ 00429 #define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) 00430 #define SPI_CRC_LENGTH_4BIT (0x00030000UL) 00431 #define SPI_CRC_LENGTH_5BIT (0x00040000UL) 00432 #define SPI_CRC_LENGTH_6BIT (0x00050000UL) 00433 #define SPI_CRC_LENGTH_7BIT (0x00060000UL) 00434 #define SPI_CRC_LENGTH_8BIT (0x00070000UL) 00435 #define SPI_CRC_LENGTH_9BIT (0x00080000UL) 00436 #define SPI_CRC_LENGTH_10BIT (0x00090000UL) 00437 #define SPI_CRC_LENGTH_11BIT (0x000A0000UL) 00438 #define SPI_CRC_LENGTH_12BIT (0x000B0000UL) 00439 #define SPI_CRC_LENGTH_13BIT (0x000C0000UL) 00440 #define SPI_CRC_LENGTH_14BIT (0x000D0000UL) 00441 #define SPI_CRC_LENGTH_15BIT (0x000E0000UL) 00442 #define SPI_CRC_LENGTH_16BIT (0x000F0000UL) 00443 #define SPI_CRC_LENGTH_17BIT (0x00100000UL) 00444 #define SPI_CRC_LENGTH_18BIT (0x00110000UL) 00445 #define SPI_CRC_LENGTH_19BIT (0x00120000UL) 00446 #define SPI_CRC_LENGTH_20BIT (0x00130000UL) 00447 #define SPI_CRC_LENGTH_21BIT (0x00140000UL) 00448 #define SPI_CRC_LENGTH_22BIT (0x00150000UL) 00449 #define SPI_CRC_LENGTH_23BIT (0x00160000UL) 00450 #define SPI_CRC_LENGTH_24BIT (0x00170000UL) 00451 #define SPI_CRC_LENGTH_25BIT (0x00180000UL) 00452 #define SPI_CRC_LENGTH_26BIT (0x00190000UL) 00453 #define SPI_CRC_LENGTH_27BIT (0x001A0000UL) 00454 #define SPI_CRC_LENGTH_28BIT (0x001B0000UL) 00455 #define SPI_CRC_LENGTH_29BIT (0x001C0000UL) 00456 #define SPI_CRC_LENGTH_30BIT (0x001D0000UL) 00457 #define SPI_CRC_LENGTH_31BIT (0x001E0000UL) 00458 #define SPI_CRC_LENGTH_32BIT (0x001F0000UL) 00459 /** 00460 * @} 00461 */ 00462 00463 /** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold 00464 * @{ 00465 */ 00466 #define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) 00467 #define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) 00468 #define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) 00469 #define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) 00470 #define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) 00471 #define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) 00472 #define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) 00473 #define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) 00474 #define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) 00475 #define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) 00476 #define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) 00477 #define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) 00478 #define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) 00479 #define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) 00480 #define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) 00481 #define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) 00482 /** 00483 * @} 00484 */ 00485 00486 /** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern 00487 * @{ 00488 */ 00489 #define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) 00490 #define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) 00491 /** 00492 * @} 00493 */ 00494 00495 /** @defgroup SPI_NSS_Polarity SPI NSS Polarity 00496 * @{ 00497 */ 00498 #define SPI_NSS_POLARITY_LOW (0x00000000UL) 00499 #define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP 00500 /** 00501 * @} 00502 */ 00503 00504 /** @defgroup SPI_Master_Keep_IO_State Keep IO State 00505 * @{ 00506 */ 00507 #define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) 00508 #define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR 00509 /** 00510 * @} 00511 */ 00512 00513 /** @defgroup SPI_IO_Swap Control SPI IO Swap 00514 * @{ 00515 */ 00516 #define SPI_IO_SWAP_DISABLE (0x00000000UL) 00517 #define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP 00518 /** 00519 * @} 00520 */ 00521 00522 /** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness 00523 * @{ 00524 */ 00525 #define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) 00526 #define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) 00527 #define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) 00528 #define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) 00529 #define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) 00530 #define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) 00531 #define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) 00532 #define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) 00533 #define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) 00534 #define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) 00535 #define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) 00536 #define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) 00537 #define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) 00538 #define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) 00539 #define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) 00540 #define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) 00541 /** 00542 * @} 00543 */ 00544 00545 /** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness 00546 * @{ 00547 */ 00548 #define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) 00549 #define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) 00550 #define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) 00551 #define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) 00552 #define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) 00553 #define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) 00554 #define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) 00555 #define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) 00556 #define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) 00557 #define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) 00558 #define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) 00559 #define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) 00560 #define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) 00561 #define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) 00562 #define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) 00563 #define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) 00564 /** 00565 * @} 00566 */ 00567 00568 /** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend 00569 * @{ 00570 */ 00571 #define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) 00572 #define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX 00573 /** 00574 * @} 00575 */ 00576 00577 /** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior 00578 * @{ 00579 */ 00580 #define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) 00581 #define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG_0 00582 #define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED SPI_CFG1_UDRCFG_1 00583 /** 00584 * @} 00585 */ 00586 00587 /** @defgroup SPI_Underrun_Detection SPI Underrun Detection 00588 * @{ 00589 */ 00590 #define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME (0x00000000UL) 00591 #define SPI_UNDERRUN_DETECT_END_DATA_FRAME SPI_CFG1_UDRDET_0 00592 #define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS SPI_CFG1_UDRDET_1 00593 /** 00594 * @} 00595 */ 00596 00597 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition 00598 * @{ 00599 */ 00600 #define SPI_IT_RXP SPI_IER_RXPIE 00601 #define SPI_IT_TXP SPI_IER_TXPIE 00602 #define SPI_IT_DXP SPI_IER_DXPIE 00603 #define SPI_IT_EOT SPI_IER_EOTIE 00604 #define SPI_IT_TXTF SPI_IER_TXTFIE 00605 #define SPI_IT_UDR SPI_IER_UDRIE 00606 #define SPI_IT_OVR SPI_IER_OVRIE 00607 #define SPI_IT_CRCERR SPI_IER_CRCEIE 00608 #define SPI_IT_FRE SPI_IER_TIFREIE 00609 #define SPI_IT_MODF SPI_IER_MODFIE 00610 #define SPI_IT_TSERF SPI_IER_TSERFIE 00611 #define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) 00612 /** 00613 * @} 00614 */ 00615 00616 /** @defgroup SPI_Flags_definition SPI Flags Definition 00617 * @{ 00618 */ 00619 #define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ 00620 #define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ 00621 #define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ 00622 #define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ 00623 #define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ 00624 #define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ 00625 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ 00626 #define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ 00627 #define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ 00628 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ 00629 #define SPI_FLAG_TSERF SPI_SR_TSERF /* SPI status flag : Additional number of data reloaded flag */ 00630 #define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ 00631 #define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ 00632 #define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ 00633 #define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ 00634 /** 00635 * @} 00636 */ 00637 00638 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level 00639 * @{ 00640 */ 00641 #define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ 00642 #define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) 00643 #define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) 00644 #define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) 00645 /** 00646 * @} 00647 */ 00648 00649 /** 00650 * @} 00651 */ 00652 00653 /* Exported macros -----------------------------------------------------------*/ 00654 /** @defgroup SPI_Exported_Macros SPI Exported Macros 00655 * @{ 00656 */ 00657 00658 /** @brief Reset SPI handle state. 00659 * @param __HANDLE__: specifies the SPI Handle. 00660 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 00661 * @retval None 00662 */ 00663 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) 00664 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00665 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ 00666 (__HANDLE__)->MspInitCallback = NULL; \ 00667 (__HANDLE__)->MspDeInitCallback = NULL; \ 00668 } while(0) 00669 #else 00670 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) 00671 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00672 00673 /** @brief Enable the specified SPI interrupts. 00674 * @param __HANDLE__: specifies the SPI Handle. 00675 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 00676 * @param __INTERRUPT__: specifies the interrupt source to enable or disable. 00677 * This parameter can be one of the following values: 00678 * @arg SPI_IT_RXP : Rx-Packet available interrupt 00679 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 00680 * @arg SPI_IT_DXP : Duplex Packet interrupt 00681 * @arg SPI_IT_EOT : End of transfer interrupt 00682 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 00683 * @arg SPI_IT_UDR : Underrun interrupt 00684 * @arg SPI_IT_OVR : Overrun interrupt 00685 * @arg SPI_IT_CRCERR : CRC error interrupt 00686 * @arg SPI_IT_FRE : TI mode frame format error interrupt 00687 * @arg SPI_IT_MODF : Mode fault interrupt 00688 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt 00689 * @arg SPI_IT_ERR : Error interrupt 00690 * @retval None 00691 */ 00692 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) 00693 00694 /** @brief Disable the specified SPI interrupts. 00695 * @param __HANDLE__: specifies the SPI Handle. 00696 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 00697 * @param __INTERRUPT__: specifies the interrupt source to enable or disable. 00698 * This parameter can be one of the following values: 00699 * @arg SPI_IT_RXP : Rx-Packet available interrupt 00700 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 00701 * @arg SPI_IT_DXP : Duplex Packet interrupt 00702 * @arg SPI_IT_EOT : End of transfer interrupt 00703 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 00704 * @arg SPI_IT_UDR : Underrun interrupt 00705 * @arg SPI_IT_OVR : Overrun interrupt 00706 * @arg SPI_IT_CRCERR : CRC error interrupt 00707 * @arg SPI_IT_FRE : TI mode frame format error interrupt 00708 * @arg SPI_IT_MODF : Mode fault interrupt 00709 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt 00710 * @arg SPI_IT_ERR : Error interrupt 00711 * @retval None 00712 */ 00713 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) 00714 00715 /** @brief Check whether the specified SPI interrupt source is enabled or not. 00716 * @param __HANDLE__: specifies the SPI Handle. 00717 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 00718 * @param __INTERRUPT__: specifies the SPI interrupt source to check. 00719 * This parameter can be one of the following values: 00720 * @arg SPI_IT_RXP : Rx-Packet available interrupt 00721 * @arg SPI_IT_TXP : Tx-Packet space available interrupt 00722 * @arg SPI_IT_DXP : Duplex Packet interrupt 00723 * @arg SPI_IT_EOT : End of transfer interrupt 00724 * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt 00725 * @arg SPI_IT_UDR : Underrun interrupt 00726 * @arg SPI_IT_OVR : Overrun interrupt 00727 * @arg SPI_IT_CRCERR : CRC error interrupt 00728 * @arg SPI_IT_FRE : TI mode frame format error interrupt 00729 * @arg SPI_IT_MODF : Mode fault interrupt 00730 * @arg SPI_IT_TSERF : Additional number of data reloaded interrupt 00731 * @arg SPI_IT_ERR : Error interrupt 00732 * @retval The new state of __IT__ (TRUE or FALSE). 00733 */ 00734 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ 00735 (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00736 00737 /** @brief Check whether the specified SPI flag is set or not. 00738 * @param __HANDLE__: specifies the SPI Handle. 00739 * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. 00740 * @param __FLAG__: specifies the flag to check. 00741 * This parameter can be one of the following values: 00742 * @arg SPI_FLAG_RXP : Rx-Packet available flag 00743 * @arg SPI_FLAG_TXP : Tx-Packet space available flag 00744 * @arg SPI_FLAG_DXP : Duplex Packet flag 00745 * @arg SPI_FLAG_EOT : End of transfer flag 00746 * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag 00747 * @arg SPI_FLAG_UDR : Underrun flag 00748 * @arg SPI_FLAG_OVR : Overrun flag 00749 * @arg SPI_FLAG_CRCERR : CRC error flag 00750 * @arg SPI_FLAG_FRE : TI mode frame format error flag 00751 * @arg SPI_FLAG_MODF : Mode fault flag 00752 * @arg SPI_FLAG_TSERF : Additional number of data reloaded flag 00753 * @arg SPI_FLAG_SUSP : Transfer suspend complete flag 00754 * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag 00755 * @arg SPI_FLAG_FRLVL : Fifo reception level flag 00756 * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag 00757 * @retval The new state of __FLAG__ (TRUE or FALSE). 00758 */ 00759 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 00760 00761 /** @brief Clear the SPI CRCERR pending flag. 00762 * @param __HANDLE__: specifies the SPI Handle. 00763 * @retval None 00764 */ 00765 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) 00766 00767 /** @brief Clear the SPI MODF pending flag. 00768 * @param __HANDLE__: specifies the SPI Handle. 00769 * @retval None 00770 */ 00771 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); 00772 00773 /** @brief Clear the SPI OVR pending flag. 00774 * @param __HANDLE__: specifies the SPI Handle. 00775 * @retval None 00776 */ 00777 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) 00778 00779 /** @brief Clear the SPI FRE pending flag. 00780 * @param __HANDLE__: specifies the SPI Handle. 00781 * @retval None 00782 */ 00783 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) 00784 00785 /** @brief Clear the SPI UDR pending flag. 00786 * @param __HANDLE__: specifies the SPI Handle. 00787 * @retval None 00788 */ 00789 #define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) 00790 00791 /** @brief Clear the SPI EOT pending flag. 00792 * @param __HANDLE__: specifies the SPI Handle. 00793 * @retval None 00794 */ 00795 #define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) 00796 00797 /** @brief Clear the SPI UDR pending flag. 00798 * @param __HANDLE__: specifies the SPI Handle. 00799 * @retval None 00800 */ 00801 #define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) 00802 00803 /** @brief Clear the SPI SUSP pending flag. 00804 * @param __HANDLE__: specifies the SPI Handle. 00805 * @retval None 00806 */ 00807 #define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) 00808 00809 /** @brief Clear the SPI TSERF pending flag. 00810 * @param __HANDLE__: specifies the SPI Handle. 00811 * @retval None 00812 */ 00813 #define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC) 00814 00815 /** @brief Enable the SPI peripheral. 00816 * @param __HANDLE__: specifies the SPI Handle. 00817 * @retval None 00818 */ 00819 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) 00820 00821 /** @brief Disable the SPI peripheral. 00822 * @param __HANDLE__: specifies the SPI Handle. 00823 * @retval None 00824 */ 00825 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) 00826 /** 00827 * @} 00828 */ 00829 00830 00831 /* Include SPI HAL Extension module */ 00832 #include "stm32h7xx_hal_spi_ex.h" 00833 00834 00835 /* Exported functions --------------------------------------------------------*/ 00836 /** @addtogroup SPI_Exported_Functions 00837 * @{ 00838 */ 00839 00840 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions 00841 * @{ 00842 */ 00843 /* Initialization/de-initialization functions ********************************/ 00844 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); 00845 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); 00846 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); 00847 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); 00848 00849 /* Callbacks Register/UnRegister functions ***********************************/ 00850 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 00851 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, 00852 pSPI_CallbackTypeDef pCallback); 00853 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); 00854 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00855 /** 00856 * @} 00857 */ 00858 00859 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions 00860 * @{ 00861 */ 00862 /* I/O operation functions ***************************************************/ 00863 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 00864 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 00865 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, 00866 uint32_t Timeout); 00867 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00868 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00869 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, 00870 uint16_t Size); 00871 00872 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00873 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00874 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, 00875 uint16_t Size); 00876 00877 #if defined(USE_SPI_RELOAD_TRANSFER) 00878 HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00879 HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00880 HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, 00881 uint8_t *pRxData, uint16_t Size); 00882 #endif /* USE_SPI_RELOAD_TRANSFER */ 00883 00884 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); 00885 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); 00886 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); 00887 00888 /* Transfer Abort functions */ 00889 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); 00890 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); 00891 00892 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); 00893 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); 00894 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); 00895 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); 00896 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); 00897 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); 00898 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); 00899 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); 00900 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); 00901 /** 00902 * @} 00903 */ 00904 00905 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions 00906 * @{ 00907 */ 00908 00909 /* Peripheral State and Error functions ***************************************/ 00910 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); 00911 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); 00912 /** 00913 * @} 00914 */ 00915 00916 /** 00917 * @} 00918 */ 00919 00920 /* Private macros ------------------------------------------------------------*/ 00921 /** @defgroup SPI_Private_Macros SPI Private Macros 00922 * @{ 00923 */ 00924 00925 /** @brief Set the SPI transmit-only mode. 00926 * @param __HANDLE__: specifies the SPI Handle. 00927 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00928 * @retval None 00929 */ 00930 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR) 00931 00932 /** @brief Set the SPI receive-only mode. 00933 * @param __HANDLE__: specifies the SPI Handle. 00934 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00935 * @retval None 00936 */ 00937 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR) 00938 00939 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ 00940 ((MODE) == SPI_MODE_MASTER)) 00941 00942 #define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ 00943 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ 00944 ((MODE) == SPI_DIRECTION_1LINE) || \ 00945 ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) 00946 00947 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) 00948 00949 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ 00950 ((MODE) == SPI_DIRECTION_1LINE) || \ 00951 ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) 00952 00953 #define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ 00954 ((MODE) == SPI_DIRECTION_1LINE) || \ 00955 ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) 00956 00957 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ 00958 ((DATASIZE) == SPI_DATASIZE_31BIT) || \ 00959 ((DATASIZE) == SPI_DATASIZE_30BIT) || \ 00960 ((DATASIZE) == SPI_DATASIZE_29BIT) || \ 00961 ((DATASIZE) == SPI_DATASIZE_28BIT) || \ 00962 ((DATASIZE) == SPI_DATASIZE_27BIT) || \ 00963 ((DATASIZE) == SPI_DATASIZE_26BIT) || \ 00964 ((DATASIZE) == SPI_DATASIZE_25BIT) || \ 00965 ((DATASIZE) == SPI_DATASIZE_24BIT) || \ 00966 ((DATASIZE) == SPI_DATASIZE_23BIT) || \ 00967 ((DATASIZE) == SPI_DATASIZE_22BIT) || \ 00968 ((DATASIZE) == SPI_DATASIZE_21BIT) || \ 00969 ((DATASIZE) == SPI_DATASIZE_20BIT) || \ 00970 ((DATASIZE) == SPI_DATASIZE_22BIT) || \ 00971 ((DATASIZE) == SPI_DATASIZE_19BIT) || \ 00972 ((DATASIZE) == SPI_DATASIZE_18BIT) || \ 00973 ((DATASIZE) == SPI_DATASIZE_17BIT) || \ 00974 ((DATASIZE) == SPI_DATASIZE_16BIT) || \ 00975 ((DATASIZE) == SPI_DATASIZE_15BIT) || \ 00976 ((DATASIZE) == SPI_DATASIZE_14BIT) || \ 00977 ((DATASIZE) == SPI_DATASIZE_13BIT) || \ 00978 ((DATASIZE) == SPI_DATASIZE_12BIT) || \ 00979 ((DATASIZE) == SPI_DATASIZE_11BIT) || \ 00980 ((DATASIZE) == SPI_DATASIZE_10BIT) || \ 00981 ((DATASIZE) == SPI_DATASIZE_9BIT) || \ 00982 ((DATASIZE) == SPI_DATASIZE_8BIT) || \ 00983 ((DATASIZE) == SPI_DATASIZE_7BIT) || \ 00984 ((DATASIZE) == SPI_DATASIZE_6BIT) || \ 00985 ((DATASIZE) == SPI_DATASIZE_5BIT) || \ 00986 ((DATASIZE) == SPI_DATASIZE_4BIT)) 00987 00988 #define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ 00989 ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ 00990 ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ 00991 ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ 00992 ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ 00993 ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ 00994 ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ 00995 ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ 00996 ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ 00997 ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ 00998 ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ 00999 ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ 01000 ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ 01001 ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ 01002 ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ 01003 ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) 01004 01005 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ 01006 ((CPOL) == SPI_POLARITY_HIGH)) 01007 01008 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ 01009 ((CPHA) == SPI_PHASE_2EDGE)) 01010 01011 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ 01012 ((NSS) == SPI_NSS_HARD_INPUT) || \ 01013 ((NSS) == SPI_NSS_HARD_OUTPUT)) 01014 01015 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ 01016 ((NSSP) == SPI_NSS_PULSE_DISABLE)) 01017 01018 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ 01019 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ 01020 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ 01021 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ 01022 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ 01023 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ 01024 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ 01025 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) 01026 01027 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ 01028 ((BIT) == SPI_FIRSTBIT_LSB)) 01029 01030 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ 01031 ((MODE) == SPI_TIMODE_ENABLE)) 01032 01033 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ 01034 ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) 01035 01036 #define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ 01037 ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) 01038 01039 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ 01040 ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ 01041 ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ 01042 ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ 01043 ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ 01044 ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ 01045 ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ 01046 ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ 01047 ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ 01048 ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ 01049 ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ 01050 ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ 01051 ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ 01052 ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ 01053 ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ 01054 ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ 01055 ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ 01056 ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ 01057 ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ 01058 ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ 01059 ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ 01060 ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ 01061 ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ 01062 ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ 01063 ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ 01064 ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ 01065 ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ 01066 ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ 01067 ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ 01068 ((LENGTH) == SPI_CRC_LENGTH_4BIT)) 01069 01070 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) 01071 01072 01073 #define IS_SPI_UNDERRUN_DETECTION(MODE) (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \ 01074 ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME) || \ 01075 ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS)) 01076 01077 #define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ 01078 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED) || \ 01079 ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED)) 01080 01081 /** 01082 * @} 01083 */ 01084 01085 /** 01086 * @} 01087 */ 01088 01089 /** 01090 * @} 01091 */ 01092 01093 #ifdef __cplusplus 01094 } 01095 #endif 01096 01097 #endif /* STM32H7xx_HAL_SPI_H */ 01098 01099 /** 01100 * @} 01101 */
1.7.6.1