|
STM32H735xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_bdma.h 00004 * @author MCD Application Team 00005 * @brief Header file of BDMA LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_LL_BDMA_H 00021 #define STM32H7xx_LL_BDMA_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx.h" 00029 #include "stm32h7xx_ll_dmamux.h" 00030 00031 /** @addtogroup STM32H7xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2) 00036 00037 /** @defgroup BDMA_LL BDMA 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 /** @defgroup BDMA_LL_Private_Variables BDMA Private Variables 00044 * @{ 00045 */ 00046 /* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */ 00047 static const uint8_t LL_BDMA_CH_OFFSET_TAB[] = 00048 { 00049 (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE), 00050 (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE), 00051 (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE), 00052 (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE), 00053 (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE), 00054 (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE), 00055 (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE), 00056 (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE) 00057 }; 00058 /** 00059 * @} 00060 */ 00061 00062 /* Private constants ---------------------------------------------------------*/ 00063 /* Private macros ------------------------------------------------------------*/ 00064 #if !defined(UNUSED) 00065 #define UNUSED(x) ((void)(x)) 00066 #endif 00067 00068 /* Exported types ------------------------------------------------------------*/ 00069 #if defined(USE_FULL_LL_DRIVER) 00070 /** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure 00071 * @{ 00072 */ 00073 typedef struct 00074 { 00075 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer 00076 or as Source base address in case of memory to memory transfer direction. 00077 00078 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00079 00080 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 00081 or as Destination base address in case of memory to memory transfer direction. 00082 00083 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00084 00085 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00086 from memory to memory or from peripheral to memory. 00087 This parameter can be a value of @ref BDMA_LL_EC_DIRECTION 00088 00089 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */ 00090 00091 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 00092 This parameter can be a value of @ref BDMA_LL_EC_MODE 00093 @note: The circular buffer mode cannot be used if the memory to memory 00094 data transfer direction is configured on the selected Channel 00095 00096 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */ 00097 00098 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 00099 is incremented or not. 00100 This parameter can be a value of @ref BDMA_LL_EC_PERIPH 00101 00102 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */ 00103 00104 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 00105 is incremented or not. 00106 This parameter can be a value of @ref BDMA_LL_EC_MEMORY 00107 00108 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */ 00109 00110 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 00111 in case of memory to memory transfer direction. 00112 This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN 00113 00114 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */ 00115 00116 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 00117 in case of memory to memory transfer direction. 00118 This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN 00119 00120 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */ 00121 00122 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 00123 The data unit is equal to the source buffer configuration set in PeripheralSize 00124 or MemorySize parameters depending in the transfer direction. 00125 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 00126 00127 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */ 00128 00129 uint32_t PeriphRequest; /*!< Specifies the peripheral request. 00130 This parameter can be a value of @ref DMAMUX2_Request_selection 00131 00132 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */ 00133 00134 uint32_t Priority; /*!< Specifies the channel priority level. 00135 This parameter can be a value of @ref BDMA_LL_EC_PRIORITY 00136 00137 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */ 00138 00139 } LL_BDMA_InitTypeDef; 00140 /** 00141 * @} 00142 */ 00143 #endif /* USE_FULL_LL_DRIVER */ 00144 00145 /* Exported constants --------------------------------------------------------*/ 00146 /** @defgroup BDMA_LL_Exported_Constants BDMA Exported Constants 00147 * @{ 00148 */ 00149 /** @defgroup BDMA_LL_EC_CLEAR_FLAG Clear Flags Defines 00150 * @brief Flags defines which can be used with LL_BDMA_WriteReg function 00151 * @{ 00152 */ 00153 #define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1 /*!< Channel 1 global flag */ 00154 #define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ 00155 #define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ 00156 #define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ 00157 #define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2 /*!< Channel 2 global flag */ 00158 #define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ 00159 #define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ 00160 #define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ 00161 #define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3 /*!< Channel 3 global flag */ 00162 #define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ 00163 #define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ 00164 #define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ 00165 #define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4 /*!< Channel 4 global flag */ 00166 #define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ 00167 #define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ 00168 #define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ 00169 #define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5 /*!< Channel 5 global flag */ 00170 #define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ 00171 #define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ 00172 #define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ 00173 #define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6 /*!< Channel 6 global flag */ 00174 #define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ 00175 #define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ 00176 #define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ 00177 #define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7 /*!< Channel 7 global flag */ 00178 #define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ 00179 #define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ 00180 #define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ 00181 /** 00182 * @} 00183 */ 00184 00185 /** @defgroup BDMA_LL_EC_GET_FLAG Get Flags Defines 00186 * @brief Flags defines which can be used with LL_BDMA_ReadReg function 00187 * @{ 00188 */ 00189 #define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0 /*!< Channel 1 global flag */ 00190 #define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0 /*!< Channel 1 transfer complete flag */ 00191 #define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0 /*!< Channel 1 half transfer flag */ 00192 #define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0 /*!< Channel 1 transfer error flag */ 00193 #define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1 /*!< Channel 1 global flag */ 00194 #define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 00195 #define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 00196 #define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 00197 #define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2 /*!< Channel 2 global flag */ 00198 #define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 00199 #define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 00200 #define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 00201 #define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3 /*!< Channel 3 global flag */ 00202 #define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 00203 #define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 00204 #define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 00205 #define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4 /*!< Channel 4 global flag */ 00206 #define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 00207 #define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 00208 #define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 00209 #define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5 /*!< Channel 5 global flag */ 00210 #define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 00211 #define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 00212 #define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 00213 #define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6 /*!< Channel 6 global flag */ 00214 #define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 00215 #define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 00216 #define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 00217 #define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7 /*!< Channel 7 global flag */ 00218 #define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 00219 #define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 00220 #define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 00221 /** 00222 * @} 00223 */ 00224 00225 /** @defgroup BDMA_LL_EC_IT IT Defines 00226 * @brief IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions 00227 * @{ 00228 */ 00229 #define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE /*!< Transfer complete interrupt */ 00230 #define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE /*!< Half Transfer interrupt */ 00231 #define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE /*!< Transfer error interrupt */ 00232 /** 00233 * @} 00234 */ 00235 00236 /** @defgroup BDMA_LL_EC_CHANNEL CHANNEL 00237 * @{ 00238 */ 00239 #define LL_BDMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */ 00240 #define LL_BDMA_CHANNEL_1 0x00000001U /*!< BDMA Channel 1 */ 00241 #define LL_BDMA_CHANNEL_2 0x00000002U /*!< BDMA Channel 2 */ 00242 #define LL_BDMA_CHANNEL_3 0x00000003U /*!< BDMA Channel 3 */ 00243 #define LL_BDMA_CHANNEL_4 0x00000004U /*!< BDMA Channel 4 */ 00244 #define LL_BDMA_CHANNEL_5 0x00000005U /*!< BDMA Channel 5 */ 00245 #define LL_BDMA_CHANNEL_6 0x00000006U /*!< BDMA Channel 6 */ 00246 #define LL_BDMA_CHANNEL_7 0x00000007U /*!< BDMA Channel 7 */ 00247 #if defined(USE_FULL_LL_DRIVER) 00248 #define LL_BDMA_CHANNEL_ALL 0xFFFF0000U /*!< BDMA Channel all (used only for function @ref LL_BDMA_DeInit(). */ 00249 #endif /*USE_FULL_LL_DRIVER*/ 00250 /** 00251 * @} 00252 */ 00253 00254 /** @defgroup BDMA_LL_EC_DIRECTION Transfer Direction 00255 * @{ 00256 */ 00257 #define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00258 #define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR /*!< Memory to peripheral direction */ 00259 #define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM /*!< Memory to memory direction */ 00260 /** 00261 * @} 00262 */ 00263 00264 /** @defgroup BDMA_LL_EC_MODE Transfer mode 00265 * @{ 00266 */ 00267 #define LL_BDMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 00268 #define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC /*!< Circular Mode */ 00269 /** 00270 * @} 00271 */ 00272 00273 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE 00274 * @{ 00275 */ 00276 #define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ 00277 #define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM /*!< Enable double buffering mode */ 00278 /** 00279 * @} 00280 */ 00281 00282 /** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode 00283 * @{ 00284 */ 00285 #define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC /*!< Peripheral increment mode Enable */ 00286 #define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 00287 /** 00288 * @} 00289 */ 00290 00291 /** @defgroup BDMA_LL_EC_MEMORY Memory increment mode 00292 * @{ 00293 */ 00294 #define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC /*!< Memory increment mode Enable */ 00295 #define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 00296 /** 00297 * @} 00298 */ 00299 00300 /** @defgroup BDMA_LL_EC_PDATAALIGN Peripheral data alignment 00301 * @{ 00302 */ 00303 #define LL_BDMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 00304 #define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 00305 #define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 00306 /** 00307 * @} 00308 */ 00309 00310 /** @defgroup BDMA_LL_EC_MDATAALIGN Memory data alignment 00311 * @{ 00312 */ 00313 #define LL_BDMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 00314 #define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 00315 #define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 00316 /** 00317 * @} 00318 */ 00319 00320 /** @defgroup BDMA_LL_EC_PRIORITY Transfer Priority level 00321 * @{ 00322 */ 00323 #define LL_BDMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 00324 #define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0 /*!< Priority level : Medium */ 00325 #define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1 /*!< Priority level : High */ 00326 #define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL /*!< Priority level : Very_High */ 00327 /** 00328 * @} 00329 */ 00330 00331 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 00332 * @{ 00333 */ 00334 #define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ 00335 #define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ 00336 /** 00337 * @} 00338 */ 00339 00340 /* Exported macro ------------------------------------------------------------*/ 00341 /** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros 00342 * @{ 00343 */ 00344 00345 /** @defgroup BDMA_LL_EM_WRITE_READ Common Write and read registers macros 00346 * @{ 00347 */ 00348 /** 00349 * @brief Write a value in BDMA register 00350 * @param __INSTANCE__ BDMA Instance 00351 * @param __REG__ Register to be written 00352 * @param __VALUE__ Value to be written in the register 00353 * @retval None 00354 */ 00355 #define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 00356 00357 /** 00358 * @brief Read a value in BDMA register 00359 * @param __INSTANCE__ BDMA Instance 00360 * @param __REG__ Register to be read 00361 * @retval Register value 00362 */ 00363 #define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00364 /** 00365 * @} 00366 */ 00367 00368 /** @defgroup BDMA_LL_EM_CONVERT_DMAxCHANNELy Convert BDMAxChannely 00369 * @{ 00370 */ 00371 /** 00372 * @brief Convert BDMAx_Channely into BDMAx 00373 * @param __CHANNEL_INSTANCE__ BDMAx_Channely 00374 * @retval BDMAx 00375 */ 00376 #if defined (BDMA1) 00377 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ 00378 (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA) 00379 #else 00380 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (BDMA) 00381 #endif /* BDMA1 */ 00382 00383 /** 00384 * @brief Convert BDMAx_Channely into LL_BDMA_CHANNEL_y 00385 * @param __CHANNEL_INSTANCE__ BDMAx_Channely 00386 * @retval LL_BDMA_CHANNEL_y 00387 */ 00388 #if defined (BDMA1) 00389 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00390 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \ 00391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \ 00392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \ 00393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \ 00394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \ 00395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \ 00396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \ 00397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \ 00398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \ 00399 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \ 00400 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \ 00401 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \ 00402 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \ 00403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \ 00404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7)) ? LL_BDMA_CHANNEL_7 : \ 00405 LL_BDMA_CHANNEL_7) 00406 #else 00407 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00408 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \ 00409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \ 00410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \ 00411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \ 00412 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \ 00413 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \ 00414 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \ 00415 LL_BDMA_CHANNEL_7) 00416 #endif /* BDMA1 */ 00417 00418 /** 00419 * @brief Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely 00420 * @param __BDMA_INSTANCE__ BDMAx 00421 * @param __CHANNEL__ LL_BDMA_CHANNEL_y 00422 * @retval BDMAx_Channely 00423 */ 00424 #if defined (BDMA1) 00425 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \ 00426 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \ 00427 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \ 00428 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \ 00429 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \ 00430 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \ 00431 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \ 00432 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \ 00433 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \ 00434 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \ 00435 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \ 00436 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \ 00437 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \ 00438 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \ 00439 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \ 00440 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7 : \ 00441 BDMA1_Channel7) 00442 #else 00443 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \ 00444 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \ 00445 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \ 00446 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \ 00447 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \ 00448 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \ 00449 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \ 00450 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \ 00451 BDMA_Channel7) 00452 #endif /* BDMA1 */ 00453 /** 00454 * @} 00455 */ 00456 00457 /** 00458 * @} 00459 */ 00460 00461 /* Exported functions --------------------------------------------------------*/ 00462 /** @defgroup BDMA_LL_Exported_Functions BDMA Exported Functions 00463 * @{ 00464 */ 00465 00466 /** @defgroup BDMA_LL_EF_Configuration Configuration 00467 * @{ 00468 */ 00469 /** 00470 * @brief Enable BDMA channel. 00471 * @rmtoll CCR EN LL_BDMA_EnableChannel 00472 * @param BDMAx BDMA Instance 00473 * @param Channel This parameter can be one of the following values: 00474 * @arg @ref LL_BDMA_CHANNEL_0 00475 * @arg @ref LL_BDMA_CHANNEL_1 00476 * @arg @ref LL_BDMA_CHANNEL_2 00477 * @arg @ref LL_BDMA_CHANNEL_3 00478 * @arg @ref LL_BDMA_CHANNEL_4 00479 * @arg @ref LL_BDMA_CHANNEL_5 00480 * @arg @ref LL_BDMA_CHANNEL_6 00481 * @arg @ref LL_BDMA_CHANNEL_7 00482 * @retval None 00483 */ 00484 __STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) 00485 { 00486 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00487 00488 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN); 00489 } 00490 00491 /** 00492 * @brief Disable BDMA channel. 00493 * @rmtoll CCR EN LL_BDMA_DisableChannel 00494 * @param BDMAx BDMA Instance 00495 * @param Channel This parameter can be one of the following values: 00496 * @arg @ref LL_BDMA_CHANNEL_0 00497 * @arg @ref LL_BDMA_CHANNEL_1 00498 * @arg @ref LL_BDMA_CHANNEL_2 00499 * @arg @ref LL_BDMA_CHANNEL_3 00500 * @arg @ref LL_BDMA_CHANNEL_4 00501 * @arg @ref LL_BDMA_CHANNEL_5 00502 * @arg @ref LL_BDMA_CHANNEL_6 00503 * @arg @ref LL_BDMA_CHANNEL_7 00504 * @retval None 00505 */ 00506 __STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) 00507 { 00508 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00509 00510 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN); 00511 } 00512 00513 /** 00514 * @brief Check if BDMA channel is enabled or disabled. 00515 * @rmtoll CCR EN LL_BDMA_IsEnabledChannel 00516 * @param BDMAx BDMA Instance 00517 * @param Channel This parameter can be one of the following values: 00518 * @arg @ref LL_BDMA_CHANNEL_0 00519 * @arg @ref LL_BDMA_CHANNEL_1 00520 * @arg @ref LL_BDMA_CHANNEL_2 00521 * @arg @ref LL_BDMA_CHANNEL_3 00522 * @arg @ref LL_BDMA_CHANNEL_4 00523 * @arg @ref LL_BDMA_CHANNEL_5 00524 * @arg @ref LL_BDMA_CHANNEL_6 00525 * @arg @ref LL_BDMA_CHANNEL_7 00526 * @retval State of bit (1 or 0). 00527 */ 00528 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel) 00529 { 00530 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00531 00532 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL); 00533 } 00534 00535 /** 00536 * @brief Configure all parameters link to BDMA transfer. 00537 * @rmtoll CCR DIR LL_BDMA_ConfigTransfer\n 00538 * CCR MEM2MEM LL_BDMA_ConfigTransfer\n 00539 * CCR CIRC LL_BDMA_ConfigTransfer\n 00540 * CCR PINC LL_BDMA_ConfigTransfer\n 00541 * CCR MINC LL_BDMA_ConfigTransfer\n 00542 * CCR PSIZE LL_BDMA_ConfigTransfer\n 00543 * CCR MSIZE LL_BDMA_ConfigTransfer\n 00544 * CCR PL LL_BDMA_ConfigTransfer 00545 * @param BDMAx BDMA Instance 00546 * @param Channel This parameter can be one of the following values: 00547 * @arg @ref LL_BDMA_CHANNEL_0 00548 * @arg @ref LL_BDMA_CHANNEL_1 00549 * @arg @ref LL_BDMA_CHANNEL_2 00550 * @arg @ref LL_BDMA_CHANNEL_3 00551 * @arg @ref LL_BDMA_CHANNEL_4 00552 * @arg @ref LL_BDMA_CHANNEL_5 00553 * @arg @ref LL_BDMA_CHANNEL_6 00554 * @arg @ref LL_BDMA_CHANNEL_7 00555 * @param Configuration This parameter must be a combination of all the following values: 00556 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY 00557 * @arg @ref LL_BDMA_MODE_NORMAL or @ref LL_BDMA_MODE_CIRCULAR 00558 * @arg @ref LL_BDMA_PERIPH_INCREMENT or @ref LL_BDMA_PERIPH_NOINCREMENT 00559 * @arg @ref LL_BDMA_MEMORY_INCREMENT or @ref LL_BDMA_MEMORY_NOINCREMENT 00560 * @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD 00561 * @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD 00562 * @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH 00563 * @retval None 00564 */ 00565 __STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration) 00566 { 00567 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00568 00569 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00570 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL, 00571 Configuration); 00572 } 00573 00574 /** 00575 * @brief Set Data transfer direction (read from peripheral or from memory). 00576 * @rmtoll CCR DIR LL_BDMA_SetDataTransferDirection\n 00577 * CCR MEM2MEM LL_BDMA_SetDataTransferDirection 00578 * @param BDMAx BDMA Instance 00579 * @param Channel This parameter can be one of the following values: 00580 * @arg @ref LL_BDMA_CHANNEL_0 00581 * @arg @ref LL_BDMA_CHANNEL_1 00582 * @arg @ref LL_BDMA_CHANNEL_2 00583 * @arg @ref LL_BDMA_CHANNEL_3 00584 * @arg @ref LL_BDMA_CHANNEL_4 00585 * @arg @ref LL_BDMA_CHANNEL_5 00586 * @arg @ref LL_BDMA_CHANNEL_6 00587 * @arg @ref LL_BDMA_CHANNEL_7 00588 * @param Direction This parameter can be one of the following values: 00589 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 00590 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH 00591 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY 00592 * @retval None 00593 */ 00594 __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction) 00595 { 00596 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00597 00598 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00599 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction); 00600 } 00601 00602 /** 00603 * @brief Get Data transfer direction (read from peripheral or from memory). 00604 * @rmtoll CCR DIR LL_BDMA_GetDataTransferDirection\n 00605 * CCR MEM2MEM LL_BDMA_GetDataTransferDirection 00606 * @param BDMAx BDMA Instance 00607 * @param Channel This parameter can be one of the following values: 00608 * @arg @ref LL_BDMA_CHANNEL_0 00609 * @arg @ref LL_BDMA_CHANNEL_1 00610 * @arg @ref LL_BDMA_CHANNEL_2 00611 * @arg @ref LL_BDMA_CHANNEL_3 00612 * @arg @ref LL_BDMA_CHANNEL_4 00613 * @arg @ref LL_BDMA_CHANNEL_5 00614 * @arg @ref LL_BDMA_CHANNEL_6 00615 * @arg @ref LL_BDMA_CHANNEL_7 00616 * @retval Returned value can be one of the following values: 00617 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 00618 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH 00619 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY 00620 */ 00621 __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel) 00622 { 00623 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00624 00625 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00626 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM)); 00627 } 00628 00629 /** 00630 * @brief Set BDMA mode circular or normal. 00631 * @note The circular buffer mode cannot be used if the memory-to-memory 00632 * data transfer is configured on the selected Channel. 00633 * @rmtoll CCR CIRC LL_BDMA_SetMode 00634 * @param BDMAx BDMA Instance 00635 * @param Channel This parameter can be one of the following values: 00636 * @arg @ref LL_BDMA_CHANNEL_0 00637 * @arg @ref LL_BDMA_CHANNEL_1 00638 * @arg @ref LL_BDMA_CHANNEL_2 00639 * @arg @ref LL_BDMA_CHANNEL_3 00640 * @arg @ref LL_BDMA_CHANNEL_4 00641 * @arg @ref LL_BDMA_CHANNEL_5 00642 * @arg @ref LL_BDMA_CHANNEL_6 00643 * @arg @ref LL_BDMA_CHANNEL_7 00644 * @param Mode This parameter can be one of the following values: 00645 * @arg @ref LL_BDMA_MODE_NORMAL 00646 * @arg @ref LL_BDMA_MODE_CIRCULAR 00647 * @retval None 00648 */ 00649 __STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode) 00650 { 00651 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00652 00653 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC, 00654 Mode); 00655 } 00656 00657 /** 00658 * @brief Get BDMA mode circular or normal. 00659 * @rmtoll CCR CIRC LL_BDMA_GetMode 00660 * @param BDMAx BDMA Instance 00661 * @param Channel This parameter can be one of the following values: 00662 * @arg @ref LL_BDMA_CHANNEL_0 00663 * @arg @ref LL_BDMA_CHANNEL_1 00664 * @arg @ref LL_BDMA_CHANNEL_2 00665 * @arg @ref LL_BDMA_CHANNEL_3 00666 * @arg @ref LL_BDMA_CHANNEL_4 00667 * @arg @ref LL_BDMA_CHANNEL_5 00668 * @arg @ref LL_BDMA_CHANNEL_6 00669 * @arg @ref LL_BDMA_CHANNEL_7 00670 * @retval Returned value can be one of the following values: 00671 * @arg @ref LL_BDMA_MODE_NORMAL 00672 * @arg @ref LL_BDMA_MODE_CIRCULAR 00673 */ 00674 __STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 00675 { 00676 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00677 00678 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00679 BDMA_CCR_CIRC)); 00680 } 00681 00682 /** 00683 * @brief Set Peripheral increment mode. 00684 * @rmtoll CCR PINC LL_BDMA_SetPeriphIncMode 00685 * @param BDMAx BDMA Instance 00686 * @param Channel This parameter can be one of the following values: 00687 * @arg @ref LL_BDMA_CHANNEL_0 00688 * @arg @ref LL_BDMA_CHANNEL_1 00689 * @arg @ref LL_BDMA_CHANNEL_2 00690 * @arg @ref LL_BDMA_CHANNEL_3 00691 * @arg @ref LL_BDMA_CHANNEL_4 00692 * @arg @ref LL_BDMA_CHANNEL_5 00693 * @arg @ref LL_BDMA_CHANNEL_6 00694 * @arg @ref LL_BDMA_CHANNEL_7 00695 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: 00696 * @arg @ref LL_BDMA_PERIPH_INCREMENT 00697 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT 00698 * @retval None 00699 */ 00700 __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) 00701 { 00702 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00703 00704 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC, 00705 PeriphOrM2MSrcIncMode); 00706 } 00707 00708 /** 00709 * @brief Get Peripheral increment mode. 00710 * @rmtoll CCR PINC LL_BDMA_GetPeriphIncMode 00711 * @param BDMAx BDMA Instance 00712 * @param Channel This parameter can be one of the following values: 00713 * @arg @ref LL_BDMA_CHANNEL_0 00714 * @arg @ref LL_BDMA_CHANNEL_1 00715 * @arg @ref LL_BDMA_CHANNEL_2 00716 * @arg @ref LL_BDMA_CHANNEL_3 00717 * @arg @ref LL_BDMA_CHANNEL_4 00718 * @arg @ref LL_BDMA_CHANNEL_5 00719 * @arg @ref LL_BDMA_CHANNEL_6 00720 * @arg @ref LL_BDMA_CHANNEL_7 00721 * @retval Returned value can be one of the following values: 00722 * @arg @ref LL_BDMA_PERIPH_INCREMENT 00723 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT 00724 */ 00725 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 00726 { 00727 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00728 00729 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00730 BDMA_CCR_PINC)); 00731 } 00732 00733 /** 00734 * @brief Set Memory increment mode. 00735 * @rmtoll CCR MINC LL_BDMA_SetMemoryIncMode 00736 * @param BDMAx BDMA Instance 00737 * @param Channel This parameter can be one of the following values: 00738 * @arg @ref LL_BDMA_CHANNEL_0 00739 * @arg @ref LL_BDMA_CHANNEL_1 00740 * @arg @ref LL_BDMA_CHANNEL_2 00741 * @arg @ref LL_BDMA_CHANNEL_3 00742 * @arg @ref LL_BDMA_CHANNEL_4 00743 * @arg @ref LL_BDMA_CHANNEL_5 00744 * @arg @ref LL_BDMA_CHANNEL_6 00745 * @arg @ref LL_BDMA_CHANNEL_7 00746 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: 00747 * @arg @ref LL_BDMA_MEMORY_INCREMENT 00748 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT 00749 * @retval None 00750 */ 00751 __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) 00752 { 00753 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00754 00755 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC, 00756 MemoryOrM2MDstIncMode); 00757 } 00758 00759 /** 00760 * @brief Get Memory increment mode. 00761 * @rmtoll CCR MINC LL_BDMA_GetMemoryIncMode 00762 * @param BDMAx BDMA Instance 00763 * @param Channel This parameter can be one of the following values: 00764 * @arg @ref LL_BDMA_CHANNEL_0 00765 * @arg @ref LL_BDMA_CHANNEL_1 00766 * @arg @ref LL_BDMA_CHANNEL_2 00767 * @arg @ref LL_BDMA_CHANNEL_3 00768 * @arg @ref LL_BDMA_CHANNEL_4 00769 * @arg @ref LL_BDMA_CHANNEL_5 00770 * @arg @ref LL_BDMA_CHANNEL_6 00771 * @arg @ref LL_BDMA_CHANNEL_7 00772 * @retval Returned value can be one of the following values: 00773 * @arg @ref LL_BDMA_MEMORY_INCREMENT 00774 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT 00775 */ 00776 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 00777 { 00778 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00779 00780 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00781 BDMA_CCR_MINC)); 00782 } 00783 00784 /** 00785 * @brief Set Peripheral size. 00786 * @rmtoll CCR PSIZE LL_BDMA_SetPeriphSize 00787 * @param BDMAx BDMA Instance 00788 * @param Channel This parameter can be one of the following values: 00789 * @arg @ref LL_BDMA_CHANNEL_0 00790 * @arg @ref LL_BDMA_CHANNEL_1 00791 * @arg @ref LL_BDMA_CHANNEL_2 00792 * @arg @ref LL_BDMA_CHANNEL_3 00793 * @arg @ref LL_BDMA_CHANNEL_4 00794 * @arg @ref LL_BDMA_CHANNEL_5 00795 * @arg @ref LL_BDMA_CHANNEL_6 00796 * @arg @ref LL_BDMA_CHANNEL_7 00797 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: 00798 * @arg @ref LL_BDMA_PDATAALIGN_BYTE 00799 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD 00800 * @arg @ref LL_BDMA_PDATAALIGN_WORD 00801 * @retval None 00802 */ 00803 __STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) 00804 { 00805 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00806 00807 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE, 00808 PeriphOrM2MSrcDataSize); 00809 } 00810 00811 /** 00812 * @brief Get Peripheral size. 00813 * @rmtoll CCR PSIZE LL_BDMA_GetPeriphSize 00814 * @param BDMAx BDMA Instance 00815 * @param Channel This parameter can be one of the following values: 00816 * @arg @ref LL_BDMA_CHANNEL_0 00817 * @arg @ref LL_BDMA_CHANNEL_1 00818 * @arg @ref LL_BDMA_CHANNEL_2 00819 * @arg @ref LL_BDMA_CHANNEL_3 00820 * @arg @ref LL_BDMA_CHANNEL_4 00821 * @arg @ref LL_BDMA_CHANNEL_5 00822 * @arg @ref LL_BDMA_CHANNEL_6 00823 * @arg @ref LL_BDMA_CHANNEL_7 00824 * @retval Returned value can be one of the following values: 00825 * @arg @ref LL_BDMA_PDATAALIGN_BYTE 00826 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD 00827 * @arg @ref LL_BDMA_PDATAALIGN_WORD 00828 */ 00829 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel) 00830 { 00831 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00832 00833 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00834 BDMA_CCR_PSIZE)); 00835 } 00836 00837 /** 00838 * @brief Set Memory size. 00839 * @rmtoll CCR MSIZE LL_BDMA_SetMemorySize 00840 * @param BDMAx BDMA Instance 00841 * @param Channel This parameter can be one of the following values: 00842 * @arg @ref LL_BDMA_CHANNEL_0 00843 * @arg @ref LL_BDMA_CHANNEL_1 00844 * @arg @ref LL_BDMA_CHANNEL_2 00845 * @arg @ref LL_BDMA_CHANNEL_3 00846 * @arg @ref LL_BDMA_CHANNEL_4 00847 * @arg @ref LL_BDMA_CHANNEL_5 00848 * @arg @ref LL_BDMA_CHANNEL_6 00849 * @arg @ref LL_BDMA_CHANNEL_7 00850 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: 00851 * @arg @ref LL_BDMA_MDATAALIGN_BYTE 00852 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD 00853 * @arg @ref LL_BDMA_MDATAALIGN_WORD 00854 * @retval None 00855 */ 00856 __STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) 00857 { 00858 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00859 00860 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE, 00861 MemoryOrM2MDstDataSize); 00862 } 00863 00864 /** 00865 * @brief Get Memory size. 00866 * @rmtoll CCR MSIZE LL_BDMA_GetMemorySize 00867 * @param BDMAx BDMA Instance 00868 * @param Channel This parameter can be one of the following values: 00869 * @arg @ref LL_BDMA_CHANNEL_0 00870 * @arg @ref LL_BDMA_CHANNEL_1 00871 * @arg @ref LL_BDMA_CHANNEL_2 00872 * @arg @ref LL_BDMA_CHANNEL_3 00873 * @arg @ref LL_BDMA_CHANNEL_4 00874 * @arg @ref LL_BDMA_CHANNEL_5 00875 * @arg @ref LL_BDMA_CHANNEL_6 00876 * @arg @ref LL_BDMA_CHANNEL_7 00877 * @retval Returned value can be one of the following values: 00878 * @arg @ref LL_BDMA_MDATAALIGN_BYTE 00879 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD 00880 * @arg @ref LL_BDMA_MDATAALIGN_WORD 00881 */ 00882 __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel) 00883 { 00884 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00885 00886 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00887 BDMA_CCR_MSIZE)); 00888 } 00889 00890 /** 00891 * @brief Set Channel priority level. 00892 * @rmtoll CCR PL LL_BDMA_SetChannelPriorityLevel 00893 * @param BDMAx BDMA Instance 00894 * @param Channel This parameter can be one of the following values: 00895 * @arg @ref LL_BDMA_CHANNEL_0 00896 * @arg @ref LL_BDMA_CHANNEL_1 00897 * @arg @ref LL_BDMA_CHANNEL_2 00898 * @arg @ref LL_BDMA_CHANNEL_3 00899 * @arg @ref LL_BDMA_CHANNEL_4 00900 * @arg @ref LL_BDMA_CHANNEL_5 00901 * @arg @ref LL_BDMA_CHANNEL_6 00902 * @arg @ref LL_BDMA_CHANNEL_7 00903 * @param Priority This parameter can be one of the following values: 00904 * @arg @ref LL_BDMA_PRIORITY_LOW 00905 * @arg @ref LL_BDMA_PRIORITY_MEDIUM 00906 * @arg @ref LL_BDMA_PRIORITY_HIGH 00907 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH 00908 * @retval None 00909 */ 00910 __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority) 00911 { 00912 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00913 00914 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL, 00915 Priority); 00916 } 00917 00918 /** 00919 * @brief Get Channel priority level. 00920 * @rmtoll CCR PL LL_BDMA_GetChannelPriorityLevel 00921 * @param BDMAx BDMA Instance 00922 * @param Channel This parameter can be one of the following values: 00923 * @arg @ref LL_BDMA_CHANNEL_0 00924 * @arg @ref LL_BDMA_CHANNEL_1 00925 * @arg @ref LL_BDMA_CHANNEL_2 00926 * @arg @ref LL_BDMA_CHANNEL_3 00927 * @arg @ref LL_BDMA_CHANNEL_4 00928 * @arg @ref LL_BDMA_CHANNEL_5 00929 * @arg @ref LL_BDMA_CHANNEL_6 00930 * @arg @ref LL_BDMA_CHANNEL_7 00931 * @retval Returned value can be one of the following values: 00932 * @arg @ref LL_BDMA_PRIORITY_LOW 00933 * @arg @ref LL_BDMA_PRIORITY_MEDIUM 00934 * @arg @ref LL_BDMA_PRIORITY_HIGH 00935 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH 00936 */ 00937 __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel) 00938 { 00939 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00940 00941 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, 00942 BDMA_CCR_PL)); 00943 } 00944 00945 /** 00946 * @brief Set Number of data to transfer. 00947 * @note This action has no effect if 00948 * channel is enabled. 00949 * @rmtoll CNDTR NDT LL_BDMA_SetDataLength 00950 * @param BDMAx BDMA Instance 00951 * @param Channel This parameter can be one of the following values: 00952 * @arg @ref LL_BDMA_CHANNEL_0 00953 * @arg @ref LL_BDMA_CHANNEL_1 00954 * @arg @ref LL_BDMA_CHANNEL_2 00955 * @arg @ref LL_BDMA_CHANNEL_3 00956 * @arg @ref LL_BDMA_CHANNEL_4 00957 * @arg @ref LL_BDMA_CHANNEL_5 00958 * @arg @ref LL_BDMA_CHANNEL_6 00959 * @arg @ref LL_BDMA_CHANNEL_7 00960 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF 00961 * @retval None 00962 */ 00963 __STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData) 00964 { 00965 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00966 00967 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR, 00968 BDMA_CNDTR_NDT, NbData); 00969 } 00970 00971 /** 00972 * @brief Get Number of data to transfer. 00973 * @note Once the channel is enabled, the return value indicate the 00974 * remaining bytes to be transmitted. 00975 * @rmtoll CNDTR NDT LL_BDMA_GetDataLength 00976 * @param BDMAx BDMA Instance 00977 * @param Channel This parameter can be one of the following values: 00978 * @arg @ref LL_BDMA_CHANNEL_0 00979 * @arg @ref LL_BDMA_CHANNEL_1 00980 * @arg @ref LL_BDMA_CHANNEL_2 00981 * @arg @ref LL_BDMA_CHANNEL_3 00982 * @arg @ref LL_BDMA_CHANNEL_4 00983 * @arg @ref LL_BDMA_CHANNEL_5 00984 * @arg @ref LL_BDMA_CHANNEL_6 00985 * @arg @ref LL_BDMA_CHANNEL_7 00986 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 00987 */ 00988 __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel) 00989 { 00990 uint32_t bdma_base_addr = (uint32_t)BDMAx; 00991 00992 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR, 00993 BDMA_CNDTR_NDT)); 00994 } 00995 00996 /** 00997 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 00998 * @rmtoll CR CT LL_BDMA_SetCurrentTargetMem 00999 * @param BDMAx BDMAx Instance 01000 * @param Channel This parameter can be one of the following values: 01001 * @arg @ref LL_BDMA_CHANNEL_0 01002 * @arg @ref LL_BDMA_CHANNEL_1 01003 * @arg @ref LL_BDMA_CHANNEL_2 01004 * @arg @ref LL_BDMA_CHANNEL_3 01005 * @arg @ref LL_BDMA_CHANNEL_4 01006 * @arg @ref LL_BDMA_CHANNEL_5 01007 * @arg @ref LL_BDMA_CHANNEL_6 01008 * @arg @ref LL_BDMA_CHANNEL_7 01009 * @param CurrentMemory This parameter can be one of the following values: 01010 * @arg @ref LL_BDMA_CURRENTTARGETMEM0 01011 * @arg @ref LL_BDMA_CURRENTTARGETMEM1 01012 * @retval None 01013 */ 01014 __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory) 01015 { 01016 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01017 01018 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory); 01019 } 01020 01021 /** 01022 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 01023 * @rmtoll CR CT LL_BDMA_GetCurrentTargetMem 01024 * @param BDMAx BDMAx Instance 01025 * @param Channel This parameter can be one of the following values: 01026 * @arg @ref LL_BDMA_CHANNEL_0 01027 * @arg @ref LL_BDMA_CHANNEL_1 01028 * @arg @ref LL_BDMA_CHANNEL_2 01029 * @arg @ref LL_BDMA_CHANNEL_3 01030 * @arg @ref LL_BDMA_CHANNEL_4 01031 * @arg @ref LL_BDMA_CHANNEL_5 01032 * @arg @ref LL_BDMA_CHANNEL_6 01033 * @arg @ref LL_BDMA_CHANNEL_7 01034 * @retval Returned value can be one of the following values: 01035 * @arg @ref LL_BDMA_CURRENTTARGETMEM0 01036 * @arg @ref LL_BDMA_CURRENTTARGETMEM1 01037 */ 01038 __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel) 01039 { 01040 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01041 01042 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT)); 01043 } 01044 01045 /** 01046 * @brief Enable the double buffer mode. 01047 * @rmtoll CR DBM LL_BDMA_EnableDoubleBufferMode 01048 * @param BDMAx BDMAx Instance 01049 * @param Channel This parameter can be one of the following values: 01050 * @arg @ref LL_BDMA_CHANNEL_0 01051 * @arg @ref LL_BDMA_CHANNEL_1 01052 * @arg @ref LL_BDMA_CHANNEL_2 01053 * @arg @ref LL_BDMA_CHANNEL_3 01054 * @arg @ref LL_BDMA_CHANNEL_4 01055 * @arg @ref LL_BDMA_CHANNEL_5 01056 * @arg @ref LL_BDMA_CHANNEL_6 01057 * @arg @ref LL_BDMA_CHANNEL_7 01058 * @retval None 01059 */ 01060 __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 01061 { 01062 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01063 01064 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM); 01065 } 01066 01067 /** 01068 * @brief Disable the double buffer mode. 01069 * @rmtoll CR DBM LL_BDMA_DisableDoubleBufferMode 01070 * @param BDMAx BDMAx Instance 01071 * @param Channel This parameter can be one of the following values: 01072 * @arg @ref LL_BDMA_CHANNEL_0 01073 * @arg @ref LL_BDMA_CHANNEL_1 01074 * @arg @ref LL_BDMA_CHANNEL_2 01075 * @arg @ref LL_BDMA_CHANNEL_3 01076 * @arg @ref LL_BDMA_CHANNEL_4 01077 * @arg @ref LL_BDMA_CHANNEL_5 01078 * @arg @ref LL_BDMA_CHANNEL_6 01079 * @arg @ref LL_BDMA_CHANNEL_7 01080 * @retval None 01081 */ 01082 __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel) 01083 { 01084 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01085 01086 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM); 01087 } 01088 01089 /** 01090 * @brief Configure the Source and Destination addresses. 01091 * @note This API must not be called when the BDMA channel is enabled. 01092 * @note Each IP using BDMA provides an API to get directly the register address (LL_PPP_BDMA_GetRegAddr). 01093 * @rmtoll CPAR PA LL_BDMA_ConfigAddresses\n 01094 * CMAR MA LL_BDMA_ConfigAddresses 01095 * @param BDMAx BDMA Instance 01096 * @param Channel This parameter can be one of the following values: 01097 * @arg @ref LL_BDMA_CHANNEL_0 01098 * @arg @ref LL_BDMA_CHANNEL_1 01099 * @arg @ref LL_BDMA_CHANNEL_2 01100 * @arg @ref LL_BDMA_CHANNEL_3 01101 * @arg @ref LL_BDMA_CHANNEL_4 01102 * @arg @ref LL_BDMA_CHANNEL_5 01103 * @arg @ref LL_BDMA_CHANNEL_6 01104 * @arg @ref LL_BDMA_CHANNEL_7 01105 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01106 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01107 * @param Direction This parameter can be one of the following values: 01108 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 01109 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH 01110 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY 01111 * @retval None 01112 */ 01113 __STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress, 01114 uint32_t DstAddress, uint32_t Direction) 01115 { 01116 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01117 01118 /* Direction Memory to Periph */ 01119 if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH) 01120 { 01121 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress); 01122 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress); 01123 } 01124 /* Direction Periph to Memory and Memory to Memory */ 01125 else 01126 { 01127 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress); 01128 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress); 01129 } 01130 } 01131 01132 /** 01133 * @brief Set the Memory address. 01134 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. 01135 * @note This API must not be called when the BDMA channel is enabled. 01136 * @rmtoll CMAR MA LL_BDMA_SetMemoryAddress 01137 * @param BDMAx BDMA Instance 01138 * @param Channel This parameter can be one of the following values: 01139 * @arg @ref LL_BDMA_CHANNEL_0 01140 * @arg @ref LL_BDMA_CHANNEL_1 01141 * @arg @ref LL_BDMA_CHANNEL_2 01142 * @arg @ref LL_BDMA_CHANNEL_3 01143 * @arg @ref LL_BDMA_CHANNEL_4 01144 * @arg @ref LL_BDMA_CHANNEL_5 01145 * @arg @ref LL_BDMA_CHANNEL_6 01146 * @arg @ref LL_BDMA_CHANNEL_7 01147 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01148 * @retval None 01149 */ 01150 __STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) 01151 { 01152 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01153 01154 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress); 01155 } 01156 01157 /** 01158 * @brief Set the Peripheral address. 01159 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. 01160 * @note This API must not be called when the BDMA channel is enabled. 01161 * @rmtoll CPAR PA LL_BDMA_SetPeriphAddress 01162 * @param BDMAx BDMA Instance 01163 * @param Channel This parameter can be one of the following values: 01164 * @arg @ref LL_BDMA_CHANNEL_0 01165 * @arg @ref LL_BDMA_CHANNEL_1 01166 * @arg @ref LL_BDMA_CHANNEL_2 01167 * @arg @ref LL_BDMA_CHANNEL_3 01168 * @arg @ref LL_BDMA_CHANNEL_4 01169 * @arg @ref LL_BDMA_CHANNEL_5 01170 * @arg @ref LL_BDMA_CHANNEL_6 01171 * @arg @ref LL_BDMA_CHANNEL_7 01172 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01173 * @retval None 01174 */ 01175 __STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress) 01176 { 01177 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01178 01179 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); 01180 } 01181 01182 /** 01183 * @brief Get Memory address. 01184 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. 01185 * @rmtoll CMAR MA LL_BDMA_GetMemoryAddress 01186 * @param BDMAx BDMA Instance 01187 * @param Channel This parameter can be one of the following values: 01188 * @arg @ref LL_BDMA_CHANNEL_0 01189 * @arg @ref LL_BDMA_CHANNEL_1 01190 * @arg @ref LL_BDMA_CHANNEL_2 01191 * @arg @ref LL_BDMA_CHANNEL_3 01192 * @arg @ref LL_BDMA_CHANNEL_4 01193 * @arg @ref LL_BDMA_CHANNEL_5 01194 * @arg @ref LL_BDMA_CHANNEL_6 01195 * @arg @ref LL_BDMA_CHANNEL_7 01196 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01197 */ 01198 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) 01199 { 01200 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01201 01202 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR)); 01203 } 01204 01205 /** 01206 * @brief Get Peripheral address. 01207 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only. 01208 * @rmtoll CPAR PA LL_BDMA_GetPeriphAddress 01209 * @param BDMAx BDMA Instance 01210 * @param Channel This parameter can be one of the following values: 01211 * @arg @ref LL_BDMA_CHANNEL_0 01212 * @arg @ref LL_BDMA_CHANNEL_1 01213 * @arg @ref LL_BDMA_CHANNEL_2 01214 * @arg @ref LL_BDMA_CHANNEL_3 01215 * @arg @ref LL_BDMA_CHANNEL_4 01216 * @arg @ref LL_BDMA_CHANNEL_5 01217 * @arg @ref LL_BDMA_CHANNEL_6 01218 * @arg @ref LL_BDMA_CHANNEL_7 01219 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01220 */ 01221 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) 01222 { 01223 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01224 01225 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR)); 01226 } 01227 01228 /** 01229 * @brief Set the Memory to Memory Source address. 01230 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. 01231 * @note This API must not be called when the BDMA channel is enabled. 01232 * @rmtoll CPAR PA LL_BDMA_SetM2MSrcAddress 01233 * @param BDMAx BDMA Instance 01234 * @param Channel This parameter can be one of the following values: 01235 * @arg @ref LL_BDMA_CHANNEL_0 01236 * @arg @ref LL_BDMA_CHANNEL_1 01237 * @arg @ref LL_BDMA_CHANNEL_2 01238 * @arg @ref LL_BDMA_CHANNEL_3 01239 * @arg @ref LL_BDMA_CHANNEL_4 01240 * @arg @ref LL_BDMA_CHANNEL_5 01241 * @arg @ref LL_BDMA_CHANNEL_6 01242 * @arg @ref LL_BDMA_CHANNEL_7 01243 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01244 * @retval None 01245 */ 01246 __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) 01247 { 01248 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01249 01250 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); 01251 } 01252 01253 /** 01254 * @brief Set the Memory to Memory Destination address. 01255 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. 01256 * @note This API must not be called when the BDMA channel is enabled. 01257 * @rmtoll CMAR MA LL_BDMA_SetM2MDstAddress 01258 * @param BDMAx BDMA Instance 01259 * @param Channel This parameter can be one of the following values: 01260 * @arg @ref LL_BDMA_CHANNEL_0 01261 * @arg @ref LL_BDMA_CHANNEL_1 01262 * @arg @ref LL_BDMA_CHANNEL_2 01263 * @arg @ref LL_BDMA_CHANNEL_3 01264 * @arg @ref LL_BDMA_CHANNEL_4 01265 * @arg @ref LL_BDMA_CHANNEL_5 01266 * @arg @ref LL_BDMA_CHANNEL_6 01267 * @arg @ref LL_BDMA_CHANNEL_7 01268 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01269 * @retval None 01270 */ 01271 __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress) 01272 { 01273 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01274 01275 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress); 01276 } 01277 01278 /** 01279 * @brief Get the Memory to Memory Source address. 01280 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. 01281 * @rmtoll CPAR PA LL_BDMA_GetM2MSrcAddress 01282 * @param BDMAx BDMA Instance 01283 * @param Channel This parameter can be one of the following values: 01284 * @arg @ref LL_BDMA_CHANNEL_0 01285 * @arg @ref LL_BDMA_CHANNEL_1 01286 * @arg @ref LL_BDMA_CHANNEL_2 01287 * @arg @ref LL_BDMA_CHANNEL_3 01288 * @arg @ref LL_BDMA_CHANNEL_4 01289 * @arg @ref LL_BDMA_CHANNEL_5 01290 * @arg @ref LL_BDMA_CHANNEL_6 01291 * @arg @ref LL_BDMA_CHANNEL_7 01292 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01293 */ 01294 __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) 01295 { 01296 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01297 01298 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR)); 01299 } 01300 01301 /** 01302 * @brief Get the Memory to Memory Destination address. 01303 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only. 01304 * @rmtoll CMAR MA LL_BDMA_GetM2MDstAddress 01305 * @param BDMAx BDMA Instance 01306 * @param Channel This parameter can be one of the following values: 01307 * @arg @ref LL_BDMA_CHANNEL_0 01308 * @arg @ref LL_BDMA_CHANNEL_1 01309 * @arg @ref LL_BDMA_CHANNEL_2 01310 * @arg @ref LL_BDMA_CHANNEL_3 01311 * @arg @ref LL_BDMA_CHANNEL_4 01312 * @arg @ref LL_BDMA_CHANNEL_5 01313 * @arg @ref LL_BDMA_CHANNEL_6 01314 * @arg @ref LL_BDMA_CHANNEL_7 01315 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01316 */ 01317 __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel) 01318 { 01319 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01320 01321 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR)); 01322 } 01323 01324 /** 01325 * @brief Set Memory 1 address (used in case of Double buffer mode). 01326 * @rmtoll M1AR M1A LL_BDMA_SetMemory1Address 01327 * @param BDMAx BDMAx Instance 01328 * @param Channel This parameter can be one of the following values: 01329 * @arg @ref LL_BDMA_CHANNEL_0 01330 * @arg @ref LL_BDMA_CHANNEL_1 01331 * @arg @ref LL_BDMA_CHANNEL_2 01332 * @arg @ref LL_BDMA_CHANNEL_3 01333 * @arg @ref LL_BDMA_CHANNEL_4 01334 * @arg @ref LL_BDMA_CHANNEL_5 01335 * @arg @ref LL_BDMA_CHANNEL_6 01336 * @arg @ref LL_BDMA_CHANNEL_7 01337 * @param Address Between 0 to 0xFFFFFFFF 01338 * @retval None 01339 */ 01340 __STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address) 01341 { 01342 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01343 01344 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address); 01345 } 01346 01347 /** 01348 * @brief Get Memory 1 address (used in case of Double buffer mode). 01349 * @rmtoll M1AR M1A LL_BDMA_GetMemory1Address 01350 * @param BDMAx BDMAx Instance 01351 * @param Channel This parameter can be one of the following values: 01352 * @arg @ref LL_BDMA_CHANNEL_0 01353 * @arg @ref LL_BDMA_CHANNEL_1 01354 * @arg @ref LL_BDMA_CHANNEL_2 01355 * @arg @ref LL_BDMA_CHANNEL_3 01356 * @arg @ref LL_BDMA_CHANNEL_4 01357 * @arg @ref LL_BDMA_CHANNEL_5 01358 * @arg @ref LL_BDMA_CHANNEL_6 01359 * @arg @ref LL_BDMA_CHANNEL_7 01360 * @retval Between 0 to 0xFFFFFFFF 01361 */ 01362 __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel) 01363 { 01364 uint32_t bdma_base_addr = (uint32_t)BDMAx; 01365 01366 return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR); 01367 } 01368 01369 /** 01370 * @brief Set BDMA request for BDMA Channels on DMAMUX Channel x. 01371 * @note DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7. 01372 * @rmtoll CxCR DMAREQ_ID LL_BDMA_SetPeriphRequest 01373 * @param BDMAx BDMAx Instance 01374 * @param Channel This parameter can be one of the following values: 01375 * @arg @ref LL_BDMA_CHANNEL_0 01376 * @arg @ref LL_BDMA_CHANNEL_1 01377 * @arg @ref LL_BDMA_CHANNEL_2 01378 * @arg @ref LL_BDMA_CHANNEL_3 01379 * @arg @ref LL_BDMA_CHANNEL_4 01380 * @arg @ref LL_BDMA_CHANNEL_5 01381 * @arg @ref LL_BDMA_CHANNEL_6 01382 * @arg @ref LL_BDMA_CHANNEL_7 01383 * @param Request This parameter can be one of the following values: 01384 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM 01385 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 01386 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 01387 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 01388 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 01389 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 01390 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 01391 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 01392 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 01393 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX 01394 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX 01395 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX 01396 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX 01397 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX 01398 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX 01399 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) 01400 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) 01401 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) 01402 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) 01403 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) 01404 * 01405 * @note (*) Availability depends on devices. 01406 * @retval None 01407 */ 01408 __STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request) 01409 { 01410 UNUSED(BDMAx); 01411 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); 01412 } 01413 01414 /** 01415 * @brief Get BDMA request for BDMA Channels on DMAMUX Channel x. 01416 * @note DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7. 01417 * @rmtoll CxCR DMAREQ_ID LL_BDMA_GetPeriphRequest 01418 * @param BDMAx BDMAx Instance 01419 * @param Channel This parameter can be one of the following values: 01420 * @arg @ref LL_BDMA_CHANNEL_0 01421 * @arg @ref LL_BDMA_CHANNEL_1 01422 * @arg @ref LL_BDMA_CHANNEL_2 01423 * @arg @ref LL_BDMA_CHANNEL_3 01424 * @arg @ref LL_BDMA_CHANNEL_4 01425 * @arg @ref LL_BDMA_CHANNEL_5 01426 * @arg @ref LL_BDMA_CHANNEL_6 01427 * @arg @ref LL_BDMA_CHANNEL_7 01428 * @retval Returned value can be one of the following values: 01429 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM 01430 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0 01431 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1 01432 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2 01433 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3 01434 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4 01435 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5 01436 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6 01437 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7 01438 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX 01439 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX 01440 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX 01441 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX 01442 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX 01443 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX 01444 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*) 01445 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*) 01446 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*) 01447 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*) 01448 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*) 01449 * 01450 * @note (*) Availability depends on devices. 01451 */ 01452 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel) 01453 { 01454 UNUSED(BDMAx); 01455 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); 01456 } 01457 01458 /** 01459 * @} 01460 */ 01461 01462 01463 /** @defgroup BDMA_LL_EF_FLAG_Management FLAG_Management 01464 * @{ 01465 */ 01466 /** 01467 * @brief Get Channel 0 global interrupt flag. 01468 * @rmtoll ISR GIF0 LL_BDMA_IsActiveFlag_GI0 01469 * @param BDMAx BDMA Instance 01470 * @retval State of bit (1 or 0). 01471 */ 01472 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx) 01473 { 01474 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL); 01475 } 01476 01477 /** 01478 * @brief Get Channel 1 global interrupt flag. 01479 * @rmtoll ISR GIF1 LL_BDMA_IsActiveFlag_GI1 01480 * @param BDMAx BDMA Instance 01481 * @retval State of bit (1 or 0). 01482 */ 01483 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx) 01484 { 01485 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL); 01486 } 01487 01488 /** 01489 * @brief Get Channel 2 global interrupt flag. 01490 * @rmtoll ISR GIF2 LL_BDMA_IsActiveFlag_GI2 01491 * @param BDMAx BDMA Instance 01492 * @retval State of bit (1 or 0). 01493 */ 01494 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx) 01495 { 01496 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL); 01497 } 01498 01499 /** 01500 * @brief Get Channel 3 global interrupt flag. 01501 * @rmtoll ISR GIF3 LL_BDMA_IsActiveFlag_GI3 01502 * @param BDMAx BDMA Instance 01503 * @retval State of bit (1 or 0). 01504 */ 01505 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx) 01506 { 01507 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL); 01508 } 01509 01510 /** 01511 * @brief Get Channel 4 global interrupt flag. 01512 * @rmtoll ISR GIF4 LL_BDMA_IsActiveFlag_GI4 01513 * @param BDMAx BDMA Instance 01514 * @retval State of bit (1 or 0). 01515 */ 01516 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx) 01517 { 01518 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL); 01519 } 01520 01521 /** 01522 * @brief Get Channel 5 global interrupt flag. 01523 * @rmtoll ISR GIF5 LL_BDMA_IsActiveFlag_GI5 01524 * @param BDMAx BDMA Instance 01525 * @retval State of bit (1 or 0). 01526 */ 01527 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx) 01528 { 01529 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL); 01530 } 01531 01532 /** 01533 * @brief Get Channel 6 global interrupt flag. 01534 * @rmtoll ISR GIF6 LL_BDMA_IsActiveFlag_GI6 01535 * @param BDMAx BDMA Instance 01536 * @retval State of bit (1 or 0). 01537 */ 01538 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx) 01539 { 01540 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL); 01541 } 01542 01543 /** 01544 * @brief Get Channel 7 global interrupt flag. 01545 * @rmtoll ISR GIF7 LL_BDMA_IsActiveFlag_GI7 01546 * @param BDMAx BDMA Instance 01547 * @retval State of bit (1 or 0). 01548 */ 01549 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx) 01550 { 01551 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL); 01552 } 01553 01554 /** 01555 * @brief Get Channel 0 transfer complete flag. 01556 * @rmtoll ISR TCIF0 LL_BDMA_IsActiveFlag_TC0 01557 * @param BDMAx BDMA Instance 01558 * @retval State of bit (1 or 0). 01559 */ 01560 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx) 01561 { 01562 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL); 01563 } 01564 /** 01565 * @brief Get Channel 1 transfer complete flag. 01566 * @rmtoll ISR TCIF1 LL_BDMA_IsActiveFlag_TC1 01567 * @param BDMAx BDMA Instance 01568 * @retval State of bit (1 or 0). 01569 */ 01570 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx) 01571 { 01572 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL); 01573 } 01574 01575 /** 01576 * @brief Get Channel 2 transfer complete flag. 01577 * @rmtoll ISR TCIF2 LL_BDMA_IsActiveFlag_TC2 01578 * @param BDMAx BDMA Instance 01579 * @retval State of bit (1 or 0). 01580 */ 01581 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx) 01582 { 01583 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL); 01584 } 01585 01586 /** 01587 * @brief Get Channel 3 transfer complete flag. 01588 * @rmtoll ISR TCIF3 LL_BDMA_IsActiveFlag_TC3 01589 * @param BDMAx BDMA Instance 01590 * @retval State of bit (1 or 0). 01591 */ 01592 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx) 01593 { 01594 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL); 01595 } 01596 01597 /** 01598 * @brief Get Channel 4 transfer complete flag. 01599 * @rmtoll ISR TCIF4 LL_BDMA_IsActiveFlag_TC4 01600 * @param BDMAx BDMA Instance 01601 * @retval State of bit (1 or 0). 01602 */ 01603 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx) 01604 { 01605 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL); 01606 } 01607 01608 /** 01609 * @brief Get Channel 5 transfer complete flag. 01610 * @rmtoll ISR TCIF5 LL_BDMA_IsActiveFlag_TC5 01611 * @param BDMAx BDMA Instance 01612 * @retval State of bit (1 or 0). 01613 */ 01614 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx) 01615 { 01616 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL); 01617 } 01618 01619 /** 01620 * @brief Get Channel 6 transfer complete flag. 01621 * @rmtoll ISR TCIF6 LL_BDMA_IsActiveFlag_TC6 01622 * @param BDMAx BDMA Instance 01623 * @retval State of bit (1 or 0). 01624 */ 01625 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx) 01626 { 01627 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL); 01628 } 01629 01630 /** 01631 * @brief Get Channel 7 transfer complete flag. 01632 * @rmtoll ISR TCIF7 LL_BDMA_IsActiveFlag_TC7 01633 * @param BDMAx BDMA Instance 01634 * @retval State of bit (1 or 0). 01635 */ 01636 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx) 01637 { 01638 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL); 01639 } 01640 01641 /** 01642 * @brief Get Channel 0 half transfer flag. 01643 * @rmtoll ISR HTIF0 LL_BDMA_IsActiveFlag_HT0 01644 * @param BDMAx BDMA Instance 01645 * @retval State of bit (1 or 0). 01646 */ 01647 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx) 01648 { 01649 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL); 01650 } 01651 01652 /** 01653 * @brief Get Channel 1 half transfer flag. 01654 * @rmtoll ISR HTIF1 LL_BDMA_IsActiveFlag_HT1 01655 * @param BDMAx BDMA Instance 01656 * @retval State of bit (1 or 0). 01657 */ 01658 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx) 01659 { 01660 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL); 01661 } 01662 01663 /** 01664 * @brief Get Channel 2 half transfer flag. 01665 * @rmtoll ISR HTIF2 LL_BDMA_IsActiveFlag_HT2 01666 * @param BDMAx BDMA Instance 01667 * @retval State of bit (1 or 0). 01668 */ 01669 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx) 01670 { 01671 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL); 01672 } 01673 01674 /** 01675 * @brief Get Channel 3 half transfer flag. 01676 * @rmtoll ISR HTIF3 LL_BDMA_IsActiveFlag_HT3 01677 * @param BDMAx BDMA Instance 01678 * @retval State of bit (1 or 0). 01679 */ 01680 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx) 01681 { 01682 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL); 01683 } 01684 01685 /** 01686 * @brief Get Channel 4 half transfer flag. 01687 * @rmtoll ISR HTIF4 LL_BDMA_IsActiveFlag_HT4 01688 * @param BDMAx BDMA Instance 01689 * @retval State of bit (1 or 0). 01690 */ 01691 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx) 01692 { 01693 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL); 01694 } 01695 01696 /** 01697 * @brief Get Channel 5 half transfer flag. 01698 * @rmtoll ISR HTIF5 LL_BDMA_IsActiveFlag_HT5 01699 * @param BDMAx BDMA Instance 01700 * @retval State of bit (1 or 0). 01701 */ 01702 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx) 01703 { 01704 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL); 01705 } 01706 01707 /** 01708 * @brief Get Channel 6 half transfer flag. 01709 * @rmtoll ISR HTIF6 LL_BDMA_IsActiveFlag_HT6 01710 * @param BDMAx BDMA Instance 01711 * @retval State of bit (1 or 0). 01712 */ 01713 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx) 01714 { 01715 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL); 01716 } 01717 01718 /** 01719 * @brief Get Channel 7 half transfer flag. 01720 * @rmtoll ISR HTIF7 LL_BDMA_IsActiveFlag_HT7 01721 * @param BDMAx BDMA Instance 01722 * @retval State of bit (1 or 0). 01723 */ 01724 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx) 01725 { 01726 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL); 01727 } 01728 01729 /** 01730 * @brief Get Channel 0 transfer error flag. 01731 * @rmtoll ISR TEIF0 LL_BDMA_IsActiveFlag_TE0 01732 * @param BDMAx BDMA Instance 01733 * @retval State of bit (1 or 0). 01734 */ 01735 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx) 01736 { 01737 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL); 01738 } 01739 01740 /** 01741 * @brief Get Channel 1 transfer error flag. 01742 * @rmtoll ISR TEIF1 LL_BDMA_IsActiveFlag_TE1 01743 * @param BDMAx BDMA Instance 01744 * @retval State of bit (1 or 0). 01745 */ 01746 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx) 01747 { 01748 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL); 01749 } 01750 01751 /** 01752 * @brief Get Channel 2 transfer error flag. 01753 * @rmtoll ISR TEIF2 LL_BDMA_IsActiveFlag_TE2 01754 * @param BDMAx BDMA Instance 01755 * @retval State of bit (1 or 0). 01756 */ 01757 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx) 01758 { 01759 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL); 01760 } 01761 01762 /** 01763 * @brief Get Channel 3 transfer error flag. 01764 * @rmtoll ISR TEIF3 LL_BDMA_IsActiveFlag_TE3 01765 * @param BDMAx BDMA Instance 01766 * @retval State of bit (1 or 0). 01767 */ 01768 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx) 01769 { 01770 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL); 01771 } 01772 01773 /** 01774 * @brief Get Channel 4 transfer error flag. 01775 * @rmtoll ISR TEIF4 LL_BDMA_IsActiveFlag_TE4 01776 * @param BDMAx BDMA Instance 01777 * @retval State of bit (1 or 0). 01778 */ 01779 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx) 01780 { 01781 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL); 01782 } 01783 01784 /** 01785 * @brief Get Channel 5 transfer error flag. 01786 * @rmtoll ISR TEIF5 LL_BDMA_IsActiveFlag_TE5 01787 * @param BDMAx BDMA Instance 01788 * @retval State of bit (1 or 0). 01789 */ 01790 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx) 01791 { 01792 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL); 01793 } 01794 01795 /** 01796 * @brief Get Channel 6 transfer error flag. 01797 * @rmtoll ISR TEIF6 LL_BDMA_IsActiveFlag_TE6 01798 * @param BDMAx BDMA Instance 01799 * @retval State of bit (1 or 0). 01800 */ 01801 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx) 01802 { 01803 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL); 01804 } 01805 01806 /** 01807 * @brief Get Channel 7 transfer error flag. 01808 * @rmtoll ISR TEIF7 LL_BDMA_IsActiveFlag_TE7 01809 * @param BDMAx BDMA Instance 01810 * @retval State of bit (1 or 0). 01811 */ 01812 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx) 01813 { 01814 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL); 01815 } 01816 01817 /** 01818 * @brief Clear Channel 0 global interrupt flag. 01819 * @note Do not Clear Channel 0 global interrupt flag when the channel in ON. 01820 Instead clear specific flags transfer complete, half transfer & transfer 01821 error flag with LL_DMA_ClearFlag_TC0, LL_DMA_ClearFlag_HT0, 01822 LL_DMA_ClearFlag_TE0. bug id 2.3.1 in Product Errata Sheet. 01823 * @rmtoll IFCR CGIF0 LL_BDMA_ClearFlag_GI0 01824 * @param BDMAx BDMA Instance 01825 * @retval None 01826 */ 01827 __STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx) 01828 { 01829 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0); 01830 } 01831 01832 /** 01833 * @brief Clear Channel 1 global interrupt flag. 01834 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON. 01835 Instead clear specific flags transfer complete, half transfer & transfer 01836 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1, 01837 LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet. 01838 * @rmtoll IFCR CGIF1 LL_BDMA_ClearFlag_GI1 01839 * @param BDMAx BDMA Instance 01840 * @retval None 01841 */ 01842 __STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx) 01843 { 01844 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1); 01845 } 01846 01847 /** 01848 * @brief Clear Channel 2 global interrupt flag. 01849 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON. 01850 Instead clear specific flags transfer complete, half transfer & transfer 01851 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2, 01852 LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet. 01853 * @rmtoll IFCR CGIF2 LL_BDMA_ClearFlag_GI2 01854 * @param BDMAx BDMA Instance 01855 * @retval None 01856 */ 01857 __STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx) 01858 { 01859 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2); 01860 } 01861 01862 /** 01863 * @brief Clear Channel 3 global interrupt flag. 01864 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON. 01865 Instead clear specific flags transfer complete, half transfer & transfer 01866 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3, 01867 LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet. 01868 * @rmtoll IFCR CGIF3 LL_BDMA_ClearFlag_GI3 01869 * @param BDMAx BDMA Instance 01870 * @retval None 01871 */ 01872 __STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx) 01873 { 01874 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3); 01875 } 01876 01877 /** 01878 * @brief Clear Channel 4 global interrupt flag. 01879 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON. 01880 Instead clear specific flags transfer complete, half transfer & transfer 01881 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4, 01882 LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet. 01883 * @rmtoll IFCR CGIF4 LL_BDMA_ClearFlag_GI4 01884 * @param BDMAx BDMA Instance 01885 * @retval None 01886 */ 01887 __STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx) 01888 { 01889 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4); 01890 } 01891 01892 /** 01893 * @brief Clear Channel 5 global interrupt flag. 01894 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON. 01895 Instead clear specific flags transfer complete, half transfer & transfer 01896 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5, 01897 LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet. 01898 * @rmtoll IFCR CGIF5 LL_BDMA_ClearFlag_GI5 01899 * @param BDMAx BDMA Instance 01900 * @retval None 01901 */ 01902 __STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx) 01903 { 01904 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5); 01905 } 01906 01907 /** 01908 * @brief Clear Channel 6 global interrupt flag. 01909 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON. 01910 Instead clear specific flags transfer complete, half transfer & transfer 01911 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6, 01912 LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet. 01913 * @rmtoll IFCR CGIF6 LL_BDMA_ClearFlag_GI6 01914 * @param BDMAx BDMA Instance 01915 * @retval None 01916 */ 01917 __STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx) 01918 { 01919 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6); 01920 } 01921 01922 /** 01923 * @brief Clear Channel 7 global interrupt flag. 01924 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON. 01925 Instead clear specific flags transfer complete, half transfer & transfer 01926 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7, 01927 LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet. 01928 * @rmtoll IFCR CGIF7 LL_BDMA_ClearFlag_GI7 01929 * @param BDMAx BDMA Instance 01930 * @retval None 01931 */ 01932 __STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx) 01933 { 01934 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7); 01935 } 01936 01937 /** 01938 * @brief Clear Channel 0 transfer complete flag. 01939 * @rmtoll IFCR CTCIF0 LL_BDMA_ClearFlag_TC0 01940 * @param BDMAx BDMA Instance 01941 * @retval None 01942 */ 01943 __STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx) 01944 { 01945 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0); 01946 } 01947 01948 /** 01949 * @brief Clear Channel 1 transfer complete flag. 01950 * @rmtoll IFCR CTCIF1 LL_BDMA_ClearFlag_TC1 01951 * @param BDMAx BDMA Instance 01952 * @retval None 01953 */ 01954 __STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx) 01955 { 01956 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1); 01957 } 01958 01959 /** 01960 * @brief Clear Channel 2 transfer complete flag. 01961 * @rmtoll IFCR CTCIF2 LL_BDMA_ClearFlag_TC2 01962 * @param BDMAx BDMA Instance 01963 * @retval None 01964 */ 01965 __STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx) 01966 { 01967 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2); 01968 } 01969 01970 /** 01971 * @brief Clear Channel 3 transfer complete flag. 01972 * @rmtoll IFCR CTCIF3 LL_BDMA_ClearFlag_TC3 01973 * @param BDMAx BDMA Instance 01974 * @retval None 01975 */ 01976 __STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx) 01977 { 01978 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3); 01979 } 01980 01981 /** 01982 * @brief Clear Channel 4 transfer complete flag. 01983 * @rmtoll IFCR CTCIF4 LL_BDMA_ClearFlag_TC4 01984 * @param BDMAx BDMA Instance 01985 * @retval None 01986 */ 01987 __STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx) 01988 { 01989 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4); 01990 } 01991 01992 /** 01993 * @brief Clear Channel 5 transfer complete flag. 01994 * @rmtoll IFCR CTCIF5 LL_BDMA_ClearFlag_TC5 01995 * @param BDMAx BDMA Instance 01996 * @retval None 01997 */ 01998 __STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx) 01999 { 02000 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5); 02001 } 02002 02003 /** 02004 * @brief Clear Channel 6 transfer complete flag. 02005 * @rmtoll IFCR CTCIF6 LL_BDMA_ClearFlag_TC6 02006 * @param BDMAx BDMA Instance 02007 * @retval None 02008 */ 02009 __STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx) 02010 { 02011 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6); 02012 } 02013 02014 /** 02015 * @brief Clear Channel 7 transfer complete flag. 02016 * @rmtoll IFCR CTCIF7 LL_BDMA_ClearFlag_TC7 02017 * @param BDMAx BDMA Instance 02018 * @retval None 02019 */ 02020 __STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx) 02021 { 02022 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7); 02023 } 02024 02025 /** 02026 * @brief Clear Channel 0 half transfer flag. 02027 * @rmtoll IFCR CHTIF0 LL_BDMA_ClearFlag_HT0 02028 * @param BDMAx BDMA Instance 02029 * @retval None 02030 */ 02031 __STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx) 02032 { 02033 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0); 02034 } 02035 02036 /** 02037 * @brief Clear Channel 1 half transfer flag. 02038 * @rmtoll IFCR CHTIF1 LL_BDMA_ClearFlag_HT1 02039 * @param BDMAx BDMA Instance 02040 * @retval None 02041 */ 02042 __STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx) 02043 { 02044 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1); 02045 } 02046 02047 /** 02048 * @brief Clear Channel 2 half transfer flag. 02049 * @rmtoll IFCR CHTIF2 LL_BDMA_ClearFlag_HT2 02050 * @param BDMAx BDMA Instance 02051 * @retval None 02052 */ 02053 __STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx) 02054 { 02055 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2); 02056 } 02057 02058 /** 02059 * @brief Clear Channel 3 half transfer flag. 02060 * @rmtoll IFCR CHTIF3 LL_BDMA_ClearFlag_HT3 02061 * @param BDMAx BDMA Instance 02062 * @retval None 02063 */ 02064 __STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx) 02065 { 02066 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3); 02067 } 02068 02069 /** 02070 * @brief Clear Channel 4 half transfer flag. 02071 * @rmtoll IFCR CHTIF4 LL_BDMA_ClearFlag_HT4 02072 * @param BDMAx BDMA Instance 02073 * @retval None 02074 */ 02075 __STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx) 02076 { 02077 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4); 02078 } 02079 02080 /** 02081 * @brief Clear Channel 5 half transfer flag. 02082 * @rmtoll IFCR CHTIF5 LL_BDMA_ClearFlag_HT5 02083 * @param BDMAx BDMA Instance 02084 * @retval None 02085 */ 02086 __STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx) 02087 { 02088 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5); 02089 } 02090 02091 /** 02092 * @brief Clear Channel 6 half transfer flag. 02093 * @rmtoll IFCR CHTIF6 LL_BDMA_ClearFlag_HT6 02094 * @param BDMAx BDMA Instance 02095 * @retval None 02096 */ 02097 __STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx) 02098 { 02099 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6); 02100 } 02101 02102 /** 02103 * @brief Clear Channel 7 half transfer flag. 02104 * @rmtoll IFCR CHTIF7 LL_BDMA_ClearFlag_HT7 02105 * @param BDMAx BDMA Instance 02106 * @retval None 02107 */ 02108 __STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx) 02109 { 02110 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7); 02111 } 02112 02113 /** 02114 * @brief Clear Channel 0 transfer error flag. 02115 * @rmtoll IFCR CTEIF0 LL_BDMA_ClearFlag_TE0 02116 * @param BDMAx BDMA Instance 02117 * @retval None 02118 */ 02119 __STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx) 02120 { 02121 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0); 02122 } 02123 02124 /** 02125 * @brief Clear Channel 1 transfer error flag. 02126 * @rmtoll IFCR CTEIF1 LL_BDMA_ClearFlag_TE1 02127 * @param BDMAx BDMA Instance 02128 * @retval None 02129 */ 02130 __STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx) 02131 { 02132 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1); 02133 } 02134 02135 /** 02136 * @brief Clear Channel 2 transfer error flag. 02137 * @rmtoll IFCR CTEIF2 LL_BDMA_ClearFlag_TE2 02138 * @param BDMAx BDMA Instance 02139 * @retval None 02140 */ 02141 __STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx) 02142 { 02143 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2); 02144 } 02145 02146 /** 02147 * @brief Clear Channel 3 transfer error flag. 02148 * @rmtoll IFCR CTEIF3 LL_BDMA_ClearFlag_TE3 02149 * @param BDMAx BDMA Instance 02150 * @retval None 02151 */ 02152 __STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx) 02153 { 02154 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3); 02155 } 02156 02157 /** 02158 * @brief Clear Channel 4 transfer error flag. 02159 * @rmtoll IFCR CTEIF4 LL_BDMA_ClearFlag_TE4 02160 * @param BDMAx BDMA Instance 02161 * @retval None 02162 */ 02163 __STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx) 02164 { 02165 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4); 02166 } 02167 02168 /** 02169 * @brief Clear Channel 5 transfer error flag. 02170 * @rmtoll IFCR CTEIF5 LL_BDMA_ClearFlag_TE5 02171 * @param BDMAx BDMA Instance 02172 * @retval None 02173 */ 02174 __STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx) 02175 { 02176 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5); 02177 } 02178 02179 /** 02180 * @brief Clear Channel 6 transfer error flag. 02181 * @rmtoll IFCR CTEIF6 LL_BDMA_ClearFlag_TE6 02182 * @param BDMAx BDMA Instance 02183 * @retval None 02184 */ 02185 __STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx) 02186 { 02187 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6); 02188 } 02189 02190 /** 02191 * @brief Clear Channel 7 transfer error flag. 02192 * @rmtoll IFCR CTEIF7 LL_BDMA_ClearFlag_TE7 02193 * @param BDMAx BDMA Instance 02194 * @retval None 02195 */ 02196 __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx) 02197 { 02198 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7); 02199 } 02200 02201 /** 02202 * @} 02203 */ 02204 02205 /** @defgroup BDMA_LL_EF_IT_Management IT_Management 02206 * @{ 02207 */ 02208 /** 02209 * @brief Enable Transfer complete interrupt. 02210 * @rmtoll CCR TCIE LL_BDMA_EnableIT_TC 02211 * @param BDMAx BDMA Instance 02212 * @param Channel This parameter can be one of the following values: 02213 * @arg @ref LL_BDMA_CHANNEL_0 02214 * @arg @ref LL_BDMA_CHANNEL_1 02215 * @arg @ref LL_BDMA_CHANNEL_2 02216 * @arg @ref LL_BDMA_CHANNEL_3 02217 * @arg @ref LL_BDMA_CHANNEL_4 02218 * @arg @ref LL_BDMA_CHANNEL_5 02219 * @arg @ref LL_BDMA_CHANNEL_6 02220 * @arg @ref LL_BDMA_CHANNEL_7 02221 * @retval None 02222 */ 02223 __STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) 02224 { 02225 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02226 02227 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE); 02228 } 02229 02230 /** 02231 * @brief Enable Half transfer interrupt. 02232 * @rmtoll CCR HTIE LL_BDMA_EnableIT_HT 02233 * @param BDMAx BDMA Instance 02234 * @param Channel This parameter can be one of the following values: 02235 * @arg @ref LL_BDMA_CHANNEL_0 02236 * @arg @ref LL_BDMA_CHANNEL_1 02237 * @arg @ref LL_BDMA_CHANNEL_2 02238 * @arg @ref LL_BDMA_CHANNEL_3 02239 * @arg @ref LL_BDMA_CHANNEL_4 02240 * @arg @ref LL_BDMA_CHANNEL_5 02241 * @arg @ref LL_BDMA_CHANNEL_6 02242 * @arg @ref LL_BDMA_CHANNEL_7 02243 * @retval None 02244 */ 02245 __STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) 02246 { 02247 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02248 02249 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE); 02250 } 02251 02252 /** 02253 * @brief Enable Transfer error interrupt. 02254 * @rmtoll CCR TEIE LL_BDMA_EnableIT_TE 02255 * @param BDMAx BDMA Instance 02256 * @param Channel This parameter can be one of the following values: 02257 * @arg @ref LL_BDMA_CHANNEL_0 02258 * @arg @ref LL_BDMA_CHANNEL_1 02259 * @arg @ref LL_BDMA_CHANNEL_2 02260 * @arg @ref LL_BDMA_CHANNEL_3 02261 * @arg @ref LL_BDMA_CHANNEL_4 02262 * @arg @ref LL_BDMA_CHANNEL_5 02263 * @arg @ref LL_BDMA_CHANNEL_6 02264 * @arg @ref LL_BDMA_CHANNEL_7 02265 * @retval None 02266 */ 02267 __STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) 02268 { 02269 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02270 02271 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE); 02272 } 02273 02274 /** 02275 * @brief Disable Transfer complete interrupt. 02276 * @rmtoll CCR TCIE LL_BDMA_DisableIT_TC 02277 * @param BDMAx BDMA Instance 02278 * @param Channel This parameter can be one of the following values: 02279 * @arg @ref LL_BDMA_CHANNEL_0 02280 * @arg @ref LL_BDMA_CHANNEL_1 02281 * @arg @ref LL_BDMA_CHANNEL_2 02282 * @arg @ref LL_BDMA_CHANNEL_3 02283 * @arg @ref LL_BDMA_CHANNEL_4 02284 * @arg @ref LL_BDMA_CHANNEL_5 02285 * @arg @ref LL_BDMA_CHANNEL_6 02286 * @arg @ref LL_BDMA_CHANNEL_7 02287 * @retval None 02288 */ 02289 __STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) 02290 { 02291 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02292 02293 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE); 02294 } 02295 02296 /** 02297 * @brief Disable Half transfer interrupt. 02298 * @rmtoll CCR HTIE LL_BDMA_DisableIT_HT 02299 * @param BDMAx BDMA Instance 02300 * @param Channel This parameter can be one of the following values: 02301 * @arg @ref LL_BDMA_CHANNEL_0 02302 * @arg @ref LL_BDMA_CHANNEL_1 02303 * @arg @ref LL_BDMA_CHANNEL_2 02304 * @arg @ref LL_BDMA_CHANNEL_3 02305 * @arg @ref LL_BDMA_CHANNEL_4 02306 * @arg @ref LL_BDMA_CHANNEL_5 02307 * @arg @ref LL_BDMA_CHANNEL_6 02308 * @arg @ref LL_BDMA_CHANNEL_7 02309 * @retval None 02310 */ 02311 __STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) 02312 { 02313 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02314 02315 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE); 02316 } 02317 02318 /** 02319 * @brief Disable Transfer error interrupt. 02320 * @rmtoll CCR TEIE LL_BDMA_DisableIT_TE 02321 * @param BDMAx BDMA Instance 02322 * @param Channel This parameter can be one of the following values: 02323 * @arg @ref LL_BDMA_CHANNEL_0 02324 * @arg @ref LL_BDMA_CHANNEL_1 02325 * @arg @ref LL_BDMA_CHANNEL_2 02326 * @arg @ref LL_BDMA_CHANNEL_3 02327 * @arg @ref LL_BDMA_CHANNEL_4 02328 * @arg @ref LL_BDMA_CHANNEL_5 02329 * @arg @ref LL_BDMA_CHANNEL_6 02330 * @arg @ref LL_BDMA_CHANNEL_7 02331 * @retval None 02332 */ 02333 __STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) 02334 { 02335 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02336 02337 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE); 02338 } 02339 02340 /** 02341 * @brief Check if Transfer complete Interrupt is enabled. 02342 * @rmtoll CCR TCIE LL_BDMA_IsEnabledIT_TC 02343 * @param BDMAx BDMA Instance 02344 * @param Channel This parameter can be one of the following values: 02345 * @arg @ref LL_BDMA_CHANNEL_0 02346 * @arg @ref LL_BDMA_CHANNEL_1 02347 * @arg @ref LL_BDMA_CHANNEL_2 02348 * @arg @ref LL_BDMA_CHANNEL_3 02349 * @arg @ref LL_BDMA_CHANNEL_4 02350 * @arg @ref LL_BDMA_CHANNEL_5 02351 * @arg @ref LL_BDMA_CHANNEL_6 02352 * @arg @ref LL_BDMA_CHANNEL_7 02353 * @retval State of bit (1 or 0). 02354 */ 02355 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel) 02356 { 02357 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02358 02359 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL); 02360 } 02361 02362 /** 02363 * @brief Check if Half transfer Interrupt is enabled. 02364 * @rmtoll CCR HTIE LL_BDMA_IsEnabledIT_HT 02365 * @param BDMAx BDMA Instance 02366 * @param Channel This parameter can be one of the following values: 02367 * @arg @ref LL_BDMA_CHANNEL_0 02368 * @arg @ref LL_BDMA_CHANNEL_1 02369 * @arg @ref LL_BDMA_CHANNEL_2 02370 * @arg @ref LL_BDMA_CHANNEL_3 02371 * @arg @ref LL_BDMA_CHANNEL_4 02372 * @arg @ref LL_BDMA_CHANNEL_5 02373 * @arg @ref LL_BDMA_CHANNEL_6 02374 * @arg @ref LL_BDMA_CHANNEL_7 02375 * @retval State of bit (1 or 0). 02376 */ 02377 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel) 02378 { 02379 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02380 02381 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL); 02382 } 02383 02384 /** 02385 * @brief Check if Transfer error Interrupt is enabled. 02386 * @rmtoll CCR TEIE LL_BDMA_IsEnabledIT_TE 02387 * @param BDMAx BDMA Instance 02388 * @param Channel This parameter can be one of the following values: 02389 * @arg @ref LL_BDMA_CHANNEL_0 02390 * @arg @ref LL_BDMA_CHANNEL_1 02391 * @arg @ref LL_BDMA_CHANNEL_2 02392 * @arg @ref LL_BDMA_CHANNEL_3 02393 * @arg @ref LL_BDMA_CHANNEL_4 02394 * @arg @ref LL_BDMA_CHANNEL_5 02395 * @arg @ref LL_BDMA_CHANNEL_6 02396 * @arg @ref LL_BDMA_CHANNEL_7 02397 * @retval State of bit (1 or 0). 02398 */ 02399 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel) 02400 { 02401 uint32_t bdma_base_addr = (uint32_t)BDMAx; 02402 02403 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL); 02404 } 02405 02406 /** 02407 * @} 02408 */ 02409 02410 #if defined(USE_FULL_LL_DRIVER) 02411 /** @defgroup BDMA_LL_EF_Init Initialization and de-initialization functions 02412 * @{ 02413 */ 02414 02415 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct); 02416 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel); 02417 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct); 02418 02419 /** 02420 * @} 02421 */ 02422 #endif /* USE_FULL_LL_DRIVER */ 02423 02424 /** 02425 * @} 02426 */ 02427 02428 /** 02429 * @} 02430 */ 02431 02432 #endif /* BDMA || BDMA1 || BDMA2 */ 02433 /** 02434 * @} 02435 */ 02436 02437 /** 02438 * @} 02439 */ 02440 02441 /** 02442 * @} 02443 */ 02444 02445 #ifdef __cplusplus 02446 } 02447 #endif 02448 02449 #endif /* STM32H7xx_LL_BDMA_H */ 02450
1.7.6.1