|
STM32H735xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX LL module. 00006 @verbatim 00007 ============================================================================== 00008 ##### How to use this driver ##### 00009 ============================================================================== 00010 [..] 00011 The LL CORTEX driver contains a set of generic APIs that can be 00012 used by user: 00013 (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick 00014 functions 00015 (+) Low power mode configuration (SCB register of Cortex-MCU) 00016 (+) MPU API to configure and enable regions 00017 (+) API to access to MCU info (CPUID register) 00018 (+) API to enable fault handler (SHCSR accesses) 00019 00020 @endverbatim 00021 ****************************************************************************** 00022 * @attention 00023 * 00024 * Copyright (c) 2017 STMicroelectronics. 00025 * All rights reserved. 00026 * 00027 * This software is licensed under terms that can be found in the LICENSE file in 00028 * the root directory of this software component. 00029 * If no LICENSE file comes with this software, it is provided AS-IS. 00030 * 00031 ****************************************************************************** 00032 */ 00033 00034 /* Define to prevent recursive inclusion -------------------------------------*/ 00035 #ifndef STM32H7xx_LL_CORTEX_H 00036 #define STM32H7xx_LL_CORTEX_H 00037 00038 #ifdef __cplusplus 00039 extern "C" { 00040 #endif 00041 00042 /* Includes ------------------------------------------------------------------*/ 00043 #include "stm32h7xx.h" 00044 00045 /** @addtogroup STM32H7xx_LL_Driver 00046 * @{ 00047 */ 00048 00049 /** @defgroup CORTEX_LL CORTEX 00050 * @{ 00051 */ 00052 00053 /* Private types -------------------------------------------------------------*/ 00054 /* Private variables ---------------------------------------------------------*/ 00055 00056 /* Private constants ---------------------------------------------------------*/ 00057 00058 /* Private macros ------------------------------------------------------------*/ 00059 00060 /* Exported types ------------------------------------------------------------*/ 00061 /* Exported constants --------------------------------------------------------*/ 00062 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants 00063 * @{ 00064 */ 00065 00066 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source 00067 * @{ 00068 */ 00069 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000UL /*!< AHB clock divided by 8 selected as SysTick clock source.*/ 00070 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ 00071 /** 00072 * @} 00073 */ 00074 00075 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type 00076 * @{ 00077 */ 00078 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ 00079 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ 00080 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ 00081 /** 00082 * @} 00083 */ 00084 00085 #if __MPU_PRESENT 00086 00087 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control 00088 * @{ 00089 */ 00090 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000UL /*!< Disable NMI and privileged SW access */ 00091 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ 00092 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ 00093 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ 00094 /** 00095 * @} 00096 */ 00097 00098 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number 00099 * @{ 00100 */ 00101 #define LL_MPU_REGION_NUMBER0 0x00UL /*!< REGION Number 0 */ 00102 #define LL_MPU_REGION_NUMBER1 0x01UL /*!< REGION Number 1 */ 00103 #define LL_MPU_REGION_NUMBER2 0x02UL /*!< REGION Number 2 */ 00104 #define LL_MPU_REGION_NUMBER3 0x03UL /*!< REGION Number 3 */ 00105 #define LL_MPU_REGION_NUMBER4 0x04UL /*!< REGION Number 4 */ 00106 #define LL_MPU_REGION_NUMBER5 0x05UL /*!< REGION Number 5 */ 00107 #define LL_MPU_REGION_NUMBER6 0x06UL /*!< REGION Number 6 */ 00108 #define LL_MPU_REGION_NUMBER7 0x07UL /*!< REGION Number 7 */ 00109 #if !defined(CORE_CM4) 00110 #define LL_MPU_REGION_NUMBER8 0x08UL /*!< REGION Number 8 */ 00111 #define LL_MPU_REGION_NUMBER9 0x09UL /*!< REGION Number 9 */ 00112 #define LL_MPU_REGION_NUMBER10 0x0AUL /*!< REGION Number 10 */ 00113 #define LL_MPU_REGION_NUMBER11 0x0BUL /*!< REGION Number 11 */ 00114 #define LL_MPU_REGION_NUMBER12 0x0CUL /*!< REGION Number 12 */ 00115 #define LL_MPU_REGION_NUMBER13 0x0DUL /*!< REGION Number 13 */ 00116 #define LL_MPU_REGION_NUMBER14 0x0EUL /*!< REGION Number 14 */ 00117 #define LL_MPU_REGION_NUMBER15 0x0FUL /*!< REGION Number 15 */ 00118 #endif /* !defined(CORE_CM4) */ 00119 /** 00120 * @} 00121 */ 00122 00123 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size 00124 * @{ 00125 */ 00126 #define LL_MPU_REGION_SIZE_32B (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ 00127 #define LL_MPU_REGION_SIZE_64B (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ 00128 #define LL_MPU_REGION_SIZE_128B (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ 00129 #define LL_MPU_REGION_SIZE_256B (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ 00130 #define LL_MPU_REGION_SIZE_512B (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ 00131 #define LL_MPU_REGION_SIZE_1KB (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ 00132 #define LL_MPU_REGION_SIZE_2KB (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ 00133 #define LL_MPU_REGION_SIZE_4KB (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ 00134 #define LL_MPU_REGION_SIZE_8KB (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ 00135 #define LL_MPU_REGION_SIZE_16KB (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ 00136 #define LL_MPU_REGION_SIZE_32KB (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ 00137 #define LL_MPU_REGION_SIZE_64KB (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ 00138 #define LL_MPU_REGION_SIZE_128KB (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ 00139 #define LL_MPU_REGION_SIZE_256KB (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ 00140 #define LL_MPU_REGION_SIZE_512KB (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ 00141 #define LL_MPU_REGION_SIZE_1MB (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ 00142 #define LL_MPU_REGION_SIZE_2MB (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ 00143 #define LL_MPU_REGION_SIZE_4MB (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ 00144 #define LL_MPU_REGION_SIZE_8MB (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ 00145 #define LL_MPU_REGION_SIZE_16MB (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ 00146 #define LL_MPU_REGION_SIZE_32MB (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ 00147 #define LL_MPU_REGION_SIZE_64MB (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ 00148 #define LL_MPU_REGION_SIZE_128MB (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ 00149 #define LL_MPU_REGION_SIZE_256MB (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ 00150 #define LL_MPU_REGION_SIZE_512MB (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ 00151 #define LL_MPU_REGION_SIZE_1GB (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ 00152 #define LL_MPU_REGION_SIZE_2GB (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ 00153 #define LL_MPU_REGION_SIZE_4GB (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ 00154 /** 00155 * @} 00156 */ 00157 00158 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges 00159 * @{ 00160 */ 00161 #define LL_MPU_REGION_NO_ACCESS (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/ 00162 #define LL_MPU_REGION_PRIV_RW (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ 00163 #define LL_MPU_REGION_PRIV_RW_URO (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ 00164 #define LL_MPU_REGION_FULL_ACCESS (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ 00165 #define LL_MPU_REGION_PRIV_RO (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ 00166 #define LL_MPU_REGION_PRIV_RO_URO (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ 00167 /** 00168 * @} 00169 */ 00170 00171 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level 00172 * @{ 00173 */ 00174 #define LL_MPU_TEX_LEVEL0 (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ 00175 #define LL_MPU_TEX_LEVEL1 (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ 00176 #define LL_MPU_TEX_LEVEL2 (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ 00177 #define LL_MPU_TEX_LEVEL4 (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ 00178 /** 00179 * @} 00180 */ 00181 00182 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access 00183 * @{ 00184 */ 00185 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00UL /*!< Instruction fetches enabled */ 00186 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ 00187 /** 00188 * @} 00189 */ 00190 00191 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access 00192 * @{ 00193 */ 00194 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ 00195 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00UL /*!< Not Shareable memory attribute */ 00196 /** 00197 * @} 00198 */ 00199 00200 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access 00201 * @{ 00202 */ 00203 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ 00204 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00UL /*!< Not Cacheable memory attribute */ 00205 /** 00206 * @} 00207 */ 00208 00209 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access 00210 * @{ 00211 */ 00212 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ 00213 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00UL /*!< Not Bufferable memory attribute */ 00214 /** 00215 * @} 00216 */ 00217 #endif /* __MPU_PRESENT */ 00218 /** 00219 * @} 00220 */ 00221 00222 /* Exported macro ------------------------------------------------------------*/ 00223 00224 /* Exported functions --------------------------------------------------------*/ 00225 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions 00226 * @{ 00227 */ 00228 00229 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK 00230 * @{ 00231 */ 00232 00233 /** 00234 * @brief This function checks if the Systick counter flag is active or not. 00235 * @note It can be used in timeout function on application side. 00236 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag 00237 * @retval State of bit (1 or 0). 00238 */ 00239 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) 00240 { 00241 return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); 00242 } 00243 00244 /** 00245 * @brief Configures the SysTick clock source 00246 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource 00247 * @param Source This parameter can be one of the following values: 00248 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00249 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00250 * @retval None 00251 */ 00252 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) 00253 { 00254 MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source); 00255 } 00256 00257 /** 00258 * @brief Get the SysTick clock source 00259 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource 00260 * @retval Returned value can be one of the following values: 00261 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00262 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00263 */ 00264 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) 00265 { 00266 return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK)); 00267 } 00268 00269 /** 00270 * @brief Enable SysTick exception request 00271 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT 00272 * @retval None 00273 */ 00274 __STATIC_INLINE void LL_SYSTICK_EnableIT(void) 00275 { 00276 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00277 } 00278 00279 /** 00280 * @brief Disable SysTick exception request 00281 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT 00282 * @retval None 00283 */ 00284 __STATIC_INLINE void LL_SYSTICK_DisableIT(void) 00285 { 00286 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00287 } 00288 00289 /** 00290 * @brief Checks if the SYSTICK interrupt is enabled or disabled. 00291 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT 00292 * @retval State of bit (1 or 0). 00293 */ 00294 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) 00295 { 00296 return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); 00297 } 00298 00299 /** 00300 * @} 00301 */ 00302 00303 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE 00304 * @{ 00305 */ 00306 00307 /** 00308 * @brief Processor uses sleep as its low power mode 00309 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep 00310 * @retval None 00311 */ 00312 __STATIC_INLINE void LL_LPM_EnableSleep(void) 00313 { 00314 /* Clear SLEEPDEEP bit of Cortex System Control Register */ 00315 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); 00316 } 00317 00318 /** 00319 * @brief Processor uses deep sleep as its low power mode 00320 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep 00321 * @retval None 00322 */ 00323 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) 00324 { 00325 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00326 SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); 00327 } 00328 00329 /** 00330 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. 00331 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an 00332 * empty main application. 00333 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit 00334 * @retval None 00335 */ 00336 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) 00337 { 00338 /* Set SLEEPONEXIT bit of Cortex System Control Register */ 00339 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); 00340 } 00341 00342 /** 00343 * @brief Do not sleep when returning to Thread mode. 00344 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit 00345 * @retval None 00346 */ 00347 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) 00348 { 00349 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 00350 CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); 00351 } 00352 00353 /** 00354 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the 00355 * processor. 00356 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend 00357 * @retval None 00358 */ 00359 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) 00360 { 00361 /* Set SEVEONPEND bit of Cortex System Control Register */ 00362 SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); 00363 } 00364 00365 /** 00366 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are 00367 * excluded 00368 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend 00369 * @retval None 00370 */ 00371 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) 00372 { 00373 /* Clear SEVEONPEND bit of Cortex System Control Register */ 00374 CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); 00375 } 00376 00377 /** 00378 * @} 00379 */ 00380 00381 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER 00382 * @{ 00383 */ 00384 00385 /** 00386 * @brief Enable a fault in System handler control register (SHCSR) 00387 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault 00388 * @param Fault This parameter can be a combination of the following values: 00389 * @arg @ref LL_HANDLER_FAULT_USG 00390 * @arg @ref LL_HANDLER_FAULT_BUS 00391 * @arg @ref LL_HANDLER_FAULT_MEM 00392 * @retval None 00393 */ 00394 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) 00395 { 00396 /* Enable the system handler fault */ 00397 SET_BIT(SCB->SHCSR, Fault); 00398 } 00399 00400 /** 00401 * @brief Disable a fault in System handler control register (SHCSR) 00402 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault 00403 * @param Fault This parameter can be a combination of the following values: 00404 * @arg @ref LL_HANDLER_FAULT_USG 00405 * @arg @ref LL_HANDLER_FAULT_BUS 00406 * @arg @ref LL_HANDLER_FAULT_MEM 00407 * @retval None 00408 */ 00409 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) 00410 { 00411 /* Disable the system handler fault */ 00412 CLEAR_BIT(SCB->SHCSR, Fault); 00413 } 00414 00415 /** 00416 * @} 00417 */ 00418 00419 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO 00420 * @{ 00421 */ 00422 00423 /** 00424 * @brief Get Implementer code 00425 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer 00426 * @retval Value should be equal to 0x41 for ARM 00427 */ 00428 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) 00429 { 00430 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); 00431 } 00432 00433 /** 00434 * @brief Get Variant number (The r value in the rnpn product revision identifier) 00435 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant 00436 * @retval Value between 0 and 255 (0x0: revision 0) 00437 */ 00438 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) 00439 { 00440 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); 00441 } 00442 00443 /** 00444 * @brief Get Constant number 00445 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant 00446 * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices 00447 */ 00448 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) 00449 { 00450 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); 00451 } 00452 00453 /** 00454 * @brief Get Part number 00455 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo 00456 * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4 00457 */ 00458 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) 00459 { 00460 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); 00461 } 00462 00463 /** 00464 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) 00465 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision 00466 * @retval Value between 0 and 255 (0x1: patch 1) 00467 */ 00468 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) 00469 { 00470 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); 00471 } 00472 00473 /** 00474 * @} 00475 */ 00476 00477 #if __MPU_PRESENT 00478 /** @defgroup CORTEX_LL_EF_MPU MPU 00479 * @{ 00480 */ 00481 00482 /** 00483 * @brief Enable MPU with input options 00484 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable 00485 * @param Options This parameter can be one of the following values: 00486 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 00487 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI 00488 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT 00489 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF 00490 * @retval None 00491 */ 00492 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) 00493 { 00494 /* Enable the MPU*/ 00495 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); 00496 /* Ensure MPU settings take effects */ 00497 __DSB(); 00498 /* Sequence instruction fetches using update settings */ 00499 __ISB(); 00500 } 00501 00502 /** 00503 * @brief Disable MPU 00504 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable 00505 * @retval None 00506 */ 00507 __STATIC_INLINE void LL_MPU_Disable(void) 00508 { 00509 /* Make sure outstanding transfers are done */ 00510 __DMB(); 00511 /* Disable MPU*/ 00512 WRITE_REG(MPU->CTRL, 0U); 00513 } 00514 00515 /** 00516 * @brief Check if MPU is enabled or not 00517 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled 00518 * @retval State of bit (1 or 0). 00519 */ 00520 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) 00521 { 00522 return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); 00523 } 00524 00525 /** 00526 * @brief Enable a MPU region 00527 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion 00528 * @param Region This parameter can be one of the following values: 00529 * @arg @ref LL_MPU_REGION_NUMBER0 00530 * @arg @ref LL_MPU_REGION_NUMBER1 00531 * @arg @ref LL_MPU_REGION_NUMBER2 00532 * @arg @ref LL_MPU_REGION_NUMBER3 00533 * @arg @ref LL_MPU_REGION_NUMBER4 00534 * @arg @ref LL_MPU_REGION_NUMBER5 00535 * @arg @ref LL_MPU_REGION_NUMBER6 00536 * @arg @ref LL_MPU_REGION_NUMBER7 00537 * @arg @ref LL_MPU_REGION_NUMBER8 00538 * @arg @ref LL_MPU_REGION_NUMBER9 00539 * @arg @ref LL_MPU_REGION_NUMBER10 00540 * @arg @ref LL_MPU_REGION_NUMBER11 00541 * @arg @ref LL_MPU_REGION_NUMBER12 00542 * @arg @ref LL_MPU_REGION_NUMBER13 00543 * @arg @ref LL_MPU_REGION_NUMBER14 00544 * @arg @ref LL_MPU_REGION_NUMBER15 00545 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. 00546 * @retval None 00547 */ 00548 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) 00549 { 00550 /* Set Region number */ 00551 WRITE_REG(MPU->RNR, Region); 00552 /* Enable the MPU region */ 00553 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00554 } 00555 00556 /** 00557 * @brief Configure and enable a region 00558 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n 00559 * MPU_RBAR REGION LL_MPU_ConfigRegion\n 00560 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n 00561 * MPU_RASR XN LL_MPU_ConfigRegion\n 00562 * MPU_RASR AP LL_MPU_ConfigRegion\n 00563 * MPU_RASR S LL_MPU_ConfigRegion\n 00564 * MPU_RASR C LL_MPU_ConfigRegion\n 00565 * MPU_RASR B LL_MPU_ConfigRegion\n 00566 * MPU_RASR SIZE LL_MPU_ConfigRegion 00567 * @param Region This parameter can be one of the following values: 00568 * @arg @ref LL_MPU_REGION_NUMBER0 00569 * @arg @ref LL_MPU_REGION_NUMBER1 00570 * @arg @ref LL_MPU_REGION_NUMBER2 00571 * @arg @ref LL_MPU_REGION_NUMBER3 00572 * @arg @ref LL_MPU_REGION_NUMBER4 00573 * @arg @ref LL_MPU_REGION_NUMBER5 00574 * @arg @ref LL_MPU_REGION_NUMBER6 00575 * @arg @ref LL_MPU_REGION_NUMBER7 00576 * @arg @ref LL_MPU_REGION_NUMBER8 00577 * @arg @ref LL_MPU_REGION_NUMBER9 00578 * @arg @ref LL_MPU_REGION_NUMBER10 00579 * @arg @ref LL_MPU_REGION_NUMBER11 00580 * @arg @ref LL_MPU_REGION_NUMBER12 00581 * @arg @ref LL_MPU_REGION_NUMBER13 00582 * @arg @ref LL_MPU_REGION_NUMBER14 00583 * @arg @ref LL_MPU_REGION_NUMBER15 00584 * @param Address Value of region base address 00585 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF 00586 * @param Attributes This parameter can be a combination of the following values: 00587 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B 00588 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB 00589 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB 00590 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB 00591 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB 00592 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB 00593 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS 00594 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO 00595 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 00596 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE 00597 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE 00598 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE 00599 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE 00600 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. 00601 * @retval None 00602 */ 00603 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) 00604 { 00605 /* Set Region number */ 00606 WRITE_REG(MPU->RNR, Region); 00607 /* Set base address */ 00608 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); 00609 /* Configure MPU */ 00610 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos))); 00611 } 00612 00613 /** 00614 * @brief Disable a region 00615 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n 00616 * MPU_RASR ENABLE LL_MPU_DisableRegion 00617 * @param Region This parameter can be one of the following values: 00618 * @arg @ref LL_MPU_REGION_NUMBER0 00619 * @arg @ref LL_MPU_REGION_NUMBER1 00620 * @arg @ref LL_MPU_REGION_NUMBER2 00621 * @arg @ref LL_MPU_REGION_NUMBER3 00622 * @arg @ref LL_MPU_REGION_NUMBER4 00623 * @arg @ref LL_MPU_REGION_NUMBER5 00624 * @arg @ref LL_MPU_REGION_NUMBER6 00625 * @arg @ref LL_MPU_REGION_NUMBER7 00626 * @arg @ref LL_MPU_REGION_NUMBER8 00627 * @arg @ref LL_MPU_REGION_NUMBER9 00628 * @arg @ref LL_MPU_REGION_NUMBER10 00629 * @arg @ref LL_MPU_REGION_NUMBER11 00630 * @arg @ref LL_MPU_REGION_NUMBER12 00631 * @arg @ref LL_MPU_REGION_NUMBER13 00632 * @arg @ref LL_MPU_REGION_NUMBER14 00633 * @arg @ref LL_MPU_REGION_NUMBER15 00634 * @note For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible. 00635 * @retval None 00636 */ 00637 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) 00638 { 00639 /* Set Region number */ 00640 WRITE_REG(MPU->RNR, Region); 00641 /* Disable the MPU region */ 00642 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00643 } 00644 00645 /** 00646 * @} 00647 */ 00648 00649 #endif /* __MPU_PRESENT */ 00650 /** 00651 * @} 00652 */ 00653 00654 /** 00655 * @} 00656 */ 00657 00658 /** 00659 * @} 00660 */ 00661 00662 #ifdef __cplusplus 00663 } 00664 #endif 00665 00666 #endif /* STM32H7xx_LL_CORTEX_H */ 00667
1.7.6.1