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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_dac.h 00004 * @author MCD Application Team 00005 * @brief Header file of DAC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_LL_DAC_H 00021 #define STM32H7xx_LL_DAC_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx.h" 00029 00030 /** @addtogroup STM32H7xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined(DAC1) || defined(DAC2) 00035 00036 /** @defgroup DAC_LL DAC 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 00043 /* Private constants ---------------------------------------------------------*/ 00044 /** @defgroup DAC_LL_Private_Constants DAC Private Constants 00045 * @{ 00046 */ 00047 00048 /* Internal masks for DAC channels definition */ 00049 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ 00050 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ 00051 /* - channel bits position into register SWTRIG */ 00052 /* - channel register offset of data holding register DHRx */ 00053 /* - channel register offset of data output register DORx */ 00054 /* - channel register offset of sample-and-hold sample time register SHSRx */ 00055 #define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers 00056 CR, MCR, CCR, SHHR, SHRR of channel 1 */ 00057 #define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers 00058 CR, MCR, CCR, SHHR, SHRR of channel 2 */ 00059 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) 00060 00061 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */ 00062 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */ 00063 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) 00064 00065 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */ 00066 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus 00067 DHR12Rx channel 1 (shifted left of 20 bits) */ 00068 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus 00069 DHR12Rx channel 1 (shifted left of 24 bits) */ 00070 00071 #define DAC_REG_DHR12R2_REGOFFSET 0x30000000UL /* Register offset of DHR12Rx channel 2 versus 00072 DHR12Rx channel 1 (shifted left of 28 bits) */ 00073 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus 00074 DHR12Rx channel 1 (shifted left of 20 bits) */ 00075 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus 00076 DHR12Rx channel 1 (shifted left of 24 bits) */ 00077 00078 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL 00079 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL 00080 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL 00081 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\ 00082 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) 00083 00084 #define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */ 00085 00086 #define DAC_REG_DOR2_REGOFFSET 0x00000020UL /* Register offset of DORx channel 1 versus 00087 DORx channel 2 (shifted left of 5 bits) */ 00088 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) 00089 00090 #define DAC_REG_SHSR1_REGOFFSET 0x00000000UL /* Register SHSRx channel 1 taken as reference */ 00091 #define DAC_REG_SHSR2_REGOFFSET 0x00000040UL /* Register offset of SHSRx channel 1 versus 00092 SHSRx channel 2 (shifted left of 6 bits) */ 00093 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) 00094 00095 00096 #define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, 00097 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */ 00098 #define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted 00099 to position 0 */ 00100 #define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted 00101 to position 0 */ 00102 00103 #define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DHR12Rx 00104 channel 1 or 2 versus DHR12Rx channel 1 00105 (shifted left of 28 bits) */ 00106 #define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx 00107 channel 1 or 2 versus DHR12Rx channel 1 00108 (shifted left of 20 bits) */ 00109 #define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx 00110 channel 1 or 2 versus DHR12Rx channel 1 00111 (shifted left of 24 bits) */ 00112 #define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 5UL /* Position of bits register offset of DORx 00113 channel 1 or 2 versus DORx channel 1 00114 (shifted left of 5 bits) */ 00115 #define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS 6UL /* Position of bits register offset of SHSRx 00116 channel 1 or 2 versus SHSRx channel 1 00117 (shifted left of 6 bits) */ 00118 00119 /* DAC registers bits positions */ 00120 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos 00121 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos 00122 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos 00123 00124 /* Miscellaneous data */ 00125 #define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12 00126 bits (voltage range determined by analog voltage 00127 references Vref+ and Vref-, refer to reference manual) */ 00128 00129 /** 00130 * @} 00131 */ 00132 00133 00134 /* Private macros ------------------------------------------------------------*/ 00135 /** @defgroup DAC_LL_Private_Macros DAC Private Macros 00136 * @{ 00137 */ 00138 00139 /** 00140 * @brief Driver macro reserved for internal use: set a pointer to 00141 * a register from a register basis from which an offset 00142 * is applied. 00143 * @param __REG__ Register basis from which the offset is applied. 00144 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 00145 * @retval Pointer to register address 00146 */ 00147 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00148 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) 00149 00150 /** 00151 * @} 00152 */ 00153 00154 00155 /* Exported types ------------------------------------------------------------*/ 00156 #if defined(USE_FULL_LL_DRIVER) 00157 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure 00158 * @{ 00159 */ 00160 00161 /** 00162 * @brief Structure definition of some features of DAC instance. 00163 */ 00164 typedef struct 00165 { 00166 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: 00167 internal (SW start) or from external peripheral 00168 (timer event, external interrupt line). 00169 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE 00170 00171 This feature can be modified afterwards using unitary 00172 function @ref LL_DAC_SetTriggerSource(). */ 00173 00174 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00175 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE 00176 00177 This feature can be modified afterwards using unitary 00178 function @ref LL_DAC_SetWaveAutoGeneration(). */ 00179 00180 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00181 If waveform automatic generation mode is set to noise, this parameter 00182 can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS 00183 If waveform automatic generation mode is set to triangle, 00184 this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE 00185 @note If waveform automatic generation mode is disabled, 00186 this parameter is discarded. 00187 00188 This feature can be modified afterwards using unitary 00189 function @ref LL_DAC_SetWaveNoiseLFSR(), 00190 @ref LL_DAC_SetWaveTriangleAmplitude() 00191 depending on the wave automatic generation selected. */ 00192 00193 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. 00194 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER 00195 00196 This feature can be modified afterwards using unitary 00197 function @ref LL_DAC_SetOutputBuffer(). */ 00198 00199 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. 00200 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION 00201 00202 This feature can be modified afterwards using unitary 00203 function @ref LL_DAC_SetOutputConnection(). */ 00204 00205 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC 00206 channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE 00207 00208 This feature can be modified afterwards using unitary 00209 function @ref LL_DAC_SetOutputMode(). */ 00210 } LL_DAC_InitTypeDef; 00211 00212 /** 00213 * @} 00214 */ 00215 #endif /* USE_FULL_LL_DRIVER */ 00216 00217 /* Exported constants --------------------------------------------------------*/ 00218 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants 00219 * @{ 00220 */ 00221 00222 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags 00223 * @brief Flags defines which can be used with LL_DAC_ReadReg function 00224 * @{ 00225 */ 00226 /* DAC channel 1 flags */ 00227 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ 00228 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */ 00229 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */ 00230 00231 /* DAC channel 2 flags */ 00232 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ 00233 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */ 00234 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */ 00235 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup DAC_LL_EC_IT DAC interruptions 00241 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions 00242 * @{ 00243 */ 00244 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ 00245 00246 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ 00247 00248 /** 00249 * @} 00250 */ 00251 00252 /** @defgroup DAC_LL_EC_CHANNEL DAC channels 00253 * @{ 00254 */ 00255 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ 00256 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ 00257 /** 00258 * @} 00259 */ 00260 00261 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode 00262 * @{ 00263 */ 00264 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000UL /*!< DAC channel in mode normal operation */ 00265 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */ 00266 /** 00267 * @} 00268 */ 00269 00270 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source 00271 * @{ 00272 */ 00273 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ 00274 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */ 00275 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */ 00276 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */ 00277 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */ 00278 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */ 00279 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */ 00280 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */ 00281 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */ 00282 #if defined (HRTIM1) 00283 #define LL_DAC_TRIG_EXT_HRTIM_TRGO1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */ 00284 #define LL_DAC_TRIG_EXT_HRTIM_TRGO2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */ 00285 #endif 00286 #define LL_DAC_TRIG_EXT_LPTIM1_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */ 00287 #define LL_DAC_TRIG_EXT_LPTIM2_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */ 00288 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */ 00289 #if defined(TIM23) 00290 #define LL_DAC_TRIG_EXT_TIM23_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */ 00291 #endif 00292 #if defined(TIM24) 00293 #define LL_DAC_TRIG_EXT_TIM24_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */ 00294 #endif 00295 #if defined (DAC2) 00296 #define LL_DAC_TRIG_EXT_LPTIM3_OUT (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */ 00297 #endif 00298 /** 00299 * @} 00300 */ 00301 00302 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode 00303 * @{ 00304 */ 00305 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL /*!< DAC channel wave auto generation mode disabled. */ 00306 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ 00307 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ 00308 /** 00309 * @} 00310 */ 00311 00312 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits 00313 * @{ 00314 */ 00315 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ 00316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ 00317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ 00318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ 00319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ 00320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ 00321 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ 00322 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ 00323 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ 00324 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ 00325 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ 00326 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ 00327 /** 00328 * @} 00329 */ 00330 00331 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude 00332 * @{ 00333 */ 00334 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ 00335 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ 00336 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ 00337 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ 00338 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ 00339 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ 00340 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ 00341 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ 00342 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ 00343 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ 00344 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ 00345 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ 00346 /** 00347 * @} 00348 */ 00349 00350 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode 00351 * @{ 00352 */ 00353 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000UL /*!< The selected DAC channel output is on mode normal. */ 00354 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */ 00355 /** 00356 * @} 00357 */ 00358 00359 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer 00360 * @{ 00361 */ 00362 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ 00363 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ 00364 /** 00365 * @} 00366 */ 00367 00368 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection 00369 * @{ 00370 */ 00371 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000UL /*!< The selected DAC channel output is connected to external pin */ 00372 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ 00373 /** 00374 * @} 00375 */ 00376 00377 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming 00378 * @{ 00379 */ 00380 #define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE) 00381 #define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO) 00382 #define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO) 00383 #define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO) 00384 #define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO) 00385 #define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO) 00386 #define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9) 00387 00388 #define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE) 00389 #define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE) 00390 #define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) 00391 00392 #define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO) 00393 #define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL) 00394 /** 00395 * @} 00396 */ 00397 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution 00398 * @{ 00399 */ 00400 #define LL_DAC_RESOLUTION_12B 0x00000000UL /*!< DAC channel resolution 12 bits */ 00401 #define LL_DAC_RESOLUTION_8B 0x00000002UL /*!< DAC channel resolution 8 bits */ 00402 /** 00403 * @} 00404 */ 00405 00406 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose 00407 * @{ 00408 */ 00409 /* List of DAC registers intended to be used (most commonly) with */ 00410 /* DMA transfer. */ 00411 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ 00412 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */ 00413 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */ 00414 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 8 bits right aligned */ 00415 /** 00416 * @} 00417 */ 00418 00419 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays 00420 * @note Only DAC peripheral HW delays are defined in DAC LL driver driver, 00421 * not timeout values. 00422 * For details on delays values, refer to descriptions in source code 00423 * above each literal definition. 00424 * @{ 00425 */ 00426 00427 /* Delay for DAC channel voltage settling time from DAC channel startup */ 00428 /* (transition from disable to enable). */ 00429 /* Note: DAC channel startup time depends on board application environment: */ 00430 /* impedance connected to DAC channel output. */ 00431 /* The delay below is specified under conditions: */ 00432 /* - voltage maximum transition (lowest to highest value) */ 00433 /* - until voltage reaches final value +-1LSB */ 00434 /* - DAC channel output buffer enabled */ 00435 /* - load impedance of 5kOhm (min), 50pF (max) */ 00436 /* Literal set to maximum value (refer to device datasheet, */ 00437 /* parameter "tWAKEUP"). */ 00438 /* Unit: us */ 00439 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8UL /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 00440 00441 /* Delay for DAC channel voltage settling time. */ 00442 /* Note: DAC channel startup time depends on board application environment: */ 00443 /* impedance connected to DAC channel output. */ 00444 /* The delay below is specified under conditions: */ 00445 /* - voltage maximum transition (lowest to highest value) */ 00446 /* - until voltage reaches final value +-1LSB */ 00447 /* - DAC channel output buffer enabled */ 00448 /* - load impedance of 5kOhm min, 50pF max */ 00449 /* Literal set to maximum value (refer to device datasheet, */ 00450 /* parameter "tSETTLING"). */ 00451 /* Unit: us */ 00452 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 3UL /*!< Delay for DAC channel voltage settling time */ 00453 00454 /** 00455 * @} 00456 */ 00457 00458 /** 00459 * @} 00460 */ 00461 00462 /* Exported macro ------------------------------------------------------------*/ 00463 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros 00464 * @{ 00465 */ 00466 00467 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros 00468 * @{ 00469 */ 00470 00471 /** 00472 * @brief Write a value in DAC register 00473 * @param __INSTANCE__ DAC Instance 00474 * @param __REG__ Register to be written 00475 * @param __VALUE__ Value to be written in the register 00476 * @retval None 00477 */ 00478 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00479 00480 /** 00481 * @brief Read a value in DAC register 00482 * @param __INSTANCE__ DAC Instance 00483 * @param __REG__ Register to be read 00484 * @retval Register value 00485 */ 00486 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00487 00488 /** 00489 * @} 00490 */ 00491 00492 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro 00493 * @{ 00494 */ 00495 00496 /** 00497 * @brief Helper macro to get DAC channel number in decimal format 00498 * from literals LL_DAC_CHANNEL_x. 00499 * Example: 00500 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) 00501 * will return decimal number "1". 00502 * @note The input can be a value from functions where a channel 00503 * number is returned. 00504 * @param __CHANNEL__ This parameter can be one of the following values: 00505 * @arg @ref LL_DAC_CHANNEL_1 00506 * @arg @ref LL_DAC_CHANNEL_2 00507 * @retval 1...2 00508 */ 00509 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 00510 ((__CHANNEL__) & DAC_SWTR_CHX_MASK) 00511 00512 /** 00513 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x 00514 * from number in decimal format. 00515 * Example: 00516 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) 00517 * will return a data equivalent to "LL_DAC_CHANNEL_1". 00518 * @note If the input parameter does not correspond to a DAC channel, 00519 * this macro returns value '0'. 00520 * @param __DECIMAL_NB__ 1...2 00521 * @retval Returned value can be one of the following values: 00522 * @arg @ref LL_DAC_CHANNEL_1 00523 * @arg @ref LL_DAC_CHANNEL_2 00524 */ 00525 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\ 00526 (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1 ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL))) 00527 00528 /** 00529 * @brief Helper macro to define the DAC conversion data full-scale digital 00530 * value corresponding to the selected DAC resolution. 00531 * @note DAC conversion data full-scale corresponds to voltage range 00532 * determined by analog voltage references Vref+ and Vref- 00533 * (refer to reference manual). 00534 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00535 * @arg @ref LL_DAC_RESOLUTION_12B 00536 * @arg @ref LL_DAC_RESOLUTION_8B 00537 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 00538 */ 00539 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00540 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL)) 00541 00542 /** 00543 * @brief Helper macro to calculate the DAC conversion data (unit: digital 00544 * value) corresponding to a voltage (unit: mVolt). 00545 * @note This helper macro is intended to provide input data in voltage 00546 * rather than digital value, 00547 * to be used with LL DAC functions such as 00548 * @ref LL_DAC_ConvertData12RightAligned(). 00549 * @note Analog reference voltage (Vref+) must be either known from 00550 * user board environment or can be calculated using ADC measurement 00551 * and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 00552 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 00553 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel 00554 * (unit: mVolt). 00555 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00556 * @arg @ref LL_DAC_RESOLUTION_12B 00557 * @arg @ref LL_DAC_RESOLUTION_8B 00558 * @retval DAC conversion data (unit: digital value) 00559 */ 00560 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ 00561 __DAC_VOLTAGE__,\ 00562 __DAC_RESOLUTION__) \ 00563 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00564 / (__VREFANALOG_VOLTAGE__) \ 00565 ) 00566 00567 /** 00568 * @} 00569 */ 00570 00571 /** 00572 * @} 00573 */ 00574 00575 00576 /* Exported functions --------------------------------------------------------*/ 00577 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions 00578 * @{ 00579 */ 00580 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels 00581 * @{ 00582 */ 00583 00584 /** 00585 * @brief Set the operating mode for the selected DAC channel: 00586 * calibration or normal operating mode. 00587 * @rmtoll CR CEN1 LL_DAC_SetMode\n 00588 * CR CEN2 LL_DAC_SetMode 00589 * @param DACx DAC instance 00590 * @param DAC_Channel This parameter can be one of the following values: 00591 * @arg @ref LL_DAC_CHANNEL_1 00592 * @arg @ref LL_DAC_CHANNEL_2 00593 * @param ChannelMode This parameter can be one of the following values: 00594 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION 00595 * @arg @ref LL_DAC_MODE_CALIBRATION 00596 * @retval None 00597 */ 00598 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode) 00599 { 00600 MODIFY_REG(DACx->CR, 00601 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00602 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00603 } 00604 00605 /** 00606 * @brief Get the operating mode for the selected DAC channel: 00607 * calibration or normal operating mode. 00608 * @rmtoll CR CEN1 LL_DAC_GetMode\n 00609 * CR CEN2 LL_DAC_GetMode 00610 * @param DACx DAC instance 00611 * @param DAC_Channel This parameter can be one of the following values: 00612 * @arg @ref LL_DAC_CHANNEL_1 00613 * @arg @ref LL_DAC_CHANNEL_2 00614 * @retval Returned value can be one of the following values: 00615 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION 00616 * @arg @ref LL_DAC_MODE_CALIBRATION 00617 */ 00618 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00619 { 00620 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00621 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00622 ); 00623 } 00624 00625 /** 00626 * @brief Set the offset trimming value for the selected DAC channel. 00627 * Trimming has an impact when output buffer is enabled 00628 * and is intended to replace factory calibration default values. 00629 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n 00630 * CCR OTRIM2 LL_DAC_SetTrimmingValue 00631 * @param DACx DAC instance 00632 * @param DAC_Channel This parameter can be one of the following values: 00633 * @arg @ref LL_DAC_CHANNEL_1 00634 * @arg @ref LL_DAC_CHANNEL_2 00635 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F 00636 * @retval None 00637 */ 00638 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue) 00639 { 00640 MODIFY_REG(DACx->CCR, 00641 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00642 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00643 } 00644 00645 /** 00646 * @brief Get the offset trimming value for the selected DAC channel. 00647 * Trimming has an impact when output buffer is enabled 00648 * and is intended to replace factory calibration default values. 00649 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n 00650 * CCR OTRIM2 LL_DAC_GetTrimmingValue 00651 * @param DACx DAC instance 00652 * @param DAC_Channel This parameter can be one of the following values: 00653 * @arg @ref LL_DAC_CHANNEL_1 00654 * @arg @ref LL_DAC_CHANNEL_2 00655 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F 00656 */ 00657 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00658 { 00659 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00660 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00661 ); 00662 } 00663 00664 /** 00665 * @brief Set the conversion trigger source for the selected DAC channel. 00666 * @note For conversion trigger source to be effective, DAC trigger 00667 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00668 * @note To set conversion trigger source, DAC channel must be disabled. 00669 * Otherwise, the setting is discarded. 00670 * @note Availability of parameters of trigger sources from timer 00671 * depends on timers availability on the selected device. 00672 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n 00673 * CR TSEL2 LL_DAC_SetTriggerSource 00674 * @param DACx DAC instance 00675 * @param DAC_Channel This parameter can be one of the following values: 00676 * @arg @ref LL_DAC_CHANNEL_1 00677 * @arg @ref LL_DAC_CHANNEL_2 00678 * @param TriggerSource This parameter can be one of the following values: 00679 * @arg @ref LL_DAC_TRIG_SOFTWARE 00680 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO 00681 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00682 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00683 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00684 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00685 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00686 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00687 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO 00688 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1) 00689 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1) 00690 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT 00691 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT 00692 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT (2) 00693 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00694 * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3) 00695 * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4) 00696 * 00697 * (1) On this STM32 series, parameter not available on all devices. 00698 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) 00699 * (2) On this STM32 series, parameter only available on DAC2. 00700 * (3) On this STM32 series, parameter not available on all devices. 00701 * Only available if TIM23 feature is supported (refer to device datasheet for supported features list) 00702 * (4) On this STM32 series, parameter not available on all devices. 00703 * Only available if TIM24 feature is supported (refer to device datasheet for supported features list) 00704 * @retval None 00705 */ 00706 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) 00707 { 00708 MODIFY_REG(DACx->CR, 00709 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00710 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00711 } 00712 00713 /** 00714 * @brief Get the conversion trigger source for the selected DAC channel. 00715 * @note For conversion trigger source to be effective, DAC trigger 00716 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00717 * @note Availability of parameters of trigger sources from timer 00718 * depends on timers availability on the selected device. 00719 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n 00720 * CR TSEL2 LL_DAC_GetTriggerSource 00721 * @param DACx DAC instance 00722 * @param DAC_Channel This parameter can be one of the following values: 00723 * @arg @ref LL_DAC_CHANNEL_1 00724 * @arg @ref LL_DAC_CHANNEL_2 00725 * @retval Returned value can be one of the following values: 00726 * @arg @ref LL_DAC_TRIG_SOFTWARE 00727 * @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO 00728 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00729 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00730 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00731 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00732 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00733 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00734 * @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO 00735 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1 (1) 00736 * @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2 (1) 00737 * @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT 00738 * @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT 00739 * @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT (2) 00740 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00741 * @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO (3) 00742 * @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO (4) 00743 * 00744 * (1) On this STM32 series, parameter not available on all devices. 00745 * Only available if HRTIM feature is supported (refer to device datasheet for supported features list) 00746 * (2) On this STM32 series, parameter only available on DAC2. 00747 * (3) On this STM32 series, parameter not available on all devices. 00748 * Only available if TIM23 feature is supported (refer to device datasheet for supported features list) 00749 * (4) On this STM32 series, parameter not available on all devices. 00750 * Only available if TIM24 feature is supported (refer to device datasheet for supported features list) 00751 */ 00752 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00753 { 00754 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00755 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00756 ); 00757 } 00758 00759 /** 00760 * @brief Set the waveform automatic generation mode 00761 * for the selected DAC channel. 00762 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n 00763 * CR WAVE2 LL_DAC_SetWaveAutoGeneration 00764 * @param DACx DAC instance 00765 * @param DAC_Channel This parameter can be one of the following values: 00766 * @arg @ref LL_DAC_CHANNEL_1 00767 * @arg @ref LL_DAC_CHANNEL_2 00768 * @param WaveAutoGeneration This parameter can be one of the following values: 00769 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00770 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00771 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00772 * @retval None 00773 */ 00774 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) 00775 { 00776 MODIFY_REG(DACx->CR, 00777 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00778 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00779 } 00780 00781 /** 00782 * @brief Get the waveform automatic generation mode 00783 * for the selected DAC channel. 00784 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n 00785 * CR WAVE2 LL_DAC_GetWaveAutoGeneration 00786 * @param DACx DAC instance 00787 * @param DAC_Channel This parameter can be one of the following values: 00788 * @arg @ref LL_DAC_CHANNEL_1 00789 * @arg @ref LL_DAC_CHANNEL_2 00790 * @retval Returned value can be one of the following values: 00791 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00792 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00793 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00794 */ 00795 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00796 { 00797 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00798 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00799 ); 00800 } 00801 00802 /** 00803 * @brief Set the noise waveform generation for the selected DAC channel: 00804 * Noise mode and parameters LFSR (linear feedback shift register). 00805 * @note For wave generation to be effective, DAC channel 00806 * wave generation mode must be enabled using 00807 * function @ref LL_DAC_SetWaveAutoGeneration(). 00808 * @note This setting can be set when the selected DAC channel is disabled 00809 * (otherwise, the setting operation is ignored). 00810 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n 00811 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR 00812 * @param DACx DAC instance 00813 * @param DAC_Channel This parameter can be one of the following values: 00814 * @arg @ref LL_DAC_CHANNEL_1 00815 * @arg @ref LL_DAC_CHANNEL_2 00816 * @param NoiseLFSRMask This parameter can be one of the following values: 00817 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00818 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00819 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00820 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00821 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00822 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00823 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00824 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00825 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00826 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00827 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00828 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00829 * @retval None 00830 */ 00831 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) 00832 { 00833 MODIFY_REG(DACx->CR, 00834 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00835 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00836 } 00837 00838 /** 00839 * @brief Get the noise waveform generation for the selected DAC channel: 00840 * Noise mode and parameters LFSR (linear feedback shift register). 00841 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n 00842 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR 00843 * @param DACx DAC instance 00844 * @param DAC_Channel This parameter can be one of the following values: 00845 * @arg @ref LL_DAC_CHANNEL_1 00846 * @arg @ref LL_DAC_CHANNEL_2 00847 * @retval Returned value can be one of the following values: 00848 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00849 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00850 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00851 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00852 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00853 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00854 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00855 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00856 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00857 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00858 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00859 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00860 */ 00861 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00862 { 00863 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00864 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00865 ); 00866 } 00867 00868 /** 00869 * @brief Set the triangle waveform generation for the selected DAC channel: 00870 * triangle mode and amplitude. 00871 * @note For wave generation to be effective, DAC channel 00872 * wave generation mode must be enabled using 00873 * function @ref LL_DAC_SetWaveAutoGeneration(). 00874 * @note This setting can be set when the selected DAC channel is disabled 00875 * (otherwise, the setting operation is ignored). 00876 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n 00877 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude 00878 * @param DACx DAC instance 00879 * @param DAC_Channel This parameter can be one of the following values: 00880 * @arg @ref LL_DAC_CHANNEL_1 00881 * @arg @ref LL_DAC_CHANNEL_2 00882 * @param TriangleAmplitude This parameter can be one of the following values: 00883 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00884 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00885 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00886 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00887 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00888 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00889 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00890 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00891 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00892 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00893 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00894 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00895 * @retval None 00896 */ 00897 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, 00898 uint32_t TriangleAmplitude) 00899 { 00900 MODIFY_REG(DACx->CR, 00901 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00902 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00903 } 00904 00905 /** 00906 * @brief Get the triangle waveform generation for the selected DAC channel: 00907 * triangle mode and amplitude. 00908 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n 00909 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude 00910 * @param DACx DAC instance 00911 * @param DAC_Channel This parameter can be one of the following values: 00912 * @arg @ref LL_DAC_CHANNEL_1 00913 * @arg @ref LL_DAC_CHANNEL_2 00914 * @retval Returned value can be one of the following values: 00915 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00916 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00917 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00919 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00920 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00921 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00922 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00923 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00924 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00925 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00926 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00927 */ 00928 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00929 { 00930 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00931 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00932 ); 00933 } 00934 00935 /** 00936 * @brief Set the output for the selected DAC channel. 00937 * @note This function set several features: 00938 * - mode normal or sample-and-hold 00939 * - buffer 00940 * - connection to GPIO or internal path. 00941 * These features can also be set individually using 00942 * dedicated functions: 00943 * - @ref LL_DAC_SetOutputBuffer() 00944 * - @ref LL_DAC_SetOutputMode() 00945 * - @ref LL_DAC_SetOutputConnection() 00946 * @note On this STM32 series, output connection depends on output mode 00947 * (normal or sample and hold) and output buffer state. 00948 * - if output connection is set to internal path and output buffer 00949 * is enabled (whatever output mode): 00950 * output connection is also connected to GPIO pin 00951 * (both connections to GPIO pin and internal path). 00952 * - if output connection is set to GPIO pin, output buffer 00953 * is disabled, output mode set to sample and hold: 00954 * output connection is also connected to internal path 00955 * (both connections to GPIO pin and internal path). 00956 * @note Mode sample-and-hold requires an external capacitor 00957 * to be connected between DAC channel output and ground. 00958 * Capacitor value depends on load on DAC channel output and 00959 * sample-and-hold timings configured. 00960 * As indication, capacitor typical value is 100nF 00961 * (refer to device datasheet, parameter "CSH"). 00962 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n 00963 * CR MODE2 LL_DAC_ConfigOutput 00964 * @param DACx DAC instance 00965 * @param DAC_Channel This parameter can be one of the following values: 00966 * @arg @ref LL_DAC_CHANNEL_1 00967 * @arg @ref LL_DAC_CHANNEL_2 00968 * @param OutputMode This parameter can be one of the following values: 00969 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 00970 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 00971 * @param OutputBuffer This parameter can be one of the following values: 00972 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 00973 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 00974 * @param OutputConnection This parameter can be one of the following values: 00975 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 00976 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 00977 * @retval None 00978 */ 00979 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, 00980 uint32_t OutputBuffer, uint32_t OutputConnection) 00981 { 00982 MODIFY_REG(DACx->MCR, 00983 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00984 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00985 } 00986 00987 /** 00988 * @brief Set the output mode normal or sample-and-hold 00989 * for the selected DAC channel. 00990 * @note Mode sample-and-hold requires an external capacitor 00991 * to be connected between DAC channel output and ground. 00992 * Capacitor value depends on load on DAC channel output and 00993 * sample-and-hold timings configured. 00994 * As indication, capacitor typical value is 100nF 00995 * (refer to device datasheet, parameter "CSH"). 00996 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n 00997 * CR MODE2 LL_DAC_SetOutputMode 00998 * @param DACx DAC instance 00999 * @param DAC_Channel This parameter can be one of the following values: 01000 * @arg @ref LL_DAC_CHANNEL_1 01001 * @arg @ref LL_DAC_CHANNEL_2 01002 * @param OutputMode This parameter can be one of the following values: 01003 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 01004 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 01005 * @retval None 01006 */ 01007 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode) 01008 { 01009 MODIFY_REG(DACx->MCR, 01010 (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01011 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01012 } 01013 01014 /** 01015 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel. 01016 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n 01017 * CR MODE2 LL_DAC_GetOutputMode 01018 * @param DACx DAC instance 01019 * @param DAC_Channel This parameter can be one of the following values: 01020 * @arg @ref LL_DAC_CHANNEL_1 01021 * @arg @ref LL_DAC_CHANNEL_2 01022 * @retval Returned value can be one of the following values: 01023 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 01024 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 01025 */ 01026 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01027 { 01028 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01029 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01030 ); 01031 } 01032 01033 /** 01034 * @brief Set the output buffer for the selected DAC channel. 01035 * @note On this STM32 series, when buffer is enabled, its offset can be 01036 * trimmed: factory calibration default values can be 01037 * replaced by user trimming values, using function 01038 * @ref LL_DAC_SetTrimmingValue(). 01039 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n 01040 * CR MODE2 LL_DAC_SetOutputBuffer 01041 * @param DACx DAC instance 01042 * @param DAC_Channel This parameter can be one of the following values: 01043 * @arg @ref LL_DAC_CHANNEL_1 01044 * @arg @ref LL_DAC_CHANNEL_2 01045 * @param OutputBuffer This parameter can be one of the following values: 01046 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 01047 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 01048 * @retval None 01049 */ 01050 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) 01051 { 01052 MODIFY_REG(DACx->MCR, 01053 (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01054 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01055 } 01056 01057 /** 01058 * @brief Get the output buffer state for the selected DAC channel. 01059 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n 01060 * CR MODE2 LL_DAC_GetOutputBuffer 01061 * @param DACx DAC instance 01062 * @param DAC_Channel This parameter can be one of the following values: 01063 * @arg @ref LL_DAC_CHANNEL_1 01064 * @arg @ref LL_DAC_CHANNEL_2 01065 * @retval Returned value can be one of the following values: 01066 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 01067 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 01068 */ 01069 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01070 { 01071 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01072 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01073 ); 01074 } 01075 01076 /** 01077 * @brief Set the output connection for the selected DAC channel. 01078 * @note On this STM32 series, output connection depends on output mode (normal or 01079 * sample and hold) and output buffer state. 01080 * - if output connection is set to internal path and output buffer 01081 * is enabled (whatever output mode): 01082 * output connection is also connected to GPIO pin 01083 * (both connections to GPIO pin and internal path). 01084 * - if output connection is set to GPIO pin, output buffer 01085 * is disabled, output mode set to sample and hold: 01086 * output connection is also connected to internal path 01087 * (both connections to GPIO pin and internal path). 01088 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n 01089 * CR MODE2 LL_DAC_SetOutputConnection 01090 * @param DACx DAC instance 01091 * @param DAC_Channel This parameter can be one of the following values: 01092 * @arg @ref LL_DAC_CHANNEL_1 01093 * @arg @ref LL_DAC_CHANNEL_2 01094 * @param OutputConnection This parameter can be one of the following values: 01095 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 01096 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 01097 * @retval None 01098 */ 01099 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection) 01100 { 01101 MODIFY_REG(DACx->MCR, 01102 (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01103 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01104 } 01105 01106 /** 01107 * @brief Get the output connection for the selected DAC channel. 01108 * @note On this STM32 series, output connection depends on output mode (normal or 01109 * sample and hold) and output buffer state. 01110 * - if output connection is set to internal path and output buffer 01111 * is enabled (whatever output mode): 01112 * output connection is also connected to GPIO pin 01113 * (both connections to GPIO pin and internal path). 01114 * - if output connection is set to GPIO pin, output buffer 01115 * is disabled, output mode set to sample and hold: 01116 * output connection is also connected to internal path 01117 * (both connections to GPIO pin and internal path). 01118 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n 01119 * CR MODE2 LL_DAC_GetOutputConnection 01120 * @param DACx DAC instance 01121 * @param DAC_Channel This parameter can be one of the following values: 01122 * @arg @ref LL_DAC_CHANNEL_1 01123 * @arg @ref LL_DAC_CHANNEL_2 01124 * @retval Returned value can be one of the following values: 01125 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 01126 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 01127 */ 01128 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01129 { 01130 return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01131 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01132 ); 01133 } 01134 01135 /** 01136 * @brief Set the sample-and-hold timing for the selected DAC channel: 01137 * sample time 01138 * @note Sample time must be set when DAC channel is disabled 01139 * or during DAC operation when DAC channel flag BWSTx is reset, 01140 * otherwise the setting is ignored. 01141 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()". 01142 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n 01143 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime 01144 * @param DACx DAC instance 01145 * @param DAC_Channel This parameter can be one of the following values: 01146 * @arg @ref LL_DAC_CHANNEL_1 01147 * @arg @ref LL_DAC_CHANNEL_2 01148 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF 01149 * @retval None 01150 */ 01151 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) 01152 { 01153 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) 01154 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); 01155 01156 MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime); 01157 } 01158 01159 /** 01160 * @brief Get the sample-and-hold timing for the selected DAC channel: 01161 * sample time 01162 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n 01163 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime 01164 * @param DACx DAC instance 01165 * @param DAC_Channel This parameter can be one of the following values: 01166 * @arg @ref LL_DAC_CHANNEL_1 01167 * @arg @ref LL_DAC_CHANNEL_2 01168 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 01169 */ 01170 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01171 { 01172 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) 01173 & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0); 01174 01175 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); 01176 } 01177 01178 /** 01179 * @brief Set the sample-and-hold timing for the selected DAC channel: 01180 * hold time 01181 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n 01182 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime 01183 * @param DACx DAC instance 01184 * @param DAC_Channel This parameter can be one of the following values: 01185 * @arg @ref LL_DAC_CHANNEL_1 01186 * @arg @ref LL_DAC_CHANNEL_2 01187 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF 01188 * @retval None 01189 */ 01190 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime) 01191 { 01192 MODIFY_REG(DACx->SHHR, 01193 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01194 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01195 } 01196 01197 /** 01198 * @brief Get the sample-and-hold timing for the selected DAC channel: 01199 * hold time 01200 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n 01201 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime 01202 * @param DACx DAC instance 01203 * @param DAC_Channel This parameter can be one of the following values: 01204 * @arg @ref LL_DAC_CHANNEL_1 01205 * @arg @ref LL_DAC_CHANNEL_2 01206 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 01207 */ 01208 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01209 { 01210 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01211 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01212 ); 01213 } 01214 01215 /** 01216 * @brief Set the sample-and-hold timing for the selected DAC channel: 01217 * refresh time 01218 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n 01219 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime 01220 * @param DACx DAC instance 01221 * @param DAC_Channel This parameter can be one of the following values: 01222 * @arg @ref LL_DAC_CHANNEL_1 01223 * @arg @ref LL_DAC_CHANNEL_2 01224 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF 01225 * @retval None 01226 */ 01227 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime) 01228 { 01229 MODIFY_REG(DACx->SHRR, 01230 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01231 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01232 } 01233 01234 /** 01235 * @brief Get the sample-and-hold timing for the selected DAC channel: 01236 * refresh time 01237 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n 01238 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime 01239 * @param DACx DAC instance 01240 * @param DAC_Channel This parameter can be one of the following values: 01241 * @arg @ref LL_DAC_CHANNEL_1 01242 * @arg @ref LL_DAC_CHANNEL_2 01243 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 01244 */ 01245 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01246 { 01247 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01248 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01249 ); 01250 } 01251 01252 /** 01253 * @} 01254 */ 01255 01256 /** @defgroup DAC_LL_EF_DMA_Management DMA Management 01257 * @{ 01258 */ 01259 01260 /** 01261 * @brief Enable DAC DMA transfer request of the selected channel. 01262 * @note To configure DMA source address (peripheral address), 01263 * use function @ref LL_DAC_DMA_GetRegAddr(). 01264 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n 01265 * CR DMAEN2 LL_DAC_EnableDMAReq 01266 * @param DACx DAC instance 01267 * @param DAC_Channel This parameter can be one of the following values: 01268 * @arg @ref LL_DAC_CHANNEL_1 01269 * @arg @ref LL_DAC_CHANNEL_2 01270 * @retval None 01271 */ 01272 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01273 { 01274 SET_BIT(DACx->CR, 01275 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01276 } 01277 01278 /** 01279 * @brief Disable DAC DMA transfer request of the selected channel. 01280 * @note To configure DMA source address (peripheral address), 01281 * use function @ref LL_DAC_DMA_GetRegAddr(). 01282 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n 01283 * CR DMAEN2 LL_DAC_DisableDMAReq 01284 * @param DACx DAC instance 01285 * @param DAC_Channel This parameter can be one of the following values: 01286 * @arg @ref LL_DAC_CHANNEL_1 01287 * @arg @ref LL_DAC_CHANNEL_2 01288 * @retval None 01289 */ 01290 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01291 { 01292 CLEAR_BIT(DACx->CR, 01293 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01294 } 01295 01296 /** 01297 * @brief Get DAC DMA transfer request state of the selected channel. 01298 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) 01299 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n 01300 * CR DMAEN2 LL_DAC_IsDMAReqEnabled 01301 * @param DACx DAC instance 01302 * @param DAC_Channel This parameter can be one of the following values: 01303 * @arg @ref LL_DAC_CHANNEL_1 01304 * @arg @ref LL_DAC_CHANNEL_2 01305 * @retval State of bit (1 or 0). 01306 */ 01307 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01308 { 01309 return ((READ_BIT(DACx->CR, 01310 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01311 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 01312 } 01313 01314 /** 01315 * @brief Function to help to configure DMA transfer to DAC: retrieve the 01316 * DAC register address from DAC instance and a list of DAC registers 01317 * intended to be used (most commonly) with DMA transfer. 01318 * @note These DAC registers are data holding registers: 01319 * when DAC conversion is requested, DAC generates a DMA transfer 01320 * request to have data available in DAC data holding registers. 01321 * @note This macro is intended to be used with LL DMA driver, refer to 01322 * function "LL_DMA_ConfigAddresses()". 01323 * Example: 01324 * LL_DMA_ConfigAddresses(DMA1, 01325 * LL_DMA_CHANNEL_1, 01326 * (uint32_t)&< array or variable >, 01327 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, 01328 * LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), 01329 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 01330 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01331 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01332 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01333 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 01334 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 01335 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr 01336 * @param DACx DAC instance 01337 * @param DAC_Channel This parameter can be one of the following values: 01338 * @arg @ref LL_DAC_CHANNEL_1 01339 * @arg @ref LL_DAC_CHANNEL_2 01340 * @param Register This parameter can be one of the following values: 01341 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED 01342 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED 01343 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED 01344 * @retval DAC register address 01345 */ 01346 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) 01347 { 01348 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ 01349 /* DAC channel selected. */ 01350 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL)) 01351 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0)))); 01352 } 01353 /** 01354 * @} 01355 */ 01356 01357 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels 01358 * @{ 01359 */ 01360 01361 /** 01362 * @brief Enable DAC selected channel. 01363 * @rmtoll CR EN1 LL_DAC_Enable\n 01364 * CR EN2 LL_DAC_Enable 01365 * @note After enable from off state, DAC channel requires a delay 01366 * for output voltage to reach accuracy +/- 1 LSB. 01367 * Refer to device datasheet, parameter "tWAKEUP". 01368 * @param DACx DAC instance 01369 * @param DAC_Channel This parameter can be one of the following values: 01370 * @arg @ref LL_DAC_CHANNEL_1 01371 * @arg @ref LL_DAC_CHANNEL_2 01372 * @retval None 01373 */ 01374 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01375 { 01376 SET_BIT(DACx->CR, 01377 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01378 } 01379 01380 /** 01381 * @brief Disable DAC selected channel. 01382 * @rmtoll CR EN1 LL_DAC_Disable\n 01383 * CR EN2 LL_DAC_Disable 01384 * @param DACx DAC instance 01385 * @param DAC_Channel This parameter can be one of the following values: 01386 * @arg @ref LL_DAC_CHANNEL_1 01387 * @arg @ref LL_DAC_CHANNEL_2 01388 * @retval None 01389 */ 01390 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01391 { 01392 CLEAR_BIT(DACx->CR, 01393 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01394 } 01395 01396 /** 01397 * @brief Get DAC enable state of the selected channel. 01398 * (0: DAC channel is disabled, 1: DAC channel is enabled) 01399 * @rmtoll CR EN1 LL_DAC_IsEnabled\n 01400 * CR EN2 LL_DAC_IsEnabled 01401 * @param DACx DAC instance 01402 * @param DAC_Channel This parameter can be one of the following values: 01403 * @arg @ref LL_DAC_CHANNEL_1 01404 * @arg @ref LL_DAC_CHANNEL_2 01405 * @retval State of bit (1 or 0). 01406 */ 01407 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01408 { 01409 return ((READ_BIT(DACx->CR, 01410 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01411 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 01412 } 01413 01414 /** 01415 * @brief Enable DAC trigger of the selected channel. 01416 * @note - If DAC trigger is disabled, DAC conversion is performed 01417 * automatically once the data holding register is updated, 01418 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01419 * @ref LL_DAC_ConvertData12RightAligned(), ... 01420 * - If DAC trigger is enabled, DAC conversion is performed 01421 * only when a hardware of software trigger event is occurring. 01422 * Select trigger source using 01423 * function @ref LL_DAC_SetTriggerSource(). 01424 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n 01425 * CR TEN2 LL_DAC_EnableTrigger 01426 * @param DACx DAC instance 01427 * @param DAC_Channel This parameter can be one of the following values: 01428 * @arg @ref LL_DAC_CHANNEL_1 01429 * @arg @ref LL_DAC_CHANNEL_2 01430 * @retval None 01431 */ 01432 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01433 { 01434 SET_BIT(DACx->CR, 01435 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01436 } 01437 01438 /** 01439 * @brief Disable DAC trigger of the selected channel. 01440 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n 01441 * CR TEN2 LL_DAC_DisableTrigger 01442 * @param DACx DAC instance 01443 * @param DAC_Channel This parameter can be one of the following values: 01444 * @arg @ref LL_DAC_CHANNEL_1 01445 * @arg @ref LL_DAC_CHANNEL_2 01446 * @retval None 01447 */ 01448 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01449 { 01450 CLEAR_BIT(DACx->CR, 01451 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01452 } 01453 01454 /** 01455 * @brief Get DAC trigger state of the selected channel. 01456 * (0: DAC trigger is disabled, 1: DAC trigger is enabled) 01457 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n 01458 * CR TEN2 LL_DAC_IsTriggerEnabled 01459 * @param DACx DAC instance 01460 * @param DAC_Channel This parameter can be one of the following values: 01461 * @arg @ref LL_DAC_CHANNEL_1 01462 * @arg @ref LL_DAC_CHANNEL_2 01463 * @retval State of bit (1 or 0). 01464 */ 01465 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01466 { 01467 return ((READ_BIT(DACx->CR, 01468 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01469 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL); 01470 } 01471 01472 /** 01473 * @brief Trig DAC conversion by software for the selected DAC channel. 01474 * @note Preliminarily, DAC trigger must be set to software trigger 01475 * using function 01476 * @ref LL_DAC_Init() 01477 * @ref LL_DAC_SetTriggerSource() 01478 * with parameter "LL_DAC_TRIGGER_SOFTWARE". 01479 * and DAC trigger must be enabled using 01480 * function @ref LL_DAC_EnableTrigger(). 01481 * @note For devices featuring DAC with 2 channels: this function 01482 * can perform a SW start of both DAC channels simultaneously. 01483 * Two channels can be selected as parameter. 01484 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) 01485 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n 01486 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion 01487 * @param DACx DAC instance 01488 * @param DAC_Channel This parameter can a combination of the following values: 01489 * @arg @ref LL_DAC_CHANNEL_1 01490 * @arg @ref LL_DAC_CHANNEL_2 01491 * @retval None 01492 */ 01493 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01494 { 01495 SET_BIT(DACx->SWTRIGR, 01496 (DAC_Channel & DAC_SWTR_CHX_MASK)); 01497 } 01498 01499 /** 01500 * @brief Set the data to be loaded in the data holding register 01501 * in format 12 bits left alignment (LSB aligned on bit 0), 01502 * for the selected DAC channel. 01503 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n 01504 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned 01505 * @param DACx DAC instance 01506 * @param DAC_Channel This parameter can be one of the following values: 01507 * @arg @ref LL_DAC_CHANNEL_1 01508 * @arg @ref LL_DAC_CHANNEL_2 01509 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01510 * @retval None 01511 */ 01512 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01513 { 01514 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) 01515 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01516 01517 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data); 01518 } 01519 01520 /** 01521 * @brief Set the data to be loaded in the data holding register 01522 * in format 12 bits left alignment (MSB aligned on bit 15), 01523 * for the selected DAC channel. 01524 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n 01525 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned 01526 * @param DACx DAC instance 01527 * @param DAC_Channel This parameter can be one of the following values: 01528 * @arg @ref LL_DAC_CHANNEL_1 01529 * @arg @ref LL_DAC_CHANNEL_2 01530 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01531 * @retval None 01532 */ 01533 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01534 { 01535 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) 01536 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01537 01538 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data); 01539 } 01540 01541 /** 01542 * @brief Set the data to be loaded in the data holding register 01543 * in format 8 bits left alignment (LSB aligned on bit 0), 01544 * for the selected DAC channel. 01545 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n 01546 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned 01547 * @param DACx DAC instance 01548 * @param DAC_Channel This parameter can be one of the following values: 01549 * @arg @ref LL_DAC_CHANNEL_1 01550 * @arg @ref LL_DAC_CHANNEL_2 01551 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 01552 * @retval None 01553 */ 01554 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01555 { 01556 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) 01557 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0); 01558 01559 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data); 01560 } 01561 01562 01563 /** 01564 * @brief Set the data to be loaded in the data holding register 01565 * in format 12 bits left alignment (LSB aligned on bit 0), 01566 * for both DAC channels. 01567 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n 01568 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned 01569 * @param DACx DAC instance 01570 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01571 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01572 * @retval None 01573 */ 01574 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01575 uint32_t DataChannel2) 01576 { 01577 MODIFY_REG(DACx->DHR12RD, 01578 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), 01579 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01580 } 01581 01582 /** 01583 * @brief Set the data to be loaded in the data holding register 01584 * in format 12 bits left alignment (MSB aligned on bit 15), 01585 * for both DAC channels. 01586 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n 01587 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned 01588 * @param DACx DAC instance 01589 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01590 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01591 * @retval None 01592 */ 01593 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01594 uint32_t DataChannel2) 01595 { 01596 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ 01597 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ 01598 /* the 4 LSB must be taken into account for the shift value. */ 01599 MODIFY_REG(DACx->DHR12LD, 01600 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), 01601 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); 01602 } 01603 01604 /** 01605 * @brief Set the data to be loaded in the data holding register 01606 * in format 8 bits left alignment (LSB aligned on bit 0), 01607 * for both DAC channels. 01608 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n 01609 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned 01610 * @param DACx DAC instance 01611 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF 01612 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF 01613 * @retval None 01614 */ 01615 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, 01616 uint32_t DataChannel2) 01617 { 01618 MODIFY_REG(DACx->DHR8RD, 01619 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), 01620 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01621 } 01622 01623 01624 /** 01625 * @brief Retrieve output data currently generated for the selected DAC channel. 01626 * @note Whatever alignment and resolution settings 01627 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01628 * @ref LL_DAC_ConvertData12RightAligned(), ...), 01629 * output data format is 12 bits right aligned (LSB aligned on bit 0). 01630 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n 01631 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData 01632 * @param DACx DAC instance 01633 * @param DAC_Channel This parameter can be one of the following values: 01634 * @arg @ref LL_DAC_CHANNEL_1 01635 * @arg @ref LL_DAC_CHANNEL_2 01636 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01637 */ 01638 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01639 { 01640 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) 01641 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0); 01642 01643 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); 01644 } 01645 01646 /** 01647 * @} 01648 */ 01649 01650 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management 01651 * @{ 01652 */ 01653 01654 /** 01655 * @brief Get DAC calibration offset flag for DAC channel 1 01656 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 01657 * @param DACx DAC instance 01658 * @retval State of bit (1 or 0). 01659 */ 01660 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) 01661 { 01662 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL); 01663 } 01664 01665 01666 /** 01667 * @brief Get DAC calibration offset flag for DAC channel 2 01668 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2 01669 * @param DACx DAC instance 01670 * @retval State of bit (1 or 0). 01671 */ 01672 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) 01673 { 01674 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL); 01675 } 01676 01677 01678 /** 01679 * @brief Get DAC busy writing sample time flag for DAC channel 1 01680 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1 01681 * @param DACx DAC instance 01682 * @retval State of bit (1 or 0). 01683 */ 01684 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) 01685 { 01686 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL); 01687 } 01688 01689 /** 01690 * @brief Get DAC busy writing sample time flag for DAC channel 2 01691 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2 01692 * @param DACx DAC instance 01693 * @retval State of bit (1 or 0). 01694 */ 01695 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) 01696 { 01697 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL); 01698 } 01699 01700 01701 /** 01702 * @brief Get DAC underrun flag for DAC channel 1 01703 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 01704 * @param DACx DAC instance 01705 * @retval State of bit (1 or 0). 01706 */ 01707 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) 01708 { 01709 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL); 01710 } 01711 01712 01713 /** 01714 * @brief Get DAC underrun flag for DAC channel 2 01715 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 01716 * @param DACx DAC instance 01717 * @retval State of bit (1 or 0). 01718 */ 01719 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) 01720 { 01721 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL); 01722 } 01723 01724 01725 /** 01726 * @brief Clear DAC underrun flag for DAC channel 1 01727 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 01728 * @param DACx DAC instance 01729 * @retval None 01730 */ 01731 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) 01732 { 01733 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); 01734 } 01735 01736 01737 /** 01738 * @brief Clear DAC underrun flag for DAC channel 2 01739 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 01740 * @param DACx DAC instance 01741 * @retval None 01742 */ 01743 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) 01744 { 01745 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); 01746 } 01747 01748 01749 /** 01750 * @} 01751 */ 01752 01753 /** @defgroup DAC_LL_EF_IT_Management IT management 01754 * @{ 01755 */ 01756 01757 /** 01758 * @brief Enable DMA underrun interrupt for DAC channel 1 01759 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 01760 * @param DACx DAC instance 01761 * @retval None 01762 */ 01763 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) 01764 { 01765 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01766 } 01767 01768 01769 /** 01770 * @brief Enable DMA underrun interrupt for DAC channel 2 01771 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 01772 * @param DACx DAC instance 01773 * @retval None 01774 */ 01775 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) 01776 { 01777 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01778 } 01779 01780 01781 /** 01782 * @brief Disable DMA underrun interrupt for DAC channel 1 01783 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 01784 * @param DACx DAC instance 01785 * @retval None 01786 */ 01787 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) 01788 { 01789 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01790 } 01791 01792 01793 /** 01794 * @brief Disable DMA underrun interrupt for DAC channel 2 01795 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 01796 * @param DACx DAC instance 01797 * @retval None 01798 */ 01799 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) 01800 { 01801 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01802 } 01803 01804 01805 /** 01806 * @brief Get DMA underrun interrupt for DAC channel 1 01807 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 01808 * @param DACx DAC instance 01809 * @retval State of bit (1 or 0). 01810 */ 01811 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) 01812 { 01813 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL); 01814 } 01815 01816 01817 /** 01818 * @brief Get DMA underrun interrupt for DAC channel 2 01819 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 01820 * @param DACx DAC instance 01821 * @retval State of bit (1 or 0). 01822 */ 01823 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) 01824 { 01825 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL); 01826 } 01827 01828 01829 /** 01830 * @} 01831 */ 01832 01833 #if defined(USE_FULL_LL_DRIVER) 01834 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions 01835 * @{ 01836 */ 01837 01838 ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); 01839 ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct); 01840 void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); 01841 01842 /** 01843 * @} 01844 */ 01845 #endif /* USE_FULL_LL_DRIVER */ 01846 01847 /** 01848 * @} 01849 */ 01850 01851 /** 01852 * @} 01853 */ 01854 01855 #endif /* DAC1 || DAC2 */ 01856 01857 /** 01858 * @} 01859 */ 01860 01861 #ifdef __cplusplus 01862 } 01863 #endif 01864 01865 #endif /* STM32H7xx_LL_DAC_H */ 01866
1.7.6.1