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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_dma2d.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA2D LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_LL_DMA2D_H 00021 #define STM32H7xx_LL_DMA2D_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx.h" 00029 00030 /** @addtogroup STM32H7xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (DMA2D) 00035 00036 /** @defgroup DMA2D_LL DMA2D 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /* Private constants ---------------------------------------------------------*/ 00043 /* Private macros ------------------------------------------------------------*/ 00044 #if defined(USE_FULL_LL_DRIVER) 00045 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros 00046 * @{ 00047 */ 00048 00049 /** 00050 * @} 00051 */ 00052 #endif /*USE_FULL_LL_DRIVER*/ 00053 00054 /* Exported types ------------------------------------------------------------*/ 00055 #if defined(USE_FULL_LL_DRIVER) 00056 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief LL DMA2D Init Structure Definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t Mode; /*!< Specifies the DMA2D transfer mode. 00066 - This parameter can be one value of @ref DMA2D_LL_EC_MODE. 00067 00068 This parameter can be modified afterwards, 00069 using unitary function @ref LL_DMA2D_SetMode(). */ 00070 00071 uint32_t ColorMode; /*!< Specifies the color format of the output image. 00072 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. 00073 00074 This parameter can be modified afterwards using, 00075 unitary function @ref LL_DMA2D_SetOutputColorMode(). */ 00076 00077 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. 00078 - This parameter must be a number between: 00079 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 00080 - This parameter must be a number between: 00081 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 00082 - This parameter must be a number between: 00083 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. 00084 - This parameter must be a number between: 00085 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 00086 - This parameter must be a number between: 00087 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 00088 00089 This parameter can be modified afterwards, 00090 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 00091 function @ref LL_DMA2D_ConfigOutputColor(). */ 00092 00093 uint32_t OutputGreen; /*!< Specifies the Green value of the output image. 00094 - This parameter must be a number between: 00095 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 00096 - This parameter must be a number between: 00097 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 00098 - This parameter must be a number between: 00099 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. 00100 - This parameter must be a number between: 00101 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 00102 - This parameter must be a number between: 00103 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 00104 00105 This parameter can be modified afterwards 00106 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 00107 function @ref LL_DMA2D_ConfigOutputColor(). */ 00108 00109 uint32_t OutputRed; /*!< Specifies the Red value of the output image. 00110 - This parameter must be a number between: 00111 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 00112 - This parameter must be a number between: 00113 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 00114 - This parameter must be a number between: 00115 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. 00116 - This parameter must be a number between: 00117 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 00118 - This parameter must be a number between: 00119 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 00120 00121 This parameter can be modified afterwards 00122 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 00123 function @ref LL_DMA2D_ConfigOutputColor(). */ 00124 00125 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. 00126 - This parameter must be a number between: 00127 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 00128 - This parameter must be a number between: 00129 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. 00130 - This parameter must be a number between: 00131 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 00132 - This parameter is not considered if RGB888 or RGB565 color mode is selected. 00133 00134 This parameter can be modified afterwards using, 00135 unitary function @ref LL_DMA2D_SetOutputColor() or configuration 00136 function @ref LL_DMA2D_ConfigOutputColor(). */ 00137 00138 uint32_t OutputMemoryAddress; /*!< Specifies the memory address. 00139 - This parameter must be a number between: 00140 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. 00141 00142 This parameter can be modified afterwards, 00143 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */ 00144 00145 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image. 00146 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE. 00147 00148 This parameter can be modified afterwards, 00149 using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */ 00150 00151 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode. 00152 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE. 00153 00154 This parameter can be modified afterwards, 00155 using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */ 00156 00157 uint32_t LineOffset; /*!< Specifies the output line offset value. 00158 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. 00159 00160 This parameter can be modified afterwards, 00161 using unitary function @ref LL_DMA2D_SetLineOffset(). */ 00162 00163 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred. 00164 - This parameter must be a number between: 00165 Min_Data = 0x0000 and Max_Data = 0xFFFF. 00166 00167 This parameter can be modified afterwards, 00168 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */ 00169 00170 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred. 00171 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. 00172 00173 This parameter can be modified afterwards using, 00174 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */ 00175 00176 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode. 00177 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. 00178 00179 This parameter can be modified afterwards, 00180 using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */ 00181 00182 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode. 00183 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP. 00184 00185 This parameter can be modified afterwards, 00186 using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */ 00187 00188 } LL_DMA2D_InitTypeDef; 00189 00190 /** 00191 * @brief LL DMA2D Layer Configuration Structure Definition 00192 */ 00193 typedef struct 00194 { 00195 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address. 00196 - This parameter must be a number between: 00197 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. 00198 00199 This parameter can be modified afterwards using unitary functions 00200 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer, 00201 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */ 00202 00203 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value. 00204 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. 00205 00206 This parameter can be modified afterwards using unitary functions 00207 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer, 00208 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */ 00209 00210 uint32_t ColorMode; /*!< Specifies the foreground or background color mode. 00211 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE. 00212 00213 This parameter can be modified afterwards using unitary functions 00214 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer, 00215 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */ 00216 00217 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode. 00218 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE. 00219 00220 This parameter can be modified afterwards using unitary functions 00221 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer, 00222 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */ 00223 00224 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size. 00225 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00226 00227 This parameter can be modified afterwards using unitary functions 00228 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer, 00229 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */ 00230 00231 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode. 00232 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE. 00233 00234 This parameter can be modified afterwards using unitary functions 00235 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer, 00236 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */ 00237 00238 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value. 00239 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00240 00241 This parameter can be modified afterwards using unitary functions 00242 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer, 00243 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */ 00244 00245 uint32_t Blue; /*!< Specifies the foreground or background Blue color value. 00246 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00247 00248 This parameter can be modified afterwards using unitary functions 00249 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer, 00250 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */ 00251 00252 uint32_t Green; /*!< Specifies the foreground or background Green color value. 00253 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00254 00255 This parameter can be modified afterwards using unitary functions 00256 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer, 00257 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */ 00258 00259 uint32_t Red; /*!< Specifies the foreground or background Red color value. 00260 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00261 00262 This parameter can be modified afterwards using unitary functions 00263 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer, 00264 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */ 00265 00266 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address. 00267 - This parameter must be a number between: 00268 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF. 00269 00270 This parameter can be modified afterwards using unitary functions 00271 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer, 00272 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */ 00273 00274 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode. 00275 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION. 00276 00277 This parameter can be modified afterwards using unitary functions 00278 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer, 00279 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */ 00280 00281 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode. 00282 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP . 00283 00284 This parameter can be modified afterwards using unitary functions 00285 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer, 00286 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */ 00287 00288 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode 00289 This parameter is applicable for foreground layer only. 00290 This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING 00291 00292 This parameter can be modified afterwards using unitary functions 00293 - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */ 00294 00295 } LL_DMA2D_LayerCfgTypeDef; 00296 00297 /** 00298 * @brief LL DMA2D Output Color Structure Definition 00299 */ 00300 typedef struct 00301 { 00302 uint32_t ColorMode; /*!< Specifies the color format of the output image. 00303 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE. 00304 00305 This parameter can be modified afterwards using 00306 unitary function @ref LL_DMA2D_SetOutputColorMode(). */ 00307 00308 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image. 00309 - This parameter must be a number between: 00310 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 00311 - This parameter must be a number between: 00312 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 00313 - This parameter must be a number between: 00314 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. 00315 - This parameter must be a number between: 00316 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 00317 - This parameter must be a number between: 00318 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 00319 00320 This parameter can be modified afterwards using, 00321 unitary function @ref LL_DMA2D_SetOutputColor() or configuration 00322 function @ref LL_DMA2D_ConfigOutputColor(). */ 00323 00324 uint32_t OutputGreen; /*!< Specifies the Green value of the output image. 00325 - This parameter must be a number between: 00326 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 00327 - This parameter must be a number between 00328 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 00329 - This parameter must be a number between: 00330 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected. 00331 - This parameter must be a number between: 00332 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 00333 - This parameter must be a number between: 00334 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 00335 00336 This parameter can be modified afterwards, 00337 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 00338 function @ref LL_DMA2D_ConfigOutputColor(). */ 00339 00340 uint32_t OutputRed; /*!< Specifies the Red value of the output image. 00341 - This parameter must be a number between: 00342 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 00343 - This parameter must be a number between: 00344 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected. 00345 - This parameter must be a number between: 00346 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected. 00347 - This parameter must be a number between: 00348 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected. 00349 - This parameter must be a number between: 00350 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 00351 00352 This parameter can be modified afterwards, 00353 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 00354 function @ref LL_DMA2D_ConfigOutputColor(). */ 00355 00356 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image. 00357 - This parameter must be a number between: 00358 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected. 00359 - This parameter must be a number between: 00360 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected. 00361 - This parameter must be a number between: 00362 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected. 00363 - This parameter is not considered if RGB888 or RGB565 color mode is selected. 00364 00365 This parameter can be modified afterwards, 00366 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration 00367 function @ref LL_DMA2D_ConfigOutputColor(). */ 00368 00369 } LL_DMA2D_ColorTypeDef; 00370 00371 /** 00372 * @} 00373 */ 00374 #endif /* USE_FULL_LL_DRIVER */ 00375 00376 /* Exported constants --------------------------------------------------------*/ 00377 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants 00378 * @{ 00379 */ 00380 00381 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines 00382 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function 00383 * @{ 00384 */ 00385 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 00386 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 00387 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 00388 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 00389 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 00390 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 00391 /** 00392 * @} 00393 */ 00394 00395 /** @defgroup DMA2D_LL_EC_IT IT Defines 00396 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions 00397 * @{ 00398 */ 00399 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 00400 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 00401 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 00402 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 00403 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 00404 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 00405 /** 00406 * @} 00407 */ 00408 00409 /** @defgroup DMA2D_LL_EC_MODE Mode 00410 * @{ 00411 */ 00412 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 00413 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 00414 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 00415 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */ 00416 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */ 00417 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */ 00418 /** 00419 * @} 00420 */ 00421 00422 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode 00423 * @{ 00424 */ 00425 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ 00426 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */ 00427 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */ 00428 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */ 00429 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */ 00430 /** 00431 * @} 00432 */ 00433 00434 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode 00435 * @{ 00436 */ 00437 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ 00438 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */ 00439 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */ 00440 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */ 00441 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */ 00442 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */ 00443 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */ 00444 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */ 00445 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */ 00446 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */ 00447 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */ 00448 #define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */ 00449 /** 00450 * @} 00451 */ 00452 00453 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode 00454 * @{ 00455 */ 00456 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */ 00457 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by 00458 programmed alpha value */ 00459 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by 00460 programmed alpha value with, 00461 original alpha channel value */ 00462 /** 00463 * @} 00464 */ 00465 00466 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode 00467 * @{ 00468 */ 00469 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */ 00470 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */ 00471 /** 00472 * @} 00473 */ 00474 00475 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap 00476 * @{ 00477 */ 00478 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */ 00479 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */ 00480 /** 00481 * @} 00482 */ 00483 00484 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion 00485 * @{ 00486 */ 00487 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */ 00488 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */ 00489 /** 00490 * @} 00491 */ 00492 00493 00494 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode 00495 * @{ 00496 */ 00497 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */ 00498 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */ 00499 /** 00500 * @} 00501 */ 00502 00503 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode 00504 * @{ 00505 */ 00506 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */ 00507 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */ 00508 /** 00509 * @} 00510 */ 00511 00512 /** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling 00513 * @{ 00514 */ 00515 #define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */ 00516 #define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */ 00517 #define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */ 00518 /** 00519 * @} 00520 */ 00521 00522 /** 00523 * @} 00524 */ 00525 00526 /* Exported macro ------------------------------------------------------------*/ 00527 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros 00528 * @{ 00529 */ 00530 00531 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros 00532 * @{ 00533 */ 00534 00535 /** 00536 * @brief Write a value in DMA2D register. 00537 * @param __INSTANCE__ DMA2D Instance 00538 * @param __REG__ Register to be written 00539 * @param __VALUE__ Value to be written in the register 00540 * @retval None 00541 */ 00542 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 00543 00544 /** 00545 * @brief Read a value in DMA2D register. 00546 * @param __INSTANCE__ DMA2D Instance 00547 * @param __REG__ Register to be read 00548 * @retval Register value 00549 */ 00550 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 00551 /** 00552 * @} 00553 */ 00554 00555 /** 00556 * @} 00557 */ 00558 00559 /* Exported functions --------------------------------------------------------*/ 00560 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions 00561 * @{ 00562 */ 00563 00564 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions 00565 * @{ 00566 */ 00567 00568 /** 00569 * @brief Start a DMA2D transfer. 00570 * @rmtoll CR START LL_DMA2D_Start 00571 * @param DMA2Dx DMA2D Instance 00572 * @retval None 00573 */ 00574 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx) 00575 { 00576 SET_BIT(DMA2Dx->CR, DMA2D_CR_START); 00577 } 00578 00579 /** 00580 * @brief Indicate if a DMA2D transfer is ongoing. 00581 * @rmtoll CR START LL_DMA2D_IsTransferOngoing 00582 * @param DMA2Dx DMA2D Instance 00583 * @retval State of bit (1 or 0). 00584 */ 00585 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx) 00586 { 00587 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL); 00588 } 00589 00590 /** 00591 * @brief Suspend DMA2D transfer. 00592 * @note This API can be used to suspend automatic foreground or background CLUT loading. 00593 * @rmtoll CR SUSP LL_DMA2D_Suspend 00594 * @param DMA2Dx DMA2D Instance 00595 * @retval None 00596 */ 00597 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx) 00598 { 00599 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP); 00600 } 00601 00602 /** 00603 * @brief Resume DMA2D transfer. 00604 * @note This API can be used to resume automatic foreground or background CLUT loading. 00605 * @rmtoll CR SUSP LL_DMA2D_Resume 00606 * @param DMA2Dx DMA2D Instance 00607 * @retval None 00608 */ 00609 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx) 00610 { 00611 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START); 00612 } 00613 00614 /** 00615 * @brief Indicate if DMA2D transfer is suspended. 00616 * @note This API can be used to indicate whether or not automatic foreground or 00617 * background CLUT loading is suspended. 00618 * @rmtoll CR SUSP LL_DMA2D_IsSuspended 00619 * @param DMA2Dx DMA2D Instance 00620 * @retval State of bit (1 or 0). 00621 */ 00622 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx) 00623 { 00624 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL); 00625 } 00626 00627 /** 00628 * @brief Abort DMA2D transfer. 00629 * @note This API can be used to abort automatic foreground or background CLUT loading. 00630 * @rmtoll CR ABORT LL_DMA2D_Abort 00631 * @param DMA2Dx DMA2D Instance 00632 * @retval None 00633 */ 00634 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx) 00635 { 00636 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT); 00637 } 00638 00639 /** 00640 * @brief Indicate if DMA2D transfer is aborted. 00641 * @note This API can be used to indicate whether or not automatic foreground or 00642 * background CLUT loading is aborted. 00643 * @rmtoll CR ABORT LL_DMA2D_IsAborted 00644 * @param DMA2Dx DMA2D Instance 00645 * @retval State of bit (1 or 0). 00646 */ 00647 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx) 00648 { 00649 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL); 00650 } 00651 00652 /** 00653 * @brief Set DMA2D mode. 00654 * @rmtoll CR MODE LL_DMA2D_SetMode 00655 * @param DMA2Dx DMA2D Instance 00656 * @param Mode This parameter can be one of the following values: 00657 * @arg @ref LL_DMA2D_MODE_M2M 00658 * @arg @ref LL_DMA2D_MODE_M2M_PFC 00659 * @arg @ref LL_DMA2D_MODE_M2M_BLEND 00660 * @arg @ref LL_DMA2D_MODE_R2M 00661 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG 00662 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG 00663 * @retval None 00664 */ 00665 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode) 00666 { 00667 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode); 00668 } 00669 00670 /** 00671 * @brief Return DMA2D mode 00672 * @rmtoll CR MODE LL_DMA2D_GetMode 00673 * @param DMA2Dx DMA2D Instance 00674 * @retval Returned value can be one of the following values: 00675 * @arg @ref LL_DMA2D_MODE_M2M 00676 * @arg @ref LL_DMA2D_MODE_M2M_PFC 00677 * @arg @ref LL_DMA2D_MODE_M2M_BLEND 00678 * @arg @ref LL_DMA2D_MODE_R2M 00679 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG 00680 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG 00681 */ 00682 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx) 00683 { 00684 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE)); 00685 } 00686 00687 /** 00688 * @brief Set DMA2D output color mode. 00689 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode 00690 * @param DMA2Dx DMA2D Instance 00691 * @param ColorMode This parameter can be one of the following values: 00692 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 00693 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 00694 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 00695 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 00696 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 00697 * @retval None 00698 */ 00699 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) 00700 { 00701 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode); 00702 } 00703 00704 /** 00705 * @brief Return DMA2D output color mode. 00706 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode 00707 * @param DMA2Dx DMA2D Instance 00708 * @retval Returned value can be one of the following values: 00709 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888 00710 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888 00711 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565 00712 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555 00713 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444 00714 */ 00715 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx) 00716 { 00717 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM)); 00718 } 00719 00720 /** 00721 * @brief Set DMA2D output Red Blue swap mode. 00722 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode 00723 * @param DMA2Dx DMA2D Instance 00724 * @param RBSwapMode This parameter can be one of the following values: 00725 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 00726 * @arg @ref LL_DMA2D_RB_MODE_SWAP 00727 * @retval None 00728 */ 00729 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) 00730 { 00731 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode); 00732 } 00733 00734 /** 00735 * @brief Return DMA2D output Red Blue swap mode. 00736 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode 00737 * @param DMA2Dx DMA2D Instance 00738 * @retval Returned value can be one of the following values: 00739 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 00740 * @arg @ref LL_DMA2D_RB_MODE_SWAP 00741 */ 00742 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx) 00743 { 00744 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS)); 00745 } 00746 00747 /** 00748 * @brief Set DMA2D output alpha inversion mode. 00749 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode 00750 * @param DMA2Dx DMA2D Instance 00751 * @param AlphaInversionMode This parameter can be one of the following values: 00752 * @arg @ref LL_DMA2D_ALPHA_REGULAR 00753 * @arg @ref LL_DMA2D_ALPHA_INVERTED 00754 * @retval None 00755 */ 00756 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) 00757 { 00758 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode); 00759 } 00760 00761 /** 00762 * @brief Return DMA2D output alpha inversion mode. 00763 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode 00764 * @param DMA2Dx DMA2D Instance 00765 * @retval Returned value can be one of the following values: 00766 * @arg @ref LL_DMA2D_ALPHA_REGULAR 00767 * @arg @ref LL_DMA2D_ALPHA_INVERTED 00768 */ 00769 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx) 00770 { 00771 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI)); 00772 } 00773 00774 00775 /** 00776 * @brief Set DMA2D output swap mode. 00777 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode 00778 * @param DMA2Dx DMA2D Instance 00779 * @param OutputSwapMode This parameter can be one of the following values: 00780 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR 00781 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO 00782 * @retval None 00783 */ 00784 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode) 00785 { 00786 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode); 00787 } 00788 00789 /** 00790 * @brief Return DMA2D output swap mode. 00791 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode 00792 * @param DMA2Dx DMA2D Instance 00793 * @retval Returned value can be one of the following values: 00794 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR 00795 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO 00796 */ 00797 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx) 00798 { 00799 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB)); 00800 } 00801 00802 /** 00803 * @brief Set DMA2D line offset mode. 00804 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode 00805 * @param DMA2Dx DMA2D Instance 00806 * @param LineOffsetMode This parameter can be one of the following values: 00807 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS 00808 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES 00809 * @retval None 00810 */ 00811 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode) 00812 { 00813 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode); 00814 } 00815 00816 /** 00817 * @brief Return DMA2D line offset mode. 00818 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode 00819 * @param DMA2Dx DMA2D Instance 00820 * @retval Returned value can be one of the following values: 00821 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS 00822 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES 00823 */ 00824 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx) 00825 { 00826 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM)); 00827 } 00828 00829 /** 00830 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits). 00831 * @rmtoll OOR LO LL_DMA2D_SetLineOffset 00832 * @param DMA2Dx DMA2D Instance 00833 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF 00834 * @retval None 00835 */ 00836 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) 00837 { 00838 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset); 00839 } 00840 00841 /** 00842 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits). 00843 * @rmtoll OOR LO LL_DMA2D_GetLineOffset 00844 * @param DMA2Dx DMA2D Instance 00845 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF 00846 */ 00847 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx) 00848 { 00849 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO)); 00850 } 00851 00852 /** 00853 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits). 00854 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines 00855 * @param DMA2Dx DMA2D Instance 00856 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF 00857 * @retval None 00858 */ 00859 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines) 00860 { 00861 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos)); 00862 } 00863 00864 /** 00865 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits) 00866 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines 00867 * @param DMA2Dx DMA2D Instance 00868 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF 00869 */ 00870 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx) 00871 { 00872 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos); 00873 } 00874 00875 /** 00876 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits). 00877 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines 00878 * @param DMA2Dx DMA2D Instance 00879 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF 00880 * @retval None 00881 */ 00882 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines) 00883 { 00884 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines); 00885 } 00886 00887 /** 00888 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits). 00889 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines 00890 * @param DMA2Dx DMA2D Instance 00891 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF 00892 */ 00893 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx) 00894 { 00895 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL)); 00896 } 00897 00898 /** 00899 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits). 00900 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr 00901 * @param DMA2Dx DMA2D Instance 00902 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 00903 * @retval None 00904 */ 00905 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress) 00906 { 00907 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress); 00908 } 00909 00910 /** 00911 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits). 00912 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr 00913 * @param DMA2Dx DMA2D Instance 00914 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 00915 */ 00916 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx) 00917 { 00918 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR)); 00919 } 00920 00921 /** 00922 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits). 00923 * @note Output color format depends on output color mode, ARGB8888, RGB888, 00924 * RGB565, ARGB1555 or ARGB4444. 00925 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting 00926 * with respect to color mode is not done by the user code. 00927 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n 00928 * OCOLR GREEN LL_DMA2D_SetOutputColor\n 00929 * OCOLR RED LL_DMA2D_SetOutputColor\n 00930 * OCOLR ALPHA LL_DMA2D_SetOutputColor 00931 * @param DMA2Dx DMA2D Instance 00932 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF 00933 * @retval None 00934 */ 00935 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor) 00936 { 00937 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \ 00938 OutputColor); 00939 } 00940 00941 /** 00942 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits). 00943 * @note Alpha channel and red, green, blue color values must be retrieved from the returned 00944 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444) 00945 * as set by @ref LL_DMA2D_SetOutputColorMode. 00946 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n 00947 * OCOLR GREEN LL_DMA2D_GetOutputColor\n 00948 * OCOLR RED LL_DMA2D_GetOutputColor\n 00949 * OCOLR ALPHA LL_DMA2D_GetOutputColor 00950 * @param DMA2Dx DMA2D Instance 00951 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF 00952 */ 00953 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx) 00954 { 00955 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \ 00956 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1))); 00957 } 00958 00959 /** 00960 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits). 00961 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark 00962 * @param DMA2Dx DMA2D Instance 00963 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF 00964 * @retval None 00965 */ 00966 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark) 00967 { 00968 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark); 00969 } 00970 00971 /** 00972 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits). 00973 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark 00974 * @param DMA2Dx DMA2D Instance 00975 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF 00976 */ 00977 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx) 00978 { 00979 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW)); 00980 } 00981 00982 /** 00983 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits). 00984 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime 00985 * @param DMA2Dx DMA2D Instance 00986 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF 00987 * @retval None 00988 */ 00989 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime) 00990 { 00991 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos)); 00992 } 00993 00994 /** 00995 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits). 00996 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime 00997 * @param DMA2Dx DMA2D Instance 00998 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF 00999 */ 01000 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx) 01001 { 01002 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos); 01003 } 01004 01005 /** 01006 * @brief Enable DMA2D dead time functionality. 01007 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime 01008 * @param DMA2Dx DMA2D Instance 01009 * @retval None 01010 */ 01011 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx) 01012 { 01013 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); 01014 } 01015 01016 /** 01017 * @brief Disable DMA2D dead time functionality. 01018 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime 01019 * @param DMA2Dx DMA2D Instance 01020 * @retval None 01021 */ 01022 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx) 01023 { 01024 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN); 01025 } 01026 01027 /** 01028 * @brief Indicate if DMA2D dead time functionality is enabled. 01029 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime 01030 * @param DMA2Dx DMA2D Instance 01031 * @retval State of bit (1 or 0). 01032 */ 01033 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx) 01034 { 01035 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL); 01036 } 01037 01038 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions 01039 * @{ 01040 */ 01041 01042 /** 01043 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). 01044 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr 01045 * @param DMA2Dx DMA2D Instance 01046 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 01047 * @retval None 01048 */ 01049 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) 01050 { 01051 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress); 01052 } 01053 01054 /** 01055 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits). 01056 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr 01057 * @param DMA2Dx DMA2D Instance 01058 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 01059 */ 01060 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) 01061 { 01062 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR)); 01063 } 01064 01065 /** 01066 * @brief Enable DMA2D foreground CLUT loading. 01067 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad 01068 * @param DMA2Dx DMA2D Instance 01069 * @retval None 01070 */ 01071 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) 01072 { 01073 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START); 01074 } 01075 01076 /** 01077 * @brief Indicate if DMA2D foreground CLUT loading is enabled. 01078 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad 01079 * @param DMA2Dx DMA2D Instance 01080 * @retval State of bit (1 or 0). 01081 */ 01082 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) 01083 { 01084 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL); 01085 } 01086 01087 /** 01088 * @brief Set DMA2D foreground color mode. 01089 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode 01090 * @param DMA2Dx DMA2D Instance 01091 * @param ColorMode This parameter can be one of the following values: 01092 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 01093 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 01094 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 01095 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 01096 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 01097 * @arg @ref LL_DMA2D_INPUT_MODE_L8 01098 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 01099 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 01100 * @arg @ref LL_DMA2D_INPUT_MODE_L4 01101 * @arg @ref LL_DMA2D_INPUT_MODE_A8 01102 * @arg @ref LL_DMA2D_INPUT_MODE_A4 01103 * @retval None 01104 */ 01105 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) 01106 { 01107 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode); 01108 } 01109 01110 /** 01111 * @brief Return DMA2D foreground color mode. 01112 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode 01113 * @param DMA2Dx DMA2D Instance 01114 * @retval Returned value can be one of the following values: 01115 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 01116 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 01117 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 01118 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 01119 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 01120 * @arg @ref LL_DMA2D_INPUT_MODE_L8 01121 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 01122 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 01123 * @arg @ref LL_DMA2D_INPUT_MODE_L4 01124 * @arg @ref LL_DMA2D_INPUT_MODE_A8 01125 * @arg @ref LL_DMA2D_INPUT_MODE_A4 01126 */ 01127 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) 01128 { 01129 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM)); 01130 } 01131 01132 /** 01133 * @brief Set DMA2D foreground alpha mode. 01134 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode 01135 * @param DMA2Dx DMA2D Instance 01136 * @param AphaMode This parameter can be one of the following values: 01137 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF 01138 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE 01139 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE 01140 * @retval None 01141 */ 01142 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) 01143 { 01144 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode); 01145 } 01146 01147 /** 01148 * @brief Return DMA2D foreground alpha mode. 01149 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode 01150 * @param DMA2Dx DMA2D Instance 01151 * @retval Returned value can be one of the following values: 01152 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF 01153 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE 01154 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE 01155 */ 01156 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) 01157 { 01158 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM)); 01159 } 01160 01161 /** 01162 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). 01163 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha 01164 * @param DMA2Dx DMA2D Instance 01165 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF 01166 * @retval None 01167 */ 01168 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) 01169 { 01170 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos)); 01171 } 01172 01173 /** 01174 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits). 01175 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha 01176 * @param DMA2Dx DMA2D Instance 01177 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF 01178 */ 01179 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) 01180 { 01181 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos); 01182 } 01183 01184 /** 01185 * @brief Set DMA2D foreground Red Blue swap mode. 01186 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode 01187 * @param DMA2Dx DMA2D Instance 01188 * @param RBSwapMode This parameter can be one of the following values: 01189 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 01190 * @arg @ref LL_DMA2D_RB_MODE_SWAP 01191 * @retval None 01192 */ 01193 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) 01194 { 01195 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode); 01196 } 01197 01198 /** 01199 * @brief Return DMA2D foreground Red Blue swap mode. 01200 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode 01201 * @param DMA2Dx DMA2D Instance 01202 * @retval Returned value can be one of the following values: 01203 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 01204 * @arg @ref LL_DMA2D_RB_MODE_SWAP 01205 */ 01206 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) 01207 { 01208 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS)); 01209 } 01210 01211 /** 01212 * @brief Set DMA2D foreground alpha inversion mode. 01213 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode 01214 * @param DMA2Dx DMA2D Instance 01215 * @param AlphaInversionMode This parameter can be one of the following values: 01216 * @arg @ref LL_DMA2D_ALPHA_REGULAR 01217 * @arg @ref LL_DMA2D_ALPHA_INVERTED 01218 * @retval None 01219 */ 01220 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) 01221 { 01222 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode); 01223 } 01224 01225 /** 01226 * @brief Return DMA2D foreground alpha inversion mode. 01227 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode 01228 * @param DMA2Dx DMA2D Instance 01229 * @retval Returned value can be one of the following values: 01230 * @arg @ref LL_DMA2D_ALPHA_REGULAR 01231 * @arg @ref LL_DMA2D_ALPHA_INVERTED 01232 */ 01233 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) 01234 { 01235 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI)); 01236 } 01237 01238 /** 01239 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). 01240 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset 01241 * @param DMA2Dx DMA2D Instance 01242 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF 01243 * @retval None 01244 */ 01245 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) 01246 { 01247 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset); 01248 } 01249 01250 /** 01251 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits). 01252 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset 01253 * @param DMA2Dx DMA2D Instance 01254 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF 01255 */ 01256 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) 01257 { 01258 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO)); 01259 } 01260 01261 /** 01262 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits). 01263 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor 01264 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor 01265 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor 01266 * @param DMA2Dx DMA2D Instance 01267 * @param Red Value between Min_Data=0 and Max_Data=0xFF 01268 * @param Green Value between Min_Data=0 and Max_Data=0xFF 01269 * @param Blue Value between Min_Data=0 and Max_Data=0xFF 01270 * @retval None 01271 */ 01272 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) 01273 { 01274 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \ 01275 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue)); 01276 } 01277 01278 /** 01279 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). 01280 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor 01281 * @param DMA2Dx DMA2D Instance 01282 * @param Red Value between Min_Data=0 and Max_Data=0xFF 01283 * @retval None 01284 */ 01285 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) 01286 { 01287 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos)); 01288 } 01289 01290 /** 01291 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits). 01292 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor 01293 * @param DMA2Dx DMA2D Instance 01294 * @retval Red color value between Min_Data=0 and Max_Data=0xFF 01295 */ 01296 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) 01297 { 01298 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos); 01299 } 01300 01301 /** 01302 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). 01303 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor 01304 * @param DMA2Dx DMA2D Instance 01305 * @param Green Value between Min_Data=0 and Max_Data=0xFF 01306 * @retval None 01307 */ 01308 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) 01309 { 01310 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos)); 01311 } 01312 01313 /** 01314 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits). 01315 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor 01316 * @param DMA2Dx DMA2D Instance 01317 * @retval Green color value between Min_Data=0 and Max_Data=0xFF 01318 */ 01319 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) 01320 { 01321 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos); 01322 } 01323 01324 /** 01325 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). 01326 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor 01327 * @param DMA2Dx DMA2D Instance 01328 * @param Blue Value between Min_Data=0 and Max_Data=0xFF 01329 * @retval None 01330 */ 01331 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) 01332 { 01333 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue); 01334 } 01335 01336 /** 01337 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits). 01338 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor 01339 * @param DMA2Dx DMA2D Instance 01340 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF 01341 */ 01342 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) 01343 { 01344 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE)); 01345 } 01346 01347 /** 01348 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). 01349 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr 01350 * @param DMA2Dx DMA2D Instance 01351 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 01352 * @retval None 01353 */ 01354 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) 01355 { 01356 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress); 01357 } 01358 01359 /** 01360 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits). 01361 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr 01362 * @param DMA2Dx DMA2D Instance 01363 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 01364 */ 01365 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) 01366 { 01367 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR)); 01368 } 01369 01370 /** 01371 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). 01372 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize 01373 * @param DMA2Dx DMA2D Instance 01374 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF 01375 * @retval None 01376 */ 01377 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) 01378 { 01379 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos)); 01380 } 01381 01382 /** 01383 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits). 01384 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize 01385 * @param DMA2Dx DMA2D Instance 01386 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF 01387 */ 01388 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) 01389 { 01390 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos); 01391 } 01392 01393 /** 01394 * @brief Set DMA2D foreground CLUT color mode. 01395 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode 01396 * @param DMA2Dx DMA2D Instance 01397 * @param CLUTColorMode This parameter can be one of the following values: 01398 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 01399 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 01400 * @retval None 01401 */ 01402 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) 01403 { 01404 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode); 01405 } 01406 01407 /** 01408 * @brief Return DMA2D foreground CLUT color mode. 01409 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode 01410 * @param DMA2Dx DMA2D Instance 01411 * @retval Returned value can be one of the following values: 01412 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 01413 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 01414 */ 01415 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) 01416 { 01417 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM)); 01418 } 01419 01420 /** 01421 * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). 01422 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling 01423 * @param DMA2Dx DMA2D Instance 01424 * @param ChromaSubSampling This parameter can be one of the following values: 01425 * @arg @ref LL_DMA2D_CSS_444 01426 * @arg @ref LL_DMA2D_CSS_422 01427 * @arg @ref LL_DMA2D_CSS_420 01428 * @retval None 01429 */ 01430 __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling) 01431 { 01432 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling); 01433 } 01434 01435 /** 01436 * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode). 01437 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling 01438 * @param DMA2Dx DMA2D Instance 01439 * @retval Returned value can be one of the following values: 01440 * @arg @ref LL_DMA2D_CSS_444 01441 * @arg @ref LL_DMA2D_CSS_422 01442 * @arg @ref LL_DMA2D_CSS_420 01443 */ 01444 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx) 01445 { 01446 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS)); 01447 } 01448 /** 01449 * @} 01450 */ 01451 01452 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions 01453 * @{ 01454 */ 01455 01456 /** 01457 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits). 01458 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr 01459 * @param DMA2Dx DMA2D Instance 01460 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 01461 * @retval None 01462 */ 01463 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress) 01464 { 01465 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress); 01466 } 01467 01468 /** 01469 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits). 01470 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr 01471 * @param DMA2Dx DMA2D Instance 01472 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 01473 */ 01474 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx) 01475 { 01476 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR)); 01477 } 01478 01479 /** 01480 * @brief Enable DMA2D background CLUT loading. 01481 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad 01482 * @param DMA2Dx DMA2D Instance 01483 * @retval None 01484 */ 01485 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx) 01486 { 01487 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START); 01488 } 01489 01490 /** 01491 * @brief Indicate if DMA2D background CLUT loading is enabled. 01492 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad 01493 * @param DMA2Dx DMA2D Instance 01494 * @retval State of bit (1 or 0). 01495 */ 01496 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx) 01497 { 01498 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL); 01499 } 01500 01501 /** 01502 * @brief Set DMA2D background color mode. 01503 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode 01504 * @param DMA2Dx DMA2D Instance 01505 * @param ColorMode This parameter can be one of the following values: 01506 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 01507 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 01508 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 01509 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 01510 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 01511 * @arg @ref LL_DMA2D_INPUT_MODE_L8 01512 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 01513 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 01514 * @arg @ref LL_DMA2D_INPUT_MODE_L4 01515 * @arg @ref LL_DMA2D_INPUT_MODE_A8 01516 * @arg @ref LL_DMA2D_INPUT_MODE_A4 01517 * @retval None 01518 */ 01519 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode) 01520 { 01521 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode); 01522 } 01523 01524 /** 01525 * @brief Return DMA2D background color mode. 01526 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode 01527 * @param DMA2Dx DMA2D Instance 01528 * @retval Returned value can be one of the following values: 01529 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888 01530 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888 01531 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565 01532 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555 01533 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444 01534 * @arg @ref LL_DMA2D_INPUT_MODE_L8 01535 * @arg @ref LL_DMA2D_INPUT_MODE_AL44 01536 * @arg @ref LL_DMA2D_INPUT_MODE_AL88 01537 * @arg @ref LL_DMA2D_INPUT_MODE_L4 01538 * @arg @ref LL_DMA2D_INPUT_MODE_A8 01539 * @arg @ref LL_DMA2D_INPUT_MODE_A4 01540 */ 01541 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx) 01542 { 01543 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM)); 01544 } 01545 01546 /** 01547 * @brief Set DMA2D background alpha mode. 01548 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode 01549 * @param DMA2Dx DMA2D Instance 01550 * @param AphaMode This parameter can be one of the following values: 01551 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF 01552 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE 01553 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE 01554 * @retval None 01555 */ 01556 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode) 01557 { 01558 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode); 01559 } 01560 01561 /** 01562 * @brief Return DMA2D background alpha mode. 01563 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode 01564 * @param DMA2Dx DMA2D Instance 01565 * @retval Returned value can be one of the following values: 01566 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF 01567 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE 01568 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE 01569 */ 01570 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx) 01571 { 01572 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM)); 01573 } 01574 01575 /** 01576 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits). 01577 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha 01578 * @param DMA2Dx DMA2D Instance 01579 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF 01580 * @retval None 01581 */ 01582 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha) 01583 { 01584 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos)); 01585 } 01586 01587 /** 01588 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits). 01589 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha 01590 * @param DMA2Dx DMA2D Instance 01591 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF 01592 */ 01593 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx) 01594 { 01595 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos); 01596 } 01597 01598 /** 01599 * @brief Set DMA2D background Red Blue swap mode. 01600 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode 01601 * @param DMA2Dx DMA2D Instance 01602 * @param RBSwapMode This parameter can be one of the following values: 01603 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 01604 * @arg @ref LL_DMA2D_RB_MODE_SWAP 01605 * @retval None 01606 */ 01607 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode) 01608 { 01609 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode); 01610 } 01611 01612 /** 01613 * @brief Return DMA2D background Red Blue swap mode. 01614 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode 01615 * @param DMA2Dx DMA2D Instance 01616 * @retval Returned value can be one of the following values: 01617 * @arg @ref LL_DMA2D_RB_MODE_REGULAR 01618 * @arg @ref LL_DMA2D_RB_MODE_SWAP 01619 */ 01620 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx) 01621 { 01622 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS)); 01623 } 01624 01625 /** 01626 * @brief Set DMA2D background alpha inversion mode. 01627 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode 01628 * @param DMA2Dx DMA2D Instance 01629 * @param AlphaInversionMode This parameter can be one of the following values: 01630 * @arg @ref LL_DMA2D_ALPHA_REGULAR 01631 * @arg @ref LL_DMA2D_ALPHA_INVERTED 01632 * @retval None 01633 */ 01634 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode) 01635 { 01636 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode); 01637 } 01638 01639 /** 01640 * @brief Return DMA2D background alpha inversion mode. 01641 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode 01642 * @param DMA2Dx DMA2D Instance 01643 * @retval Returned value can be one of the following values: 01644 * @arg @ref LL_DMA2D_ALPHA_REGULAR 01645 * @arg @ref LL_DMA2D_ALPHA_INVERTED 01646 */ 01647 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx) 01648 { 01649 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI)); 01650 } 01651 01652 /** 01653 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits). 01654 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset 01655 * @param DMA2Dx DMA2D Instance 01656 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF 01657 * @retval None 01658 */ 01659 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset) 01660 { 01661 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset); 01662 } 01663 01664 /** 01665 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits). 01666 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset 01667 * @param DMA2Dx DMA2D Instance 01668 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF 01669 */ 01670 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx) 01671 { 01672 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO)); 01673 } 01674 01675 /** 01676 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits). 01677 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor 01678 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor 01679 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor 01680 * @param DMA2Dx DMA2D Instance 01681 * @param Red Value between Min_Data=0 and Max_Data=0xFF 01682 * @param Green Value between Min_Data=0 and Max_Data=0xFF 01683 * @param Blue Value between Min_Data=0 and Max_Data=0xFF 01684 * @retval None 01685 */ 01686 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue) 01687 { 01688 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \ 01689 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue)); 01690 } 01691 01692 /** 01693 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits). 01694 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor 01695 * @param DMA2Dx DMA2D Instance 01696 * @param Red Value between Min_Data=0 and Max_Data=0xFF 01697 * @retval None 01698 */ 01699 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red) 01700 { 01701 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos)); 01702 } 01703 01704 /** 01705 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits). 01706 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor 01707 * @param DMA2Dx DMA2D Instance 01708 * @retval Red color value between Min_Data=0 and Max_Data=0xFF 01709 */ 01710 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx) 01711 { 01712 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos); 01713 } 01714 01715 /** 01716 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits). 01717 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor 01718 * @param DMA2Dx DMA2D Instance 01719 * @param Green Value between Min_Data=0 and Max_Data=0xFF 01720 * @retval None 01721 */ 01722 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green) 01723 { 01724 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos)); 01725 } 01726 01727 /** 01728 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits). 01729 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor 01730 * @param DMA2Dx DMA2D Instance 01731 * @retval Green color value between Min_Data=0 and Max_Data=0xFF 01732 */ 01733 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx) 01734 { 01735 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos); 01736 } 01737 01738 /** 01739 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits). 01740 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor 01741 * @param DMA2Dx DMA2D Instance 01742 * @param Blue Value between Min_Data=0 and Max_Data=0xFF 01743 * @retval None 01744 */ 01745 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue) 01746 { 01747 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue); 01748 } 01749 01750 /** 01751 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits). 01752 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor 01753 * @param DMA2Dx DMA2D Instance 01754 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF 01755 */ 01756 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx) 01757 { 01758 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE)); 01759 } 01760 01761 /** 01762 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). 01763 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr 01764 * @param DMA2Dx DMA2D Instance 01765 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF 01766 * @retval None 01767 */ 01768 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress) 01769 { 01770 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress); 01771 } 01772 01773 /** 01774 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits). 01775 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr 01776 * @param DMA2Dx DMA2D Instance 01777 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF 01778 */ 01779 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx) 01780 { 01781 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR)); 01782 } 01783 01784 /** 01785 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). 01786 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize 01787 * @param DMA2Dx DMA2D Instance 01788 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF 01789 * @retval None 01790 */ 01791 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize) 01792 { 01793 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos)); 01794 } 01795 01796 /** 01797 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits). 01798 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize 01799 * @param DMA2Dx DMA2D Instance 01800 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF 01801 */ 01802 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx) 01803 { 01804 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos); 01805 } 01806 01807 /** 01808 * @brief Set DMA2D background CLUT color mode. 01809 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode 01810 * @param DMA2Dx DMA2D Instance 01811 * @param CLUTColorMode This parameter can be one of the following values: 01812 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 01813 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 01814 * @retval None 01815 */ 01816 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode) 01817 { 01818 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode); 01819 } 01820 01821 /** 01822 * @brief Return DMA2D background CLUT color mode. 01823 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode 01824 * @param DMA2Dx DMA2D Instance 01825 * @retval Returned value can be one of the following values: 01826 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 01827 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888 01828 */ 01829 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx) 01830 { 01831 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM)); 01832 } 01833 01834 /** 01835 * @} 01836 */ 01837 01838 /** 01839 * @} 01840 */ 01841 01842 01843 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management 01844 * @{ 01845 */ 01846 01847 /** 01848 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not 01849 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE 01850 * @param DMA2Dx DMA2D Instance 01851 * @retval State of bit (1 or 0). 01852 */ 01853 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx) 01854 { 01855 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL); 01856 } 01857 01858 /** 01859 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not 01860 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC 01861 * @param DMA2Dx DMA2D Instance 01862 * @retval State of bit (1 or 0). 01863 */ 01864 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx) 01865 { 01866 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL); 01867 } 01868 01869 /** 01870 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not 01871 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE 01872 * @param DMA2Dx DMA2D Instance 01873 * @retval State of bit (1 or 0). 01874 */ 01875 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx) 01876 { 01877 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL); 01878 } 01879 01880 /** 01881 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not 01882 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW 01883 * @param DMA2Dx DMA2D Instance 01884 * @retval State of bit (1 or 0). 01885 */ 01886 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx) 01887 { 01888 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL); 01889 } 01890 01891 /** 01892 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not 01893 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC 01894 * @param DMA2Dx DMA2D Instance 01895 * @retval State of bit (1 or 0). 01896 */ 01897 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx) 01898 { 01899 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL); 01900 } 01901 01902 /** 01903 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not 01904 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE 01905 * @param DMA2Dx DMA2D Instance 01906 * @retval State of bit (1 or 0). 01907 */ 01908 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx) 01909 { 01910 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL); 01911 } 01912 01913 /** 01914 * @brief Clear DMA2D Configuration Error Interrupt Flag 01915 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE 01916 * @param DMA2Dx DMA2D Instance 01917 * @retval None 01918 */ 01919 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx) 01920 { 01921 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF); 01922 } 01923 01924 /** 01925 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag 01926 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC 01927 * @param DMA2Dx DMA2D Instance 01928 * @retval None 01929 */ 01930 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx) 01931 { 01932 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF); 01933 } 01934 01935 /** 01936 * @brief Clear DMA2D CLUT Access Error Interrupt Flag 01937 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE 01938 * @param DMA2Dx DMA2D Instance 01939 * @retval None 01940 */ 01941 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx) 01942 { 01943 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF); 01944 } 01945 01946 /** 01947 * @brief Clear DMA2D Transfer Watermark Interrupt Flag 01948 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW 01949 * @param DMA2Dx DMA2D Instance 01950 * @retval None 01951 */ 01952 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx) 01953 { 01954 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF); 01955 } 01956 01957 /** 01958 * @brief Clear DMA2D Transfer Complete Interrupt Flag 01959 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC 01960 * @param DMA2Dx DMA2D Instance 01961 * @retval None 01962 */ 01963 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx) 01964 { 01965 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF); 01966 } 01967 01968 /** 01969 * @brief Clear DMA2D Transfer Error Interrupt Flag 01970 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE 01971 * @param DMA2Dx DMA2D Instance 01972 * @retval None 01973 */ 01974 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx) 01975 { 01976 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF); 01977 } 01978 01979 /** 01980 * @} 01981 */ 01982 01983 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management 01984 * @{ 01985 */ 01986 01987 /** 01988 * @brief Enable Configuration Error Interrupt 01989 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE 01990 * @param DMA2Dx DMA2D Instance 01991 * @retval None 01992 */ 01993 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx) 01994 { 01995 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); 01996 } 01997 01998 /** 01999 * @brief Enable CLUT Transfer Complete Interrupt 02000 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC 02001 * @param DMA2Dx DMA2D Instance 02002 * @retval None 02003 */ 02004 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx) 02005 { 02006 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); 02007 } 02008 02009 /** 02010 * @brief Enable CLUT Access Error Interrupt 02011 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE 02012 * @param DMA2Dx DMA2D Instance 02013 * @retval None 02014 */ 02015 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx) 02016 { 02017 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); 02018 } 02019 02020 /** 02021 * @brief Enable Transfer Watermark Interrupt 02022 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW 02023 * @param DMA2Dx DMA2D Instance 02024 * @retval None 02025 */ 02026 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx) 02027 { 02028 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); 02029 } 02030 02031 /** 02032 * @brief Enable Transfer Complete Interrupt 02033 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC 02034 * @param DMA2Dx DMA2D Instance 02035 * @retval None 02036 */ 02037 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx) 02038 { 02039 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); 02040 } 02041 02042 /** 02043 * @brief Enable Transfer Error Interrupt 02044 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE 02045 * @param DMA2Dx DMA2D Instance 02046 * @retval None 02047 */ 02048 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx) 02049 { 02050 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); 02051 } 02052 02053 /** 02054 * @brief Disable Configuration Error Interrupt 02055 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE 02056 * @param DMA2Dx DMA2D Instance 02057 * @retval None 02058 */ 02059 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx) 02060 { 02061 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE); 02062 } 02063 02064 /** 02065 * @brief Disable CLUT Transfer Complete Interrupt 02066 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC 02067 * @param DMA2Dx DMA2D Instance 02068 * @retval None 02069 */ 02070 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx) 02071 { 02072 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE); 02073 } 02074 02075 /** 02076 * @brief Disable CLUT Access Error Interrupt 02077 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE 02078 * @param DMA2Dx DMA2D Instance 02079 * @retval None 02080 */ 02081 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx) 02082 { 02083 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE); 02084 } 02085 02086 /** 02087 * @brief Disable Transfer Watermark Interrupt 02088 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW 02089 * @param DMA2Dx DMA2D Instance 02090 * @retval None 02091 */ 02092 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx) 02093 { 02094 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE); 02095 } 02096 02097 /** 02098 * @brief Disable Transfer Complete Interrupt 02099 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC 02100 * @param DMA2Dx DMA2D Instance 02101 * @retval None 02102 */ 02103 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx) 02104 { 02105 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE); 02106 } 02107 02108 /** 02109 * @brief Disable Transfer Error Interrupt 02110 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE 02111 * @param DMA2Dx DMA2D Instance 02112 * @retval None 02113 */ 02114 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx) 02115 { 02116 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE); 02117 } 02118 02119 /** 02120 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled. 02121 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE 02122 * @param DMA2Dx DMA2D Instance 02123 * @retval State of bit (1 or 0). 02124 */ 02125 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx) 02126 { 02127 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL); 02128 } 02129 02130 /** 02131 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled. 02132 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC 02133 * @param DMA2Dx DMA2D Instance 02134 * @retval State of bit (1 or 0). 02135 */ 02136 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx) 02137 { 02138 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL); 02139 } 02140 02141 /** 02142 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled. 02143 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE 02144 * @param DMA2Dx DMA2D Instance 02145 * @retval State of bit (1 or 0). 02146 */ 02147 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx) 02148 { 02149 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL); 02150 } 02151 02152 /** 02153 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled. 02154 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW 02155 * @param DMA2Dx DMA2D Instance 02156 * @retval State of bit (1 or 0). 02157 */ 02158 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx) 02159 { 02160 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL); 02161 } 02162 02163 /** 02164 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled. 02165 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC 02166 * @param DMA2Dx DMA2D Instance 02167 * @retval State of bit (1 or 0). 02168 */ 02169 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx) 02170 { 02171 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL); 02172 } 02173 02174 /** 02175 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled. 02176 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE 02177 * @param DMA2Dx DMA2D Instance 02178 * @retval State of bit (1 or 0). 02179 */ 02180 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx) 02181 { 02182 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL); 02183 } 02184 02185 02186 02187 /** 02188 * @} 02189 */ 02190 02191 #if defined(USE_FULL_LL_DRIVER) 02192 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions 02193 * @{ 02194 */ 02195 02196 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx); 02197 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct); 02198 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct); 02199 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx); 02200 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg); 02201 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct); 02202 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); 02203 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); 02204 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); 02205 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode); 02206 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines); 02207 02208 /** 02209 * @} 02210 */ 02211 #endif /* USE_FULL_LL_DRIVER */ 02212 02213 /** 02214 * @} 02215 */ 02216 02217 /** 02218 * @} 02219 */ 02220 02221 #endif /* defined (DMA2D) */ 02222 02223 /** 02224 * @} 02225 */ 02226 02227 #ifdef __cplusplus 02228 } 02229 #endif 02230 02231 #endif /* STM32H7xx_LL_DMA2D_H */
1.7.6.1