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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_LL_DMA_H 00021 #define STM32H7xx_LL_DMA_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx.h" 00029 #include "stm32h7xx_ll_dmamux.h" 00030 00031 /** @addtogroup STM32H7xx_LL_Driver 00032 * @{ 00033 */ 00034 00035 #if defined (DMA1) || defined (DMA2) 00036 00037 /** @defgroup DMA_LL DMA 00038 * @{ 00039 */ 00040 00041 /* Private types -------------------------------------------------------------*/ 00042 /* Private variables ---------------------------------------------------------*/ 00043 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 00044 * @{ 00045 */ 00046 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ 00047 static const uint8_t LL_DMA_STR_OFFSET_TAB[] = 00048 { 00049 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 00050 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 00051 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 00052 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 00053 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 00054 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 00055 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 00056 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) 00057 }; 00058 00059 00060 /** 00061 * @} 00062 */ 00063 00064 /* Private macros ------------------------------------------------------------*/ 00065 00066 /** 00067 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel 00068 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. 00069 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. 00070 * @param __DMA_INSTANCE__ DMAx 00071 * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0). 00072 */ 00073 #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ 00074 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL) 00075 00076 /* Exported types ------------------------------------------------------------*/ 00077 #if defined(USE_FULL_LL_DRIVER) 00078 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 00079 * @{ 00080 */ 00081 typedef struct 00082 { 00083 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 00084 or as Source base address in case of memory to memory transfer direction. 00085 00086 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00087 00088 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 00089 or as Destination base address in case of memory to memory transfer direction. 00090 00091 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00092 00093 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00094 from memory to memory or from peripheral to memory. 00095 This parameter can be a value of @ref DMA_LL_EC_DIRECTION 00096 00097 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ 00098 00099 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 00100 This parameter can be a value of @ref DMA_LL_EC_MODE 00101 @note The circular buffer mode cannot be used if the memory to memory 00102 data transfer direction is configured on the selected Stream 00103 00104 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ 00105 00106 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 00107 is incremented or not. 00108 This parameter can be a value of @ref DMA_LL_EC_PERIPH 00109 00110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ 00111 00112 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 00113 is incremented or not. 00114 This parameter can be a value of @ref DMA_LL_EC_MEMORY 00115 00116 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ 00117 00118 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 00119 in case of memory to memory transfer direction. 00120 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 00121 00122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ 00123 00124 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 00125 in case of memory to memory transfer direction. 00126 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 00127 00128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ 00129 00130 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 00131 The data unit is equal to the source buffer configuration set in PeripheralSize 00132 or MemorySize parameters depending in the transfer direction. 00133 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 00134 00135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ 00136 00137 uint32_t PeriphRequest; /*!< Specifies the peripheral request. 00138 This parameter can be a value of @ref DMAMUX1_Request_selection 00139 00140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ 00141 00142 uint32_t Priority; /*!< Specifies the channel priority level. 00143 This parameter can be a value of @ref DMA_LL_EC_PRIORITY 00144 00145 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ 00146 00147 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 00148 This parameter can be a value of @ref DMA_LL_FIFOMODE 00149 @note The Direct mode (FIFO mode disabled) cannot be used if the 00150 memory-to-memory data transfer is configured on the selected stream 00151 00152 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ 00153 00154 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 00155 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD 00156 00157 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ 00158 00159 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 00160 It specifies the amount of data to be transferred in a single non interruptible 00161 transaction. 00162 This parameter can be a value of @ref DMA_LL_EC_MBURST 00163 @note The burst mode is possible only if the address Increment mode is enabled. 00164 00165 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ 00166 00167 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 00168 It specifies the amount of data to be transferred in a single non interruptible 00169 transaction. 00170 This parameter can be a value of @ref DMA_LL_EC_PBURST 00171 @note The burst mode is possible only if the address Increment mode is enabled. 00172 00173 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ 00174 00175 } LL_DMA_InitTypeDef; 00176 /** 00177 * @} 00178 */ 00179 #endif /*USE_FULL_LL_DRIVER*/ 00180 /* Exported constants --------------------------------------------------------*/ 00181 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 00182 * @{ 00183 */ 00184 00185 /** @defgroup DMA_LL_EC_STREAM STREAM 00186 * @{ 00187 */ 00188 #define LL_DMA_STREAM_0 0x00000000U 00189 #define LL_DMA_STREAM_1 0x00000001U 00190 #define LL_DMA_STREAM_2 0x00000002U 00191 #define LL_DMA_STREAM_3 0x00000003U 00192 #define LL_DMA_STREAM_4 0x00000004U 00193 #define LL_DMA_STREAM_5 0x00000005U 00194 #define LL_DMA_STREAM_6 0x00000006U 00195 #define LL_DMA_STREAM_7 0x00000007U 00196 #define LL_DMA_STREAM_ALL 0xFFFF0000U 00197 /** 00198 * @} 00199 */ 00200 00201 00202 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 00203 * @{ 00204 */ 00205 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00206 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ 00207 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup DMA_LL_EC_MODE MODE 00213 * @{ 00214 */ 00215 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 00216 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ 00217 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ 00218 /** 00219 * @} 00220 */ 00221 00222 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE 00223 * @{ 00224 */ 00225 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ 00226 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup DMA_LL_EC_PERIPH PERIPH 00232 * @{ 00233 */ 00234 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 00235 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ 00236 /** 00237 * @} 00238 */ 00239 00240 /** @defgroup DMA_LL_EC_MEMORY MEMORY 00241 * @{ 00242 */ 00243 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 00244 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ 00245 /** 00246 * @} 00247 */ 00248 00249 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 00250 * @{ 00251 */ 00252 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 00253 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 00254 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 00255 /** 00256 * @} 00257 */ 00258 00259 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 00260 * @{ 00261 */ 00262 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 00263 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 00264 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ 00265 /** 00266 * @} 00267 */ 00268 00269 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE 00270 * @{ 00271 */ 00272 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ 00273 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ 00274 /** 00275 * @} 00276 */ 00277 00278 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 00279 * @{ 00280 */ 00281 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 00282 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ 00283 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ 00284 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ 00285 /** 00286 * @} 00287 */ 00288 00289 00290 /** @defgroup DMA_LL_EC_MBURST MBURST 00291 * @{ 00292 */ 00293 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ 00294 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ 00295 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ 00296 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ 00297 /** 00298 * @} 00299 */ 00300 00301 /** @defgroup DMA_LL_EC_PBURST PBURST 00302 * @{ 00303 */ 00304 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ 00305 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ 00306 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ 00307 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ 00308 /** 00309 * @} 00310 */ 00311 00312 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE 00313 * @{ 00314 */ 00315 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ 00316 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ 00317 /** 00318 * @} 00319 */ 00320 00321 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 00322 * @{ 00323 */ 00324 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ 00325 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ 00326 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ 00327 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ 00328 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ 00329 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ 00330 /** 00331 * @} 00332 */ 00333 00334 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD 00335 * @{ 00336 */ 00337 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 00338 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ 00339 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ 00340 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ 00341 /** 00342 * @} 00343 */ 00344 00345 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 00346 * @{ 00347 */ 00348 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ 00349 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ 00350 /** 00351 * @} 00352 */ 00353 00354 /** 00355 * @} 00356 */ 00357 00358 /* Exported macro ------------------------------------------------------------*/ 00359 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 00360 * @{ 00361 */ 00362 00363 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 00364 * @{ 00365 */ 00366 /** 00367 * @brief Write a value in DMA register 00368 * @param __INSTANCE__ DMA Instance 00369 * @param __REG__ Register to be written 00370 * @param __VALUE__ Value to be written in the register 00371 * @retval None 00372 */ 00373 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 00374 00375 /** 00376 * @brief Read a value in DMA register 00377 * @param __INSTANCE__ DMA Instance 00378 * @param __REG__ Register to be read 00379 * @retval Register value 00380 */ 00381 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00382 /** 00383 * @} 00384 */ 00385 00386 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy 00387 * @{ 00388 */ 00389 /** 00390 * @brief Convert DMAx_Streamy into DMAx 00391 * @param __STREAM_INSTANCE__ DMAx_Streamy 00392 * @retval DMAx 00393 */ 00394 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ 00395 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) 00396 00397 /** 00398 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y 00399 * @param __STREAM_INSTANCE__ DMAx_Streamy 00400 * @retval LL_DMA_STREAM_y 00401 */ 00402 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ 00403 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ 00404 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ 00405 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ 00406 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ 00407 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ 00408 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ 00409 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ 00410 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ 00411 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ 00412 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ 00413 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ 00414 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ 00415 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ 00416 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ 00417 LL_DMA_STREAM_7) 00418 00419 /** 00420 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy 00421 * @param __DMA_INSTANCE__ DMAx 00422 * @param __STREAM__ LL_DMA_STREAM_y 00423 * @retval DMAx_Streamy 00424 */ 00425 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ 00426 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ 00427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ 00428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ 00429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ 00430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ 00431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ 00432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ 00433 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ 00434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ 00435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ 00436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ 00437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ 00438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ 00439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ 00440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ 00441 DMA2_Stream7) 00442 00443 /** 00444 * @} 00445 */ 00446 00447 /** 00448 * @} 00449 */ 00450 00451 00452 /* Exported functions --------------------------------------------------------*/ 00453 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 00454 * @{ 00455 */ 00456 00457 /** @defgroup DMA_LL_EF_Configuration Configuration 00458 * @{ 00459 */ 00460 /** 00461 * @brief Enable DMA stream. 00462 * @rmtoll CR EN LL_DMA_EnableStream 00463 * @param DMAx DMAx Instance 00464 * @param Stream This parameter can be one of the following values: 00465 * @arg @ref LL_DMA_STREAM_0 00466 * @arg @ref LL_DMA_STREAM_1 00467 * @arg @ref LL_DMA_STREAM_2 00468 * @arg @ref LL_DMA_STREAM_3 00469 * @arg @ref LL_DMA_STREAM_4 00470 * @arg @ref LL_DMA_STREAM_5 00471 * @arg @ref LL_DMA_STREAM_6 00472 * @arg @ref LL_DMA_STREAM_7 00473 * @retval None 00474 */ 00475 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) 00476 { 00477 uint32_t dma_base_addr = (uint32_t)DMAx; 00478 00479 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); 00480 } 00481 00482 /** 00483 * @brief Disable DMA stream. 00484 * @rmtoll CR EN LL_DMA_DisableStream 00485 * @param DMAx DMAx Instance 00486 * @param Stream This parameter can be one of the following values: 00487 * @arg @ref LL_DMA_STREAM_0 00488 * @arg @ref LL_DMA_STREAM_1 00489 * @arg @ref LL_DMA_STREAM_2 00490 * @arg @ref LL_DMA_STREAM_3 00491 * @arg @ref LL_DMA_STREAM_4 00492 * @arg @ref LL_DMA_STREAM_5 00493 * @arg @ref LL_DMA_STREAM_6 00494 * @arg @ref LL_DMA_STREAM_7 00495 * @retval None 00496 */ 00497 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) 00498 { 00499 uint32_t dma_base_addr = (uint32_t)DMAx; 00500 00501 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN); 00502 } 00503 00504 /** 00505 * @brief Check if DMA stream is enabled or disabled. 00506 * @rmtoll CR EN LL_DMA_IsEnabledStream 00507 * @param DMAx DMAx Instance 00508 * @param Stream This parameter can be one of the following values: 00509 * @arg @ref LL_DMA_STREAM_0 00510 * @arg @ref LL_DMA_STREAM_1 00511 * @arg @ref LL_DMA_STREAM_2 00512 * @arg @ref LL_DMA_STREAM_3 00513 * @arg @ref LL_DMA_STREAM_4 00514 * @arg @ref LL_DMA_STREAM_5 00515 * @arg @ref LL_DMA_STREAM_6 00516 * @arg @ref LL_DMA_STREAM_7 00517 * @retval State of bit (1 or 0). 00518 */ 00519 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) 00520 { 00521 uint32_t dma_base_addr = (uint32_t)DMAx; 00522 00523 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL); 00524 } 00525 00526 /** 00527 * @brief Configure all parameters linked to DMA transfer. 00528 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n 00529 * CR CIRC LL_DMA_ConfigTransfer\n 00530 * CR PINC LL_DMA_ConfigTransfer\n 00531 * CR MINC LL_DMA_ConfigTransfer\n 00532 * CR PSIZE LL_DMA_ConfigTransfer\n 00533 * CR MSIZE LL_DMA_ConfigTransfer\n 00534 * CR PL LL_DMA_ConfigTransfer\n 00535 * CR PFCTRL LL_DMA_ConfigTransfer 00536 * @param DMAx DMAx Instance 00537 * @param Stream This parameter can be one of the following values: 00538 * @arg @ref LL_DMA_STREAM_0 00539 * @arg @ref LL_DMA_STREAM_1 00540 * @arg @ref LL_DMA_STREAM_2 00541 * @arg @ref LL_DMA_STREAM_3 00542 * @arg @ref LL_DMA_STREAM_4 00543 * @arg @ref LL_DMA_STREAM_5 00544 * @arg @ref LL_DMA_STREAM_6 00545 * @arg @ref LL_DMA_STREAM_7 00546 * @param Configuration This parameter must be a combination of all the following values: 00547 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00548 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL 00549 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 00550 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 00551 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 00552 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 00553 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 00554 *@retval None 00555 */ 00556 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) 00557 { 00558 uint32_t dma_base_addr = (uint32_t)DMAx; 00559 00560 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, 00561 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, 00562 Configuration); 00563 } 00564 00565 /** 00566 * @brief Set Data transfer direction (read from peripheral or from memory). 00567 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection 00568 * @param DMAx DMAx Instance 00569 * @param Stream This parameter can be one of the following values: 00570 * @arg @ref LL_DMA_STREAM_0 00571 * @arg @ref LL_DMA_STREAM_1 00572 * @arg @ref LL_DMA_STREAM_2 00573 * @arg @ref LL_DMA_STREAM_3 00574 * @arg @ref LL_DMA_STREAM_4 00575 * @arg @ref LL_DMA_STREAM_5 00576 * @arg @ref LL_DMA_STREAM_6 00577 * @arg @ref LL_DMA_STREAM_7 00578 * @param Direction This parameter can be one of the following values: 00579 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00580 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00581 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00582 * @retval None 00583 */ 00584 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) 00585 { 00586 uint32_t dma_base_addr = (uint32_t)DMAx; 00587 00588 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction); 00589 } 00590 00591 /** 00592 * @brief Get Data transfer direction (read from peripheral or from memory). 00593 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection 00594 * @param DMAx DMAx Instance 00595 * @param Stream This parameter can be one of the following values: 00596 * @arg @ref LL_DMA_STREAM_0 00597 * @arg @ref LL_DMA_STREAM_1 00598 * @arg @ref LL_DMA_STREAM_2 00599 * @arg @ref LL_DMA_STREAM_3 00600 * @arg @ref LL_DMA_STREAM_4 00601 * @arg @ref LL_DMA_STREAM_5 00602 * @arg @ref LL_DMA_STREAM_6 00603 * @arg @ref LL_DMA_STREAM_7 00604 * @retval Returned value can be one of the following values: 00605 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00606 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00607 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00608 */ 00609 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) 00610 { 00611 uint32_t dma_base_addr = (uint32_t)DMAx; 00612 00613 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR)); 00614 } 00615 00616 /** 00617 * @brief Set DMA mode normal, circular or peripheral flow control. 00618 * @rmtoll CR CIRC LL_DMA_SetMode\n 00619 * CR PFCTRL LL_DMA_SetMode 00620 * @param DMAx DMAx Instance 00621 * @param Stream This parameter can be one of the following values: 00622 * @arg @ref LL_DMA_STREAM_0 00623 * @arg @ref LL_DMA_STREAM_1 00624 * @arg @ref LL_DMA_STREAM_2 00625 * @arg @ref LL_DMA_STREAM_3 00626 * @arg @ref LL_DMA_STREAM_4 00627 * @arg @ref LL_DMA_STREAM_5 00628 * @arg @ref LL_DMA_STREAM_6 00629 * @arg @ref LL_DMA_STREAM_7 00630 * @param Mode This parameter can be one of the following values: 00631 * @arg @ref LL_DMA_MODE_NORMAL 00632 * @arg @ref LL_DMA_MODE_CIRCULAR 00633 * @arg @ref LL_DMA_MODE_PFCTRL 00634 * @retval None 00635 */ 00636 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) 00637 { 00638 uint32_t dma_base_addr = (uint32_t)DMAx; 00639 00640 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); 00641 } 00642 00643 /** 00644 * @brief Get DMA mode normal, circular or peripheral flow control. 00645 * @rmtoll CR CIRC LL_DMA_GetMode\n 00646 * CR PFCTRL LL_DMA_GetMode 00647 * @param DMAx DMAx Instance 00648 * @param Stream This parameter can be one of the following values: 00649 * @arg @ref LL_DMA_STREAM_0 00650 * @arg @ref LL_DMA_STREAM_1 00651 * @arg @ref LL_DMA_STREAM_2 00652 * @arg @ref LL_DMA_STREAM_3 00653 * @arg @ref LL_DMA_STREAM_4 00654 * @arg @ref LL_DMA_STREAM_5 00655 * @arg @ref LL_DMA_STREAM_6 00656 * @arg @ref LL_DMA_STREAM_7 00657 * @retval Returned value can be one of the following values: 00658 * @arg @ref LL_DMA_MODE_NORMAL 00659 * @arg @ref LL_DMA_MODE_CIRCULAR 00660 * @arg @ref LL_DMA_MODE_PFCTRL 00661 */ 00662 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) 00663 { 00664 uint32_t dma_base_addr = (uint32_t)DMAx; 00665 00666 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); 00667 } 00668 00669 /** 00670 * @brief Set Peripheral increment mode. 00671 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode 00672 * @param DMAx DMAx Instance 00673 * @param Stream This parameter can be one of the following values: 00674 * @arg @ref LL_DMA_STREAM_0 00675 * @arg @ref LL_DMA_STREAM_1 00676 * @arg @ref LL_DMA_STREAM_2 00677 * @arg @ref LL_DMA_STREAM_3 00678 * @arg @ref LL_DMA_STREAM_4 00679 * @arg @ref LL_DMA_STREAM_5 00680 * @arg @ref LL_DMA_STREAM_6 00681 * @arg @ref LL_DMA_STREAM_7 00682 * @param IncrementMode This parameter can be one of the following values: 00683 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00684 * @arg @ref LL_DMA_PERIPH_INCREMENT 00685 * @retval None 00686 */ 00687 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) 00688 { 00689 uint32_t dma_base_addr = (uint32_t)DMAx; 00690 00691 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode); 00692 } 00693 00694 /** 00695 * @brief Get Peripheral increment mode. 00696 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode 00697 * @param DMAx DMAx Instance 00698 * @param Stream This parameter can be one of the following values: 00699 * @arg @ref LL_DMA_STREAM_0 00700 * @arg @ref LL_DMA_STREAM_1 00701 * @arg @ref LL_DMA_STREAM_2 00702 * @arg @ref LL_DMA_STREAM_3 00703 * @arg @ref LL_DMA_STREAM_4 00704 * @arg @ref LL_DMA_STREAM_5 00705 * @arg @ref LL_DMA_STREAM_6 00706 * @arg @ref LL_DMA_STREAM_7 00707 * @retval Returned value can be one of the following values: 00708 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00709 * @arg @ref LL_DMA_PERIPH_INCREMENT 00710 */ 00711 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 00712 { 00713 uint32_t dma_base_addr = (uint32_t)DMAx; 00714 00715 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC)); 00716 } 00717 00718 /** 00719 * @brief Set Memory increment mode. 00720 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode 00721 * @param DMAx DMAx Instance 00722 * @param Stream This parameter can be one of the following values: 00723 * @arg @ref LL_DMA_STREAM_0 00724 * @arg @ref LL_DMA_STREAM_1 00725 * @arg @ref LL_DMA_STREAM_2 00726 * @arg @ref LL_DMA_STREAM_3 00727 * @arg @ref LL_DMA_STREAM_4 00728 * @arg @ref LL_DMA_STREAM_5 00729 * @arg @ref LL_DMA_STREAM_6 00730 * @arg @ref LL_DMA_STREAM_7 00731 * @param IncrementMode This parameter can be one of the following values: 00732 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00733 * @arg @ref LL_DMA_MEMORY_INCREMENT 00734 * @retval None 00735 */ 00736 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) 00737 { 00738 uint32_t dma_base_addr = (uint32_t)DMAx; 00739 00740 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode); 00741 } 00742 00743 /** 00744 * @brief Get Memory increment mode. 00745 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode 00746 * @param DMAx DMAx Instance 00747 * @param Stream This parameter can be one of the following values: 00748 * @arg @ref LL_DMA_STREAM_0 00749 * @arg @ref LL_DMA_STREAM_1 00750 * @arg @ref LL_DMA_STREAM_2 00751 * @arg @ref LL_DMA_STREAM_3 00752 * @arg @ref LL_DMA_STREAM_4 00753 * @arg @ref LL_DMA_STREAM_5 00754 * @arg @ref LL_DMA_STREAM_6 00755 * @arg @ref LL_DMA_STREAM_7 00756 * @retval Returned value can be one of the following values: 00757 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00758 * @arg @ref LL_DMA_MEMORY_INCREMENT 00759 */ 00760 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 00761 { 00762 uint32_t dma_base_addr = (uint32_t)DMAx; 00763 00764 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC)); 00765 } 00766 00767 /** 00768 * @brief Set Peripheral size. 00769 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize 00770 * @param DMAx DMAx Instance 00771 * @param Stream This parameter can be one of the following values: 00772 * @arg @ref LL_DMA_STREAM_0 00773 * @arg @ref LL_DMA_STREAM_1 00774 * @arg @ref LL_DMA_STREAM_2 00775 * @arg @ref LL_DMA_STREAM_3 00776 * @arg @ref LL_DMA_STREAM_4 00777 * @arg @ref LL_DMA_STREAM_5 00778 * @arg @ref LL_DMA_STREAM_6 00779 * @arg @ref LL_DMA_STREAM_7 00780 * @param Size This parameter can be one of the following values: 00781 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00782 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00783 * @arg @ref LL_DMA_PDATAALIGN_WORD 00784 * @retval None 00785 */ 00786 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 00787 { 00788 uint32_t dma_base_addr = (uint32_t)DMAx; 00789 00790 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size); 00791 } 00792 00793 /** 00794 * @brief Get Peripheral size. 00795 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize 00796 * @param DMAx DMAx Instance 00797 * @param Stream This parameter can be one of the following values: 00798 * @arg @ref LL_DMA_STREAM_0 00799 * @arg @ref LL_DMA_STREAM_1 00800 * @arg @ref LL_DMA_STREAM_2 00801 * @arg @ref LL_DMA_STREAM_3 00802 * @arg @ref LL_DMA_STREAM_4 00803 * @arg @ref LL_DMA_STREAM_5 00804 * @arg @ref LL_DMA_STREAM_6 00805 * @arg @ref LL_DMA_STREAM_7 00806 * @retval Returned value can be one of the following values: 00807 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00808 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00809 * @arg @ref LL_DMA_PDATAALIGN_WORD 00810 */ 00811 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) 00812 { 00813 uint32_t dma_base_addr = (uint32_t)DMAx; 00814 00815 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE)); 00816 } 00817 00818 /** 00819 * @brief Set Memory size. 00820 * @rmtoll CR MSIZE LL_DMA_SetMemorySize 00821 * @param DMAx DMAx Instance 00822 * @param Stream This parameter can be one of the following values: 00823 * @arg @ref LL_DMA_STREAM_0 00824 * @arg @ref LL_DMA_STREAM_1 00825 * @arg @ref LL_DMA_STREAM_2 00826 * @arg @ref LL_DMA_STREAM_3 00827 * @arg @ref LL_DMA_STREAM_4 00828 * @arg @ref LL_DMA_STREAM_5 00829 * @arg @ref LL_DMA_STREAM_6 00830 * @arg @ref LL_DMA_STREAM_7 00831 * @param Size This parameter can be one of the following values: 00832 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00833 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00834 * @arg @ref LL_DMA_MDATAALIGN_WORD 00835 * @retval None 00836 */ 00837 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 00838 { 00839 uint32_t dma_base_addr = (uint32_t)DMAx; 00840 00841 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size); 00842 } 00843 00844 /** 00845 * @brief Get Memory size. 00846 * @rmtoll CR MSIZE LL_DMA_GetMemorySize 00847 * @param DMAx DMAx Instance 00848 * @param Stream This parameter can be one of the following values: 00849 * @arg @ref LL_DMA_STREAM_0 00850 * @arg @ref LL_DMA_STREAM_1 00851 * @arg @ref LL_DMA_STREAM_2 00852 * @arg @ref LL_DMA_STREAM_3 00853 * @arg @ref LL_DMA_STREAM_4 00854 * @arg @ref LL_DMA_STREAM_5 00855 * @arg @ref LL_DMA_STREAM_6 00856 * @arg @ref LL_DMA_STREAM_7 00857 * @retval Returned value can be one of the following values: 00858 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00859 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00860 * @arg @ref LL_DMA_MDATAALIGN_WORD 00861 */ 00862 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) 00863 { 00864 uint32_t dma_base_addr = (uint32_t)DMAx; 00865 00866 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE)); 00867 } 00868 00869 /** 00870 * @brief Set Peripheral increment offset size. 00871 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize 00872 * @param DMAx DMAx Instance 00873 * @param Stream This parameter can be one of the following values: 00874 * @arg @ref LL_DMA_STREAM_0 00875 * @arg @ref LL_DMA_STREAM_1 00876 * @arg @ref LL_DMA_STREAM_2 00877 * @arg @ref LL_DMA_STREAM_3 00878 * @arg @ref LL_DMA_STREAM_4 00879 * @arg @ref LL_DMA_STREAM_5 00880 * @arg @ref LL_DMA_STREAM_6 00881 * @arg @ref LL_DMA_STREAM_7 00882 * @param OffsetSize This parameter can be one of the following values: 00883 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 00884 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 00885 * @retval None 00886 */ 00887 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) 00888 { 00889 uint32_t dma_base_addr = (uint32_t)DMAx; 00890 00891 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize); 00892 } 00893 00894 /** 00895 * @brief Get Peripheral increment offset size. 00896 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize 00897 * @param DMAx DMAx Instance 00898 * @param Stream This parameter can be one of the following values: 00899 * @arg @ref LL_DMA_STREAM_0 00900 * @arg @ref LL_DMA_STREAM_1 00901 * @arg @ref LL_DMA_STREAM_2 00902 * @arg @ref LL_DMA_STREAM_3 00903 * @arg @ref LL_DMA_STREAM_4 00904 * @arg @ref LL_DMA_STREAM_5 00905 * @arg @ref LL_DMA_STREAM_6 00906 * @arg @ref LL_DMA_STREAM_7 00907 * @retval Returned value can be one of the following values: 00908 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 00909 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 00910 */ 00911 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) 00912 { 00913 uint32_t dma_base_addr = (uint32_t)DMAx; 00914 00915 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS)); 00916 } 00917 00918 /** 00919 * @brief Set Stream priority level. 00920 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel 00921 * @param DMAx DMAx Instance 00922 * @param Stream This parameter can be one of the following values: 00923 * @arg @ref LL_DMA_STREAM_0 00924 * @arg @ref LL_DMA_STREAM_1 00925 * @arg @ref LL_DMA_STREAM_2 00926 * @arg @ref LL_DMA_STREAM_3 00927 * @arg @ref LL_DMA_STREAM_4 00928 * @arg @ref LL_DMA_STREAM_5 00929 * @arg @ref LL_DMA_STREAM_6 00930 * @arg @ref LL_DMA_STREAM_7 00931 * @param Priority This parameter can be one of the following values: 00932 * @arg @ref LL_DMA_PRIORITY_LOW 00933 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00934 * @arg @ref LL_DMA_PRIORITY_HIGH 00935 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00936 * @retval None 00937 */ 00938 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) 00939 { 00940 uint32_t dma_base_addr = (uint32_t)DMAx; 00941 00942 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority); 00943 } 00944 00945 /** 00946 * @brief Get Stream priority level. 00947 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel 00948 * @param DMAx DMAx Instance 00949 * @param Stream This parameter can be one of the following values: 00950 * @arg @ref LL_DMA_STREAM_0 00951 * @arg @ref LL_DMA_STREAM_1 00952 * @arg @ref LL_DMA_STREAM_2 00953 * @arg @ref LL_DMA_STREAM_3 00954 * @arg @ref LL_DMA_STREAM_4 00955 * @arg @ref LL_DMA_STREAM_5 00956 * @arg @ref LL_DMA_STREAM_6 00957 * @arg @ref LL_DMA_STREAM_7 00958 * @retval Returned value can be one of the following values: 00959 * @arg @ref LL_DMA_PRIORITY_LOW 00960 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00961 * @arg @ref LL_DMA_PRIORITY_HIGH 00962 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00963 */ 00964 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) 00965 { 00966 uint32_t dma_base_addr = (uint32_t)DMAx; 00967 00968 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL)); 00969 } 00970 00971 /** 00972 * @brief Enable DMA stream bufferable transfer. 00973 * @rmtoll CR TRBUFF LL_DMA_EnableBufferableTransfer 00974 * @param DMAx DMAx Instance 00975 * @param Stream This parameter can be one of the following values: 00976 * @arg @ref LL_DMA_STREAM_0 00977 * @arg @ref LL_DMA_STREAM_1 00978 * @arg @ref LL_DMA_STREAM_2 00979 * @arg @ref LL_DMA_STREAM_3 00980 * @arg @ref LL_DMA_STREAM_4 00981 * @arg @ref LL_DMA_STREAM_5 00982 * @arg @ref LL_DMA_STREAM_6 00983 * @arg @ref LL_DMA_STREAM_7 00984 * @retval None 00985 */ 00986 __STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) 00987 { 00988 uint32_t dma_base_addr = (uint32_t)DMAx; 00989 00990 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); 00991 } 00992 00993 /** 00994 * @brief Disable DMA stream bufferable transfer. 00995 * @rmtoll CR TRBUFF LL_DMA_DisableBufferableTransfer 00996 * @param DMAx DMAx Instance 00997 * @param Stream This parameter can be one of the following values: 00998 * @arg @ref LL_DMA_STREAM_0 00999 * @arg @ref LL_DMA_STREAM_1 01000 * @arg @ref LL_DMA_STREAM_2 01001 * @arg @ref LL_DMA_STREAM_3 01002 * @arg @ref LL_DMA_STREAM_4 01003 * @arg @ref LL_DMA_STREAM_5 01004 * @arg @ref LL_DMA_STREAM_6 01005 * @arg @ref LL_DMA_STREAM_7 01006 * @retval None 01007 */ 01008 __STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream) 01009 { 01010 uint32_t dma_base_addr = (uint32_t)DMAx; 01011 01012 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF); 01013 } 01014 01015 /** 01016 * @brief Set Number of data to transfer. 01017 * @rmtoll NDTR NDT LL_DMA_SetDataLength 01018 * @note This action has no effect if 01019 * stream is enabled. 01020 * @param DMAx DMAx Instance 01021 * @param Stream This parameter can be one of the following values: 01022 * @arg @ref LL_DMA_STREAM_0 01023 * @arg @ref LL_DMA_STREAM_1 01024 * @arg @ref LL_DMA_STREAM_2 01025 * @arg @ref LL_DMA_STREAM_3 01026 * @arg @ref LL_DMA_STREAM_4 01027 * @arg @ref LL_DMA_STREAM_5 01028 * @arg @ref LL_DMA_STREAM_6 01029 * @arg @ref LL_DMA_STREAM_7 01030 * @param NbData Between 0 to 0xFFFFFFFF 01031 * @retval None 01032 */ 01033 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData) 01034 { 01035 uint32_t dma_base_addr = (uint32_t)DMAx; 01036 01037 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData); 01038 } 01039 01040 /** 01041 * @brief Get Number of data to transfer. 01042 * @rmtoll NDTR NDT LL_DMA_GetDataLength 01043 * @note Once the stream is enabled, the return value indicate the 01044 * remaining bytes to be transmitted. 01045 * @param DMAx DMAx Instance 01046 * @param Stream This parameter can be one of the following values: 01047 * @arg @ref LL_DMA_STREAM_0 01048 * @arg @ref LL_DMA_STREAM_1 01049 * @arg @ref LL_DMA_STREAM_2 01050 * @arg @ref LL_DMA_STREAM_3 01051 * @arg @ref LL_DMA_STREAM_4 01052 * @arg @ref LL_DMA_STREAM_5 01053 * @arg @ref LL_DMA_STREAM_6 01054 * @arg @ref LL_DMA_STREAM_7 01055 * @retval Between 0 to 0xFFFFFFFF 01056 */ 01057 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream) 01058 { 01059 uint32_t dma_base_addr = (uint32_t)DMAx; 01060 01061 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT)); 01062 } 01063 /** 01064 * @brief Set DMA request for DMA Streams on DMAMUX Channel x. 01065 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. 01066 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. 01067 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest 01068 * @param DMAx DMAx Instance 01069 * @param Stream This parameter can be one of the following values: 01070 * @arg @ref LL_DMA_STREAM_0 01071 * @arg @ref LL_DMA_STREAM_1 01072 * @arg @ref LL_DMA_STREAM_2 01073 * @arg @ref LL_DMA_STREAM_3 01074 * @arg @ref LL_DMA_STREAM_4 01075 * @arg @ref LL_DMA_STREAM_5 01076 * @arg @ref LL_DMA_STREAM_6 01077 * @arg @ref LL_DMA_STREAM_7 01078 * @param Request This parameter can be one of the following values: 01079 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM 01080 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 01081 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 01082 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 01083 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 01084 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 01085 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 01086 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 01087 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 01088 * @arg @ref LL_DMAMUX1_REQ_ADC1 01089 * @arg @ref LL_DMAMUX1_REQ_ADC2 01090 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 01091 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 01092 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 01093 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 01094 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP 01095 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG 01096 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM 01097 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 01098 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 01099 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 01100 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 01101 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP 01102 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 01103 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 01104 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 01105 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 01106 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP 01107 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG 01108 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 01109 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 01110 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 01111 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP 01112 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX 01113 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX 01114 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX 01115 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX 01116 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX 01117 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX 01118 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX 01119 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX 01120 * @arg @ref LL_DMAMUX1_REQ_USART1_RX 01121 * @arg @ref LL_DMAMUX1_REQ_USART1_TX 01122 * @arg @ref LL_DMAMUX1_REQ_USART2_RX 01123 * @arg @ref LL_DMAMUX1_REQ_USART2_TX 01124 * @arg @ref LL_DMAMUX1_REQ_USART3_RX 01125 * @arg @ref LL_DMAMUX1_REQ_USART3_TX 01126 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 01127 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 01128 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 01129 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 01130 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP 01131 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG 01132 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM 01133 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 01134 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 01135 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 01136 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 01137 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP 01138 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG 01139 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX 01140 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX 01141 * @arg @ref LL_DMAMUX1_REQ_UART4_RX 01142 * @arg @ref LL_DMAMUX1_REQ_UART4_TX 01143 * @arg @ref LL_DMAMUX1_REQ_UART5_RX 01144 * @arg @ref LL_DMAMUX1_REQ_UART5_TX 01145 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 01146 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 01147 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP 01148 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP 01149 * @arg @ref LL_DMAMUX1_REQ_USART6_RX 01150 * @arg @ref LL_DMAMUX1_REQ_USART6_TX 01151 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX 01152 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX 01153 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) 01154 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN 01155 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT 01156 * @arg @ref LL_DMAMUX1_REQ_HASH_IN 01157 * @arg @ref LL_DMAMUX1_REQ_UART7_RX 01158 * @arg @ref LL_DMAMUX1_REQ_UART7_TX 01159 * @arg @ref LL_DMAMUX1_REQ_UART8_RX 01160 * @arg @ref LL_DMAMUX1_REQ_UART8_TX 01161 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX 01162 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX 01163 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX 01164 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX 01165 * @arg @ref LL_DMAMUX1_REQ_SAI1_A 01166 * @arg @ref LL_DMAMUX1_REQ_SAI1_B 01167 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) 01168 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) 01169 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX 01170 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX 01171 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT 01172 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS 01173 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) 01174 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) 01175 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) 01176 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) 01177 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) 01178 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) 01179 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 01180 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 01181 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 01182 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 01183 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 01184 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP 01185 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG 01186 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM 01187 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 01188 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP 01189 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 01190 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP 01191 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) 01192 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) 01193 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) 01194 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) 01195 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) 01196 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) 01197 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) 01198 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) 01199 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) 01200 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) 01201 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) 01202 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) 01203 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) 01204 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) 01205 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) 01206 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) 01207 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) 01208 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) 01209 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) 01210 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) 01211 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) 01212 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) 01213 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) 01214 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) 01215 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) 01216 * 01217 * @note (*) Availability depends on devices. 01218 * @retval None 01219 */ 01220 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request) 01221 { 01222 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); 01223 } 01224 01225 /** 01226 * @brief Get DMA request for DMA Channels on DMAMUX Channel x. 01227 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7. 01228 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7. 01229 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest 01230 * @param DMAx DMAx Instance 01231 * @param Stream This parameter can be one of the following values: 01232 * @arg @ref LL_DMA_STREAM_0 01233 * @arg @ref LL_DMA_STREAM_1 01234 * @arg @ref LL_DMA_STREAM_2 01235 * @arg @ref LL_DMA_STREAM_3 01236 * @arg @ref LL_DMA_STREAM_4 01237 * @arg @ref LL_DMA_STREAM_5 01238 * @arg @ref LL_DMA_STREAM_6 01239 * @arg @ref LL_DMA_STREAM_7 01240 * @retval Returned value can be one of the following values: 01241 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM 01242 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0 01243 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1 01244 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2 01245 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3 01246 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4 01247 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5 01248 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6 01249 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7 01250 * @arg @ref LL_DMAMUX1_REQ_ADC1 01251 * @arg @ref LL_DMAMUX1_REQ_ADC2 01252 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1 01253 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2 01254 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3 01255 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4 01256 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP 01257 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG 01258 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM 01259 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1 01260 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2 01261 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3 01262 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4 01263 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP 01264 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1 01265 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2 01266 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3 01267 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4 01268 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP 01269 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG 01270 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1 01271 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2 01272 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3 01273 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP 01274 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX 01275 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX 01276 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX 01277 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX 01278 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX 01279 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX 01280 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX 01281 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX 01282 * @arg @ref LL_DMAMUX1_REQ_USART1_RX 01283 * @arg @ref LL_DMAMUX1_REQ_USART1_TX 01284 * @arg @ref LL_DMAMUX1_REQ_USART2_RX 01285 * @arg @ref LL_DMAMUX1_REQ_USART2_TX 01286 * @arg @ref LL_DMAMUX1_REQ_USART3_RX 01287 * @arg @ref LL_DMAMUX1_REQ_USART3_TX 01288 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1 01289 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2 01290 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3 01291 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4 01292 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP 01293 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG 01294 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM 01295 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1 01296 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2 01297 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3 01298 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4 01299 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP 01300 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG 01301 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX 01302 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX 01303 * @arg @ref LL_DMAMUX1_REQ_UART4_RX 01304 * @arg @ref LL_DMAMUX1_REQ_UART4_TX 01305 * @arg @ref LL_DMAMUX1_REQ_UART5_RX 01306 * @arg @ref LL_DMAMUX1_REQ_UART5_TX 01307 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1 01308 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2 01309 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP 01310 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP 01311 * @arg @ref LL_DMAMUX1_REQ_USART6_RX 01312 * @arg @ref LL_DMAMUX1_REQ_USART6_TX 01313 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX 01314 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX 01315 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI (*) 01316 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN 01317 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT 01318 * @arg @ref LL_DMAMUX1_REQ_HASH_IN 01319 * @arg @ref LL_DMAMUX1_REQ_UART7_RX 01320 * @arg @ref LL_DMAMUX1_REQ_UART7_TX 01321 * @arg @ref LL_DMAMUX1_REQ_UART8_RX 01322 * @arg @ref LL_DMAMUX1_REQ_UART8_TX 01323 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX 01324 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX 01325 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX 01326 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX 01327 * @arg @ref LL_DMAMUX1_REQ_SAI1_A 01328 * @arg @ref LL_DMAMUX1_REQ_SAI1_B 01329 * @arg @ref LL_DMAMUX1_REQ_SAI2_A (*) 01330 * @arg @ref LL_DMAMUX1_REQ_SAI2_B (*) 01331 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX 01332 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX 01333 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT 01334 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS 01335 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*) 01336 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*) 01337 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*) 01338 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*) 01339 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*) 01340 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*) 01341 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0 01342 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1 01343 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2 01344 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3 01345 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1 01346 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP 01347 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG 01348 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM 01349 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1 01350 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP 01351 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1 01352 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP 01353 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*) 01354 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*) 01355 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*) 01356 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*) 01357 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*) 01358 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*) 01359 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*) 01360 * @arg @ref LL_DMAMUX1_REQ_FMAC_READ (*) 01361 * @arg @ref LL_DMAMUX1_REQ_FMAC_WRITE (*) 01362 * @arg @ref LL_DMAMUX1_REQ_CORDIC_READ (*) 01363 * @arg @ref LL_DMAMUX1_REQ_CORDIC_WRITE(*) 01364 * @arg @ref LL_DMAMUX1_REQ_I2C5_RX (*) 01365 * @arg @ref LL_DMAMUX1_REQ_I2C5_TX (*) 01366 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH1 (*) 01367 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH2 (*) 01368 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH3 (*) 01369 * @arg @ref LL_DMAMUX1_REQ_TIM23_CH4 (*) 01370 * @arg @ref LL_DMAMUX1_REQ_TIM23_UP (*) 01371 * @arg @ref LL_DMAMUX1_REQ_TIM23_TRIG (*) 01372 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH1 (*) 01373 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH2 (*) 01374 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH3 (*) 01375 * @arg @ref LL_DMAMUX1_REQ_TIM24_CH4 (*) 01376 * @arg @ref LL_DMAMUX1_REQ_TIM24_UP (*) 01377 * @arg @ref LL_DMAMUX1_REQ_TIM24_TRIG (*) 01378 * 01379 * @note (*) Availability depends on devices. 01380 */ 01381 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream) 01382 { 01383 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); 01384 } 01385 01386 /** 01387 * @brief Set Memory burst transfer configuration. 01388 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer 01389 * @param DMAx DMAx Instance 01390 * @param Stream This parameter can be one of the following values: 01391 * @arg @ref LL_DMA_STREAM_0 01392 * @arg @ref LL_DMA_STREAM_1 01393 * @arg @ref LL_DMA_STREAM_2 01394 * @arg @ref LL_DMA_STREAM_3 01395 * @arg @ref LL_DMA_STREAM_4 01396 * @arg @ref LL_DMA_STREAM_5 01397 * @arg @ref LL_DMA_STREAM_6 01398 * @arg @ref LL_DMA_STREAM_7 01399 * @param Mburst This parameter can be one of the following values: 01400 * @arg @ref LL_DMA_MBURST_SINGLE 01401 * @arg @ref LL_DMA_MBURST_INC4 01402 * @arg @ref LL_DMA_MBURST_INC8 01403 * @arg @ref LL_DMA_MBURST_INC16 01404 * @retval None 01405 */ 01406 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) 01407 { 01408 uint32_t dma_base_addr = (uint32_t)DMAx; 01409 01410 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst); 01411 } 01412 01413 /** 01414 * @brief Get Memory burst transfer configuration. 01415 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer 01416 * @param DMAx DMAx Instance 01417 * @param Stream This parameter can be one of the following values: 01418 * @arg @ref LL_DMA_STREAM_0 01419 * @arg @ref LL_DMA_STREAM_1 01420 * @arg @ref LL_DMA_STREAM_2 01421 * @arg @ref LL_DMA_STREAM_3 01422 * @arg @ref LL_DMA_STREAM_4 01423 * @arg @ref LL_DMA_STREAM_5 01424 * @arg @ref LL_DMA_STREAM_6 01425 * @arg @ref LL_DMA_STREAM_7 01426 * @retval Returned value can be one of the following values: 01427 * @arg @ref LL_DMA_MBURST_SINGLE 01428 * @arg @ref LL_DMA_MBURST_INC4 01429 * @arg @ref LL_DMA_MBURST_INC8 01430 * @arg @ref LL_DMA_MBURST_INC16 01431 */ 01432 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 01433 { 01434 uint32_t dma_base_addr = (uint32_t)DMAx; 01435 01436 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST)); 01437 } 01438 01439 /** 01440 * @brief Set Peripheral burst transfer configuration. 01441 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer 01442 * @param DMAx DMAx Instance 01443 * @param Stream This parameter can be one of the following values: 01444 * @arg @ref LL_DMA_STREAM_0 01445 * @arg @ref LL_DMA_STREAM_1 01446 * @arg @ref LL_DMA_STREAM_2 01447 * @arg @ref LL_DMA_STREAM_3 01448 * @arg @ref LL_DMA_STREAM_4 01449 * @arg @ref LL_DMA_STREAM_5 01450 * @arg @ref LL_DMA_STREAM_6 01451 * @arg @ref LL_DMA_STREAM_7 01452 * @param Pburst This parameter can be one of the following values: 01453 * @arg @ref LL_DMA_PBURST_SINGLE 01454 * @arg @ref LL_DMA_PBURST_INC4 01455 * @arg @ref LL_DMA_PBURST_INC8 01456 * @arg @ref LL_DMA_PBURST_INC16 01457 * @retval None 01458 */ 01459 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) 01460 { 01461 uint32_t dma_base_addr = (uint32_t)DMAx; 01462 01463 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst); 01464 } 01465 01466 /** 01467 * @brief Get Peripheral burst transfer configuration. 01468 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer 01469 * @param DMAx DMAx Instance 01470 * @param Stream This parameter can be one of the following values: 01471 * @arg @ref LL_DMA_STREAM_0 01472 * @arg @ref LL_DMA_STREAM_1 01473 * @arg @ref LL_DMA_STREAM_2 01474 * @arg @ref LL_DMA_STREAM_3 01475 * @arg @ref LL_DMA_STREAM_4 01476 * @arg @ref LL_DMA_STREAM_5 01477 * @arg @ref LL_DMA_STREAM_6 01478 * @arg @ref LL_DMA_STREAM_7 01479 * @retval Returned value can be one of the following values: 01480 * @arg @ref LL_DMA_PBURST_SINGLE 01481 * @arg @ref LL_DMA_PBURST_INC4 01482 * @arg @ref LL_DMA_PBURST_INC8 01483 * @arg @ref LL_DMA_PBURST_INC16 01484 */ 01485 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 01486 { 01487 uint32_t dma_base_addr = (uint32_t)DMAx; 01488 01489 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST)); 01490 } 01491 01492 /** 01493 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 01494 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem 01495 * @param DMAx DMAx Instance 01496 * @param Stream This parameter can be one of the following values: 01497 * @arg @ref LL_DMA_STREAM_0 01498 * @arg @ref LL_DMA_STREAM_1 01499 * @arg @ref LL_DMA_STREAM_2 01500 * @arg @ref LL_DMA_STREAM_3 01501 * @arg @ref LL_DMA_STREAM_4 01502 * @arg @ref LL_DMA_STREAM_5 01503 * @arg @ref LL_DMA_STREAM_6 01504 * @arg @ref LL_DMA_STREAM_7 01505 * @param CurrentMemory This parameter can be one of the following values: 01506 * @arg @ref LL_DMA_CURRENTTARGETMEM0 01507 * @arg @ref LL_DMA_CURRENTTARGETMEM1 01508 * @retval None 01509 */ 01510 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) 01511 { 01512 uint32_t dma_base_addr = (uint32_t)DMAx; 01513 01514 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory); 01515 } 01516 01517 /** 01518 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 01519 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem 01520 * @param DMAx DMAx Instance 01521 * @param Stream This parameter can be one of the following values: 01522 * @arg @ref LL_DMA_STREAM_0 01523 * @arg @ref LL_DMA_STREAM_1 01524 * @arg @ref LL_DMA_STREAM_2 01525 * @arg @ref LL_DMA_STREAM_3 01526 * @arg @ref LL_DMA_STREAM_4 01527 * @arg @ref LL_DMA_STREAM_5 01528 * @arg @ref LL_DMA_STREAM_6 01529 * @arg @ref LL_DMA_STREAM_7 01530 * @retval Returned value can be one of the following values: 01531 * @arg @ref LL_DMA_CURRENTTARGETMEM0 01532 * @arg @ref LL_DMA_CURRENTTARGETMEM1 01533 */ 01534 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) 01535 { 01536 uint32_t dma_base_addr = (uint32_t)DMAx; 01537 01538 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT)); 01539 } 01540 01541 /** 01542 * @brief Enable the double buffer mode. 01543 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode 01544 * @param DMAx DMAx Instance 01545 * @param Stream This parameter can be one of the following values: 01546 * @arg @ref LL_DMA_STREAM_0 01547 * @arg @ref LL_DMA_STREAM_1 01548 * @arg @ref LL_DMA_STREAM_2 01549 * @arg @ref LL_DMA_STREAM_3 01550 * @arg @ref LL_DMA_STREAM_4 01551 * @arg @ref LL_DMA_STREAM_5 01552 * @arg @ref LL_DMA_STREAM_6 01553 * @arg @ref LL_DMA_STREAM_7 01554 * @retval None 01555 */ 01556 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 01557 { 01558 uint32_t dma_base_addr = (uint32_t)DMAx; 01559 01560 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); 01561 } 01562 01563 /** 01564 * @brief Disable the double buffer mode. 01565 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode 01566 * @param DMAx DMAx Instance 01567 * @param Stream This parameter can be one of the following values: 01568 * @arg @ref LL_DMA_STREAM_0 01569 * @arg @ref LL_DMA_STREAM_1 01570 * @arg @ref LL_DMA_STREAM_2 01571 * @arg @ref LL_DMA_STREAM_3 01572 * @arg @ref LL_DMA_STREAM_4 01573 * @arg @ref LL_DMA_STREAM_5 01574 * @arg @ref LL_DMA_STREAM_6 01575 * @arg @ref LL_DMA_STREAM_7 01576 * @retval None 01577 */ 01578 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 01579 { 01580 uint32_t dma_base_addr = (uint32_t)DMAx; 01581 01582 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM); 01583 } 01584 01585 /** 01586 * @brief Get FIFO status. 01587 * @rmtoll FCR FS LL_DMA_GetFIFOStatus 01588 * @param DMAx DMAx Instance 01589 * @param Stream This parameter can be one of the following values: 01590 * @arg @ref LL_DMA_STREAM_0 01591 * @arg @ref LL_DMA_STREAM_1 01592 * @arg @ref LL_DMA_STREAM_2 01593 * @arg @ref LL_DMA_STREAM_3 01594 * @arg @ref LL_DMA_STREAM_4 01595 * @arg @ref LL_DMA_STREAM_5 01596 * @arg @ref LL_DMA_STREAM_6 01597 * @arg @ref LL_DMA_STREAM_7 01598 * @retval Returned value can be one of the following values: 01599 * @arg @ref LL_DMA_FIFOSTATUS_0_25 01600 * @arg @ref LL_DMA_FIFOSTATUS_25_50 01601 * @arg @ref LL_DMA_FIFOSTATUS_50_75 01602 * @arg @ref LL_DMA_FIFOSTATUS_75_100 01603 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY 01604 * @arg @ref LL_DMA_FIFOSTATUS_FULL 01605 */ 01606 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) 01607 { 01608 uint32_t dma_base_addr = (uint32_t)DMAx; 01609 01610 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS)); 01611 } 01612 01613 /** 01614 * @brief Disable Fifo mode. 01615 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode 01616 * @param DMAx DMAx Instance 01617 * @param Stream This parameter can be one of the following values: 01618 * @arg @ref LL_DMA_STREAM_0 01619 * @arg @ref LL_DMA_STREAM_1 01620 * @arg @ref LL_DMA_STREAM_2 01621 * @arg @ref LL_DMA_STREAM_3 01622 * @arg @ref LL_DMA_STREAM_4 01623 * @arg @ref LL_DMA_STREAM_5 01624 * @arg @ref LL_DMA_STREAM_6 01625 * @arg @ref LL_DMA_STREAM_7 01626 * @retval None 01627 */ 01628 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 01629 { 01630 uint32_t dma_base_addr = (uint32_t)DMAx; 01631 01632 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); 01633 } 01634 01635 /** 01636 * @brief Enable Fifo mode. 01637 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode 01638 * @param DMAx DMAx Instance 01639 * @param Stream This parameter can be one of the following values: 01640 * @arg @ref LL_DMA_STREAM_0 01641 * @arg @ref LL_DMA_STREAM_1 01642 * @arg @ref LL_DMA_STREAM_2 01643 * @arg @ref LL_DMA_STREAM_3 01644 * @arg @ref LL_DMA_STREAM_4 01645 * @arg @ref LL_DMA_STREAM_5 01646 * @arg @ref LL_DMA_STREAM_6 01647 * @arg @ref LL_DMA_STREAM_7 01648 * @retval None 01649 */ 01650 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 01651 { 01652 uint32_t dma_base_addr = (uint32_t)DMAx; 01653 01654 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS); 01655 } 01656 01657 /** 01658 * @brief Select FIFO threshold. 01659 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold 01660 * @param DMAx DMAx Instance 01661 * @param Stream This parameter can be one of the following values: 01662 * @arg @ref LL_DMA_STREAM_0 01663 * @arg @ref LL_DMA_STREAM_1 01664 * @arg @ref LL_DMA_STREAM_2 01665 * @arg @ref LL_DMA_STREAM_3 01666 * @arg @ref LL_DMA_STREAM_4 01667 * @arg @ref LL_DMA_STREAM_5 01668 * @arg @ref LL_DMA_STREAM_6 01669 * @arg @ref LL_DMA_STREAM_7 01670 * @param Threshold This parameter can be one of the following values: 01671 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01672 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01673 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01674 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01675 * @retval None 01676 */ 01677 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) 01678 { 01679 uint32_t dma_base_addr = (uint32_t)DMAx; 01680 01681 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold); 01682 } 01683 01684 /** 01685 * @brief Get FIFO threshold. 01686 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold 01687 * @param DMAx DMAx Instance 01688 * @param Stream This parameter can be one of the following values: 01689 * @arg @ref LL_DMA_STREAM_0 01690 * @arg @ref LL_DMA_STREAM_1 01691 * @arg @ref LL_DMA_STREAM_2 01692 * @arg @ref LL_DMA_STREAM_3 01693 * @arg @ref LL_DMA_STREAM_4 01694 * @arg @ref LL_DMA_STREAM_5 01695 * @arg @ref LL_DMA_STREAM_6 01696 * @arg @ref LL_DMA_STREAM_7 01697 * @retval Returned value can be one of the following values: 01698 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01699 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01700 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01701 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01702 */ 01703 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) 01704 { 01705 uint32_t dma_base_addr = (uint32_t)DMAx; 01706 01707 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH)); 01708 } 01709 01710 /** 01711 * @brief Configure the FIFO . 01712 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n 01713 * FCR DMDIS LL_DMA_ConfigFifo 01714 * @param DMAx DMAx Instance 01715 * @param Stream This parameter can be one of the following values: 01716 * @arg @ref LL_DMA_STREAM_0 01717 * @arg @ref LL_DMA_STREAM_1 01718 * @arg @ref LL_DMA_STREAM_2 01719 * @arg @ref LL_DMA_STREAM_3 01720 * @arg @ref LL_DMA_STREAM_4 01721 * @arg @ref LL_DMA_STREAM_5 01722 * @arg @ref LL_DMA_STREAM_6 01723 * @arg @ref LL_DMA_STREAM_7 01724 * @param FifoMode This parameter can be one of the following values: 01725 * @arg @ref LL_DMA_FIFOMODE_ENABLE 01726 * @arg @ref LL_DMA_FIFOMODE_DISABLE 01727 * @param FifoThreshold This parameter can be one of the following values: 01728 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01729 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01730 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01731 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01732 * @retval None 01733 */ 01734 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) 01735 { 01736 uint32_t dma_base_addr = (uint32_t)DMAx; 01737 01738 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold); 01739 } 01740 01741 /** 01742 * @brief Configure the Source and Destination addresses. 01743 * @note This API must not be called when the DMA stream is enabled. 01744 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n 01745 * PAR PA LL_DMA_ConfigAddresses 01746 * @param DMAx DMAx Instance 01747 * @param Stream This parameter can be one of the following values: 01748 * @arg @ref LL_DMA_STREAM_0 01749 * @arg @ref LL_DMA_STREAM_1 01750 * @arg @ref LL_DMA_STREAM_2 01751 * @arg @ref LL_DMA_STREAM_3 01752 * @arg @ref LL_DMA_STREAM_4 01753 * @arg @ref LL_DMA_STREAM_5 01754 * @arg @ref LL_DMA_STREAM_6 01755 * @arg @ref LL_DMA_STREAM_7 01756 * @param SrcAddress Between 0 to 0xFFFFFFFF 01757 * @param DstAddress Between 0 to 0xFFFFFFFF 01758 * @param Direction This parameter can be one of the following values: 01759 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 01760 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 01761 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 01762 * @retval None 01763 */ 01764 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) 01765 { 01766 uint32_t dma_base_addr = (uint32_t)DMAx; 01767 01768 /* Direction Memory to Periph */ 01769 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 01770 { 01771 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress); 01772 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress); 01773 } 01774 /* Direction Periph to Memory and Memory to Memory */ 01775 else 01776 { 01777 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress); 01778 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress); 01779 } 01780 } 01781 01782 /** 01783 * @brief Set the Memory address. 01784 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress 01785 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01786 * @note This API must not be called when the DMA stream is enabled. 01787 * @param DMAx DMAx Instance 01788 * @param Stream This parameter can be one of the following values: 01789 * @arg @ref LL_DMA_STREAM_0 01790 * @arg @ref LL_DMA_STREAM_1 01791 * @arg @ref LL_DMA_STREAM_2 01792 * @arg @ref LL_DMA_STREAM_3 01793 * @arg @ref LL_DMA_STREAM_4 01794 * @arg @ref LL_DMA_STREAM_5 01795 * @arg @ref LL_DMA_STREAM_6 01796 * @arg @ref LL_DMA_STREAM_7 01797 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01798 * @retval None 01799 */ 01800 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) 01801 { 01802 uint32_t dma_base_addr = (uint32_t)DMAx; 01803 01804 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); 01805 } 01806 01807 /** 01808 * @brief Set the Peripheral address. 01809 * @rmtoll PAR PA LL_DMA_SetPeriphAddress 01810 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01811 * @note This API must not be called when the DMA stream is enabled. 01812 * @param DMAx DMAx Instance 01813 * @param Stream This parameter can be one of the following values: 01814 * @arg @ref LL_DMA_STREAM_0 01815 * @arg @ref LL_DMA_STREAM_1 01816 * @arg @ref LL_DMA_STREAM_2 01817 * @arg @ref LL_DMA_STREAM_3 01818 * @arg @ref LL_DMA_STREAM_4 01819 * @arg @ref LL_DMA_STREAM_5 01820 * @arg @ref LL_DMA_STREAM_6 01821 * @arg @ref LL_DMA_STREAM_7 01822 * @param PeriphAddress Between 0 to 0xFFFFFFFF 01823 * @retval None 01824 */ 01825 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress) 01826 { 01827 uint32_t dma_base_addr = (uint32_t)DMAx; 01828 01829 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress); 01830 } 01831 01832 /** 01833 * @brief Get the Memory address. 01834 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress 01835 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01836 * @param DMAx DMAx Instance 01837 * @param Stream This parameter can be one of the following values: 01838 * @arg @ref LL_DMA_STREAM_0 01839 * @arg @ref LL_DMA_STREAM_1 01840 * @arg @ref LL_DMA_STREAM_2 01841 * @arg @ref LL_DMA_STREAM_3 01842 * @arg @ref LL_DMA_STREAM_4 01843 * @arg @ref LL_DMA_STREAM_5 01844 * @arg @ref LL_DMA_STREAM_6 01845 * @arg @ref LL_DMA_STREAM_7 01846 * @retval Between 0 to 0xFFFFFFFF 01847 */ 01848 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream) 01849 { 01850 uint32_t dma_base_addr = (uint32_t)DMAx; 01851 01852 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); 01853 } 01854 01855 /** 01856 * @brief Get the Peripheral address. 01857 * @rmtoll PAR PA LL_DMA_GetPeriphAddress 01858 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01859 * @param DMAx DMAx Instance 01860 * @param Stream This parameter can be one of the following values: 01861 * @arg @ref LL_DMA_STREAM_0 01862 * @arg @ref LL_DMA_STREAM_1 01863 * @arg @ref LL_DMA_STREAM_2 01864 * @arg @ref LL_DMA_STREAM_3 01865 * @arg @ref LL_DMA_STREAM_4 01866 * @arg @ref LL_DMA_STREAM_5 01867 * @arg @ref LL_DMA_STREAM_6 01868 * @arg @ref LL_DMA_STREAM_7 01869 * @retval Between 0 to 0xFFFFFFFF 01870 */ 01871 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream) 01872 { 01873 uint32_t dma_base_addr = (uint32_t)DMAx; 01874 01875 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); 01876 } 01877 01878 /** 01879 * @brief Set the Memory to Memory Source address. 01880 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress 01881 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01882 * @note This API must not be called when the DMA stream is enabled. 01883 * @param DMAx DMAx Instance 01884 * @param Stream This parameter can be one of the following values: 01885 * @arg @ref LL_DMA_STREAM_0 01886 * @arg @ref LL_DMA_STREAM_1 01887 * @arg @ref LL_DMA_STREAM_2 01888 * @arg @ref LL_DMA_STREAM_3 01889 * @arg @ref LL_DMA_STREAM_4 01890 * @arg @ref LL_DMA_STREAM_5 01891 * @arg @ref LL_DMA_STREAM_6 01892 * @arg @ref LL_DMA_STREAM_7 01893 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01894 * @retval None 01895 */ 01896 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) 01897 { 01898 uint32_t dma_base_addr = (uint32_t)DMAx; 01899 01900 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress); 01901 } 01902 01903 /** 01904 * @brief Set the Memory to Memory Destination address. 01905 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress 01906 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01907 * @note This API must not be called when the DMA stream is enabled. 01908 * @param DMAx DMAx Instance 01909 * @param Stream This parameter can be one of the following values: 01910 * @arg @ref LL_DMA_STREAM_0 01911 * @arg @ref LL_DMA_STREAM_1 01912 * @arg @ref LL_DMA_STREAM_2 01913 * @arg @ref LL_DMA_STREAM_3 01914 * @arg @ref LL_DMA_STREAM_4 01915 * @arg @ref LL_DMA_STREAM_5 01916 * @arg @ref LL_DMA_STREAM_6 01917 * @arg @ref LL_DMA_STREAM_7 01918 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01919 * @retval None 01920 */ 01921 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress) 01922 { 01923 uint32_t dma_base_addr = (uint32_t)DMAx; 01924 01925 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress); 01926 } 01927 01928 /** 01929 * @brief Get the Memory to Memory Source address. 01930 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress 01931 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01932 * @param DMAx DMAx Instance 01933 * @param Stream This parameter can be one of the following values: 01934 * @arg @ref LL_DMA_STREAM_0 01935 * @arg @ref LL_DMA_STREAM_1 01936 * @arg @ref LL_DMA_STREAM_2 01937 * @arg @ref LL_DMA_STREAM_3 01938 * @arg @ref LL_DMA_STREAM_4 01939 * @arg @ref LL_DMA_STREAM_5 01940 * @arg @ref LL_DMA_STREAM_6 01941 * @arg @ref LL_DMA_STREAM_7 01942 * @retval Between 0 to 0xFFFFFFFF 01943 */ 01944 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream) 01945 { 01946 uint32_t dma_base_addr = (uint32_t)DMAx; 01947 01948 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR)); 01949 } 01950 01951 /** 01952 * @brief Get the Memory to Memory Destination address. 01953 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress 01954 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01955 * @param DMAx DMAx Instance 01956 * @param Stream This parameter can be one of the following values: 01957 * @arg @ref LL_DMA_STREAM_0 01958 * @arg @ref LL_DMA_STREAM_1 01959 * @arg @ref LL_DMA_STREAM_2 01960 * @arg @ref LL_DMA_STREAM_3 01961 * @arg @ref LL_DMA_STREAM_4 01962 * @arg @ref LL_DMA_STREAM_5 01963 * @arg @ref LL_DMA_STREAM_6 01964 * @arg @ref LL_DMA_STREAM_7 01965 * @retval Between 0 to 0xFFFFFFFF 01966 */ 01967 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream) 01968 { 01969 uint32_t dma_base_addr = (uint32_t)DMAx; 01970 01971 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR)); 01972 } 01973 01974 /** 01975 * @brief Set Memory 1 address (used in case of Double buffer mode). 01976 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address 01977 * @param DMAx DMAx Instance 01978 * @param Stream This parameter can be one of the following values: 01979 * @arg @ref LL_DMA_STREAM_0 01980 * @arg @ref LL_DMA_STREAM_1 01981 * @arg @ref LL_DMA_STREAM_2 01982 * @arg @ref LL_DMA_STREAM_3 01983 * @arg @ref LL_DMA_STREAM_4 01984 * @arg @ref LL_DMA_STREAM_5 01985 * @arg @ref LL_DMA_STREAM_6 01986 * @arg @ref LL_DMA_STREAM_7 01987 * @param Address Between 0 to 0xFFFFFFFF 01988 * @retval None 01989 */ 01990 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) 01991 { 01992 uint32_t dma_base_addr = (uint32_t)DMAx; 01993 01994 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address); 01995 } 01996 01997 /** 01998 * @brief Get Memory 1 address (used in case of Double buffer mode). 01999 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address 02000 * @param DMAx DMAx Instance 02001 * @param Stream This parameter can be one of the following values: 02002 * @arg @ref LL_DMA_STREAM_0 02003 * @arg @ref LL_DMA_STREAM_1 02004 * @arg @ref LL_DMA_STREAM_2 02005 * @arg @ref LL_DMA_STREAM_3 02006 * @arg @ref LL_DMA_STREAM_4 02007 * @arg @ref LL_DMA_STREAM_5 02008 * @arg @ref LL_DMA_STREAM_6 02009 * @arg @ref LL_DMA_STREAM_7 02010 * @retval Between 0 to 0xFFFFFFFF 02011 */ 02012 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) 02013 { 02014 uint32_t dma_base_addr = (uint32_t)DMAx; 02015 02016 return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR); 02017 } 02018 02019 /** 02020 * @} 02021 */ 02022 02023 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 02024 * @{ 02025 */ 02026 02027 /** 02028 * @brief Get Stream 0 half transfer flag. 02029 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 02030 * @param DMAx DMAx Instance 02031 * @retval State of bit (1 or 0). 02032 */ 02033 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) 02034 { 02035 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL); 02036 } 02037 02038 /** 02039 * @brief Get Stream 1 half transfer flag. 02040 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 02041 * @param DMAx DMAx Instance 02042 * @retval State of bit (1 or 0). 02043 */ 02044 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 02045 { 02046 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL); 02047 } 02048 02049 /** 02050 * @brief Get Stream 2 half transfer flag. 02051 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 02052 * @param DMAx DMAx Instance 02053 * @retval State of bit (1 or 0). 02054 */ 02055 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 02056 { 02057 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL); 02058 } 02059 02060 /** 02061 * @brief Get Stream 3 half transfer flag. 02062 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 02063 * @param DMAx DMAx Instance 02064 * @retval State of bit (1 or 0). 02065 */ 02066 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 02067 { 02068 return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL); 02069 } 02070 02071 /** 02072 * @brief Get Stream 4 half transfer flag. 02073 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 02074 * @param DMAx DMAx Instance 02075 * @retval State of bit (1 or 0). 02076 */ 02077 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 02078 { 02079 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL); 02080 } 02081 02082 /** 02083 * @brief Get Stream 5 half transfer flag. 02084 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 02085 * @param DMAx DMAx Instance 02086 * @retval State of bit (1 or 0). 02087 */ 02088 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 02089 { 02090 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL); 02091 } 02092 02093 /** 02094 * @brief Get Stream 6 half transfer flag. 02095 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 02096 * @param DMAx DMAx Instance 02097 * @retval State of bit (1 or 0). 02098 */ 02099 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 02100 { 02101 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL); 02102 } 02103 02104 /** 02105 * @brief Get Stream 7 half transfer flag. 02106 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 02107 * @param DMAx DMAx Instance 02108 * @retval State of bit (1 or 0). 02109 */ 02110 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 02111 { 02112 return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL); 02113 } 02114 02115 /** 02116 * @brief Get Stream 0 transfer complete flag. 02117 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 02118 * @param DMAx DMAx Instance 02119 * @retval State of bit (1 or 0). 02120 */ 02121 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) 02122 { 02123 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL); 02124 } 02125 02126 /** 02127 * @brief Get Stream 1 transfer complete flag. 02128 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 02129 * @param DMAx DMAx Instance 02130 * @retval State of bit (1 or 0). 02131 */ 02132 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 02133 { 02134 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL); 02135 } 02136 02137 /** 02138 * @brief Get Stream 2 transfer complete flag. 02139 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 02140 * @param DMAx DMAx Instance 02141 * @retval State of bit (1 or 0). 02142 */ 02143 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 02144 { 02145 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL); 02146 } 02147 02148 /** 02149 * @brief Get Stream 3 transfer complete flag. 02150 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 02151 * @param DMAx DMAx Instance 02152 * @retval State of bit (1 or 0). 02153 */ 02154 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 02155 { 02156 return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL); 02157 } 02158 02159 /** 02160 * @brief Get Stream 4 transfer complete flag. 02161 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 02162 * @param DMAx DMAx Instance 02163 * @retval State of bit (1 or 0). 02164 */ 02165 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 02166 { 02167 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL); 02168 } 02169 02170 /** 02171 * @brief Get Stream 5 transfer complete flag. 02172 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 02173 * @param DMAx DMAx Instance 02174 * @retval State of bit (1 or 0). 02175 */ 02176 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 02177 { 02178 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL); 02179 } 02180 02181 /** 02182 * @brief Get Stream 6 transfer complete flag. 02183 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 02184 * @param DMAx DMAx Instance 02185 * @retval State of bit (1 or 0). 02186 */ 02187 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 02188 { 02189 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL); 02190 } 02191 02192 /** 02193 * @brief Get Stream 7 transfer complete flag. 02194 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 02195 * @param DMAx DMAx Instance 02196 * @retval State of bit (1 or 0). 02197 */ 02198 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 02199 { 02200 return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL); 02201 } 02202 02203 /** 02204 * @brief Get Stream 0 transfer error flag. 02205 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 02206 * @param DMAx DMAx Instance 02207 * @retval State of bit (1 or 0). 02208 */ 02209 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) 02210 { 02211 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL); 02212 } 02213 02214 /** 02215 * @brief Get Stream 1 transfer error flag. 02216 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 02217 * @param DMAx DMAx Instance 02218 * @retval State of bit (1 or 0). 02219 */ 02220 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 02221 { 02222 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL); 02223 } 02224 02225 /** 02226 * @brief Get Stream 2 transfer error flag. 02227 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 02228 * @param DMAx DMAx Instance 02229 * @retval State of bit (1 or 0). 02230 */ 02231 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 02232 { 02233 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL); 02234 } 02235 02236 /** 02237 * @brief Get Stream 3 transfer error flag. 02238 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 02239 * @param DMAx DMAx Instance 02240 * @retval State of bit (1 or 0). 02241 */ 02242 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 02243 { 02244 return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL); 02245 } 02246 02247 /** 02248 * @brief Get Stream 4 transfer error flag. 02249 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 02250 * @param DMAx DMAx Instance 02251 * @retval State of bit (1 or 0). 02252 */ 02253 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 02254 { 02255 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL); 02256 } 02257 02258 /** 02259 * @brief Get Stream 5 transfer error flag. 02260 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 02261 * @param DMAx DMAx Instance 02262 * @retval State of bit (1 or 0). 02263 */ 02264 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 02265 { 02266 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL); 02267 } 02268 02269 /** 02270 * @brief Get Stream 6 transfer error flag. 02271 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 02272 * @param DMAx DMAx Instance 02273 * @retval State of bit (1 or 0). 02274 */ 02275 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 02276 { 02277 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL); 02278 } 02279 02280 /** 02281 * @brief Get Stream 7 transfer error flag. 02282 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 02283 * @param DMAx DMAx Instance 02284 * @retval State of bit (1 or 0). 02285 */ 02286 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 02287 { 02288 return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL); 02289 } 02290 02291 /** 02292 * @brief Get Stream 0 direct mode error flag. 02293 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 02294 * @param DMAx DMAx Instance 02295 * @retval State of bit (1 or 0). 02296 */ 02297 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) 02298 { 02299 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL); 02300 } 02301 02302 /** 02303 * @brief Get Stream 1 direct mode error flag. 02304 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 02305 * @param DMAx DMAx Instance 02306 * @retval State of bit (1 or 0). 02307 */ 02308 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) 02309 { 02310 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL); 02311 } 02312 02313 /** 02314 * @brief Get Stream 2 direct mode error flag. 02315 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 02316 * @param DMAx DMAx Instance 02317 * @retval State of bit (1 or 0). 02318 */ 02319 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) 02320 { 02321 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL); 02322 } 02323 02324 /** 02325 * @brief Get Stream 3 direct mode error flag. 02326 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 02327 * @param DMAx DMAx Instance 02328 * @retval State of bit (1 or 0). 02329 */ 02330 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) 02331 { 02332 return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL); 02333 } 02334 02335 /** 02336 * @brief Get Stream 4 direct mode error flag. 02337 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 02338 * @param DMAx DMAx Instance 02339 * @retval State of bit (1 or 0). 02340 */ 02341 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) 02342 { 02343 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL); 02344 } 02345 02346 /** 02347 * @brief Get Stream 5 direct mode error flag. 02348 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 02349 * @param DMAx DMAx Instance 02350 * @retval State of bit (1 or 0). 02351 */ 02352 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) 02353 { 02354 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL); 02355 } 02356 02357 /** 02358 * @brief Get Stream 6 direct mode error flag. 02359 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 02360 * @param DMAx DMAx Instance 02361 * @retval State of bit (1 or 0). 02362 */ 02363 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) 02364 { 02365 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL); 02366 } 02367 02368 /** 02369 * @brief Get Stream 7 direct mode error flag. 02370 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 02371 * @param DMAx DMAx Instance 02372 * @retval State of bit (1 or 0). 02373 */ 02374 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) 02375 { 02376 return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL); 02377 } 02378 02379 /** 02380 * @brief Get Stream 0 FIFO error flag. 02381 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 02382 * @param DMAx DMAx Instance 02383 * @retval State of bit (1 or 0). 02384 */ 02385 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) 02386 { 02387 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL); 02388 } 02389 02390 /** 02391 * @brief Get Stream 1 FIFO error flag. 02392 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 02393 * @param DMAx DMAx Instance 02394 * @retval State of bit (1 or 0). 02395 */ 02396 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) 02397 { 02398 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL); 02399 } 02400 02401 /** 02402 * @brief Get Stream 2 FIFO error flag. 02403 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 02404 * @param DMAx DMAx Instance 02405 * @retval State of bit (1 or 0). 02406 */ 02407 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) 02408 { 02409 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL); 02410 } 02411 02412 /** 02413 * @brief Get Stream 3 FIFO error flag. 02414 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 02415 * @param DMAx DMAx Instance 02416 * @retval State of bit (1 or 0). 02417 */ 02418 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) 02419 { 02420 return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL); 02421 } 02422 02423 /** 02424 * @brief Get Stream 4 FIFO error flag. 02425 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 02426 * @param DMAx DMAx Instance 02427 * @retval State of bit (1 or 0). 02428 */ 02429 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) 02430 { 02431 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL); 02432 } 02433 02434 /** 02435 * @brief Get Stream 5 FIFO error flag. 02436 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 02437 * @param DMAx DMAx Instance 02438 * @retval State of bit (1 or 0). 02439 */ 02440 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) 02441 { 02442 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL); 02443 } 02444 02445 /** 02446 * @brief Get Stream 6 FIFO error flag. 02447 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 02448 * @param DMAx DMAx Instance 02449 * @retval State of bit (1 or 0). 02450 */ 02451 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) 02452 { 02453 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL); 02454 } 02455 02456 /** 02457 * @brief Get Stream 7 FIFO error flag. 02458 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 02459 * @param DMAx DMAx Instance 02460 * @retval State of bit (1 or 0). 02461 */ 02462 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) 02463 { 02464 return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL); 02465 } 02466 02467 /** 02468 * @brief Clear Stream 0 half transfer flag. 02469 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 02470 * @param DMAx DMAx Instance 02471 * @retval None 02472 */ 02473 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) 02474 { 02475 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0); 02476 } 02477 02478 /** 02479 * @brief Clear Stream 1 half transfer flag. 02480 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 02481 * @param DMAx DMAx Instance 02482 * @retval None 02483 */ 02484 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 02485 { 02486 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1); 02487 } 02488 02489 /** 02490 * @brief Clear Stream 2 half transfer flag. 02491 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 02492 * @param DMAx DMAx Instance 02493 * @retval None 02494 */ 02495 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 02496 { 02497 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2); 02498 } 02499 02500 /** 02501 * @brief Clear Stream 3 half transfer flag. 02502 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 02503 * @param DMAx DMAx Instance 02504 * @retval None 02505 */ 02506 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 02507 { 02508 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3); 02509 } 02510 02511 /** 02512 * @brief Clear Stream 4 half transfer flag. 02513 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 02514 * @param DMAx DMAx Instance 02515 * @retval None 02516 */ 02517 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 02518 { 02519 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4); 02520 } 02521 02522 /** 02523 * @brief Clear Stream 5 half transfer flag. 02524 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 02525 * @param DMAx DMAx Instance 02526 * @retval None 02527 */ 02528 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 02529 { 02530 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5); 02531 } 02532 02533 /** 02534 * @brief Clear Stream 6 half transfer flag. 02535 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 02536 * @param DMAx DMAx Instance 02537 * @retval None 02538 */ 02539 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 02540 { 02541 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6); 02542 } 02543 02544 /** 02545 * @brief Clear Stream 7 half transfer flag. 02546 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 02547 * @param DMAx DMAx Instance 02548 * @retval None 02549 */ 02550 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 02551 { 02552 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7); 02553 } 02554 02555 /** 02556 * @brief Clear Stream 0 transfer complete flag. 02557 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 02558 * @param DMAx DMAx Instance 02559 * @retval None 02560 */ 02561 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) 02562 { 02563 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0); 02564 } 02565 02566 /** 02567 * @brief Clear Stream 1 transfer complete flag. 02568 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 02569 * @param DMAx DMAx Instance 02570 * @retval None 02571 */ 02572 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 02573 { 02574 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1); 02575 } 02576 02577 /** 02578 * @brief Clear Stream 2 transfer complete flag. 02579 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 02580 * @param DMAx DMAx Instance 02581 * @retval None 02582 */ 02583 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 02584 { 02585 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2); 02586 } 02587 02588 /** 02589 * @brief Clear Stream 3 transfer complete flag. 02590 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 02591 * @param DMAx DMAx Instance 02592 * @retval None 02593 */ 02594 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 02595 { 02596 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3); 02597 } 02598 02599 /** 02600 * @brief Clear Stream 4 transfer complete flag. 02601 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 02602 * @param DMAx DMAx Instance 02603 * @retval None 02604 */ 02605 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 02606 { 02607 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4); 02608 } 02609 02610 /** 02611 * @brief Clear Stream 5 transfer complete flag. 02612 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 02613 * @param DMAx DMAx Instance 02614 * @retval None 02615 */ 02616 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 02617 { 02618 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5); 02619 } 02620 02621 /** 02622 * @brief Clear Stream 6 transfer complete flag. 02623 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 02624 * @param DMAx DMAx Instance 02625 * @retval None 02626 */ 02627 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 02628 { 02629 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6); 02630 } 02631 02632 /** 02633 * @brief Clear Stream 7 transfer complete flag. 02634 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 02635 * @param DMAx DMAx Instance 02636 * @retval None 02637 */ 02638 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 02639 { 02640 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7); 02641 } 02642 02643 /** 02644 * @brief Clear Stream 0 transfer error flag. 02645 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 02646 * @param DMAx DMAx Instance 02647 * @retval None 02648 */ 02649 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) 02650 { 02651 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0); 02652 } 02653 02654 /** 02655 * @brief Clear Stream 1 transfer error flag. 02656 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 02657 * @param DMAx DMAx Instance 02658 * @retval None 02659 */ 02660 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 02661 { 02662 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1); 02663 } 02664 02665 /** 02666 * @brief Clear Stream 2 transfer error flag. 02667 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 02668 * @param DMAx DMAx Instance 02669 * @retval None 02670 */ 02671 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 02672 { 02673 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2); 02674 } 02675 02676 /** 02677 * @brief Clear Stream 3 transfer error flag. 02678 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 02679 * @param DMAx DMAx Instance 02680 * @retval None 02681 */ 02682 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 02683 { 02684 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3); 02685 } 02686 02687 /** 02688 * @brief Clear Stream 4 transfer error flag. 02689 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 02690 * @param DMAx DMAx Instance 02691 * @retval None 02692 */ 02693 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 02694 { 02695 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4); 02696 } 02697 02698 /** 02699 * @brief Clear Stream 5 transfer error flag. 02700 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 02701 * @param DMAx DMAx Instance 02702 * @retval None 02703 */ 02704 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 02705 { 02706 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5); 02707 } 02708 02709 /** 02710 * @brief Clear Stream 6 transfer error flag. 02711 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 02712 * @param DMAx DMAx Instance 02713 * @retval None 02714 */ 02715 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 02716 { 02717 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6); 02718 } 02719 02720 /** 02721 * @brief Clear Stream 7 transfer error flag. 02722 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 02723 * @param DMAx DMAx Instance 02724 * @retval None 02725 */ 02726 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 02727 { 02728 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7); 02729 } 02730 02731 /** 02732 * @brief Clear Stream 0 direct mode error flag. 02733 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 02734 * @param DMAx DMAx Instance 02735 * @retval None 02736 */ 02737 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) 02738 { 02739 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0); 02740 } 02741 02742 /** 02743 * @brief Clear Stream 1 direct mode error flag. 02744 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 02745 * @param DMAx DMAx Instance 02746 * @retval None 02747 */ 02748 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) 02749 { 02750 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1); 02751 } 02752 02753 /** 02754 * @brief Clear Stream 2 direct mode error flag. 02755 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 02756 * @param DMAx DMAx Instance 02757 * @retval None 02758 */ 02759 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) 02760 { 02761 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2); 02762 } 02763 02764 /** 02765 * @brief Clear Stream 3 direct mode error flag. 02766 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 02767 * @param DMAx DMAx Instance 02768 * @retval None 02769 */ 02770 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) 02771 { 02772 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3); 02773 } 02774 02775 /** 02776 * @brief Clear Stream 4 direct mode error flag. 02777 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 02778 * @param DMAx DMAx Instance 02779 * @retval None 02780 */ 02781 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) 02782 { 02783 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4); 02784 } 02785 02786 /** 02787 * @brief Clear Stream 5 direct mode error flag. 02788 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 02789 * @param DMAx DMAx Instance 02790 * @retval None 02791 */ 02792 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) 02793 { 02794 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5); 02795 } 02796 02797 /** 02798 * @brief Clear Stream 6 direct mode error flag. 02799 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 02800 * @param DMAx DMAx Instance 02801 * @retval None 02802 */ 02803 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) 02804 { 02805 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6); 02806 } 02807 02808 /** 02809 * @brief Clear Stream 7 direct mode error flag. 02810 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 02811 * @param DMAx DMAx Instance 02812 * @retval None 02813 */ 02814 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) 02815 { 02816 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7); 02817 } 02818 02819 /** 02820 * @brief Clear Stream 0 FIFO error flag. 02821 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 02822 * @param DMAx DMAx Instance 02823 * @retval None 02824 */ 02825 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) 02826 { 02827 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0); 02828 } 02829 02830 /** 02831 * @brief Clear Stream 1 FIFO error flag. 02832 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 02833 * @param DMAx DMAx Instance 02834 * @retval None 02835 */ 02836 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) 02837 { 02838 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1); 02839 } 02840 02841 /** 02842 * @brief Clear Stream 2 FIFO error flag. 02843 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 02844 * @param DMAx DMAx Instance 02845 * @retval None 02846 */ 02847 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) 02848 { 02849 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2); 02850 } 02851 02852 /** 02853 * @brief Clear Stream 3 FIFO error flag. 02854 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 02855 * @param DMAx DMAx Instance 02856 * @retval None 02857 */ 02858 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) 02859 { 02860 WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3); 02861 } 02862 02863 /** 02864 * @brief Clear Stream 4 FIFO error flag. 02865 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 02866 * @param DMAx DMAx Instance 02867 * @retval None 02868 */ 02869 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) 02870 { 02871 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4); 02872 } 02873 02874 /** 02875 * @brief Clear Stream 5 FIFO error flag. 02876 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 02877 * @param DMAx DMAx Instance 02878 * @retval None 02879 */ 02880 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) 02881 { 02882 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5); 02883 } 02884 02885 /** 02886 * @brief Clear Stream 6 FIFO error flag. 02887 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 02888 * @param DMAx DMAx Instance 02889 * @retval None 02890 */ 02891 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) 02892 { 02893 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6); 02894 } 02895 02896 /** 02897 * @brief Clear Stream 7 FIFO error flag. 02898 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 02899 * @param DMAx DMAx Instance 02900 * @retval None 02901 */ 02902 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) 02903 { 02904 WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7); 02905 } 02906 02907 /** 02908 * @} 02909 */ 02910 02911 /** @defgroup DMA_LL_EF_IT_Management IT_Management 02912 * @{ 02913 */ 02914 02915 /** 02916 * @brief Enable Half transfer interrupt. 02917 * @rmtoll CR HTIE LL_DMA_EnableIT_HT 02918 * @param DMAx DMAx Instance 02919 * @param Stream This parameter can be one of the following values: 02920 * @arg @ref LL_DMA_STREAM_0 02921 * @arg @ref LL_DMA_STREAM_1 02922 * @arg @ref LL_DMA_STREAM_2 02923 * @arg @ref LL_DMA_STREAM_3 02924 * @arg @ref LL_DMA_STREAM_4 02925 * @arg @ref LL_DMA_STREAM_5 02926 * @arg @ref LL_DMA_STREAM_6 02927 * @arg @ref LL_DMA_STREAM_7 02928 * @retval None 02929 */ 02930 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 02931 { 02932 uint32_t dma_base_addr = (uint32_t)DMAx; 02933 02934 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); 02935 } 02936 02937 /** 02938 * @brief Enable Transfer error interrupt. 02939 * @rmtoll CR TEIE LL_DMA_EnableIT_TE 02940 * @param DMAx DMAx Instance 02941 * @param Stream This parameter can be one of the following values: 02942 * @arg @ref LL_DMA_STREAM_0 02943 * @arg @ref LL_DMA_STREAM_1 02944 * @arg @ref LL_DMA_STREAM_2 02945 * @arg @ref LL_DMA_STREAM_3 02946 * @arg @ref LL_DMA_STREAM_4 02947 * @arg @ref LL_DMA_STREAM_5 02948 * @arg @ref LL_DMA_STREAM_6 02949 * @arg @ref LL_DMA_STREAM_7 02950 * @retval None 02951 */ 02952 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 02953 { 02954 uint32_t dma_base_addr = (uint32_t)DMAx; 02955 02956 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); 02957 } 02958 02959 /** 02960 * @brief Enable Transfer complete interrupt. 02961 * @rmtoll CR TCIE LL_DMA_EnableIT_TC 02962 * @param DMAx DMAx Instance 02963 * @param Stream This parameter can be one of the following values: 02964 * @arg @ref LL_DMA_STREAM_0 02965 * @arg @ref LL_DMA_STREAM_1 02966 * @arg @ref LL_DMA_STREAM_2 02967 * @arg @ref LL_DMA_STREAM_3 02968 * @arg @ref LL_DMA_STREAM_4 02969 * @arg @ref LL_DMA_STREAM_5 02970 * @arg @ref LL_DMA_STREAM_6 02971 * @arg @ref LL_DMA_STREAM_7 02972 * @retval None 02973 */ 02974 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 02975 { 02976 uint32_t dma_base_addr = (uint32_t)DMAx; 02977 02978 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); 02979 } 02980 02981 /** 02982 * @brief Enable Direct mode error interrupt. 02983 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME 02984 * @param DMAx DMAx Instance 02985 * @param Stream This parameter can be one of the following values: 02986 * @arg @ref LL_DMA_STREAM_0 02987 * @arg @ref LL_DMA_STREAM_1 02988 * @arg @ref LL_DMA_STREAM_2 02989 * @arg @ref LL_DMA_STREAM_3 02990 * @arg @ref LL_DMA_STREAM_4 02991 * @arg @ref LL_DMA_STREAM_5 02992 * @arg @ref LL_DMA_STREAM_6 02993 * @arg @ref LL_DMA_STREAM_7 02994 * @retval None 02995 */ 02996 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 02997 { 02998 uint32_t dma_base_addr = (uint32_t)DMAx; 02999 03000 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); 03001 } 03002 03003 /** 03004 * @brief Enable FIFO error interrupt. 03005 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE 03006 * @param DMAx DMAx Instance 03007 * @param Stream This parameter can be one of the following values: 03008 * @arg @ref LL_DMA_STREAM_0 03009 * @arg @ref LL_DMA_STREAM_1 03010 * @arg @ref LL_DMA_STREAM_2 03011 * @arg @ref LL_DMA_STREAM_3 03012 * @arg @ref LL_DMA_STREAM_4 03013 * @arg @ref LL_DMA_STREAM_5 03014 * @arg @ref LL_DMA_STREAM_6 03015 * @arg @ref LL_DMA_STREAM_7 03016 * @retval None 03017 */ 03018 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 03019 { 03020 uint32_t dma_base_addr = (uint32_t)DMAx; 03021 03022 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); 03023 } 03024 03025 /** 03026 * @brief Disable Half transfer interrupt. 03027 * @rmtoll CR HTIE LL_DMA_DisableIT_HT 03028 * @param DMAx DMAx Instance 03029 * @param Stream This parameter can be one of the following values: 03030 * @arg @ref LL_DMA_STREAM_0 03031 * @arg @ref LL_DMA_STREAM_1 03032 * @arg @ref LL_DMA_STREAM_2 03033 * @arg @ref LL_DMA_STREAM_3 03034 * @arg @ref LL_DMA_STREAM_4 03035 * @arg @ref LL_DMA_STREAM_5 03036 * @arg @ref LL_DMA_STREAM_6 03037 * @arg @ref LL_DMA_STREAM_7 03038 * @retval None 03039 */ 03040 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 03041 { 03042 uint32_t dma_base_addr = (uint32_t)DMAx; 03043 03044 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE); 03045 } 03046 03047 /** 03048 * @brief Disable Transfer error interrupt. 03049 * @rmtoll CR TEIE LL_DMA_DisableIT_TE 03050 * @param DMAx DMAx Instance 03051 * @param Stream This parameter can be one of the following values: 03052 * @arg @ref LL_DMA_STREAM_0 03053 * @arg @ref LL_DMA_STREAM_1 03054 * @arg @ref LL_DMA_STREAM_2 03055 * @arg @ref LL_DMA_STREAM_3 03056 * @arg @ref LL_DMA_STREAM_4 03057 * @arg @ref LL_DMA_STREAM_5 03058 * @arg @ref LL_DMA_STREAM_6 03059 * @arg @ref LL_DMA_STREAM_7 03060 * @retval None 03061 */ 03062 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 03063 { 03064 uint32_t dma_base_addr = (uint32_t)DMAx; 03065 03066 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE); 03067 } 03068 03069 /** 03070 * @brief Disable Transfer complete interrupt. 03071 * @rmtoll CR TCIE LL_DMA_DisableIT_TC 03072 * @param DMAx DMAx Instance 03073 * @param Stream This parameter can be one of the following values: 03074 * @arg @ref LL_DMA_STREAM_0 03075 * @arg @ref LL_DMA_STREAM_1 03076 * @arg @ref LL_DMA_STREAM_2 03077 * @arg @ref LL_DMA_STREAM_3 03078 * @arg @ref LL_DMA_STREAM_4 03079 * @arg @ref LL_DMA_STREAM_5 03080 * @arg @ref LL_DMA_STREAM_6 03081 * @arg @ref LL_DMA_STREAM_7 03082 * @retval None 03083 */ 03084 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 03085 { 03086 uint32_t dma_base_addr = (uint32_t)DMAx; 03087 03088 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE); 03089 } 03090 03091 /** 03092 * @brief Disable Direct mode error interrupt. 03093 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME 03094 * @param DMAx DMAx Instance 03095 * @param Stream This parameter can be one of the following values: 03096 * @arg @ref LL_DMA_STREAM_0 03097 * @arg @ref LL_DMA_STREAM_1 03098 * @arg @ref LL_DMA_STREAM_2 03099 * @arg @ref LL_DMA_STREAM_3 03100 * @arg @ref LL_DMA_STREAM_4 03101 * @arg @ref LL_DMA_STREAM_5 03102 * @arg @ref LL_DMA_STREAM_6 03103 * @arg @ref LL_DMA_STREAM_7 03104 * @retval None 03105 */ 03106 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 03107 { 03108 uint32_t dma_base_addr = (uint32_t)DMAx; 03109 03110 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE); 03111 } 03112 03113 /** 03114 * @brief Disable FIFO error interrupt. 03115 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE 03116 * @param DMAx DMAx Instance 03117 * @param Stream This parameter can be one of the following values: 03118 * @arg @ref LL_DMA_STREAM_0 03119 * @arg @ref LL_DMA_STREAM_1 03120 * @arg @ref LL_DMA_STREAM_2 03121 * @arg @ref LL_DMA_STREAM_3 03122 * @arg @ref LL_DMA_STREAM_4 03123 * @arg @ref LL_DMA_STREAM_5 03124 * @arg @ref LL_DMA_STREAM_6 03125 * @arg @ref LL_DMA_STREAM_7 03126 * @retval None 03127 */ 03128 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 03129 { 03130 uint32_t dma_base_addr = (uint32_t)DMAx; 03131 03132 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE); 03133 } 03134 03135 /** 03136 * @brief Check if Half transfer interrup is enabled. 03137 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT 03138 * @param DMAx DMAx Instance 03139 * @param Stream This parameter can be one of the following values: 03140 * @arg @ref LL_DMA_STREAM_0 03141 * @arg @ref LL_DMA_STREAM_1 03142 * @arg @ref LL_DMA_STREAM_2 03143 * @arg @ref LL_DMA_STREAM_3 03144 * @arg @ref LL_DMA_STREAM_4 03145 * @arg @ref LL_DMA_STREAM_5 03146 * @arg @ref LL_DMA_STREAM_6 03147 * @arg @ref LL_DMA_STREAM_7 03148 * @retval State of bit (1 or 0). 03149 */ 03150 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 03151 { 03152 uint32_t dma_base_addr = (uint32_t)DMAx; 03153 03154 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL); 03155 } 03156 03157 /** 03158 * @brief Check if Transfer error nterrup is enabled. 03159 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE 03160 * @param DMAx DMAx Instance 03161 * @param Stream This parameter can be one of the following values: 03162 * @arg @ref LL_DMA_STREAM_0 03163 * @arg @ref LL_DMA_STREAM_1 03164 * @arg @ref LL_DMA_STREAM_2 03165 * @arg @ref LL_DMA_STREAM_3 03166 * @arg @ref LL_DMA_STREAM_4 03167 * @arg @ref LL_DMA_STREAM_5 03168 * @arg @ref LL_DMA_STREAM_6 03169 * @arg @ref LL_DMA_STREAM_7 03170 * @retval State of bit (1 or 0). 03171 */ 03172 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 03173 { 03174 uint32_t dma_base_addr = (uint32_t)DMAx; 03175 03176 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL); 03177 } 03178 03179 /** 03180 * @brief Check if Transfer complete interrup is enabled. 03181 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC 03182 * @param DMAx DMAx Instance 03183 * @param Stream This parameter can be one of the following values: 03184 * @arg @ref LL_DMA_STREAM_0 03185 * @arg @ref LL_DMA_STREAM_1 03186 * @arg @ref LL_DMA_STREAM_2 03187 * @arg @ref LL_DMA_STREAM_3 03188 * @arg @ref LL_DMA_STREAM_4 03189 * @arg @ref LL_DMA_STREAM_5 03190 * @arg @ref LL_DMA_STREAM_6 03191 * @arg @ref LL_DMA_STREAM_7 03192 * @retval State of bit (1 or 0). 03193 */ 03194 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 03195 { 03196 uint32_t dma_base_addr = (uint32_t)DMAx; 03197 03198 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL); 03199 } 03200 03201 /** 03202 * @brief Check if Direct mode error interrupt is enabled. 03203 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME 03204 * @param DMAx DMAx Instance 03205 * @param Stream This parameter can be one of the following values: 03206 * @arg @ref LL_DMA_STREAM_0 03207 * @arg @ref LL_DMA_STREAM_1 03208 * @arg @ref LL_DMA_STREAM_2 03209 * @arg @ref LL_DMA_STREAM_3 03210 * @arg @ref LL_DMA_STREAM_4 03211 * @arg @ref LL_DMA_STREAM_5 03212 * @arg @ref LL_DMA_STREAM_6 03213 * @arg @ref LL_DMA_STREAM_7 03214 * @retval State of bit (1 or 0). 03215 */ 03216 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 03217 { 03218 uint32_t dma_base_addr = (uint32_t)DMAx; 03219 03220 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL); 03221 } 03222 03223 /** 03224 * @brief Check if FIFO error interrup is enabled. 03225 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE 03226 * @param DMAx DMAx Instance 03227 * @param Stream This parameter can be one of the following values: 03228 * @arg @ref LL_DMA_STREAM_0 03229 * @arg @ref LL_DMA_STREAM_1 03230 * @arg @ref LL_DMA_STREAM_2 03231 * @arg @ref LL_DMA_STREAM_3 03232 * @arg @ref LL_DMA_STREAM_4 03233 * @arg @ref LL_DMA_STREAM_5 03234 * @arg @ref LL_DMA_STREAM_6 03235 * @arg @ref LL_DMA_STREAM_7 03236 * @retval State of bit (1 or 0). 03237 */ 03238 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 03239 { 03240 uint32_t dma_base_addr = (uint32_t)DMAx; 03241 03242 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL); 03243 } 03244 03245 /** 03246 * @} 03247 */ 03248 03249 #if defined(USE_FULL_LL_DRIVER) 03250 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions 03251 * @{ 03252 */ 03253 03254 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); 03255 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); 03256 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); 03257 03258 /** 03259 * @} 03260 */ 03261 #endif /* USE_FULL_LL_DRIVER */ 03262 03263 /** 03264 * @} 03265 */ 03266 03267 /** 03268 * @} 03269 */ 03270 03271 #endif /* DMA1 || DMA2 */ 03272 03273 /** 03274 * @} 03275 */ 03276 03277 #ifdef __cplusplus 03278 } 03279 #endif 03280 03281 #endif /* __STM32H7xx_LL_DMA_H */ 03282
1.7.6.1