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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_exti.c 00004 * @author MCD Application Team 00005 * @brief EXTI LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 #if defined(USE_FULL_LL_DRIVER) 00019 00020 /* Includes ------------------------------------------------------------------*/ 00021 #include "stm32h7xx_ll_exti.h" 00022 #ifdef USE_FULL_ASSERT 00023 #include "stm32_assert.h" 00024 #else 00025 #define assert_param(expr) ((void)0U) 00026 #endif 00027 00028 /** @addtogroup STM32H7xx_LL_Driver 00029 * @{ 00030 */ 00031 00032 #if defined (EXTI) 00033 00034 /** @defgroup EXTI_LL EXTI 00035 * @{ 00036 */ 00037 00038 /* Private types -------------------------------------------------------------*/ 00039 /* Private variables ---------------------------------------------------------*/ 00040 /* Private constants ---------------------------------------------------------*/ 00041 /* Private macros ------------------------------------------------------------*/ 00042 /** @addtogroup EXTI_LL_Private_Macros 00043 * @{ 00044 */ 00045 00046 #define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) 00047 #define IS_LL_EXTI_LINE_32_63(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_32_63) == 0x00000000U) 00048 #define IS_LL_EXTI_LINE_64_95(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_64_95) == 0x00000000U) 00049 00050 #define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ 00051 || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ 00052 || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) 00053 00054 00055 #define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ 00056 || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ 00057 || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ 00058 || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) 00059 00060 /** 00061 * @} 00062 */ 00063 00064 /* Private function prototypes -----------------------------------------------*/ 00065 00066 /* Exported functions --------------------------------------------------------*/ 00067 /** @addtogroup EXTI_LL_Exported_Functions 00068 * @{ 00069 */ 00070 00071 /** @addtogroup EXTI_LL_EF_Init 00072 * @{ 00073 */ 00074 00075 /** 00076 * @brief De-initialize the EXTI registers to their default reset values. 00077 * @retval An ErrorStatus enumeration value: 00078 * - SUCCESS: EXTI registers are de-initialized 00079 * - ERROR: not applicable 00080 */ 00081 ErrorStatus LL_EXTI_DeInit(void) 00082 { 00083 /* Rising Trigger selection register set to default reset values */ 00084 LL_EXTI_WriteReg(RTSR1, 0x00000000U); 00085 LL_EXTI_WriteReg(RTSR2, 0x00000000U); 00086 LL_EXTI_WriteReg(RTSR3, 0x00000000U); 00087 00088 /* Falling Trigger selection register set to default reset values */ 00089 LL_EXTI_WriteReg(FTSR1, 0x00000000U); 00090 LL_EXTI_WriteReg(FTSR2, 0x00000000U); 00091 LL_EXTI_WriteReg(FTSR3, 0x00000000U); 00092 00093 /* Software interrupt event register set to default reset values */ 00094 LL_EXTI_WriteReg(SWIER1, 0x00000000U); 00095 LL_EXTI_WriteReg(SWIER2, 0x00000000U); 00096 LL_EXTI_WriteReg(SWIER3, 0x00000000U); 00097 00098 /* D3 Pending register set to default reset values */ 00099 LL_EXTI_WriteReg(D3PMR1, 0x00000000U); 00100 LL_EXTI_WriteReg(D3PMR2, 0x00000000U); 00101 LL_EXTI_WriteReg(D3PMR3, 0x00000000U); 00102 00103 /* D3 Pending clear selection register low to default reset values */ 00104 LL_EXTI_WriteReg(D3PCR1L, 0x00000000U); 00105 LL_EXTI_WriteReg(D3PCR2L, 0x00000000U); 00106 LL_EXTI_WriteReg(D3PCR3L, 0x00000000U); 00107 00108 /* D3 Pending clear selection register high to default reset values */ 00109 LL_EXTI_WriteReg(D3PCR1H, 0x00000000U); 00110 LL_EXTI_WriteReg(D3PCR2H, 0x00000000U); 00111 LL_EXTI_WriteReg(D3PCR3H, 0x00000000U); 00112 00113 /* Interrupt mask register reset */ 00114 LL_EXTI_WriteReg(IMR1, 0x00000000U); 00115 LL_EXTI_WriteReg(IMR2, 0x00000000U); 00116 LL_EXTI_WriteReg(IMR3, 0x00000000U); 00117 00118 /* Event mask register reset */ 00119 LL_EXTI_WriteReg(EMR1, 0x00000000U); 00120 LL_EXTI_WriteReg(EMR2, 0x00000000U); 00121 LL_EXTI_WriteReg(EMR3, 0x00000000U); 00122 00123 /* Clear Pending requests */ 00124 LL_EXTI_WriteReg(PR1, EXTI_PR1_PR_Msk); 00125 LL_EXTI_WriteReg(PR2, EXTI_PR2_PR_Msk); 00126 LL_EXTI_WriteReg(PR3, EXTI_PR3_PR_Msk); 00127 00128 #if defined(DUAL_CORE) 00129 /* Interrupt mask register set to default reset values for Core 2 (Coretx-M4)*/ 00130 LL_EXTI_WriteReg(C2IMR1, 0x00000000U); 00131 LL_EXTI_WriteReg(C2IMR2, 0x00000000U); 00132 LL_EXTI_WriteReg(C2IMR3, 0x00000000U); 00133 00134 /* Event mask register set to default reset values */ 00135 LL_EXTI_WriteReg(C2EMR1, 0x00000000U); 00136 LL_EXTI_WriteReg(C2EMR2, 0x00000000U); 00137 LL_EXTI_WriteReg(C2EMR3, 0x00000000U); 00138 00139 /* Clear Pending requests */ 00140 LL_EXTI_WriteReg(C2PR1, EXTI_PR1_PR_Msk); 00141 LL_EXTI_WriteReg(C2PR2, EXTI_PR2_PR_Msk); 00142 LL_EXTI_WriteReg(C2PR3, EXTI_PR3_PR_Msk); 00143 00144 #endif /* DUAL_CORE*/ 00145 return SUCCESS; 00146 } 00147 00148 /** 00149 * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. 00150 * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. 00151 * @retval An ErrorStatus enumeration value: 00152 * - SUCCESS: EXTI registers are initialized 00153 * - ERROR: not applicable 00154 */ 00155 ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) 00156 { 00157 ErrorStatus status = SUCCESS; 00158 /* Check the parameters */ 00159 assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); 00160 assert_param(IS_LL_EXTI_LINE_32_63(EXTI_InitStruct->Line_32_63)); 00161 assert_param(IS_LL_EXTI_LINE_64_95(EXTI_InitStruct->Line_64_95)); 00162 assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); 00163 assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); 00164 00165 /* ENABLE LineCommand */ 00166 if (EXTI_InitStruct->LineCommand != DISABLE) 00167 { 00168 assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); 00169 00170 /* Configure EXTI Lines in range from 0 to 31 */ 00171 if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) 00172 { 00173 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT) 00174 { 00175 /* Enable IT on provided Lines for Cortex-M7*/ 00176 LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); 00177 } 00178 else 00179 { 00180 /* Disable IT on provided Lines for Cortex-M7*/ 00181 LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); 00182 } 00183 00184 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT) 00185 { 00186 /* Enable event on provided Lines for Cortex-M7 */ 00187 LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); 00188 } 00189 else 00190 { 00191 /* Disable event on provided Lines for Cortex-M7 */ 00192 LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); 00193 } 00194 #if defined(DUAL_CORE) 00195 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT) 00196 { 00197 /* Enable IT on provided Lines for Cortex-M4 */ 00198 LL_C2_EXTI_EnableIT_0_31 (EXTI_InitStruct->Line_0_31); 00199 } 00200 else 00201 { 00202 /* Disable IT on provided Lines for Cortex-M4*/ 00203 LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); 00204 } 00205 00206 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT) 00207 { 00208 /* Enable event on provided Lines for Cortex-M4 */ 00209 LL_C2_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); 00210 } 00211 else 00212 { 00213 /* Disable event on provided Lines for Cortex-M4*/ 00214 LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); 00215 } 00216 #endif /* DUAL_CORE */ 00217 00218 if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) 00219 { 00220 switch (EXTI_InitStruct->Trigger) 00221 { 00222 case LL_EXTI_TRIGGER_RISING: 00223 /* First Disable Falling Trigger on provided Lines */ 00224 LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); 00225 /* Then Enable Rising Trigger on provided Lines */ 00226 LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); 00227 break; 00228 case LL_EXTI_TRIGGER_FALLING: 00229 /* First Disable Rising Trigger on provided Lines */ 00230 LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); 00231 /* Then Enable Falling Trigger on provided Lines */ 00232 LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); 00233 break; 00234 case LL_EXTI_TRIGGER_RISING_FALLING: 00235 LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); 00236 LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); 00237 break; 00238 default: 00239 status = ERROR; 00240 break; 00241 } 00242 } 00243 } 00244 /* Configure EXTI Lines in range from 32 to 63 */ 00245 if (EXTI_InitStruct->Line_32_63 != LL_EXTI_LINE_NONE) 00246 { 00247 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT) 00248 { 00249 /* Enable IT on provided Lines for Cortex-M7*/ 00250 LL_EXTI_EnableIT_32_63(EXTI_InitStruct->Line_32_63); 00251 } 00252 else 00253 { 00254 /* Disable IT on provided Lines for Cortex-M7*/ 00255 LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); 00256 } 00257 00258 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT) 00259 { 00260 /* Enable event on provided Lines for Cortex-M7 */ 00261 LL_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); 00262 } 00263 else 00264 { 00265 /* Disable event on provided Lines for Cortex-M7 */ 00266 LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); 00267 } 00268 #if defined(DUAL_CORE) 00269 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT) 00270 { 00271 /* Enable IT on provided Lines for Cortex-M4 */ 00272 LL_C2_EXTI_EnableIT_32_63 (EXTI_InitStruct->Line_32_63); 00273 } 00274 else 00275 { 00276 /* Disable IT on provided Lines for Cortex-M4 */ 00277 LL_C2_EXTI_DisableIT_32_63 (EXTI_InitStruct->Line_32_63); 00278 } 00279 00280 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT) 00281 { 00282 /* Enable event on provided Lines for Cortex-M4 */ 00283 LL_C2_EXTI_EnableEvent_32_63(EXTI_InitStruct->Line_32_63); 00284 } 00285 else 00286 { 00287 /* Disable event on provided Lines for Cortex-M4 */ 00288 LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); 00289 } 00290 #endif /* DUAL_CORE */ 00291 00292 if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) 00293 { 00294 switch (EXTI_InitStruct->Trigger) 00295 { 00296 case LL_EXTI_TRIGGER_RISING: 00297 /* First Disable Falling Trigger on provided Lines */ 00298 LL_EXTI_DisableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); 00299 /* Then Enable IT on provided Lines */ 00300 LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); 00301 break; 00302 case LL_EXTI_TRIGGER_FALLING: 00303 /* First Disable Rising Trigger on provided Lines */ 00304 LL_EXTI_DisableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); 00305 /* Then Enable Falling Trigger on provided Lines */ 00306 LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); 00307 break; 00308 case LL_EXTI_TRIGGER_RISING_FALLING: 00309 LL_EXTI_EnableRisingTrig_32_63(EXTI_InitStruct->Line_32_63); 00310 LL_EXTI_EnableFallingTrig_32_63(EXTI_InitStruct->Line_32_63); 00311 break; 00312 default: 00313 status = ERROR; 00314 break; 00315 } 00316 } 00317 } 00318 /* Configure EXTI Lines in range from 64 to 95 */ 00319 if (EXTI_InitStruct->Line_64_95 != LL_EXTI_LINE_NONE) 00320 { 00321 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_IT) == LL_EXTI_MODE_IT) 00322 { 00323 /* Enable IT on provided Lines for Cortex-M7*/ 00324 LL_EXTI_EnableIT_64_95(EXTI_InitStruct->Line_64_95); 00325 } 00326 else 00327 { 00328 /* Disable IT on provided Lines for Cortex-M7*/ 00329 LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95); 00330 } 00331 00332 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_EVENT) == LL_EXTI_MODE_EVENT) 00333 { 00334 /* Enable event on provided Lines for Cortex-M7 */ 00335 LL_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95); 00336 } 00337 else 00338 { 00339 /* Disable event on provided Lines for Cortex-M7 */ 00340 LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); 00341 } 00342 00343 #if defined(DUAL_CORE) 00344 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_IT) == LL_EXTI_MODE_C2_IT) 00345 { 00346 /* Enable IT on provided Lines for Cortex-M4 */ 00347 LL_C2_EXTI_EnableIT_64_95 (EXTI_InitStruct->Line_64_95); 00348 } 00349 else 00350 { 00351 /* Disable IT on provided Lines for Cortex-M4 */ 00352 LL_C2_EXTI_DisableIT_64_95 (EXTI_InitStruct->Line_64_95); 00353 } 00354 00355 if((EXTI_InitStruct->Mode & LL_EXTI_MODE_C2_EVENT) == LL_EXTI_MODE_C2_EVENT) 00356 { 00357 /* Enable event on provided Lines for Cortex-M4 */ 00358 LL_C2_EXTI_EnableEvent_64_95(EXTI_InitStruct->Line_64_95); 00359 } 00360 else 00361 { 00362 /* Disable event on provided Lines for Cortex-M4 */ 00363 LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); 00364 } 00365 #endif /* DUAL_CORE */ 00366 00367 if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) 00368 { 00369 switch (EXTI_InitStruct->Trigger) 00370 { 00371 case LL_EXTI_TRIGGER_RISING: 00372 /* First Disable Falling Trigger on provided Lines */ 00373 LL_EXTI_DisableFallingTrig_64_95(EXTI_InitStruct->Line_64_95); 00374 /* Then Enable IT on provided Lines */ 00375 LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95); 00376 break; 00377 case LL_EXTI_TRIGGER_FALLING: 00378 /* First Disable Rising Trigger on provided Lines */ 00379 LL_EXTI_DisableRisingTrig_64_95(EXTI_InitStruct->Line_64_95); 00380 /* Then Enable Falling Trigger on provided Lines */ 00381 LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95); 00382 break; 00383 case LL_EXTI_TRIGGER_RISING_FALLING: 00384 LL_EXTI_EnableRisingTrig_64_95(EXTI_InitStruct->Line_64_95); 00385 LL_EXTI_EnableFallingTrig_64_95(EXTI_InitStruct->Line_64_95); 00386 break; 00387 default: 00388 status = ERROR; 00389 break; 00390 } 00391 } 00392 } 00393 } 00394 else /* DISABLE LineCommand */ 00395 { 00396 /* Disable IT on provided Lines for Cortex-M7*/ 00397 LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); 00398 LL_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); 00399 LL_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95); 00400 00401 /* Disable event on provided Lines for Cortex-M7 */ 00402 LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); 00403 LL_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); 00404 LL_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); 00405 00406 #if defined(DUAL_CORE) 00407 /* Disable IT on provided Lines for Cortex-M4*/ 00408 LL_C2_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); 00409 LL_C2_EXTI_DisableIT_32_63(EXTI_InitStruct->Line_32_63); 00410 LL_C2_EXTI_DisableIT_64_95(EXTI_InitStruct->Line_64_95); 00411 00412 /* Disable event on provided Lines for Cortex-M4 */ 00413 LL_C2_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); 00414 LL_C2_EXTI_DisableEvent_32_63(EXTI_InitStruct->Line_32_63); 00415 LL_C2_EXTI_DisableEvent_64_95(EXTI_InitStruct->Line_64_95); 00416 #endif /* DUAL_CORE */ 00417 } 00418 00419 return status; 00420 } 00421 00422 /** 00423 * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. 00424 * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. 00425 * @retval None 00426 */ 00427 void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) 00428 { 00429 EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; 00430 EXTI_InitStruct->Line_32_63 = LL_EXTI_LINE_NONE; 00431 EXTI_InitStruct->Line_64_95 = LL_EXTI_LINE_NONE; 00432 EXTI_InitStruct->LineCommand = DISABLE; 00433 EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; 00434 EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; 00435 } 00436 00437 /** 00438 * @} 00439 */ 00440 00441 /** 00442 * @} 00443 */ 00444 00445 /** 00446 * @} 00447 */ 00448 00449 #endif /* defined (EXTI) */ 00450 00451 /** 00452 * @} 00453 */ 00454 00455 #endif /* USE_FULL_LL_DRIVER */ 00456
1.7.6.1