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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_hrtim.h 00004 * @author MCD Application Team 00005 * @brief Header file of HRTIM LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_LL_HRTIM_H 00021 #define STM32H7xx_LL_HRTIM_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx.h" 00029 00030 /** @addtogroup STM32H7xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (HRTIM1) 00035 00036 /** @defgroup HRTIM_LL HRTIM 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables 00043 * @{ 00044 */ 00045 static const uint16_t REG_OFFSET_TAB_TIMER[] = 00046 { 00047 0x00U, /* 0: MASTER */ 00048 0x80U, /* 1: TIMER A */ 00049 0x100U, /* 2: TIMER B */ 00050 0x180U, /* 3: TIMER C */ 00051 0x200U, /* 4: TIMER D */ 00052 0x280U /* 5: TIMER E */ 00053 }; 00054 00055 static const uint8_t REG_OFFSET_TAB_ADCxR[] = 00056 { 00057 0x00U, /* 0: HRTIM_ADC1R */ 00058 0x04U, /* 1: HRTIM_ADC2R */ 00059 0x08U, /* 2: HRTIM_ADC3R */ 00060 0x0CU, /* 3: HRTIM_ADC4R */ 00061 }; 00062 00063 static const uint16_t REG_OFFSET_TAB_SETxR[] = 00064 { 00065 0x00U, /* 0: TA1 */ 00066 0x08U, /* 1: TA2 */ 00067 0x80U, /* 2: TB1 */ 00068 0x88U, /* 3: TB2 */ 00069 0x100U, /* 4: TC1 */ 00070 0x108U, /* 5: TC2 */ 00071 0x180U, /* 6: TD1 */ 00072 0x188U, /* 7: TD2 */ 00073 0x200U, /* 8: TE1 */ 00074 0x208U /* 9: TE2 */ 00075 }; 00076 00077 static const uint16_t REG_OFFSET_TAB_OUTxR[] = 00078 { 00079 0x00U, /* 0: TA1 */ 00080 0x00U, /* 1: TA2 */ 00081 0x80U, /* 2: TB1 */ 00082 0x80U, /* 3: TB2 */ 00083 0x100U, /* 4: TC1 */ 00084 0x100U, /* 5: TC2 */ 00085 0x180U, /* 6: TD1 */ 00086 0x180U, /* 7: TD2 */ 00087 0x200U, /* 8: TE1 */ 00088 0x200U /* 9: TE2 */ 00089 }; 00090 00091 static const uint8_t REG_OFFSET_TAB_EECR[] = 00092 { 00093 0x00U, /* LL_HRTIM_EVENT_1 */ 00094 0x00U, /* LL_HRTIM_EVENT_2 */ 00095 0x00U, /* LL_HRTIM_EVENT_3 */ 00096 0x00U, /* LL_HRTIM_EVENT_4 */ 00097 0x00U, /* LL_HRTIM_EVENT_5 */ 00098 0x04U, /* LL_HRTIM_EVENT_6 */ 00099 0x04U, /* LL_HRTIM_EVENT_7 */ 00100 0x04U, /* LL_HRTIM_EVENT_8 */ 00101 0x04U, /* LL_HRTIM_EVENT_9 */ 00102 0x04U /* LL_HRTIM_EVENT_10 */ 00103 }; 00104 00105 static const uint8_t REG_OFFSET_TAB_FLTINR[] = 00106 { 00107 0x00U, /* LL_HRTIM_FAULT_1 */ 00108 0x00U, /* LL_HRTIM_FAULT_2 */ 00109 0x00U, /* LL_HRTIM_FAULT_3 */ 00110 0x00U, /* LL_HRTIM_FAULT_4 */ 00111 0x04U /* LL_HRTIM_FAULT_5 */ 00112 }; 00113 00114 static const uint32_t REG_MASK_TAB_UPDATETRIG[] = 00115 { 00116 0x20000000U, /* 0: MASTER */ 00117 0x01FE0000U, /* 1: TIMER A */ 00118 0x01FE0000U, /* 2: TIMER B */ 00119 0x01FE0000U, /* 3: TIMER C */ 00120 0x01FE0000U, /* 4: TIMER D */ 00121 0x01FE0000U /* 5: TIMER E */ 00122 }; 00123 00124 static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] = 00125 { 00126 12U, /* 0: MASTER */ 00127 0U, /* 1: TIMER A */ 00128 0U, /* 2: TIMER B */ 00129 0U, /* 3: TIMER C */ 00130 0U, /* 4: TIMER D */ 00131 0U /* 5: TIMER E */ 00132 }; 00133 00134 static const uint8_t REG_SHIFT_TAB_EExSRC[] = 00135 { 00136 0U, /* LL_HRTIM_EVENT_1 */ 00137 6U, /* LL_HRTIM_EVENT_2 */ 00138 12U, /* LL_HRTIM_EVENT_3 */ 00139 18U, /* LL_HRTIM_EVENT_4 */ 00140 24U, /* LL_HRTIM_EVENT_5 */ 00141 0U, /* LL_HRTIM_EVENT_6 */ 00142 6U, /* LL_HRTIM_EVENT_7 */ 00143 12U, /* LL_HRTIM_EVENT_8 */ 00144 18U, /* LL_HRTIM_EVENT_9 */ 00145 24U /* LL_HRTIM_EVENT_10 */ 00146 }; 00147 00148 static const uint32_t REG_MASK_TAB_UPDATEGATING[] = 00149 { 00150 HRTIM_MCR_BRSTDMA, /* 0: MASTER */ 00151 HRTIM_TIMCR_UPDGAT, /* 1: TIMER A */ 00152 HRTIM_TIMCR_UPDGAT, /* 2: TIMER B */ 00153 HRTIM_TIMCR_UPDGAT, /* 3: TIMER C */ 00154 HRTIM_TIMCR_UPDGAT, /* 4: TIMER D */ 00155 HRTIM_TIMCR_UPDGAT /* 5: TIMER E */ 00156 }; 00157 00158 static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] = 00159 { 00160 2U, /* 0: MASTER */ 00161 0U, /* 1: TIMER A */ 00162 0U, /* 2: TIMER B */ 00163 0U, /* 3: TIMER C */ 00164 0U, /* 4: TIMER D */ 00165 0U /* 5: TIMER E */ 00166 }; 00167 00168 static const uint8_t REG_SHIFT_TAB_OUTxR[] = 00169 { 00170 0U, /* 0: TA1 */ 00171 16U, /* 1: TA2 */ 00172 0U, /* 2: TB1 */ 00173 16U, /* 3: TB2 */ 00174 0U, /* 4: TC1 */ 00175 16U, /* 5: TC2 */ 00176 0U, /* 6: TD1 */ 00177 16U, /* 7: TD2 */ 00178 0U, /* 8: TE1 */ 00179 16U /* 9: TE2 */ 00180 }; 00181 00182 static const uint8_t REG_SHIFT_TAB_OxSTAT[] = 00183 { 00184 0U, /* 0: TA1 */ 00185 1U, /* 1: TA2 */ 00186 0U, /* 2: TB1 */ 00187 1U, /* 3: TB2 */ 00188 0U, /* 4: TC1 */ 00189 1U, /* 5: TC2 */ 00190 0U, /* 6: TD1 */ 00191 1U, /* 7: TD2 */ 00192 0U, /* 8: TE1 */ 00193 1U /* 9: TE2 */ 00194 }; 00195 00196 static const uint8_t REG_SHIFT_TAB_FLTxE[] = 00197 { 00198 0U, /* LL_HRTIM_FAULT_1 */ 00199 8U, /* LL_HRTIM_FAULT_2 */ 00200 16U, /* LL_HRTIM_FAULT_3 */ 00201 24U, /* LL_HRTIM_FAULT_4 */ 00202 0U /* LL_HRTIM_FAULT_5 */ 00203 }; 00204 00205 /** 00206 * @} 00207 */ 00208 00209 00210 /* Private constants ---------------------------------------------------------*/ 00211 /** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants 00212 * @{ 00213 */ 00214 #define HRTIM_CR1_UDIS_MASK ((uint32_t)(HRTIM_CR1_MUDIS |\ 00215 HRTIM_CR1_TAUDIS |\ 00216 HRTIM_CR1_TBUDIS |\ 00217 HRTIM_CR1_TCUDIS |\ 00218 HRTIM_CR1_TDUDIS |\ 00219 HRTIM_CR1_TEUDIS)) 00220 00221 #define HRTIM_CR2_SWUPD_MASK ((uint32_t)(HRTIM_CR2_MSWU |\ 00222 HRTIM_CR2_TASWU |\ 00223 HRTIM_CR2_TBSWU |\ 00224 HRTIM_CR2_TCSWU |\ 00225 HRTIM_CR2_TDSWU |\ 00226 HRTIM_CR2_TESWU)) 00227 00228 #define HRTIM_CR2_SWRST_MASK ((uint32_t)(HRTIM_CR2_MRST |\ 00229 HRTIM_CR2_TARST |\ 00230 HRTIM_CR2_TBRST |\ 00231 HRTIM_CR2_TCRST |\ 00232 HRTIM_CR2_TDRST |\ 00233 HRTIM_CR2_TERST)) 00234 00235 #define HRTIM_OENR_OEN_MASK ((uint32_t)(HRTIM_OENR_TA1OEN |\ 00236 HRTIM_OENR_TA2OEN |\ 00237 HRTIM_OENR_TB1OEN |\ 00238 HRTIM_OENR_TB2OEN |\ 00239 HRTIM_OENR_TC1OEN |\ 00240 HRTIM_OENR_TC2OEN |\ 00241 HRTIM_OENR_TD1OEN |\ 00242 HRTIM_OENR_TD2OEN |\ 00243 HRTIM_OENR_TE1OEN |\ 00244 HRTIM_OENR_TE2OEN)) 00245 00246 #define HRTIM_OENR_ODIS_MASK ((uint32_t)(HRTIM_ODISR_TA1ODIS |\ 00247 HRTIM_ODISR_TA2ODIS |\ 00248 HRTIM_ODISR_TB1ODIS |\ 00249 HRTIM_ODISR_TB2ODIS |\ 00250 HRTIM_ODISR_TC1ODIS |\ 00251 HRTIM_ODISR_TC2ODIS |\ 00252 HRTIM_ODISR_TD1ODIS |\ 00253 HRTIM_ODISR_TD2ODIS |\ 00254 HRTIM_ODISR_TE1ODIS |\ 00255 HRTIM_ODISR_TE2ODIS)) 00256 00257 #define HRTIM_OUT_CONFIG_MASK ((uint32_t)(HRTIM_OUTR_POL1 |\ 00258 HRTIM_OUTR_IDLM1 |\ 00259 HRTIM_OUTR_IDLES1 |\ 00260 HRTIM_OUTR_FAULT1 |\ 00261 HRTIM_OUTR_CHP1 |\ 00262 HRTIM_OUTR_DIDL1)) 00263 00264 #define HRTIM_EE_CONFIG_MASK ((uint32_t)(HRTIM_EECR1_EE1SRC |\ 00265 HRTIM_EECR1_EE1POL |\ 00266 HRTIM_EECR1_EE1SNS |\ 00267 HRTIM_EECR1_EE1FAST)) 00268 00269 #define HRTIM_FLT_CONFIG_MASK ((uint32_t)(HRTIM_FLTINR1_FLT1P |\ 00270 HRTIM_FLTINR1_FLT1SRC)) 00271 00272 #define HRTIM_BM_CONFIG_MASK ((uint32_t)( HRTIM_BMCR_BMPRSC |\ 00273 HRTIM_BMCR_BMCLK |\ 00274 HRTIM_BMCR_BMOM)) 00275 00276 /** 00277 * @} 00278 */ 00279 00280 00281 /* Private macros ------------------------------------------------------------*/ 00282 /* Exported types ------------------------------------------------------------*/ 00283 /* Exported constants --------------------------------------------------------*/ 00284 /** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants 00285 * @{ 00286 */ 00287 00288 /** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines 00289 * @brief Flags defines which can be used with LL_HRTIM_ReadReg function 00290 * @{ 00291 */ 00292 #define LL_HRTIM_ISR_FLT1 HRTIM_ISR_FLT1 00293 #define LL_HRTIM_ISR_FLT2 HRTIM_ISR_FLT2 00294 #define LL_HRTIM_ISR_FLT3 HRTIM_ISR_FLT3 00295 #define LL_HRTIM_ISR_FLT4 HRTIM_ISR_FLT4 00296 #define LL_HRTIM_ISR_FLT5 HRTIM_ISR_FLT5 00297 #define LL_HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT 00298 #define LL_HRTIM_ISR_BMPER HRTIM_ISR_BMPER 00299 00300 #define LL_HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1 00301 #define LL_HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2 00302 #define LL_HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3 00303 #define LL_HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4 00304 #define LL_HRTIM_MISR_MREP HRTIM_MISR_MREP 00305 #define LL_HRTIM_MISR_SYNC HRTIM_MISR_SYNC 00306 #define LL_HRTIM_MISR_MUPD HRTIM_MISR_MUPD 00307 00308 #define LL_HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1 00309 #define LL_HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2 00310 #define LL_HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3 00311 #define LL_HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4 00312 #define LL_HRTIM_TIMISR_REP HRTIM_TIMISR_REP 00313 #define LL_HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD 00314 #define LL_HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1 00315 #define LL_HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2 00316 #define LL_HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1 00317 #define LL_HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1 00318 #define LL_HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2 00319 #define LL_HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2 00320 #define LL_HRTIM_TIMISR_RST HRTIM_TIMISR_RST 00321 #define LL_HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT 00322 /** 00323 * @} 00324 */ 00325 00326 /** @defgroup HRTIM_LL_EC_IT IT Defines 00327 * @brief IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions 00328 * @{ 00329 */ 00330 #define LL_HRTIM_IER_FLT1IE HRTIM_IER_FLT1IE 00331 #define LL_HRTIM_IER_FLT2IE HRTIM_IER_FLT2IE 00332 #define LL_HRTIM_IER_FLT3IE HRTIM_IER_FLT3IE 00333 #define LL_HRTIM_IER_FLT4IE HRTIM_IER_FLT4IE 00334 #define LL_HRTIM_IER_FLT5IE HRTIM_IER_FLT5IE 00335 #define LL_HRTIM_IER_SYSFLTIE HRTIM_IER_SYSFLTIE 00336 #define LL_HRTIM_IER_BMPERIE HRTIM_IER_BMPERIE 00337 00338 #define LL_HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE 00339 #define LL_HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE 00340 #define LL_HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE 00341 #define LL_HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE 00342 #define LL_HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE 00343 #define LL_HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE 00344 #define LL_HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE 00345 00346 #define LL_HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE 00347 #define LL_HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE 00348 #define LL_HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE 00349 #define LL_HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE 00350 #define LL_HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE 00351 #define LL_HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE 00352 #define LL_HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE 00353 #define LL_HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE 00354 #define LL_HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE 00355 #define LL_HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE 00356 #define LL_HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE 00357 #define LL_HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE 00358 #define LL_HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE 00359 #define LL_HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup HRTIM_LL_EC_SYNCIN_SRC SYNCHRONIZATION INPUT SOURCE 00365 * @{ 00366 * @brief Constants defining defining the synchronization input source. 00367 */ 00368 #define LL_HRTIM_SYNCIN_SRC_NONE 0x00000000U /*!< HRTIM is not synchronized and runs in standalone mode */ 00369 #define LL_HRTIM_SYNCIN_SRC_TIM_EVENT (HRTIM_MCR_SYNC_IN_1) /*!< The HRTIM is synchronized with the on-chip timer */ 00370 #define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */ 00371 /** 00372 * @} 00373 */ 00374 00375 /** @defgroup HRTIM_LL_EC_SYNCOUT_SRC SYNCHRONIZATION OUTPUT SOURCE 00376 * @{ 00377 * @brief Constants defining the source and event to be sent on the synchronization output. 00378 */ 00379 #define LL_HRTIM_SYNCOUT_SRC_MASTER_START 0x00000000U /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event */ 00380 #define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event */ 00381 #define LL_HRTIM_SYNCOUT_SRC_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */ 00382 #define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event */ 00383 /** 00384 * @} 00385 */ 00386 00387 /** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY SYNCHRONIZATION OUTPUT POLARITY 00388 * @{ 00389 * @brief Constants defining the routing and conditioning of the synchronization output event. 00390 */ 00391 #define LL_HRTIM_SYNCOUT_DISABLED 0x00000000U /*!< Synchronization output event is disabled */ 00392 #define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */ 00393 #define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */ 00394 /** 00395 * @} 00396 */ 00397 00398 /** @defgroup HRTIM_LL_EC_TIMER TIMER ID 00399 * @{ 00400 * @brief Constants identifying a timing unit. 00401 */ 00402 #define LL_HRTIM_TIMER_NONE 0U /*!< Master timer identifier */ 00403 #define LL_HRTIM_TIMER_MASTER HRTIM_MCR_MCEN /*!< Master timer identifier */ 00404 #define LL_HRTIM_TIMER_A HRTIM_MCR_TACEN /*!< Timer A identifier */ 00405 #define LL_HRTIM_TIMER_B HRTIM_MCR_TBCEN /*!< Timer B identifier */ 00406 #define LL_HRTIM_TIMER_C HRTIM_MCR_TCCEN /*!< Timer C identifier */ 00407 #define LL_HRTIM_TIMER_D HRTIM_MCR_TDCEN /*!< Timer D identifier */ 00408 #define LL_HRTIM_TIMER_E HRTIM_MCR_TECEN /*!< Timer E identifier */ 00409 #define LL_HRTIM_TIMER_X (HRTIM_MCR_TACEN |\ 00410 HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\ 00411 HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN ) 00412 #define LL_HRTIM_TIMER_ALL (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X) 00413 00414 /** 00415 * @} 00416 */ 00417 00418 /** @defgroup HRTIM_LL_EC_OUTPUT OUTPUT ID 00419 * @{ 00420 * @brief Constants identifying an HRTIM output. 00421 */ 00422 #define LL_HRTIM_OUTPUT_TA1 HRTIM_OENR_TA1OEN /*!< Timer A - Output 1 identifier */ 00423 #define LL_HRTIM_OUTPUT_TA2 HRTIM_OENR_TA2OEN /*!< Timer A - Output 2 identifier */ 00424 #define LL_HRTIM_OUTPUT_TB1 HRTIM_OENR_TB1OEN /*!< Timer B - Output 1 identifier */ 00425 #define LL_HRTIM_OUTPUT_TB2 HRTIM_OENR_TB2OEN /*!< Timer B - Output 2 identifier */ 00426 #define LL_HRTIM_OUTPUT_TC1 HRTIM_OENR_TC1OEN /*!< Timer C - Output 1 identifier */ 00427 #define LL_HRTIM_OUTPUT_TC2 HRTIM_OENR_TC2OEN /*!< Timer C - Output 2 identifier */ 00428 #define LL_HRTIM_OUTPUT_TD1 HRTIM_OENR_TD1OEN /*!< Timer D - Output 1 identifier */ 00429 #define LL_HRTIM_OUTPUT_TD2 HRTIM_OENR_TD2OEN /*!< Timer D - Output 2 identifier */ 00430 #define LL_HRTIM_OUTPUT_TE1 HRTIM_OENR_TE1OEN /*!< Timer E - Output 1 identifier */ 00431 #define LL_HRTIM_OUTPUT_TE2 HRTIM_OENR_TE2OEN /*!< Timer E - Output 2 identifier */ 00432 /** 00433 * @} 00434 */ 00435 00436 /** @defgroup HRTIM_LL_EC_COMPAREUNIT COMPARE UNIT ID 00437 * @{ 00438 * @brief Constants identifying a compare unit. 00439 */ 00440 #define LL_HRTIM_COMPAREUNIT_2 HRTIM_TIMCR_DELCMP2 /*!< Compare unit 2 identifier */ 00441 #define LL_HRTIM_COMPAREUNIT_4 HRTIM_TIMCR_DELCMP4 /*!< Compare unit 4 identifier */ 00442 /** 00443 * @} 00444 */ 00445 00446 /** @defgroup HRTIM_LL_EC_CAPTUREUNIT CAPTURE UNIT ID 00447 * @{ 00448 * @brief Constants identifying a capture unit. 00449 */ 00450 #define LL_HRTIM_CAPTUREUNIT_1 0 /*!< Capture unit 1 identifier */ 00451 #define LL_HRTIM_CAPTUREUNIT_2 1 /*!< Capture unit 2 identifier */ 00452 /** 00453 * @} 00454 */ 00455 00456 /** @defgroup HRTIM_LL_EC_FAULT FAULT ID 00457 * @{ 00458 * @brief Constants identifying a fault channel. 00459 */ 00460 #define LL_HRTIM_FAULT_1 HRTIM_FLTR_FLT1EN /*!< Fault channel 1 identifier */ 00461 #define LL_HRTIM_FAULT_2 HRTIM_FLTR_FLT2EN /*!< Fault channel 2 identifier */ 00462 #define LL_HRTIM_FAULT_3 HRTIM_FLTR_FLT3EN /*!< Fault channel 3 identifier */ 00463 #define LL_HRTIM_FAULT_4 HRTIM_FLTR_FLT4EN /*!< Fault channel 4 identifier */ 00464 #define LL_HRTIM_FAULT_5 HRTIM_FLTR_FLT5EN /*!< Fault channel 5 identifier */ 00465 /** 00466 * @} 00467 */ 00468 00469 /** @defgroup HRTIM_LL_EC_EVENT EXTERNAL EVENT ID 00470 * @{ 00471 * @brief Constants identifying an external event channel. 00472 */ 00473 #define LL_HRTIM_EVENT_1 ((uint32_t)0x00000001U) /*!< External event channel 1 identifier */ 00474 #define LL_HRTIM_EVENT_2 ((uint32_t)0x00000002U) /*!< External event channel 2 identifier */ 00475 #define LL_HRTIM_EVENT_3 ((uint32_t)0x00000004U) /*!< External event channel 3 identifier */ 00476 #define LL_HRTIM_EVENT_4 ((uint32_t)0x00000008U) /*!< External event channel 4 identifier */ 00477 #define LL_HRTIM_EVENT_5 ((uint32_t)0x00000010U) /*!< External event channel 5 identifier */ 00478 #define LL_HRTIM_EVENT_6 ((uint32_t)0x00000020U) /*!< External event channel 6 identifier */ 00479 #define LL_HRTIM_EVENT_7 ((uint32_t)0x00000040U) /*!< External event channel 7 identifier */ 00480 #define LL_HRTIM_EVENT_8 ((uint32_t)0x00000080U) /*!< External event channel 8 identifier */ 00481 #define LL_HRTIM_EVENT_9 ((uint32_t)0x00000100U) /*!< External event channel 9 identifier */ 00482 #define LL_HRTIM_EVENT_10 ((uint32_t)0x00000200U) /*!< External event channel 10 identifier */ 00483 /** 00484 * @} 00485 */ 00486 00487 /** @defgroup HRTIM_LL_EC_OUTPUTSTATE OUTPUT STATE 00488 * @{ 00489 * @brief Constants defining the state of an HRTIM output. 00490 */ 00491 #define LL_HRTIM_OUTPUTSTATE_IDLE ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */ 00492 #define LL_HRTIM_OUTPUTSTATE_RUN ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */ 00493 #define LL_HRTIM_OUTPUTSTATE_FAULT ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */ 00494 /** 00495 * @} 00496 */ 00497 00498 /** @defgroup HRTIM_LL_EC_ADCTRIG ADC TRIGGER 00499 * @{ 00500 * @brief Constants identifying an ADC trigger. 00501 */ 00502 #define LL_HRTIM_ADCTRIG_1 ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */ 00503 #define LL_HRTIM_ADCTRIG_2 ((uint32_t)0x00000001U) /*!< ADC trigger 2 identifier */ 00504 #define LL_HRTIM_ADCTRIG_3 ((uint32_t)0x00000002U) /*!< ADC trigger 3 identifier */ 00505 #define LL_HRTIM_ADCTRIG_4 ((uint32_t)0x00000003U) /*!< ADC trigger 4 identifier */ 00506 /** 00507 * @} 00508 */ 00509 00510 /** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE 00511 * @{ 00512 * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register). 00513 */ 00514 #define LL_HRTIM_ADCTRIG_UPDATE_MASTER 0x00000000U /*!< HRTIM_ADCxR register update is triggered by the Master timer */ 00515 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer A */ 00516 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1) /*!< HRTIM_ADCxR register update is triggered by the Timer B */ 00517 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */ 00518 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2) /*!< HRTIM_ADCxR register update is triggered by the Timer D */ 00519 #define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */ 00520 /** 00521 * @} 00522 */ 00523 00524 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13 ADC TRIGGER 1/3 SOURCE 00525 * @{ 00526 * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3. 00527 */ 00528 #define LL_HRTIM_ADCTRIG_SRC13_NONE 0x00000000U /*!< No ADC trigger event */ 00529 #define LL_HRTIM_ADCTRIG_SRC13_MCMP1 HRTIM_ADC1R_AD1MC1 /*!< ADC Trigger on master compare 1 */ 00530 #define LL_HRTIM_ADCTRIG_SRC13_MCMP2 HRTIM_ADC1R_AD1MC2 /*!< ADC Trigger on master compare 2 */ 00531 #define LL_HRTIM_ADCTRIG_SRC13_MCMP3 HRTIM_ADC1R_AD1MC3 /*!< ADC Trigger on master compare 3 */ 00532 #define LL_HRTIM_ADCTRIG_SRC13_MCMP4 HRTIM_ADC1R_AD1MC4 /*!< ADC Trigger on master compare 4 */ 00533 #define LL_HRTIM_ADCTRIG_SRC13_MPER HRTIM_ADC1R_AD1MPER /*!< ADC Trigger on master period */ 00534 #define LL_HRTIM_ADCTRIG_SRC13_EEV1 HRTIM_ADC1R_AD1EEV1 /*!< ADC Trigger on external event 1 */ 00535 #define LL_HRTIM_ADCTRIG_SRC13_EEV2 HRTIM_ADC1R_AD1EEV2 /*!< ADC Trigger on external event 2 */ 00536 #define LL_HRTIM_ADCTRIG_SRC13_EEV3 HRTIM_ADC1R_AD1EEV3 /*!< ADC Trigger on external event 3 */ 00537 #define LL_HRTIM_ADCTRIG_SRC13_EEV4 HRTIM_ADC1R_AD1EEV4 /*!< ADC Trigger on external event 4 */ 00538 #define LL_HRTIM_ADCTRIG_SRC13_EEV5 HRTIM_ADC1R_AD1EEV5 /*!< ADC Trigger on external event 5 */ 00539 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 HRTIM_ADC1R_AD1TAC2 /*!< ADC Trigger on Timer A compare 2 */ 00540 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 HRTIM_ADC1R_AD1TAC3 /*!< ADC Trigger on Timer A compare 3 */ 00541 #define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 HRTIM_ADC1R_AD1TAC4 /*!< ADC Trigger on Timer A compare 4 */ 00542 #define LL_HRTIM_ADCTRIG_SRC13_TIMAPER HRTIM_ADC1R_AD1TAPER /*!< ADC Trigger on Timer A period */ 00543 #define LL_HRTIM_ADCTRIG_SRC13_TIMARST HRTIM_ADC1R_AD1TARST /*!< ADC Trigger on Timer A reset */ 00544 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 HRTIM_ADC1R_AD1TBC2 /*!< ADC Trigger on Timer B compare 2 */ 00545 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 HRTIM_ADC1R_AD1TBC3 /*!< ADC Trigger on Timer B compare 3 */ 00546 #define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 HRTIM_ADC1R_AD1TBC4 /*!< ADC Trigger on Timer B compare 4 */ 00547 #define LL_HRTIM_ADCTRIG_SRC13_TIMBPER HRTIM_ADC1R_AD1TBPER /*!< ADC Trigger on Timer B period */ 00548 #define LL_HRTIM_ADCTRIG_SRC13_TIMBRST HRTIM_ADC1R_AD1TBRST /*!< ADC Trigger on Timer B reset */ 00549 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 HRTIM_ADC1R_AD1TCC2 /*!< ADC Trigger on Timer C compare 2 */ 00550 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 HRTIM_ADC1R_AD1TCC3 /*!< ADC Trigger on Timer C compare 3 */ 00551 #define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 HRTIM_ADC1R_AD1TCC4 /*!< ADC Trigger on Timer C compare 4 */ 00552 #define LL_HRTIM_ADCTRIG_SRC13_TIMCPER HRTIM_ADC1R_AD1TCPER /*!< ADC Trigger on Timer C period */ 00553 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 HRTIM_ADC1R_AD1TDC2 /*!< ADC Trigger on Timer D compare 2 */ 00554 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 HRTIM_ADC1R_AD1TDC3 /*!< ADC Trigger on Timer D compare 3 */ 00555 #define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 HRTIM_ADC1R_AD1TDC4 /*!< ADC Trigger on Timer D compare 4 */ 00556 #define LL_HRTIM_ADCTRIG_SRC13_TIMDPER HRTIM_ADC1R_AD1TDPER /*!< ADC Trigger on Timer D period */ 00557 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 HRTIM_ADC1R_AD1TEC2 /*!< ADC Trigger on Timer E compare 2 */ 00558 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 HRTIM_ADC1R_AD1TEC3 /*!< ADC Trigger on Timer E compare 3 */ 00559 #define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 HRTIM_ADC1R_AD1TEC4 /*!< ADC Trigger on Timer E compare 4 */ 00560 #define LL_HRTIM_ADCTRIG_SRC13_TIMEPER HRTIM_ADC1R_AD1TEPER /*!< ADC Trigger on Timer E period */ 00561 /** 00562 * @} 00563 */ 00564 00565 /** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24 ADC TRIGGER 2/4 SOURCE 00566 * @{ 00567 * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4. 00568 */ 00569 #define LL_HRTIM_ADCTRIG_SRC24_NONE 0x00000000U /*!< No ADC trigger event */ 00570 #define LL_HRTIM_ADCTRIG_SRC24_MCMP1 HRTIM_ADC2R_AD2MC1 /*!< ADC Trigger on master compare 1 */ 00571 #define LL_HRTIM_ADCTRIG_SRC24_MCMP2 HRTIM_ADC2R_AD2MC2 /*!< ADC Trigger on master compare 2 */ 00572 #define LL_HRTIM_ADCTRIG_SRC24_MCMP3 HRTIM_ADC2R_AD2MC3 /*!< ADC Trigger on master compare 3 */ 00573 #define LL_HRTIM_ADCTRIG_SRC24_MCMP4 HRTIM_ADC2R_AD2MC4 /*!< ADC Trigger on master compare 4 */ 00574 #define LL_HRTIM_ADCTRIG_SRC24_MPER HRTIM_ADC2R_AD2MPER /*!< ADC Trigger on master period */ 00575 #define LL_HRTIM_ADCTRIG_SRC24_EEV6 HRTIM_ADC2R_AD2EEV6 /*!< ADC Trigger on external event 6 */ 00576 #define LL_HRTIM_ADCTRIG_SRC24_EEV7 HRTIM_ADC2R_AD2EEV7 /*!< ADC Trigger on external event 7 */ 00577 #define LL_HRTIM_ADCTRIG_SRC24_EEV8 HRTIM_ADC2R_AD2EEV8 /*!< ADC Trigger on external event 8 */ 00578 #define LL_HRTIM_ADCTRIG_SRC24_EEV9 HRTIM_ADC2R_AD2EEV9 /*!< ADC Trigger on external event 9 */ 00579 #define LL_HRTIM_ADCTRIG_SRC24_EEV10 HRTIM_ADC2R_AD2EEV10 /*!< ADC Trigger on external event 10 */ 00580 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 HRTIM_ADC2R_AD2TAC2 /*!< ADC Trigger on Timer A compare 2 */ 00581 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 HRTIM_ADC2R_AD2TAC3 /*!< ADC Trigger on Timer A compare 3 */ 00582 #define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 HRTIM_ADC2R_AD2TAC4 /*!< ADC Trigger on Timer A compare 4 */ 00583 #define LL_HRTIM_ADCTRIG_SRC24_TIMAPER HRTIM_ADC2R_AD2TAPER /*!< ADC Trigger on Timer A period */ 00584 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 HRTIM_ADC2R_AD2TBC2 /*!< ADC Trigger on Timer B compare 2 */ 00585 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 HRTIM_ADC2R_AD2TBC3 /*!< ADC Trigger on Timer B compare 3 */ 00586 #define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 HRTIM_ADC2R_AD2TBC4 /*!< ADC Trigger on Timer B compare 4 */ 00587 #define LL_HRTIM_ADCTRIG_SRC24_TIMBPER HRTIM_ADC2R_AD2TBPER /*!< ADC Trigger on Timer B period */ 00588 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 HRTIM_ADC2R_AD2TCC2 /*!< ADC Trigger on Timer C compare 2 */ 00589 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 HRTIM_ADC2R_AD2TCC3 /*!< ADC Trigger on Timer C compare 3 */ 00590 #define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 HRTIM_ADC2R_AD2TCC4 /*!< ADC Trigger on Timer C compare 4 */ 00591 #define LL_HRTIM_ADCTRIG_SRC24_TIMCPER HRTIM_ADC2R_AD2TCPER /*!< ADC Trigger on Timer C period */ 00592 #define LL_HRTIM_ADCTRIG_SRC24_TIMCRST HRTIM_ADC2R_AD2TCRST /*!< ADC Trigger on Timer C reset */ 00593 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 HRTIM_ADC2R_AD2TDC2 /*!< ADC Trigger on Timer D compare 2 */ 00594 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 HRTIM_ADC2R_AD2TDC3 /*!< ADC Trigger on Timer D compare 3 */ 00595 #define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 HRTIM_ADC2R_AD2TDC4 /*!< ADC Trigger on Timer D compare 4 */ 00596 #define LL_HRTIM_ADCTRIG_SRC24_TIMDPER HRTIM_ADC2R_AD2TDPER /*!< ADC Trigger on Timer D period */ 00597 #define LL_HRTIM_ADCTRIG_SRC24_TIMDRST HRTIM_ADC2R_AD2TDRST /*!< ADC Trigger on Timer D reset */ 00598 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 HRTIM_ADC2R_AD2TEC2 /*!< ADC Trigger on Timer E compare 2 */ 00599 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 HRTIM_ADC2R_AD2TEC3 /*!< ADC Trigger on Timer E compare 3 */ 00600 #define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 HRTIM_ADC2R_AD2TEC4 /*!< ADC Trigger on Timer E compare 4 */ 00601 #define LL_HRTIM_ADCTRIG_SRC24_TIMERST HRTIM_ADC2R_AD2TERST /*!< ADC Trigger on Timer E reset */ 00602 /** 00603 * @} 00604 */ 00605 00606 /** @defgroup HRTIM_LL_EC_PRESCALERRATIO PRESCALER RATIO 00607 * @{ 00608 * @brief Constants defining timer high-resolution clock prescaler ratio. 00609 */ 00610 #define LL_HRTIM_PRESCALERRATIO_DIV1 ((uint32_t)0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */ 00611 #define LL_HRTIM_PRESCALERRATIO_DIV2 ((uint32_t)0x00000006U) /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */ 00612 #define LL_HRTIM_PRESCALERRATIO_DIV4 ((uint32_t)0x00000007U) /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */ 00613 /** 00614 * @} 00615 */ 00616 00617 /** @defgroup HRTIM_LL_EC_MODE COUNTER MODE 00618 * @{ 00619 * @brief Constants defining timer counter operating mode. 00620 */ 00621 #define LL_HRTIM_MODE_CONTINUOUS ((uint32_t)0x00000008U) /*!< The timer operates in continuous (free-running) mode */ 00622 #define LL_HRTIM_MODE_SINGLESHOT 0x00000000U /*!< The timer operates in non retriggerable single-shot mode */ 00623 #define LL_HRTIM_MODE_RETRIGGERABLE ((uint32_t)0x00000010U) /*!< The timer operates in retriggerable single-shot mode */ 00624 /** 00625 * @} 00626 */ 00627 00628 /** @defgroup HRTIM_LL_EC_DACTRIG DAC TRIGGER 00629 * @{ 00630 * @brief Constants defining on which output the DAC synchronization event is sent. 00631 */ 00632 #define LL_HRTIM_DACTRIG_NONE 0x00000000U /*!< No DAC synchronization event generated */ 00633 #define LL_HRTIM_DACTRIG_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */ 00634 #define LL_HRTIM_DACTRIG_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */ 00635 #define LL_HRTIM_DACTRIG_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */ 00636 /** 00637 * @} 00638 */ 00639 00640 /** @defgroup HRTIM_LL_EC_UPDATETRIG UPDATE TRIGGER 00641 * @{ 00642 * @brief Constants defining whether the registers update is done synchronously with any other timer or master update. 00643 */ 00644 #define LL_HRTIM_UPDATETRIG_NONE 0x00000000U /*!< Register update is disabled */ 00645 #define LL_HRTIM_UPDATETRIG_MASTER HRTIM_TIMCR_MSTU /*!< Register update is triggered by the master timer update */ 00646 #define LL_HRTIM_UPDATETRIG_TIMER_A HRTIM_TIMCR_TAU /*!< Register update is triggered by the timer A update */ 00647 #define LL_HRTIM_UPDATETRIG_TIMER_B HRTIM_TIMCR_TBU /*!< Register update is triggered by the timer B update */ 00648 #define LL_HRTIM_UPDATETRIG_TIMER_C HRTIM_TIMCR_TCU /*!< Register update is triggered by the timer C update*/ 00649 #define LL_HRTIM_UPDATETRIG_TIMER_D HRTIM_TIMCR_TDU /*!< Register update is triggered by the timer D update */ 00650 #define LL_HRTIM_UPDATETRIG_TIMER_E HRTIM_TIMCR_TEU /*!< Register update is triggered by the timer E update */ 00651 #define LL_HRTIM_UPDATETRIG_REPETITION HRTIM_TIMCR_TREPU /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/ 00652 #define LL_HRTIM_UPDATETRIG_RESET HRTIM_TIMCR_TRSTU /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */ 00653 /** 00654 * @} 00655 */ 00656 00657 /** @defgroup HRTIM_LL_EC_UPDATEGATING UPDATE GATING 00658 * @{ 00659 * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3. 00660 */ 00661 #define LL_HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */ 00662 #define LL_HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */ 00663 #define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/ 00664 #define LL_HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */ 00665 #define LL_HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */ 00666 #define LL_HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */ 00667 #define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1 */ 00668 #define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */ 00669 #define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */ 00670 /** 00671 * @} 00672 */ 00673 00674 /** @defgroup HRTIM_LL_EC_COMPAREMODE COMPARE MODE 00675 * @{ 00676 * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode. 00677 */ 00678 #define LL_HRTIM_COMPAREMODE_REGULAR 0x00000000U /*!< standard compare mode */ 00679 #define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */ 00680 #define LL_HRTIM_COMPAREMODE_DELAY_CMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */ 00681 #define LL_HRTIM_COMPAREMODE_DELAY_CMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */ 00682 /** 00683 * @} 00684 */ 00685 00686 /** @defgroup HRTIM_LL_EC_RESETTRIG RESET TRIGGER 00687 * @{ 00688 * @brief Constants defining the events that can be selected to trigger the reset of the timer counter. 00689 */ 00690 #define LL_HRTIM_RESETTRIG_NONE 0x00000000U /*!< No counter reset trigger */ 00691 #define LL_HRTIM_RESETTRIG_UPDATE HRTIM_RSTR_UPDATE /*!< The timer counter is reset upon update event */ 00692 #define LL_HRTIM_RESETTRIG_CMP2 HRTIM_RSTR_CMP2 /*!< The timer counter is reset upon Timer Compare 2 event */ 00693 #define LL_HRTIM_RESETTRIG_CMP4 HRTIM_RSTR_CMP4 /*!< The timer counter is reset upon Timer Compare 4 event */ 00694 #define LL_HRTIM_RESETTRIG_MASTER_PER HRTIM_RSTR_MSTPER /*!< The timer counter is reset upon master timer period event */ 00695 #define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1 /*!< The timer counter is reset upon master timer Compare 1 event */ 00696 #define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2 /*!< The timer counter is reset upon master timer Compare 2 event */ 00697 #define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3 /*!< The timer counter is reset upon master timer Compare 3 event */ 00698 #define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4 /*!< The timer counter is reset upon master timer Compare 4 event */ 00699 #define LL_HRTIM_RESETTRIG_EEV_1 HRTIM_RSTR_EXTEVNT1 /*!< The timer counter is reset upon external event 1 */ 00700 #define LL_HRTIM_RESETTRIG_EEV_2 HRTIM_RSTR_EXTEVNT2 /*!< The timer counter is reset upon external event 2 */ 00701 #define LL_HRTIM_RESETTRIG_EEV_3 HRTIM_RSTR_EXTEVNT3 /*!< The timer counter is reset upon external event 3 */ 00702 #define LL_HRTIM_RESETTRIG_EEV_4 HRTIM_RSTR_EXTEVNT4 /*!< The timer counter is reset upon external event 4 */ 00703 #define LL_HRTIM_RESETTRIG_EEV_5 HRTIM_RSTR_EXTEVNT5 /*!< The timer counter is reset upon external event 5 */ 00704 #define LL_HRTIM_RESETTRIG_EEV_6 HRTIM_RSTR_EXTEVNT6 /*!< The timer counter is reset upon external event 6 */ 00705 #define LL_HRTIM_RESETTRIG_EEV_7 HRTIM_RSTR_EXTEVNT7 /*!< The timer counter is reset upon external event 7 */ 00706 #define LL_HRTIM_RESETTRIG_EEV_8 HRTIM_RSTR_EXTEVNT8 /*!< The timer counter is reset upon external event 8 */ 00707 #define LL_HRTIM_RESETTRIG_EEV_9 HRTIM_RSTR_EXTEVNT9 /*!< The timer counter is reset upon external event 9 */ 00708 #define LL_HRTIM_RESETTRIG_EEV_10 HRTIM_RSTR_EXTEVNT10 /*!< The timer counter is reset upon external event 10 */ 00709 #define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */ 00710 #define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */ 00711 #define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */ 00712 #define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */ 00713 #define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */ 00714 #define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */ 00715 #define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1 /*!< The timer counter is reset upon other timer Compare 1 event */ 00716 #define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2 /*!< The timer counter is reset upon other timer Compare 2 event */ 00717 #define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4 /*!< The timer counter is reset upon other timer Compare 4 event */ 00718 #define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1 /*!< The timer counter is reset upon other timer Compare 1 event */ 00719 #define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2 /*!< The timer counter is reset upon other timer Compare 2 event */ 00720 #define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4 /*!< The timer counter is reset upon other timer Compare 4 event */ 00721 /** 00722 * @} 00723 */ 00724 00725 /** @defgroup HRTIM_LL_EC_CAPTURETRIG CAPTURE TRIGGER 00726 * @{ 00727 * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter. 00728 */ 00729 #define LL_HRTIM_CAPTURETRIG_NONE ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */ 00730 #define LL_HRTIM_CAPTURETRIG_UPDATE HRTIM_CPT1CR_UPDCPT /*!< The update event triggers the Capture */ 00731 #define LL_HRTIM_CAPTURETRIG_EEV_1 HRTIM_CPT1CR_EXEV1CPT /*!< The External event 1 triggers the Capture */ 00732 #define LL_HRTIM_CAPTURETRIG_EEV_2 HRTIM_CPT1CR_EXEV2CPT /*!< The External event 2 triggers the Capture */ 00733 #define LL_HRTIM_CAPTURETRIG_EEV_3 HRTIM_CPT1CR_EXEV3CPT /*!< The External event 3 triggers the Capture */ 00734 #define LL_HRTIM_CAPTURETRIG_EEV_4 HRTIM_CPT1CR_EXEV4CPT /*!< The External event 4 triggers the Capture */ 00735 #define LL_HRTIM_CAPTURETRIG_EEV_5 HRTIM_CPT1CR_EXEV5CPT /*!< The External event 5 triggers the Capture */ 00736 #define LL_HRTIM_CAPTURETRIG_EEV_6 HRTIM_CPT1CR_EXEV6CPT /*!< The External event 6 triggers the Capture */ 00737 #define LL_HRTIM_CAPTURETRIG_EEV_7 HRTIM_CPT1CR_EXEV7CPT /*!< The External event 7 triggers the Capture */ 00738 #define LL_HRTIM_CAPTURETRIG_EEV_8 HRTIM_CPT1CR_EXEV8CPT /*!< The External event 8 triggers the Capture */ 00739 #define LL_HRTIM_CAPTURETRIG_EEV_9 HRTIM_CPT1CR_EXEV9CPT /*!< The External event 9 triggers the Capture */ 00740 #define LL_HRTIM_CAPTURETRIG_EEV_10 HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */ 00741 #define LL_HRTIM_CAPTURETRIG_TA1_SET HRTIM_CPT1CR_TA1SET /*!< Capture is triggered by TA1 output inactive to active transition */ 00742 #define LL_HRTIM_CAPTURETRIG_TA1_RESET HRTIM_CPT1CR_TA1RST /*!< Capture is triggered by TA1 output active to inactive transition */ 00743 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP1 HRTIM_CPT1CR_TIMACMP1 /*!< Timer A Compare 1 triggers Capture */ 00744 #define LL_HRTIM_CAPTURETRIG_TIMA_CMP2 HRTIM_CPT1CR_TIMACMP2 /*!< Timer A Compare 2 triggers Capture */ 00745 #define LL_HRTIM_CAPTURETRIG_TB1_SET HRTIM_CPT1CR_TB1SET /*!< Capture is triggered by TB1 output inactive to active transition */ 00746 #define LL_HRTIM_CAPTURETRIG_TB1_RESET HRTIM_CPT1CR_TB1RST /*!< Capture is triggered by TB1 output active to inactive transition */ 00747 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP1 HRTIM_CPT1CR_TIMBCMP1 /*!< Timer B Compare 1 triggers Capture */ 00748 #define LL_HRTIM_CAPTURETRIG_TIMB_CMP2 HRTIM_CPT1CR_TIMBCMP2 /*!< Timer B Compare 2 triggers Capture */ 00749 #define LL_HRTIM_CAPTURETRIG_TC1_SET HRTIM_CPT1CR_TC1SET /*!< Capture is triggered by TC1 output inactive to active transition */ 00750 #define LL_HRTIM_CAPTURETRIG_TC1_RESET HRTIM_CPT1CR_TC1RST /*!< Capture is triggered by TC1 output active to inactive transition */ 00751 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP1 HRTIM_CPT1CR_TIMCCMP1 /*!< Timer C Compare 1 triggers Capture */ 00752 #define LL_HRTIM_CAPTURETRIG_TIMC_CMP2 HRTIM_CPT1CR_TIMCCMP2 /*!< Timer C Compare 2 triggers Capture */ 00753 #define LL_HRTIM_CAPTURETRIG_TD1_SET HRTIM_CPT1CR_TD1SET /*!< Capture is triggered by TD1 output inactive to active transition */ 00754 #define LL_HRTIM_CAPTURETRIG_TD1_RESET HRTIM_CPT1CR_TD1RST /*!< Capture is triggered by TD1 output active to inactive transition */ 00755 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP1 HRTIM_CPT1CR_TIMDCMP1 /*!< Timer D Compare 1 triggers Capture */ 00756 #define LL_HRTIM_CAPTURETRIG_TIMD_CMP2 HRTIM_CPT1CR_TIMDCMP2 /*!< Timer D Compare 2 triggers Capture */ 00757 #define LL_HRTIM_CAPTURETRIG_TE1_SET HRTIM_CPT1CR_TE1SET /*!< Capture is triggered by TE1 output inactive to active transition */ 00758 #define LL_HRTIM_CAPTURETRIG_TE1_RESET HRTIM_CPT1CR_TE1RST /*!< Capture is triggered by TE1 output active to inactive transition */ 00759 #define LL_HRTIM_CAPTURETRIG_TIME_CMP1 HRTIM_CPT1CR_TIMECMP1 /*!< Timer E Compare 1 triggers Capture */ 00760 #define LL_HRTIM_CAPTURETRIG_TIME_CMP2 HRTIM_CPT1CR_TIMECMP2 /*!< Timer E Compare 2 triggers Capture */ 00761 /** 00762 * @} 00763 */ 00764 00765 /** @defgroup HRTIM_LL_EC_DLYPRT DELAYED PROTECTION (DLYPRT) MODE 00766 * @{ 00767 * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied). 00768 */ 00769 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 0x00000000U /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */ 00770 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */ 00771 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */ 00772 #define LL_HRTIM_DLYPRT_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 6 */ 00773 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 (HRTIM_OUTR_DLYPRT_2) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */ 00774 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */ 00775 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */ 00776 #define LL_HRTIM_DLYPRT_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */ 00777 00778 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 0x00000000U /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */ 00779 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */ 00780 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */ 00781 #define LL_HRTIM_DLYPRT_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 8 */ 00782 #define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 (HRTIM_OUTR_DLYPRT_2) /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */ 00783 #define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */ 00784 #define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */ 00785 #define LL_HRTIM_DLYPRT_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers D, E: Balanced Idle on external Event 9 */ 00786 /** 00787 * @} 00788 */ 00789 00790 /** @defgroup HRTIM_LL_EC_BURSTMODE BURST MODE 00791 * @{ 00792 * @brief Constants defining how the timer behaves during a burst mode operation. 00793 */ 00794 #define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */ 00795 #define LL_HRTIM_BURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */ 00796 /** 00797 * @} 00798 */ 00799 00800 /** @defgroup HRTIM_LL_EC_BURSTDMA BURST DMA 00801 * @{ 00802 * @brief Constants defining the registers that can be written during a burst DMA operation. 00803 */ 00804 #define LL_HRTIM_BURSTDMA_NONE 0x00000000U /*!< No register is updated by Burst DMA accesses */ 00805 #define LL_HRTIM_BURSTDMA_MCR (HRTIM_BDMUPR_MCR) /*!< MCR register is updated by Burst DMA accesses */ 00806 #define LL_HRTIM_BURSTDMA_MICR (HRTIM_BDMUPR_MICR) /*!< MICR register is updated by Burst DMA accesses */ 00807 #define LL_HRTIM_BURSTDMA_MDIER (HRTIM_BDMUPR_MDIER) /*!< MDIER register is updated by Burst DMA accesses */ 00808 #define LL_HRTIM_BURSTDMA_MCNT (HRTIM_BDMUPR_MCNT) /*!< MCNTR register is updated by Burst DMA accesses */ 00809 #define LL_HRTIM_BURSTDMA_MPER (HRTIM_BDMUPR_MPER) /*!< MPER register is updated by Burst DMA accesses */ 00810 #define LL_HRTIM_BURSTDMA_MREP (HRTIM_BDMUPR_MREP) /*!< MREPR register is updated by Burst DMA accesses */ 00811 #define LL_HRTIM_BURSTDMA_MCMP1 (HRTIM_BDMUPR_MCMP1) /*!< MCMP1R register is updated by Burst DMA accesses */ 00812 #define LL_HRTIM_BURSTDMA_MCMP2 (HRTIM_BDMUPR_MCMP2) /*!< MCMP2R register is updated by Burst DMA accesses */ 00813 #define LL_HRTIM_BURSTDMA_MCMP3 (HRTIM_BDMUPR_MCMP3) /*!< MCMP3R register is updated by Burst DMA accesses */ 00814 #define LL_HRTIM_BURSTDMA_MCMP4 (HRTIM_BDMUPR_MCMP4) /*!< MCMP4R register is updated by Burst DMA accesses */ 00815 #define LL_HRTIM_BURSTDMA_TIMMCR (HRTIM_BDTUPR_TIMCR) /*!< TIMxCR register is updated by Burst DMA accesses */ 00816 #define LL_HRTIM_BURSTDMA_TIMICR (HRTIM_BDTUPR_TIMICR) /*!< TIMxICR register is updated by Burst DMA accesses */ 00817 #define LL_HRTIM_BURSTDMA_TIMDIER (HRTIM_BDTUPR_TIMDIER) /*!< TIMxDIER register is updated by Burst DMA accesses */ 00818 #define LL_HRTIM_BURSTDMA_TIMCNT (HRTIM_BDTUPR_TIMCNT) /*!< CNTxCR register is updated by Burst DMA accesses */ 00819 #define LL_HRTIM_BURSTDMA_TIMPER (HRTIM_BDTUPR_TIMPER) /*!< PERxR register is updated by Burst DMA accesses */ 00820 #define LL_HRTIM_BURSTDMA_TIMREP (HRTIM_BDTUPR_TIMREP) /*!< REPxR register is updated by Burst DMA accesses */ 00821 #define LL_HRTIM_BURSTDMA_TIMCMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< CMP1xR register is updated by Burst DMA accesses */ 00822 #define LL_HRTIM_BURSTDMA_TIMCMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< CMP2xR register is updated by Burst DMA accesses */ 00823 #define LL_HRTIM_BURSTDMA_TIMCMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< CMP3xR register is updated by Burst DMA accesses */ 00824 #define LL_HRTIM_BURSTDMA_TIMCMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< CMP4xR register is updated by Burst DMA accesses */ 00825 #define LL_HRTIM_BURSTDMA_TIMDTR (HRTIM_BDTUPR_TIMDTR) /*!< DTxR register is updated by Burst DMA accesses */ 00826 #define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */ 00827 #define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */ 00828 #define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */ 00829 #define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */ 00830 #define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */ 00831 #define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */ 00832 #define LL_HRTIM_BURSTDMA_TIMRSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */ 00833 #define LL_HRTIM_BURSTDMA_TIMCHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */ 00834 #define LL_HRTIM_BURSTDMA_TIMOUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */ 00835 #define LL_HRTIM_BURSTDMA_TIMFLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */ 00836 /** 00837 * @} 00838 */ 00839 00840 /** @defgroup HRTIM_LL_EC_CPPSTAT CURRENT PUSH-PULL STATUS 00841 * @{ 00842 * @brief Constants defining on which output the signal is currently applied in push-pull mode. 00843 */ 00844 #define LL_HRTIM_CPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */ 00845 #define LL_HRTIM_CPPSTAT_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */ 00846 /** 00847 * @} 00848 */ 00849 00850 /** @defgroup HRTIM_LL_EC_IPPSTAT IDLE PUSH-PULL STATUS 00851 * @{ 00852 * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered. 00853 */ 00854 #define LL_HRTIM_IPPSTAT_OUTPUT1 ((uint32_t) 0x00000000U) /*!< Protection occurred when the output 1 was active and output 2 forced inactive */ 00855 #define LL_HRTIM_IPPSTAT_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */ 00856 /** 00857 * @} 00858 */ 00859 00860 /** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER 00861 * @{ 00862 * @brief Constants defining the event filtering applied to external events by a timer. 00863 */ 00864 #define LL_HRTIM_EEFLTR_NONE (0x00000000U) 00865 #define LL_HRTIM_EEFLTR_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1 */ 00866 #define LL_HRTIM_EEFLTR_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2 */ 00867 #define LL_HRTIM_EEFLTR_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3 */ 00868 #define LL_HRTIM_EEFLTR_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4 */ 00869 #define LL_HRTIM_EEFLTR_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */ 00870 #define LL_HRTIM_EEFLTR_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */ 00871 #define LL_HRTIM_EEFLTR_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */ 00872 #define LL_HRTIM_EEFLTR_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */ 00873 #define LL_HRTIM_EEFLTR_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */ 00874 #define LL_HRTIM_EEFLTR_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */ 00875 #define LL_HRTIM_EEFLTR_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */ 00876 #define LL_HRTIM_EEFLTR_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */ 00877 #define LL_HRTIM_EEFLTR_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2 */ 00878 #define LL_HRTIM_EEFLTR_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3 */ 00879 #define LL_HRTIM_EEFLTR_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */ 00880 /** 00881 * @} 00882 */ 00883 00884 /** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS 00885 * @{ 00886 * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends. 00887 */ 00888 #define LL_HRTIM_EELATCH_DISABLED 0x00000000U /*!< Event is ignored if it happens during a blank, or passed through during a window */ 00889 #define LL_HRTIM_EELATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */ 00890 /** 00891 * @} 00892 */ 00893 00894 /** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER 00895 * @{ 00896 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG). 00897 */ 00898 #define LL_HRTIM_DT_PRESCALER_MUL8 0x00000000U /*!< fDTG = fHRTIM * 8 */ 00899 #define LL_HRTIM_DT_PRESCALER_MUL4 (HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM * 4 */ 00900 #define LL_HRTIM_DT_PRESCALER_MUL2 (HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM * 2 */ 00901 #define LL_HRTIM_DT_PRESCALER_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */ 00902 #define LL_HRTIM_DT_PRESCALER_DIV2 (HRTIM_DTR_DTPRSC_2) /*!< fDTG = fHRTIM / 2 */ 00903 #define LL_HRTIM_DT_PRESCALER_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4 */ 00904 #define LL_HRTIM_DT_PRESCALER_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8 */ 00905 #define LL_HRTIM_DT_PRESCALER_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16 */ 00906 /** 00907 * @} 00908 */ 00909 00910 /** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN 00911 * @{ 00912 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge. 00913 */ 00914 #define LL_HRTIM_DT_RISING_POSITIVE 0x00000000U /*!< Positive deadtime on rising edge */ 00915 #define LL_HRTIM_DT_RISING_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */ 00916 /** 00917 * @} 00918 */ 00919 00920 /** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN 00921 * @{ 00922 * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge. 00923 */ 00924 #define LL_HRTIM_DT_FALLING_POSITIVE 0x00000000U /*!< Positive deadtime on falling edge */ 00925 #define LL_HRTIM_DT_FALLING_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */ 00926 /** 00927 * @} 00928 */ 00929 00930 /** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER 00931 * @{ 00932 * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ). 00933 */ 00934 #define LL_HRTIM_CHP_PRESCALER_DIV16 0x00000000U /*!< fCHPFRQ = fHRTIM / 16 */ 00935 #define LL_HRTIM_CHP_PRESCALER_DIV32 (HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 32 */ 00936 #define LL_HRTIM_CHP_PRESCALER_DIV48 (HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 48 */ 00937 #define LL_HRTIM_CHP_PRESCALER_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */ 00938 #define LL_HRTIM_CHP_PRESCALER_DIV80 (HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 80 */ 00939 #define LL_HRTIM_CHP_PRESCALER_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */ 00940 #define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */ 00941 #define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */ 00942 #define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */ 00943 #define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */ 00944 #define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */ 00945 #define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */ 00946 #define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */ 00947 #define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */ 00948 #define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */ 00949 #define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */ 00950 /** 00951 * @} 00952 */ 00953 00954 /** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE 00955 * @{ 00956 * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8). 00957 */ 00958 #define LL_HRTIM_CHP_DUTYCYCLE_0 0x00000000U /*!< Only 1st pulse is present */ 00959 #define LL_HRTIM_CHP_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5 % */ 00960 #define LL_HRTIM_CHP_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25 % */ 00961 #define LL_HRTIM_CHP_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5 % */ 00962 #define LL_HRTIM_CHP_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50 % */ 00963 #define LL_HRTIM_CHP_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5 % */ 00964 #define LL_HRTIM_CHP_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75 % */ 00965 #define LL_HRTIM_CHP_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */ 00966 /** 00967 * @} 00968 */ 00969 00970 /** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH 00971 * @{ 00972 * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier. 00973 */ 00974 #define LL_HRTIM_CHP_PULSEWIDTH_16 0x00000000U /*!< tSTPW = tHRTIM x 16 */ 00975 #define LL_HRTIM_CHP_PULSEWIDTH_32 (HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 32 */ 00976 #define LL_HRTIM_CHP_PULSEWIDTH_48 (HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 48 */ 00977 #define LL_HRTIM_CHP_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */ 00978 #define LL_HRTIM_CHP_PULSEWIDTH_80 (HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 80 */ 00979 #define LL_HRTIM_CHP_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */ 00980 #define LL_HRTIM_CHP_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */ 00981 #define LL_HRTIM_CHP_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */ 00982 #define LL_HRTIM_CHP_PULSEWIDTH_144 (HRTIM_CHPR_STRPW_3) /*!< tSTPW = tHRTIM x 144 */ 00983 #define LL_HRTIM_CHP_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */ 00984 #define LL_HRTIM_CHP_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */ 00985 #define LL_HRTIM_CHP_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */ 00986 #define LL_HRTIM_CHP_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */ 00987 #define LL_HRTIM_CHP_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */ 00988 #define LL_HRTIM_CHP_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */ 00989 #define LL_HRTIM_CHP_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */ 00990 /** 00991 * @} 00992 */ 00993 00994 /** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT 00995 * @{ 00996 * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output. 00997 */ 00998 #define LL_HRTIM_CROSSBAR_NONE 0x00000000U /*!< Reset the output set crossbar */ 00999 #define LL_HRTIM_CROSSBAR_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */ 01000 #define LL_HRTIM_CROSSBAR_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces an output level transition */ 01001 #define LL_HRTIM_CROSSBAR_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces an output level transition */ 01002 #define LL_HRTIM_CROSSBAR_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces an output level transition */ 01003 #define LL_HRTIM_CROSSBAR_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces an output level transition */ 01004 #define LL_HRTIM_CROSSBAR_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces an output level transition */ 01005 #define LL_HRTIM_CROSSBAR_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces an output level transition */ 01006 #define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces an output level transition */ 01007 #define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces an output level transition */ 01008 #define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces an output level transition */ 01009 #define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces an output level transition */ 01010 #define LL_HRTIM_CROSSBAR_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces an output level transition */ 01011 #define LL_HRTIM_CROSSBAR_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces an output level transition */ 01012 #define LL_HRTIM_CROSSBAR_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces an output level transition */ 01013 #define LL_HRTIM_CROSSBAR_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces an output level transition */ 01014 #define LL_HRTIM_CROSSBAR_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces an output level transition */ 01015 #define LL_HRTIM_CROSSBAR_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces an output level transition */ 01016 #define LL_HRTIM_CROSSBAR_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces an output level transition */ 01017 #define LL_HRTIM_CROSSBAR_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces an output level transition */ 01018 #define LL_HRTIM_CROSSBAR_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces an output level transition */ 01019 #define LL_HRTIM_CROSSBAR_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces an output level transition */ 01020 #define LL_HRTIM_CROSSBAR_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces an output level transition */ 01021 #define LL_HRTIM_CROSSBAR_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces an output level transition */ 01022 #define LL_HRTIM_CROSSBAR_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces an output level transition */ 01023 #define LL_HRTIM_CROSSBAR_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces an output level transition */ 01024 #define LL_HRTIM_CROSSBAR_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces an output level transition */ 01025 #define LL_HRTIM_CROSSBAR_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces an output level transition */ 01026 #define LL_HRTIM_CROSSBAR_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces an output level transition */ 01027 #define LL_HRTIM_CROSSBAR_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces an output level transition */ 01028 #define LL_HRTIM_CROSSBAR_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces an output level transition */ 01029 #define LL_HRTIM_CROSSBAR_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces an output level transition */ 01030 /** 01031 * @} 01032 */ 01033 01034 /** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY 01035 * @{ 01036 * @brief Constants defining the polarity of a timer output. 01037 */ 01038 #define LL_HRTIM_OUT_POSITIVE_POLARITY 0x00000000U /*!< Output is active HIGH */ 01039 #define LL_HRTIM_OUT_NEGATIVE_POLARITY (HRTIM_OUTR_POL1) /*!< Output is active LOW */ 01040 /** 01041 * @} 01042 */ 01043 01044 /** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE 01045 * @{ 01046 * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered. 01047 */ 01048 #define LL_HRTIM_OUT_NO_IDLE 0x00000000U /*!< The output is not affected by the burst mode operation */ 01049 #define LL_HRTIM_OUT_IDLE_WHEN_BURST (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */ 01050 /** 01051 * @} 01052 */ 01053 01054 /** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE 01055 * @{ 01056 * @brief Constants defining the half mode of an HRTIM Timer instance. 01057 */ 01058 #define LL_HRTIM_HALF_MODE_DISABLED 0x000U /*!< HRTIM Half Mode is disabled */ 01059 #define LL_HRTIM_HALF_MODE_ENABLE HRTIM_MCR_HALF /*!< HRTIM Half Mode is Half */ 01060 /** 01061 * @} 01062 */ 01063 01064 /** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL 01065 * @{ 01066 * @brief Constants defining the output level when output is in IDLE state 01067 */ 01068 #define LL_HRTIM_OUT_IDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */ 01069 #define LL_HRTIM_OUT_IDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */ 01070 /** 01071 * @} 01072 */ 01073 01074 /** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE 01075 * @{ 01076 * @brief Constants defining the output level when output is in FAULT state. 01077 */ 01078 #define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U /*!< The output is not affected by the fault input */ 01079 #define LL_HRTIM_OUT_FAULTSTATE_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */ 01080 #define LL_HRTIM_OUT_FAULTSTATE_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */ 01081 #define LL_HRTIM_OUT_FAULTSTATE_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */ 01082 /** 01083 * @} 01084 */ 01085 01086 /** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE 01087 * @{ 01088 * @brief Constants defining whether or not chopper mode is enabled for a timer output. 01089 */ 01090 #define LL_HRTIM_OUT_CHOPPERMODE_DISABLED 0x00000000U /*!< Output signal is not altered */ 01091 #define LL_HRTIM_OUT_CHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */ 01092 /** 01093 * @} 01094 */ 01095 01096 /** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE 01097 * @{ 01098 * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state 01099 during a programmable period before the output takes its idle state. 01100 */ 01101 #define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */ 01102 #define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */ 01103 /** 01104 * @} 01105 */ 01106 /** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL 01107 * @{ 01108 * @brief Constants defining the level of a timer output. 01109 */ 01110 #define LL_HRTIM_OUT_LEVEL_INACTIVE 0x00000000U /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */ 01111 #define LL_HRTIM_OUT_LEVEL_ACTIVE ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */ 01112 /** 01113 * @} 01114 */ 01115 01116 /** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE 01117 * @{ 01118 * @brief Constants defining available sources associated to external events. 01119 */ 01120 #define LL_HRTIM_EE_SRC_1 0x00000000U /*!< External event source 1 (EExSrc1)*/ 01121 #define LL_HRTIM_EE_SRC_2 (HRTIM_EECR1_EE1SRC_0) /*!< External event source 2 (EExSrc2) */ 01122 #define LL_HRTIM_EE_SRC_3 (HRTIM_EECR1_EE1SRC_1) /*!< External event source 3 (EExSrc3) */ 01123 #define LL_HRTIM_EE_SRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 (EExSrc4) */ 01124 /** 01125 * @} 01126 */ 01127 /** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY 01128 * @{ 01129 * @brief Constants defining the polarity of an external event. 01130 */ 01131 #define LL_HRTIM_EE_POLARITY_HIGH 0x00000000U /*!< External event is active high */ 01132 #define LL_HRTIM_EE_POLARITY_LOW (HRTIM_EECR1_EE1POL) /*!< External event is active low */ 01133 /** 01134 * @} 01135 */ 01136 01137 /** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY 01138 * @{ 01139 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event. 01140 */ 01141 #define LL_HRTIM_EE_SENSITIVITY_LEVEL 0x00000000U /*!< External event is active on level */ 01142 #define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */ 01143 #define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */ 01144 #define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */ 01145 /** 01146 * @} 01147 */ 01148 01149 /** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE 01150 * @{ 01151 * @brief Constants defining whether or not an external event is programmed in fast mode. 01152 */ 01153 #define LL_HRTIM_EE_FASTMODE_DISABLE 0x00000000U /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */ 01154 #define LL_HRTIM_EE_FASTMODE_ENABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */ 01155 /** 01156 * @} 01157 */ 01158 01159 /** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER 01160 * @{ 01161 * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied. 01162 */ 01163 #define LL_HRTIM_EE_FILTER_NONE 0x00000000U /*!< Filter disabled */ 01164 #define LL_HRTIM_EE_FILTER_1 (HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=2 */ 01165 #define LL_HRTIM_EE_FILTER_2 (HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fHRTIM, N=4 */ 01166 #define LL_HRTIM_EE_FILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fHRTIM, N=8 */ 01167 #define LL_HRTIM_EE_FILTER_4 (HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/2, N=6 */ 01168 #define LL_HRTIM_EE_FILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/2, N=8 */ 01169 #define LL_HRTIM_EE_FILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/4, N=6 */ 01170 #define LL_HRTIM_EE_FILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/4, N=8 */ 01171 #define LL_HRTIM_EE_FILTER_8 (HRTIM_EECR3_EE6F_3) /*!< fSAMPLING = fEEVS/8, N=6 */ 01172 #define LL_HRTIM_EE_FILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/8, N=8 */ 01173 #define LL_HRTIM_EE_FILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/16, N=5 */ 01174 #define LL_HRTIM_EE_FILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/16, N=6 */ 01175 #define LL_HRTIM_EE_FILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING = fEEVS/16, N=8 */ 01176 #define LL_HRTIM_EE_FILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=5 */ 01177 #define LL_HRTIM_EE_FILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING = fEEVS/32, N=6 */ 01178 #define LL_HRTIM_EE_FILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING = fEEVS/32, N=8 */ 01179 /** 01180 * @} 01181 */ 01182 01183 /** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER 01184 * @{ 01185 * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters. 01186 */ 01187 #define LL_HRTIM_EE_PRESCALER_DIV1 0x00000000U /*!< fEEVS = fHRTIM */ 01188 #define LL_HRTIM_EE_PRESCALER_DIV2 (HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 2 */ 01189 #define LL_HRTIM_EE_PRESCALER_DIV4 (HRTIM_EECR3_EEVSD_1) /*!< fEEVS = fHRTIM / 4 */ 01190 #define LL_HRTIM_EE_PRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */ 01191 /** 01192 * @} 01193 */ 01194 01195 /** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE 01196 * @{ 01197 * @brief Constants defining whether a faults is be triggered by any external or internal fault source. 01198 */ 01199 #define LL_HRTIM_FLT_SRC_DIGITALINPUT 0x00000000U /*!< Fault input is FLT input pin */ 01200 #define LL_HRTIM_FLT_SRC_INTERNAL HRTIM_FLTINR1_FLT1SRC /*!< Fault input is FLT_Int signal (e.g. internal comparator) */ 01201 /** 01202 * @} 01203 */ 01204 01205 /** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY 01206 * @{ 01207 * @brief Constants defining the polarity of a fault event. 01208 */ 01209 #define LL_HRTIM_FLT_POLARITY_LOW 0x00000000U /*!< Fault input is active low */ 01210 #define LL_HRTIM_FLT_POLARITY_HIGH (HRTIM_FLTINR1_FLT1P) /*!< Fault input is active high */ 01211 /** 01212 * @} 01213 */ 01214 01215 /** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER 01216 * @{ 01217 * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied. 01218 */ 01219 #define LL_HRTIM_FLT_FILTER_NONE 0x00000000U /*!< Filter disabled */ 01220 #define LL_HRTIM_FLT_FILTER_1 (HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=2 */ 01221 #define LL_HRTIM_FLT_FILTER_2 (HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fHRTIM, N=4 */ 01222 #define LL_HRTIM_FLT_FILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8 */ 01223 #define LL_HRTIM_FLT_FILTER_4 (HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/2, N=6 */ 01224 #define LL_HRTIM_FLT_FILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2, N=8 */ 01225 #define LL_HRTIM_FLT_FILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4, N=6 */ 01226 #define LL_HRTIM_FLT_FILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4, N=8 */ 01227 #define LL_HRTIM_FLT_FILTER_8 (HRTIM_FLTINR1_FLT1F_3) /*!< fSAMPLING= fFLTS/8, N=6 */ 01228 #define LL_HRTIM_FLT_FILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8, N=8 */ 01229 #define LL_HRTIM_FLT_FILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16, N=5 */ 01230 #define LL_HRTIM_FLT_FILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16, N=6 */ 01231 #define LL_HRTIM_FLT_FILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16, N=8 */ 01232 #define LL_HRTIM_FLT_FILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=5 */ 01233 #define LL_HRTIM_FLT_FILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32, N=6 */ 01234 #define LL_HRTIM_FLT_FILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32, N=8 */ 01235 /** 01236 * @} 01237 */ 01238 01239 /** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER 01240 * @{ 01241 * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used by the digital filters. 01242 */ 01243 #define LL_HRTIM_FLT_PRESCALER_DIV1 0x00000000U /*!< fFLTS = fHRTIM */ 01244 #define LL_HRTIM_FLT_PRESCALER_DIV2 (HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 2 */ 01245 #define LL_HRTIM_FLT_PRESCALER_DIV4 (HRTIM_FLTINR2_FLTSD_1) /*!< fFLTS = fHRTIM / 4 */ 01246 #define LL_HRTIM_FLT_PRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */ 01247 /** 01248 * @} 01249 */ 01250 01251 /** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE 01252 * @{ 01253 * @brief Constants defining if the burst mode is entered once or if it is continuously operating. 01254 */ 01255 #define LL_HRTIM_BM_MODE_SINGLESHOT 0x00000000U /*!< Burst mode operates in single shot mode */ 01256 #define LL_HRTIM_BM_MODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */ 01257 /** 01258 * @} 01259 */ 01260 01261 /** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE 01262 * @{ 01263 * @brief Constants defining the clock source for the burst mode counter. 01264 */ 01265 #define LL_HRTIM_BM_CLKSRC_MASTER 0x00000000U /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */ 01266 #define LL_HRTIM_BM_CLKSRC_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */ 01267 #define LL_HRTIM_BM_CLKSRC_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */ 01268 #define LL_HRTIM_BM_CLKSRC_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */ 01269 #define LL_HRTIM_BM_CLKSRC_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */ 01270 #define LL_HRTIM_BM_CLKSRC_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */ 01271 #define LL_HRTIM_BM_CLKSRC_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */ 01272 #define LL_HRTIM_BM_CLKSRC_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */ 01273 #define LL_HRTIM_BM_CLKSRC_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */ 01274 #define LL_HRTIM_BM_CLKSRC_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */ 01275 /** 01276 * @} 01277 */ 01278 01279 /** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER 01280 * @{ 01281 * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST). 01282 */ 01283 #define LL_HRTIM_BM_PRESCALER_DIV1 0x00000000U /*!< fBRST = fHRTIM */ 01284 #define LL_HRTIM_BM_PRESCALER_DIV2 (HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2 */ 01285 #define LL_HRTIM_BM_PRESCALER_DIV4 (HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/4 */ 01286 #define LL_HRTIM_BM_PRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8 */ 01287 #define LL_HRTIM_BM_PRESCALER_DIV16 (HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/16 */ 01288 #define LL_HRTIM_BM_PRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32 */ 01289 #define LL_HRTIM_BM_PRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64 */ 01290 #define LL_HRTIM_BM_PRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128 */ 01291 #define LL_HRTIM_BM_PRESCALER_DIV256 (HRTIM_BMCR_BMPRSC_3) /*!< fBRST = fHRTIM/256 */ 01292 #define LL_HRTIM_BM_PRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512 */ 01293 #define LL_HRTIM_BM_PRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024 */ 01294 #define LL_HRTIM_BM_PRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048*/ 01295 #define LL_HRTIM_BM_PRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096 */ 01296 #define LL_HRTIM_BM_PRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192 */ 01297 #define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384 */ 01298 #define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */ 01299 /** 01300 * @} 01301 */ 01302 01303 /** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER 01304 * @{ 01305 * @brief Constants defining the events that can be used to trig the burst mode operation. 01306 */ 01307 #define LL_HRTIM_BM_TRIG_NONE 0x00000000U /*!< No trigger */ 01308 #define LL_HRTIM_BM_TRIG_MASTER_RESET (HRTIM_BMTRGR_MSTRST) /*!< Master timer reset event is starting the burst mode operation */ 01309 #define LL_HRTIM_BM_TRIG_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master timer repetition event is starting the burst mode operation */ 01310 #define LL_HRTIM_BM_TRIG_MASTER_CMP1 (HRTIM_BMTRGR_MSTCMP1) /*!< Master timer compare 1 event is starting the burst mode operation */ 01311 #define LL_HRTIM_BM_TRIG_MASTER_CMP2 (HRTIM_BMTRGR_MSTCMP2) /*!< Master timer compare 2 event is starting the burst mode operation */ 01312 #define LL_HRTIM_BM_TRIG_MASTER_CMP3 (HRTIM_BMTRGR_MSTCMP3) /*!< Master timer compare 3 event is starting the burst mode operation */ 01313 #define LL_HRTIM_BM_TRIG_MASTER_CMP4 (HRTIM_BMTRGR_MSTCMP4) /*!< Master timer compare 4 event is starting the burst mode operation */ 01314 #define LL_HRTIM_BM_TRIG_TIMA_RESET (HRTIM_BMTRGR_TARST) /*!< Timer A reset event is starting the burst mode operation */ 01315 #define LL_HRTIM_BM_TRIG_TIMA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition event is starting the burst mode operation */ 01316 #define LL_HRTIM_BM_TRIG_TIMA_CMP1 (HRTIM_BMTRGR_TACMP1) /*!< Timer A compare 1 event is starting the burst mode operation */ 01317 #define LL_HRTIM_BM_TRIG_TIMA_CMP2 (HRTIM_BMTRGR_TACMP2) /*!< Timer A compare 2 event is starting the burst mode operation */ 01318 #define LL_HRTIM_BM_TRIG_TIMB_RESET (HRTIM_BMTRGR_TBRST) /*!< Timer B reset event is starting the burst mode operation */ 01319 #define LL_HRTIM_BM_TRIG_TIMB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition event is starting the burst mode operation */ 01320 #define LL_HRTIM_BM_TRIG_TIMB_CMP1 (HRTIM_BMTRGR_TBCMP1) /*!< Timer B compare 1 event is starting the burst mode operation */ 01321 #define LL_HRTIM_BM_TRIG_TIMB_CMP2 (HRTIM_BMTRGR_TBCMP2) /*!< Timer B compare 2 event is starting the burst mode operation */ 01322 #define LL_HRTIM_BM_TRIG_TIMC_RESET (HRTIM_BMTRGR_TCRST) /*!< Timer C resetevent is starting the burst mode operation */ 01323 #define LL_HRTIM_BM_TRIG_TIMC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition event is starting the burst mode operation */ 01324 #define LL_HRTIM_BM_TRIG_TIMC_CMP1 (HRTIM_BMTRGR_TCCMP1) /*!< Timer C compare 1 event is starting the burst mode operation */ 01325 #define LL_HRTIM_BM_TRIG_TIMC_CMP2 (HRTIM_BMTRGR_TCCMP2) /*!< Timer C compare 2 event is starting the burst mode operation */ 01326 #define LL_HRTIM_BM_TRIG_TIMD_RESET (HRTIM_BMTRGR_TDRST) /*!< Timer D reset event is starting the burst mode operation */ 01327 #define LL_HRTIM_BM_TRIG_TIMD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition event is starting the burst mode operation */ 01328 #define LL_HRTIM_BM_TRIG_TIMD_CMP1 (HRTIM_BMTRGR_TDCMP1) /*!< Timer D compare 1 event is starting the burst mode operation */ 01329 #define LL_HRTIM_BM_TRIG_TIMD_CMP2 (HRTIM_BMTRGR_TDCMP2) /*!< Timer D compare 2 event is starting the burst mode operation */ 01330 #define LL_HRTIM_BM_TRIG_TIME_RESET (HRTIM_BMTRGR_TERST) /*!< Timer E reset event is starting the burst mode operation */ 01331 #define LL_HRTIM_BM_TRIG_TIME_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition event is starting the burst mode operation */ 01332 #define LL_HRTIM_BM_TRIG_TIME_CMP1 (HRTIM_BMTRGR_TECMP1) /*!< Timer E compare 1 event is starting the burst mode operation */ 01333 #define LL_HRTIM_BM_TRIG_TIME_CMP2 (HRTIM_BMTRGR_TECMP2) /*!< Timer E compare 2 event is starting the burst mode operation */ 01334 #define LL_HRTIM_BM_TRIG_TIMA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation */ 01335 #define LL_HRTIM_BM_TRIG_TIMD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation */ 01336 #define LL_HRTIM_BM_TRIG_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */ 01337 #define LL_HRTIM_BM_TRIG_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */ 01338 #define LL_HRTIM_BM_TRIG_EVENT_ONCHIP (HRTIM_BMTRGR_OCHPEV) /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */ 01339 /** 01340 * @} 01341 */ 01342 01343 /** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS 01344 * @{ 01345 * @brief Constants defining the operating state of the burst mode controller. 01346 */ 01347 #define LL_HRTIM_BM_STATUS_NORMAL 0x00000000U /*!< Normal operation */ 01348 #define LL_HRTIM_BM_STATUS_BURST_ONGOING HRTIM_BMCR_BMSTAT /*!< Burst operation on-going */ 01349 /** 01350 * @} 01351 */ 01352 01353 /** 01354 * @} 01355 */ 01356 01357 /* Exported macro ------------------------------------------------------------*/ 01358 /** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros 01359 * @{ 01360 */ 01361 01362 /** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros 01363 * @{ 01364 */ 01365 01366 /** 01367 * @brief Write a value in HRTIM register 01368 * @param __INSTANCE__ HRTIM Instance 01369 * @param __REG__ Register to be written 01370 * @param __VALUE__ Value to be written in the register 01371 * @retval None 01372 */ 01373 #define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 01374 01375 /** 01376 * @brief Read a value in HRTIM register 01377 * @param __INSTANCE__ HRTIM Instance 01378 * @param __REG__ Register to be read 01379 * @retval Register value 01380 */ 01381 #define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 01382 /** 01383 * @} 01384 */ 01385 01386 /** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros 01387 * @{ 01388 */ 01389 /** 01390 * @brief HELPER macro returning the output state from output enable/disable status 01391 * @param __OUTPUT_STATUS_EN__ output enable status 01392 * @param __OUTPUT_STATUS_DIS__ output Disable status 01393 * @retval Returned value can be one of the following values: 01394 * @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE 01395 * @arg @ref LL_HRTIM_OUTPUTSTATE_RUN 01396 * @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT 01397 */ 01398 #define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\ 01399 (((__OUTPUT_STATUS_EN__) == 1) ? LL_HRTIM_OUTPUTSTATE_RUN :\ 01400 ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT) 01401 /** 01402 * @} 01403 */ 01404 01405 /** 01406 * @} 01407 */ 01408 01409 /* Exported functions --------------------------------------------------------*/ 01410 /** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions 01411 * @{ 01412 */ 01413 /** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control 01414 * @{ 01415 */ 01416 01417 /** 01418 * @brief Select the HRTIM synchronization input source. 01419 * @note This function must not be called when the concerned timer(s) is (are) enabled . 01420 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc 01421 * @param HRTIMx High Resolution Timer instance 01422 * @param SyncInSrc This parameter can be one of the following values: 01423 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE 01424 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT 01425 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT 01426 * @retval None 01427 */ 01428 __STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc) 01429 { 01430 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc); 01431 } 01432 01433 /** 01434 * @brief Get actual HRTIM synchronization input source. 01435 * @rmtoll MCR SYNCIN LL_HRTIM_SetSyncInSrc 01436 * @param HRTIMx High Resolution Timer instance 01437 * @retval SyncInSrc Returned value can be one of the following values: 01438 * @arg @ref LL_HRTIM_SYNCIN_SRC_NONE 01439 * @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT 01440 * @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT 01441 */ 01442 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx) 01443 { 01444 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN)); 01445 } 01446 01447 /** 01448 * @brief Configure the HRTIM synchronization output. 01449 * @rmtoll MCR SYNCSRC LL_HRTIM_ConfigSyncOut\n 01450 * MCR SYNCOUT LL_HRTIM_ConfigSyncOut 01451 * @param HRTIMx High Resolution Timer instance 01452 * @param Config This parameter can be one of the following values: 01453 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED 01454 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE 01455 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE 01456 * @param Src This parameter can be one of the following values: 01457 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START 01458 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 01459 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START 01460 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 01461 * @retval None 01462 */ 01463 __STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src) 01464 { 01465 MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src)); 01466 } 01467 01468 /** 01469 * @brief Set the routing and conditioning of the synchronization output event. 01470 * @rmtoll MCR SYNCOUT LL_HRTIM_SetSyncOutConfig 01471 * @note This function can be called only when the master timer is enabled. 01472 * @param HRTIMx High Resolution Timer instance 01473 * @param SyncOutConfig This parameter can be one of the following values: 01474 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED 01475 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE 01476 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE 01477 * @retval None 01478 */ 01479 __STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig) 01480 { 01481 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig); 01482 } 01483 01484 /** 01485 * @brief Get actual routing and conditioning of the synchronization output event. 01486 * @rmtoll MCR SYNCOUT LL_HRTIM_GetSyncOutConfig 01487 * @param HRTIMx High Resolution Timer instance 01488 * @retval SyncOutConfig Returned value can be one of the following values: 01489 * @arg @ref LL_HRTIM_SYNCOUT_DISABLED 01490 * @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE 01491 * @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE 01492 */ 01493 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx) 01494 { 01495 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT)); 01496 } 01497 01498 /** 01499 * @brief Set the source and event to be sent on the HRTIM synchronization output. 01500 * @rmtoll MCR SYNCSRC LL_HRTIM_SetSyncOutSrc 01501 * @param HRTIMx High Resolution Timer instance 01502 * @param SyncOutSrc This parameter can be one of the following values: 01503 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START 01504 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 01505 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START 01506 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 01507 * @retval None 01508 */ 01509 __STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc) 01510 { 01511 MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc); 01512 } 01513 01514 /** 01515 * @brief Get actual source and event sent on the HRTIM synchronization output. 01516 * @rmtoll MCR SYNCSRC LL_HRTIM_GetSyncOutSrc 01517 * @param HRTIMx High Resolution Timer instance 01518 * @retval SyncOutSrc Returned value can be one of the following values: 01519 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START 01520 * @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1 01521 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START 01522 * @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1 01523 */ 01524 __STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx) 01525 { 01526 return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC)); 01527 } 01528 01529 /** 01530 * @brief Disable (temporarily) update event generation. 01531 * @rmtoll CR1 MUDIS LL_HRTIM_SuspendUpdate\n 01532 * CR1 TAUDIS LL_HRTIM_SuspendUpdate\n 01533 * CR1 TBUDIS LL_HRTIM_SuspendUpdate\n 01534 * CR1 TCUDIS LL_HRTIM_SuspendUpdate\n 01535 * CR1 TDUDIS LL_HRTIM_SuspendUpdate\n 01536 * CR1 TEUDIS LL_HRTIM_SuspendUpdate 01537 * @note Allow to temporarily disable the transfer from preload to active 01538 * registers, whatever the selected update event. This allows to modify 01539 * several registers in multiple timers. 01540 * @param HRTIMx High Resolution Timer instance 01541 * @param Timers This parameter can be a combination of the following values: 01542 * @arg @ref LL_HRTIM_TIMER_MASTER 01543 * @arg @ref LL_HRTIM_TIMER_A 01544 * @arg @ref LL_HRTIM_TIMER_B 01545 * @arg @ref LL_HRTIM_TIMER_C 01546 * @arg @ref LL_HRTIM_TIMER_D 01547 * @arg @ref LL_HRTIM_TIMER_E 01548 * @retval None 01549 */ 01550 __STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 01551 { 01552 SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); 01553 } 01554 01555 /** 01556 * @brief Enable update event generation. 01557 * @rmtoll CR1 MUDIS LL_HRTIM_ResumeUpdate\n 01558 * CR1 TAUDIS LL_HRTIM_ResumeUpdate\n 01559 * CR1 TBUDIS LL_HRTIM_ResumeUpdate\n 01560 * CR1 TCUDIS LL_HRTIM_ResumeUpdate\n 01561 * CR1 TDUDIS LL_HRTIM_ResumeUpdate\n 01562 * CR1 TEUDIS LL_HRTIM_ResumeUpdate 01563 * @note The regular update event takes place. 01564 * @param HRTIMx High Resolution Timer instance 01565 * @param Timers This parameter can be a combination of the following values: 01566 * @arg @ref LL_HRTIM_TIMER_MASTER 01567 * @arg @ref LL_HRTIM_TIMER_A 01568 * @arg @ref LL_HRTIM_TIMER_B 01569 * @arg @ref LL_HRTIM_TIMER_C 01570 * @arg @ref LL_HRTIM_TIMER_D 01571 * @arg @ref LL_HRTIM_TIMER_E 01572 * @retval None 01573 */ 01574 __STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 01575 { 01576 CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK)); 01577 } 01578 01579 /** 01580 * @brief Force an immediate transfer from the preload to the active register . 01581 * @rmtoll CR2 MSWU LL_HRTIM_ForceUpdate\n 01582 * CR2 TASWU LL_HRTIM_ForceUpdate\n 01583 * CR2 TBSWU LL_HRTIM_ForceUpdate\n 01584 * CR2 TCSWU LL_HRTIM_ForceUpdate\n 01585 * CR2 TDSWU LL_HRTIM_ForceUpdate\n 01586 * CR2 TESWU LL_HRTIM_ForceUpdate 01587 * @note Any pending update request is cancelled. 01588 * @param HRTIMx High Resolution Timer instance 01589 * @param Timers This parameter can be a combination of the following values: 01590 * @arg @ref LL_HRTIM_TIMER_MASTER 01591 * @arg @ref LL_HRTIM_TIMER_A 01592 * @arg @ref LL_HRTIM_TIMER_B 01593 * @arg @ref LL_HRTIM_TIMER_C 01594 * @arg @ref LL_HRTIM_TIMER_D 01595 * @arg @ref LL_HRTIM_TIMER_E 01596 * @retval None 01597 */ 01598 __STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 01599 { 01600 SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK)); 01601 } 01602 01603 /** 01604 * @brief Reset the HRTIM timer(s) counter. 01605 * @rmtoll CR2 MRST LL_HRTIM_CounterReset\n 01606 * CR2 TARST LL_HRTIM_CounterReset\n 01607 * CR2 TBRST LL_HRTIM_CounterReset\n 01608 * CR2 TCRST LL_HRTIM_CounterReset\n 01609 * CR2 TDRST LL_HRTIM_CounterReset\n 01610 * CR2 TERST LL_HRTIM_CounterReset 01611 * @param HRTIMx High Resolution Timer instance 01612 * @param Timers This parameter can be a combination of the following values: 01613 * @arg @ref LL_HRTIM_TIMER_MASTER 01614 * @arg @ref LL_HRTIM_TIMER_A 01615 * @arg @ref LL_HRTIM_TIMER_B 01616 * @arg @ref LL_HRTIM_TIMER_C 01617 * @arg @ref LL_HRTIM_TIMER_D 01618 * @arg @ref LL_HRTIM_TIMER_E 01619 * @retval None 01620 */ 01621 __STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 01622 { 01623 SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK)); 01624 } 01625 01626 /** 01627 * @brief Enable the HRTIM timer(s) output(s) . 01628 * @rmtoll OENR TA1OEN LL_HRTIM_EnableOutput\n 01629 * OENR TA2OEN LL_HRTIM_EnableOutput\n 01630 * OENR TB1OEN LL_HRTIM_EnableOutput\n 01631 * OENR TB2OEN LL_HRTIM_EnableOutput\n 01632 * OENR TC1OEN LL_HRTIM_EnableOutput\n 01633 * OENR TC2OEN LL_HRTIM_EnableOutput\n 01634 * OENR TD1OEN LL_HRTIM_EnableOutput\n 01635 * OENR TD2OEN LL_HRTIM_EnableOutput\n 01636 * OENR TE1OEN LL_HRTIM_EnableOutput\n 01637 * OENR TE2OEN LL_HRTIM_EnableOutput 01638 * @param HRTIMx High Resolution Timer instance 01639 * @param Outputs This parameter can be a combination of the following values: 01640 * @arg @ref LL_HRTIM_OUTPUT_TA1 01641 * @arg @ref LL_HRTIM_OUTPUT_TA2 01642 * @arg @ref LL_HRTIM_OUTPUT_TB1 01643 * @arg @ref LL_HRTIM_OUTPUT_TB2 01644 * @arg @ref LL_HRTIM_OUTPUT_TC1 01645 * @arg @ref LL_HRTIM_OUTPUT_TC2 01646 * @arg @ref LL_HRTIM_OUTPUT_TD1 01647 * @arg @ref LL_HRTIM_OUTPUT_TD2 01648 * @arg @ref LL_HRTIM_OUTPUT_TE1 01649 * @arg @ref LL_HRTIM_OUTPUT_TE2 01650 * @retval None 01651 */ 01652 __STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs) 01653 { 01654 SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK)); 01655 } 01656 01657 /** 01658 * @brief Disable the HRTIM timer(s) output(s) . 01659 * @rmtoll OENR TA1OEN LL_HRTIM_DisableOutput\n 01660 * OENR TA2OEN LL_HRTIM_DisableOutput\n 01661 * OENR TB1OEN LL_HRTIM_DisableOutput\n 01662 * OENR TB2OEN LL_HRTIM_DisableOutput\n 01663 * OENR TC1OEN LL_HRTIM_DisableOutput\n 01664 * OENR TC2OEN LL_HRTIM_DisableOutput\n 01665 * OENR TD1OEN LL_HRTIM_DisableOutput\n 01666 * OENR TD2OEN LL_HRTIM_DisableOutput\n 01667 * OENR TE1OEN LL_HRTIM_DisableOutput\n 01668 * OENR TE2OEN LL_HRTIM_DisableOutput 01669 * @param HRTIMx High Resolution Timer instance 01670 * @param Outputs This parameter can be a combination of the following values: 01671 * @arg @ref LL_HRTIM_OUTPUT_TA1 01672 * @arg @ref LL_HRTIM_OUTPUT_TA2 01673 * @arg @ref LL_HRTIM_OUTPUT_TB1 01674 * @arg @ref LL_HRTIM_OUTPUT_TB2 01675 * @arg @ref LL_HRTIM_OUTPUT_TC1 01676 * @arg @ref LL_HRTIM_OUTPUT_TC2 01677 * @arg @ref LL_HRTIM_OUTPUT_TD1 01678 * @arg @ref LL_HRTIM_OUTPUT_TD2 01679 * @arg @ref LL_HRTIM_OUTPUT_TE1 01680 * @arg @ref LL_HRTIM_OUTPUT_TE2 01681 * @retval None 01682 */ 01683 __STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs) 01684 { 01685 SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK)); 01686 } 01687 01688 /** 01689 * @brief Indicates whether the HRTIM timer output is enabled. 01690 * @rmtoll OENR TA1OEN LL_HRTIM_IsEnabledOutput\n 01691 * OENR TA2OEN LL_HRTIM_IsEnabledOutput\n 01692 * OENR TB1OEN LL_HRTIM_IsEnabledOutput\n 01693 * OENR TB2OEN LL_HRTIM_IsEnabledOutput\n 01694 * OENR TC1OEN LL_HRTIM_IsEnabledOutput\n 01695 * OENR TC2OEN LL_HRTIM_IsEnabledOutput\n 01696 * OENR TD1OEN LL_HRTIM_IsEnabledOutput\n 01697 * OENR TD2OEN LL_HRTIM_IsEnabledOutput\n 01698 * OENR TE1OEN LL_HRTIM_IsEnabledOutput\n 01699 * OENR TE2OEN LL_HRTIM_IsEnabledOutput 01700 * @param HRTIMx High Resolution Timer instance 01701 * @param Output This parameter can be one of the following values: 01702 * @arg @ref LL_HRTIM_OUTPUT_TA1 01703 * @arg @ref LL_HRTIM_OUTPUT_TA2 01704 * @arg @ref LL_HRTIM_OUTPUT_TB1 01705 * @arg @ref LL_HRTIM_OUTPUT_TB2 01706 * @arg @ref LL_HRTIM_OUTPUT_TC1 01707 * @arg @ref LL_HRTIM_OUTPUT_TC2 01708 * @arg @ref LL_HRTIM_OUTPUT_TD1 01709 * @arg @ref LL_HRTIM_OUTPUT_TD2 01710 * @arg @ref LL_HRTIM_OUTPUT_TE1 01711 * @arg @ref LL_HRTIM_OUTPUT_TE2 01712 * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0). 01713 */ 01714 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output) 01715 { 01716 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL); 01717 } 01718 01719 /** 01720 * @brief Indicates whether the HRTIM timer output is disabled. 01721 * @rmtoll ODISR TA1ODIS LL_HRTIM_IsDisabledOutput\n 01722 * ODISR TA2ODIS LL_HRTIM_IsDisabledOutput\n 01723 * ODISR TB1ODIS LL_HRTIM_IsDisabledOutput\n 01724 * ODISR TB2ODIS LL_HRTIM_IsDisabledOutput\n 01725 * ODISR TC1ODIS LL_HRTIM_IsDisabledOutput\n 01726 * ODISR TC2ODIS LL_HRTIM_IsDisabledOutput\n 01727 * ODISR TD1ODIS LL_HRTIM_IsDisabledOutput\n 01728 * ODISR TD2ODIS LL_HRTIM_IsDisabledOutput\n 01729 * ODISR TE1ODIS LL_HRTIM_IsDisabledOutput\n 01730 * ODISR TE2ODIS LL_HRTIM_IsDisabledOutput 01731 * @param HRTIMx High Resolution Timer instance 01732 * @param Output This parameter can be one of the following values: 01733 * @arg @ref LL_HRTIM_OUTPUT_TA1 01734 * @arg @ref LL_HRTIM_OUTPUT_TA2 01735 * @arg @ref LL_HRTIM_OUTPUT_TB1 01736 * @arg @ref LL_HRTIM_OUTPUT_TB2 01737 * @arg @ref LL_HRTIM_OUTPUT_TC1 01738 * @arg @ref LL_HRTIM_OUTPUT_TC2 01739 * @arg @ref LL_HRTIM_OUTPUT_TD1 01740 * @arg @ref LL_HRTIM_OUTPUT_TD2 01741 * @arg @ref LL_HRTIM_OUTPUT_TE1 01742 * @arg @ref LL_HRTIM_OUTPUT_TE2 01743 * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0). 01744 */ 01745 __STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output) 01746 { 01747 return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL); 01748 } 01749 01750 /** 01751 * @brief Configure an ADC trigger. 01752 * @rmtoll CR1 ADC1USRC LL_HRTIM_ConfigADCTrig\n 01753 * CR1 ADC2USRC LL_HRTIM_ConfigADCTrig\n 01754 * CR1 ADC3USRC LL_HRTIM_ConfigADCTrig\n 01755 * CR1 ADC4USRC LL_HRTIM_ConfigADCTrig\n 01756 * ADC1R ADC1MC1 LL_HRTIM_ConfigADCTrig\n 01757 * ADC1R ADC1MC2 LL_HRTIM_ConfigADCTrig\n 01758 * ADC1R ADC1MC3 LL_HRTIM_ConfigADCTrig\n 01759 * ADC1R ADC1MC4 LL_HRTIM_ConfigADCTrig\n 01760 * ADC1R ADC1MPER LL_HRTIM_ConfigADCTrig\n 01761 * ADC1R ADC1EEV1 LL_HRTIM_ConfigADCTrig\n 01762 * ADC1R ADC1EEV2 LL_HRTIM_ConfigADCTrig\n 01763 * ADC1R ADC1EEV3 LL_HRTIM_ConfigADCTrig\n 01764 * ADC1R ADC1EEV4 LL_HRTIM_ConfigADCTrig\n 01765 * ADC1R ADC1EEV5 LL_HRTIM_ConfigADCTrig\n 01766 * ADC1R ADC1TAC2 LL_HRTIM_ConfigADCTrig\n 01767 * ADC1R ADC1TAC3 LL_HRTIM_ConfigADCTrig\n 01768 * ADC1R ADC1TAC4 LL_HRTIM_ConfigADCTrig\n 01769 * ADC1R ADC1TAPER LL_HRTIM_ConfigADCTrig\n 01770 * ADC1R ADC1TARST LL_HRTIM_ConfigADCTrig\n 01771 * ADC1R ADC1TBC2 LL_HRTIM_ConfigADCTrig\n 01772 * ADC1R ADC1TBC3 LL_HRTIM_ConfigADCTrig\n 01773 * ADC1R ADC1TBC4 LL_HRTIM_ConfigADCTrig\n 01774 * ADC1R ADC1TBPER LL_HRTIM_ConfigADCTrig\n 01775 * ADC1R ADC1TBRST LL_HRTIM_ConfigADCTrig\n 01776 * ADC1R ADC1TCC2 LL_HRTIM_ConfigADCTrig\n 01777 * ADC1R ADC1TCC3 LL_HRTIM_ConfigADCTrig\n 01778 * ADC1R ADC1TCC4 LL_HRTIM_ConfigADCTrig\n 01779 * ADC1R ADC1TCPER LL_HRTIM_ConfigADCTrig\n 01780 * ADC1R ADC1TDC2 LL_HRTIM_ConfigADCTrig\n 01781 * ADC1R ADC1TDC3 LL_HRTIM_ConfigADCTrig\n 01782 * ADC1R ADC1TDC4 LL_HRTIM_ConfigADCTrig\n 01783 * ADC1R ADC1TDPER LL_HRTIM_ConfigADCTrig\n 01784 * ADC1R ADC1TEC2 LL_HRTIM_ConfigADCTrig\n 01785 * ADC1R ADC1TEC3 LL_HRTIM_ConfigADCTrig\n 01786 * ADC1R ADC1TEC4 LL_HRTIM_ConfigADCTrig\n 01787 * ADC1R ADC1TEPER LL_HRTIM_ConfigADCTrig\n 01788 * ADC2R ADC2MC1 LL_HRTIM_ConfigADCTrig\n 01789 * ADC2R ADC2MC2 LL_HRTIM_ConfigADCTrig\n 01790 * ADC2R ADC2MC3 LL_HRTIM_ConfigADCTrig\n 01791 * ADC2R ADC2MC4 LL_HRTIM_ConfigADCTrig\n 01792 * ADC2R ADC2MPER LL_HRTIM_ConfigADCTrig\n 01793 * ADC2R ADC2EEV6 LL_HRTIM_ConfigADCTrig\n 01794 * ADC2R ADC2EEV7 LL_HRTIM_ConfigADCTrig\n 01795 * ADC2R ADC2EEV8 LL_HRTIM_ConfigADCTrig\n 01796 * ADC2R ADC2EEV9 LL_HRTIM_ConfigADCTrig\n 01797 * ADC2R ADC2EEV10 LL_HRTIM_ConfigADCTrig\n 01798 * ADC2R ADC2TAC2 LL_HRTIM_ConfigADCTrig\n 01799 * ADC2R ADC2TAC3 LL_HRTIM_ConfigADCTrig\n 01800 * ADC2R ADC2TAC4 LL_HRTIM_ConfigADCTrig\n 01801 * ADC2R ADC2TAPER LL_HRTIM_ConfigADCTrig\n 01802 * ADC2R ADC2TBC2 LL_HRTIM_ConfigADCTrig\n 01803 * ADC2R ADC2TBC3 LL_HRTIM_ConfigADCTrig\n 01804 * ADC2R ADC2TBC4 LL_HRTIM_ConfigADCTrig\n 01805 * ADC2R ADC2TBPER LL_HRTIM_ConfigADCTrig\n 01806 * ADC2R ADC2TCC2 LL_HRTIM_ConfigADCTrig\n 01807 * ADC2R ADC2TCC3 LL_HRTIM_ConfigADCTrig\n 01808 * ADC2R ADC2TCC4 LL_HRTIM_ConfigADCTrig\n 01809 * ADC2R ADC2TCPER LL_HRTIM_ConfigADCTrig\n 01810 * ADC2R ADC2TCRST LL_HRTIM_ConfigADCTrig\n 01811 * ADC2R ADC2TDC2 LL_HRTIM_ConfigADCTrig\n 01812 * ADC2R ADC2TDC3 LL_HRTIM_ConfigADCTrig\n 01813 * ADC2R ADC2TDC4 LL_HRTIM_ConfigADCTrig\n 01814 * ADC2R ADC2TDPER LL_HRTIM_ConfigADCTrig\n 01815 * ADC2R ADC2TDRST LL_HRTIM_ConfigADCTrig\n 01816 * ADC2R ADC2TEC2 LL_HRTIM_ConfigADCTrig\n 01817 * ADC2R ADC2TEC3 LL_HRTIM_ConfigADCTrig\n 01818 * ADC2R ADC2TEC4 LL_HRTIM_ConfigADCTrig\n 01819 * ADC2R ADC2TERST LL_HRTIM_ConfigADCTrig\n 01820 * ADC3R ADC3MC1 LL_HRTIM_ConfigADCTrig\n 01821 * ADC3R ADC3MC2 LL_HRTIM_ConfigADCTrig\n 01822 * ADC3R ADC3MC3 LL_HRTIM_ConfigADCTrig\n 01823 * ADC3R ADC3MC4 LL_HRTIM_ConfigADCTrig\n 01824 * ADC3R ADC3MPER LL_HRTIM_ConfigADCTrig\n 01825 * ADC3R ADC3EEV1 LL_HRTIM_ConfigADCTrig\n 01826 * ADC3R ADC3EEV2 LL_HRTIM_ConfigADCTrig\n 01827 * ADC3R ADC3EEV3 LL_HRTIM_ConfigADCTrig\n 01828 * ADC3R ADC3EEV4 LL_HRTIM_ConfigADCTrig\n 01829 * ADC3R ADC3EEV5 LL_HRTIM_ConfigADCTrig\n 01830 * ADC3R ADC3TAC2 LL_HRTIM_ConfigADCTrig\n 01831 * ADC3R ADC3TAC3 LL_HRTIM_ConfigADCTrig\n 01832 * ADC3R ADC3TAC4 LL_HRTIM_ConfigADCTrig\n 01833 * ADC3R ADC3TAPER LL_HRTIM_ConfigADCTrig\n 01834 * ADC3R ADC3TARST LL_HRTIM_ConfigADCTrig\n 01835 * ADC3R ADC3TBC2 LL_HRTIM_ConfigADCTrig\n 01836 * ADC3R ADC3TBC3 LL_HRTIM_ConfigADCTrig\n 01837 * ADC3R ADC3TBC4 LL_HRTIM_ConfigADCTrig\n 01838 * ADC3R ADC3TBPER LL_HRTIM_ConfigADCTrig\n 01839 * ADC3R ADC3TBRST LL_HRTIM_ConfigADCTrig\n 01840 * ADC3R ADC3TCC2 LL_HRTIM_ConfigADCTrig\n 01841 * ADC3R ADC3TCC3 LL_HRTIM_ConfigADCTrig\n 01842 * ADC3R ADC3TCC4 LL_HRTIM_ConfigADCTrig\n 01843 * ADC3R ADC3TCPER LL_HRTIM_ConfigADCTrig\n 01844 * ADC3R ADC3TDC2 LL_HRTIM_ConfigADCTrig\n 01845 * ADC3R ADC3TDC3 LL_HRTIM_ConfigADCTrig\n 01846 * ADC3R ADC3TDC4 LL_HRTIM_ConfigADCTrig\n 01847 * ADC3R ADC3TDPER LL_HRTIM_ConfigADCTrig\n 01848 * ADC3R ADC3TEC2 LL_HRTIM_ConfigADCTrig\n 01849 * ADC3R ADC3TEC3 LL_HRTIM_ConfigADCTrig\n 01850 * ADC3R ADC3TEC4 LL_HRTIM_ConfigADCTrig\n 01851 * ADC3R ADC3TEPER LL_HRTIM_ConfigADCTrig\n 01852 * ADC4R ADC4MC1 LL_HRTIM_ConfigADCTrig\n 01853 * ADC4R ADC4MC2 LL_HRTIM_ConfigADCTrig\n 01854 * ADC4R ADC4MC3 LL_HRTIM_ConfigADCTrig\n 01855 * ADC4R ADC4MC4 LL_HRTIM_ConfigADCTrig\n 01856 * ADC4R ADC4MPER LL_HRTIM_ConfigADCTrig\n 01857 * ADC4R ADC4EEV6 LL_HRTIM_ConfigADCTrig\n 01858 * ADC4R ADC4EEV7 LL_HRTIM_ConfigADCTrig\n 01859 * ADC4R ADC4EEV8 LL_HRTIM_ConfigADCTrig\n 01860 * ADC4R ADC4EEV9 LL_HRTIM_ConfigADCTrig\n 01861 * ADC4R ADC4EEV10 LL_HRTIM_ConfigADCTrig\n 01862 * ADC4R ADC4TAC2 LL_HRTIM_ConfigADCTrig\n 01863 * ADC4R ADC4TAC3 LL_HRTIM_ConfigADCTrig\n 01864 * ADC4R ADC4TAC4 LL_HRTIM_ConfigADCTrig\n 01865 * ADC4R ADC4TAPER LL_HRTIM_ConfigADCTrig\n 01866 * ADC4R ADC4TBC2 LL_HRTIM_ConfigADCTrig\n 01867 * ADC4R ADC4TBC3 LL_HRTIM_ConfigADCTrig\n 01868 * ADC4R ADC4TBC4 LL_HRTIM_ConfigADCTrig\n 01869 * ADC4R ADC4TBPER LL_HRTIM_ConfigADCTrig\n 01870 * ADC4R ADC4TCC2 LL_HRTIM_ConfigADCTrig\n 01871 * ADC4R ADC4TCC3 LL_HRTIM_ConfigADCTrig\n 01872 * ADC4R ADC4TCC4 LL_HRTIM_ConfigADCTrig\n 01873 * ADC4R ADC4TCPER LL_HRTIM_ConfigADCTrig\n 01874 * ADC4R ADC4TCRST LL_HRTIM_ConfigADCTrig\n 01875 * ADC4R ADC4TDC2 LL_HRTIM_ConfigADCTrig\n 01876 * ADC4R ADC4TDC3 LL_HRTIM_ConfigADCTrig\n 01877 * ADC4R ADC4TDC4 LL_HRTIM_ConfigADCTrig\n 01878 * ADC4R ADC4TDPER LL_HRTIM_ConfigADCTrig\n 01879 * ADC4R ADC4TDRST LL_HRTIM_ConfigADCTrig\n 01880 * ADC4R ADC4TEC2 LL_HRTIM_ConfigADCTrig\n 01881 * ADC4R ADC4TEC3 LL_HRTIM_ConfigADCTrig\n 01882 * ADC4R ADC4TEC4 LL_HRTIM_ConfigADCTrig\n 01883 * ADC4R ADC4TERST LL_HRTIM_ConfigADCTrig 01884 * @param HRTIMx High Resolution Timer instance 01885 * @param ADCTrig This parameter can be one of the following values: 01886 * @arg @ref LL_HRTIM_ADCTRIG_1 01887 * @arg @ref LL_HRTIM_ADCTRIG_2 01888 * @arg @ref LL_HRTIM_ADCTRIG_3 01889 * @arg @ref LL_HRTIM_ADCTRIG_4 01890 * @param Update This parameter can be one of the following values: 01891 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER 01892 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 01893 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 01894 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 01895 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 01896 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 01897 * @param Src This parameter can be a combination of the following values: 01898 * 01899 * For ADC trigger 1 and ADC trigger 3: 01900 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE 01901 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1 01902 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2 01903 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3 01904 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4 01905 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER 01906 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1 01907 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2 01908 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3 01909 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4 01910 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5 01911 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 01912 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 01913 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 01914 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER 01915 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST 01916 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 01917 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 01918 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 01919 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER 01920 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST 01921 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 01922 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 01923 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 01924 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER 01925 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 01926 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 01927 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 01928 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER 01929 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 01930 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 01931 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 01932 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER 01933 * 01934 * For ADC trigger 2 and ADC trigger 4: 01935 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE 01936 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1 01937 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2 01938 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3 01939 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4 01940 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER 01941 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6 01942 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7 01943 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8 01944 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9 01945 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10 01946 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 01947 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 01948 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 01949 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER 01950 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 01951 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 01952 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 01953 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER 01954 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 01955 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 01956 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 01957 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER 01958 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST 01959 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 01960 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 01961 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 01962 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER 01963 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST 01964 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 01965 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 01966 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 01967 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST 01968 * 01969 * @retval None 01970 */ 01971 __STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src) 01972 { 01973 uint32_t shift = ((3U * ADCTrig) & 0x1FU); 01974 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + 01975 REG_OFFSET_TAB_ADCxR[ADCTrig])); 01976 MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); 01977 WRITE_REG(*pReg, Src); 01978 } 01979 01980 /** 01981 * @brief Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register. 01982 * @rmtoll CR1 ADC1USRC LL_HRTIM_SetADCTrigUpdate\n 01983 * CR1 ADC2USRC LL_HRTIM_SetADCTrigUpdate\n 01984 * CR1 ADC3USRC LL_HRTIM_SetADCTrigUpdate\n 01985 * CR1 ADC4USRC LL_HRTIM_SetADCTrigUpdate\n 01986 * @note When the preload is disabled in the source timer, the HRTIM_ADCxR 01987 * registers are not preloaded either: a write access will result in an 01988 * immediate update of the trigger source. 01989 * @param HRTIMx High Resolution Timer instance 01990 * @param ADCTrig This parameter can be one of the following values: 01991 * @arg @ref LL_HRTIM_ADCTRIG_1 01992 * @arg @ref LL_HRTIM_ADCTRIG_2 01993 * @arg @ref LL_HRTIM_ADCTRIG_3 01994 * @arg @ref LL_HRTIM_ADCTRIG_4 01995 * @param Update This parameter can be one of the following values: 01996 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER 01997 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 01998 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 01999 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 02000 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 02001 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 02002 * @retval None 02003 */ 02004 __STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update) 02005 { 02006 uint32_t shift = ((3U * ADCTrig) & 0x1FU); 02007 MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift)); 02008 } 02009 02010 /** 02011 * @brief Get the source timer triggering the update of the HRTIM_ADCxR register. 02012 * @rmtoll CR1 ADC1USRC LL_HRTIM_GetADCTrigUpdate\n 02013 * CR1 ADC2USRC LL_HRTIM_GetADCTrigUpdate\n 02014 * CR1 ADC3USRC LL_HRTIM_GetADCTrigUpdate\n 02015 * CR1 ADC4USRC LL_HRTIM_GetADCTrigUpdate\n 02016 * @param HRTIMx High Resolution Timer instance 02017 * @param ADCTrig This parameter can be one of the following values: 02018 * @arg @ref LL_HRTIM_ADCTRIG_1 02019 * @arg @ref LL_HRTIM_ADCTRIG_2 02020 * @arg @ref LL_HRTIM_ADCTRIG_3 02021 * @arg @ref LL_HRTIM_ADCTRIG_4 02022 * @retval Update Returned value can be one of the following values: 02023 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER 02024 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 02025 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 02026 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 02027 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 02028 * @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 02029 */ 02030 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) 02031 { 02032 const uint32_t shift = ((3U * ADCTrig) & 0x1FU); 02033 return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift); 02034 } 02035 02036 /** 02037 * @brief Specify which events (timer events and/or external events) are used as triggers for ADC conversion. 02038 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_SetADCTrigSrc\n 02039 * ADC1R ADC1MC2 LL_HRTIM_SetADCTrigSrc\n 02040 * ADC1R ADC1MC3 LL_HRTIM_SetADCTrigSrc\n 02041 * ADC1R ADC1MC4 LL_HRTIM_SetADCTrigSrc\n 02042 * ADC1R ADC1MPER LL_HRTIM_SetADCTrigSrc\n 02043 * ADC1R ADC1EEV1 LL_HRTIM_SetADCTrigSrc\n 02044 * ADC1R ADC1EEV2 LL_HRTIM_SetADCTrigSrc\n 02045 * ADC1R ADC1EEV3 LL_HRTIM_SetADCTrigSrc\n 02046 * ADC1R ADC1EEV4 LL_HRTIM_SetADCTrigSrc\n 02047 * ADC1R ADC1EEV5 LL_HRTIM_SetADCTrigSrc\n 02048 * ADC1R ADC1TAC2 LL_HRTIM_SetADCTrigSrc\n 02049 * ADC1R ADC1TAC3 LL_HRTIM_SetADCTrigSrc\n 02050 * ADC1R ADC1TAC4 LL_HRTIM_SetADCTrigSrc\n 02051 * ADC1R ADC1TAPER LL_HRTIM_SetADCTrigSrc\n 02052 * ADC1R ADC1TARST LL_HRTIM_SetADCTrigSrc\n 02053 * ADC1R ADC1TBC2 LL_HRTIM_SetADCTrigSrc\n 02054 * ADC1R ADC1TBC3 LL_HRTIM_SetADCTrigSrc\n 02055 * ADC1R ADC1TBC4 LL_HRTIM_SetADCTrigSrc\n 02056 * ADC1R ADC1TBPER LL_HRTIM_SetADCTrigSrc\n 02057 * ADC1R ADC1TBRST LL_HRTIM_SetADCTrigSrc\n 02058 * ADC1R ADC1TCC2 LL_HRTIM_SetADCTrigSrc\n 02059 * ADC1R ADC1TCC3 LL_HRTIM_SetADCTrigSrc\n 02060 * ADC1R ADC1TCC4 LL_HRTIM_SetADCTrigSrc\n 02061 * ADC1R ADC1TCPER LL_HRTIM_SetADCTrigSrc\n 02062 * ADC1R ADC1TDC2 LL_HRTIM_SetADCTrigSrc\n 02063 * ADC1R ADC1TDC3 LL_HRTIM_SetADCTrigSrc\n 02064 * ADC1R ADC1TDC4 LL_HRTIM_SetADCTrigSrc\n 02065 * ADC1R ADC1TDPER LL_HRTIM_SetADCTrigSrc\n 02066 * ADC1R ADC1TEC2 LL_HRTIM_SetADCTrigSrc\n 02067 * ADC1R ADC1TEC3 LL_HRTIM_SetADCTrigSrc\n 02068 * ADC1R ADC1TEC4 LL_HRTIM_SetADCTrigSrc\n 02069 * ADC1R ADC1TEPER LL_HRTIM_SetADCTrigSrc\n 02070 * ADC2R ADC2MC1 LL_HRTIM_SetADCTrigSrc\n 02071 * ADC2R ADC2MC2 LL_HRTIM_SetADCTrigSrc\n 02072 * ADC2R ADC2MC3 LL_HRTIM_SetADCTrigSrc\n 02073 * ADC2R ADC2MC4 LL_HRTIM_SetADCTrigSrc\n 02074 * ADC2R ADC2MPER LL_HRTIM_SetADCTrigSrc\n 02075 * ADC2R ADC2EEV6 LL_HRTIM_SetADCTrigSrc\n 02076 * ADC2R ADC2EEV7 LL_HRTIM_SetADCTrigSrc\n 02077 * ADC2R ADC2EEV8 LL_HRTIM_SetADCTrigSrc\n 02078 * ADC2R ADC2EEV9 LL_HRTIM_SetADCTrigSrc\n 02079 * ADC2R ADC2EEV10 LL_HRTIM_SetADCTrigSrc\n 02080 * ADC2R ADC2TAC2 LL_HRTIM_SetADCTrigSrc\n 02081 * ADC2R ADC2TAC3 LL_HRTIM_SetADCTrigSrc\n 02082 * ADC2R ADC2TAC4 LL_HRTIM_SetADCTrigSrc\n 02083 * ADC2R ADC2TAPER LL_HRTIM_SetADCTrigSrc\n 02084 * ADC2R ADC2TBC2 LL_HRTIM_SetADCTrigSrc\n 02085 * ADC2R ADC2TBC3 LL_HRTIM_SetADCTrigSrc\n 02086 * ADC2R ADC2TBC4 LL_HRTIM_SetADCTrigSrc\n 02087 * ADC2R ADC2TBPER LL_HRTIM_SetADCTrigSrc\n 02088 * ADC2R ADC2TCC2 LL_HRTIM_SetADCTrigSrc\n 02089 * ADC2R ADC2TCC3 LL_HRTIM_SetADCTrigSrc\n 02090 * ADC2R ADC2TCC4 LL_HRTIM_SetADCTrigSrc\n 02091 * ADC2R ADC2TCPER LL_HRTIM_SetADCTrigSrc\n 02092 * ADC2R ADC2TCRST LL_HRTIM_SetADCTrigSrc\n 02093 * ADC2R ADC2TDC2 LL_HRTIM_SetADCTrigSrc\n 02094 * ADC2R ADC2TDC3 LL_HRTIM_SetADCTrigSrc\n 02095 * ADC2R ADC2TDC4 LL_HRTIM_SetADCTrigSrc\n 02096 * ADC2R ADC2TDPER LL_HRTIM_SetADCTrigSrc\n 02097 * ADC2R ADC2TDRST LL_HRTIM_SetADCTrigSrc\n 02098 * ADC2R ADC2TEC2 LL_HRTIM_SetADCTrigSrc\n 02099 * ADC2R ADC2TEC3 LL_HRTIM_SetADCTrigSrc\n 02100 * ADC2R ADC2TEC4 LL_HRTIM_SetADCTrigSrc\n 02101 * ADC2R ADC2TERST LL_HRTIM_SetADCTrigSrc\n 02102 * ADC3R ADC3MC1 LL_HRTIM_SetADCTrigSrc\n 02103 * ADC3R ADC3MC2 LL_HRTIM_SetADCTrigSrc\n 02104 * ADC3R ADC3MC3 LL_HRTIM_SetADCTrigSrc\n 02105 * ADC3R ADC3MC4 LL_HRTIM_SetADCTrigSrc\n 02106 * ADC3R ADC3MPER LL_HRTIM_SetADCTrigSrc\n 02107 * ADC3R ADC3EEV1 LL_HRTIM_SetADCTrigSrc\n 02108 * ADC3R ADC3EEV2 LL_HRTIM_SetADCTrigSrc\n 02109 * ADC3R ADC3EEV3 LL_HRTIM_SetADCTrigSrc\n 02110 * ADC3R ADC3EEV4 LL_HRTIM_SetADCTrigSrc\n 02111 * ADC3R ADC3EEV5 LL_HRTIM_SetADCTrigSrc\n 02112 * ADC3R ADC3TAC2 LL_HRTIM_SetADCTrigSrc\n 02113 * ADC3R ADC3TAC3 LL_HRTIM_SetADCTrigSrc\n 02114 * ADC3R ADC3TAC4 LL_HRTIM_SetADCTrigSrc\n 02115 * ADC3R ADC3TAPER LL_HRTIM_SetADCTrigSrc\n 02116 * ADC3R ADC3TARST LL_HRTIM_SetADCTrigSrc\n 02117 * ADC3R ADC3TBC2 LL_HRTIM_SetADCTrigSrc\n 02118 * ADC3R ADC3TBC3 LL_HRTIM_SetADCTrigSrc\n 02119 * ADC3R ADC3TBC4 LL_HRTIM_SetADCTrigSrc\n 02120 * ADC3R ADC3TBPER LL_HRTIM_SetADCTrigSrc\n 02121 * ADC3R ADC3TBRST LL_HRTIM_SetADCTrigSrc\n 02122 * ADC3R ADC3TCC2 LL_HRTIM_SetADCTrigSrc\n 02123 * ADC3R ADC3TCC3 LL_HRTIM_SetADCTrigSrc\n 02124 * ADC3R ADC3TCC4 LL_HRTIM_SetADCTrigSrc\n 02125 * ADC3R ADC3TCPER LL_HRTIM_SetADCTrigSrc\n 02126 * ADC3R ADC3TDC2 LL_HRTIM_SetADCTrigSrc\n 02127 * ADC3R ADC3TDC3 LL_HRTIM_SetADCTrigSrc\n 02128 * ADC3R ADC3TDC4 LL_HRTIM_SetADCTrigSrc\n 02129 * ADC3R ADC3TDPER LL_HRTIM_SetADCTrigSrc\n 02130 * ADC3R ADC3TEC2 LL_HRTIM_SetADCTrigSrc\n 02131 * ADC3R ADC3TEC3 LL_HRTIM_SetADCTrigSrc\n 02132 * ADC3R ADC3TEC4 LL_HRTIM_SetADCTrigSrc\n 02133 * ADC3R ADC3TEPER LL_HRTIM_SetADCTrigSrc\n 02134 * ADC4R ADC4MC1 LL_HRTIM_SetADCTrigSrc\n 02135 * ADC4R ADC4MC2 LL_HRTIM_SetADCTrigSrc\n 02136 * ADC4R ADC4MC3 LL_HRTIM_SetADCTrigSrc\n 02137 * ADC4R ADC4MC4 LL_HRTIM_SetADCTrigSrc\n 02138 * ADC4R ADC4MPER LL_HRTIM_SetADCTrigSrc\n 02139 * ADC4R ADC4EEV6 LL_HRTIM_SetADCTrigSrc\n 02140 * ADC4R ADC4EEV7 LL_HRTIM_SetADCTrigSrc\n 02141 * ADC4R ADC4EEV8 LL_HRTIM_SetADCTrigSrc\n 02142 * ADC4R ADC4EEV9 LL_HRTIM_SetADCTrigSrc\n 02143 * ADC4R ADC4EEV10 LL_HRTIM_SetADCTrigSrc\n 02144 * ADC4R ADC4TAC2 LL_HRTIM_SetADCTrigSrc\n 02145 * ADC4R ADC4TAC3 LL_HRTIM_SetADCTrigSrc\n 02146 * ADC4R ADC4TAC4 LL_HRTIM_SetADCTrigSrc\n 02147 * ADC4R ADC4TAPER LL_HRTIM_SetADCTrigSrc\n 02148 * ADC4R ADC4TBC2 LL_HRTIM_SetADCTrigSrc\n 02149 * ADC4R ADC4TBC3 LL_HRTIM_SetADCTrigSrc\n 02150 * ADC4R ADC4TBC4 LL_HRTIM_SetADCTrigSrc\n 02151 * ADC4R ADC4TBPER LL_HRTIM_SetADCTrigSrc\n 02152 * ADC4R ADC4TCC2 LL_HRTIM_SetADCTrigSrc\n 02153 * ADC4R ADC4TCC3 LL_HRTIM_SetADCTrigSrc\n 02154 * ADC4R ADC4TCC4 LL_HRTIM_SetADCTrigSrc\n 02155 * ADC4R ADC4TCPER LL_HRTIM_SetADCTrigSrc\n 02156 * ADC4R ADC4TCRST LL_HRTIM_SetADCTrigSrc\n 02157 * ADC4R ADC4TDC2 LL_HRTIM_SetADCTrigSrc\n 02158 * ADC4R ADC4TDC3 LL_HRTIM_SetADCTrigSrc\n 02159 * ADC4R ADC4TDC4 LL_HRTIM_SetADCTrigSrc\n 02160 * ADC4R ADC4TDPER LL_HRTIM_SetADCTrigSrc\n 02161 * ADC4R ADC4TDRST LL_HRTIM_SetADCTrigSrc\n 02162 * ADC4R ADC4TEC2 LL_HRTIM_SetADCTrigSrc\n 02163 * ADC4R ADC4TEC3 LL_HRTIM_SetADCTrigSrc\n 02164 * ADC4R ADC4TEC4 LL_HRTIM_SetADCTrigSrc\n 02165 * ADC4R ADC4TERST LL_HRTIM_SetADCTrigSrc\n 02166 * @param HRTIMx High Resolution Timer instance 02167 * @param ADCTrig This parameter can be one of the following values: 02168 * @arg @ref LL_HRTIM_ADCTRIG_1 02169 * @arg @ref LL_HRTIM_ADCTRIG_2 02170 * @arg @ref LL_HRTIM_ADCTRIG_3 02171 * @arg @ref LL_HRTIM_ADCTRIG_4 02172 * @param Src 02173 * For ADC trigger 1 and ADC trigger 3 this parameter can be a 02174 * combination of the following values: 02175 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE 02176 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1 02177 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2 02178 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3 02179 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4 02180 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER 02181 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1 02182 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2 02183 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3 02184 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4 02185 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5 02186 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 02187 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 02188 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 02189 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER 02190 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST 02191 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 02192 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 02193 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 02194 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER 02195 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST 02196 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 02197 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 02198 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 02199 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER 02200 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 02201 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 02202 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 02203 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER 02204 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 02205 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 02206 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 02207 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER 02208 * 02209 * For ADC trigger 2 and ADC trigger 4 this parameter can be a 02210 * combination of the following values: 02211 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE 02212 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1 02213 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2 02214 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3 02215 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4 02216 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER 02217 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6 02218 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7 02219 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8 02220 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9 02221 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10 02222 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 02223 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 02224 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 02225 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER 02226 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 02227 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 02228 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 02229 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER 02230 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 02231 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 02232 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 02233 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER 02234 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST 02235 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 02236 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 02237 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 02238 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER 02239 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST 02240 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 02241 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 02242 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 02243 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST 02244 * 02245 * @retval None 02246 */ 02247 __STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src) 02248 { 02249 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + 02250 REG_OFFSET_TAB_ADCxR[ADCTrig])); 02251 WRITE_REG(*pReg, Src); 02252 } 02253 02254 /** 02255 * @brief Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion. 02256 * @rmtoll ADC1R ADC1MC1 LL_HRTIM_GetADCTrigSrc\n 02257 * ADC1R ADC1MC2 LL_HRTIM_GetADCTrigSrc\n 02258 * ADC1R ADC1MC3 LL_HRTIM_GetADCTrigSrc\n 02259 * ADC1R ADC1MC4 LL_HRTIM_GetADCTrigSrc\n 02260 * ADC1R ADC1MPER LL_HRTIM_GetADCTrigSrc\n 02261 * ADC1R ADC1EEV1 LL_HRTIM_GetADCTrigSrc\n 02262 * ADC1R ADC1EEV2 LL_HRTIM_GetADCTrigSrc\n 02263 * ADC1R ADC1EEV3 LL_HRTIM_GetADCTrigSrc\n 02264 * ADC1R ADC1EEV4 LL_HRTIM_GetADCTrigSrc\n 02265 * ADC1R ADC1EEV5 LL_HRTIM_GetADCTrigSrc\n 02266 * ADC1R ADC1TAC2 LL_HRTIM_GetADCTrigSrc\n 02267 * ADC1R ADC1TAC3 LL_HRTIM_GetADCTrigSrc\n 02268 * ADC1R ADC1TAC4 LL_HRTIM_GetADCTrigSrc\n 02269 * ADC1R ADC1TAPER LL_HRTIM_GetADCTrigSrc\n 02270 * ADC1R ADC1TARST LL_HRTIM_GetADCTrigSrc\n 02271 * ADC1R ADC1TBC2 LL_HRTIM_GetADCTrigSrc\n 02272 * ADC1R ADC1TBC3 LL_HRTIM_GetADCTrigSrc\n 02273 * ADC1R ADC1TBC4 LL_HRTIM_GetADCTrigSrc\n 02274 * ADC1R ADC1TBPER LL_HRTIM_GetADCTrigSrc\n 02275 * ADC1R ADC1TBRST LL_HRTIM_GetADCTrigSrc\n 02276 * ADC1R ADC1TCC2 LL_HRTIM_GetADCTrigSrc\n 02277 * ADC1R ADC1TCC3 LL_HRTIM_GetADCTrigSrc\n 02278 * ADC1R ADC1TCC4 LL_HRTIM_GetADCTrigSrc\n 02279 * ADC1R ADC1TCPER LL_HRTIM_GetADCTrigSrc\n 02280 * ADC1R ADC1TDC2 LL_HRTIM_GetADCTrigSrc\n 02281 * ADC1R ADC1TDC3 LL_HRTIM_GetADCTrigSrc\n 02282 * ADC1R ADC1TDC4 LL_HRTIM_GetADCTrigSrc\n 02283 * ADC1R ADC1TDPER LL_HRTIM_GetADCTrigSrc\n 02284 * ADC1R ADC1TEC2 LL_HRTIM_GetADCTrigSrc\n 02285 * ADC1R ADC1TEC3 LL_HRTIM_GetADCTrigSrc\n 02286 * ADC1R ADC1TEC4 LL_HRTIM_GetADCTrigSrc\n 02287 * ADC1R ADC1TEPER LL_HRTIM_GetADCTrigSrc\n 02288 * ADC2R ADC2MC1 LL_HRTIM_GetADCTrigSrc\n 02289 * ADC2R ADC2MC2 LL_HRTIM_GetADCTrigSrc\n 02290 * ADC2R ADC2MC3 LL_HRTIM_GetADCTrigSrc\n 02291 * ADC2R ADC2MC4 LL_HRTIM_GetADCTrigSrc\n 02292 * ADC2R ADC2MPER LL_HRTIM_GetADCTrigSrc\n 02293 * ADC2R ADC2EEV6 LL_HRTIM_GetADCTrigSrc\n 02294 * ADC2R ADC2EEV7 LL_HRTIM_GetADCTrigSrc\n 02295 * ADC2R ADC2EEV8 LL_HRTIM_GetADCTrigSrc\n 02296 * ADC2R ADC2EEV9 LL_HRTIM_GetADCTrigSrc\n 02297 * ADC2R ADC2EEV10 LL_HRTIM_GetADCTrigSrc\n 02298 * ADC2R ADC2TAC2 LL_HRTIM_GetADCTrigSrc\n 02299 * ADC2R ADC2TAC3 LL_HRTIM_GetADCTrigSrc\n 02300 * ADC2R ADC2TAC4 LL_HRTIM_GetADCTrigSrc\n 02301 * ADC2R ADC2TAPER LL_HRTIM_GetADCTrigSrc\n 02302 * ADC2R ADC2TBC2 LL_HRTIM_GetADCTrigSrc\n 02303 * ADC2R ADC2TBC3 LL_HRTIM_GetADCTrigSrc\n 02304 * ADC2R ADC2TBC4 LL_HRTIM_GetADCTrigSrc\n 02305 * ADC2R ADC2TBPER LL_HRTIM_GetADCTrigSrc\n 02306 * ADC2R ADC2TCC2 LL_HRTIM_GetADCTrigSrc\n 02307 * ADC2R ADC2TCC3 LL_HRTIM_GetADCTrigSrc\n 02308 * ADC2R ADC2TCC4 LL_HRTIM_GetADCTrigSrc\n 02309 * ADC2R ADC2TCPER LL_HRTIM_GetADCTrigSrc\n 02310 * ADC2R ADC2TCRST LL_HRTIM_GetADCTrigSrc\n 02311 * ADC2R ADC2TDC2 LL_HRTIM_GetADCTrigSrc\n 02312 * ADC2R ADC2TDC3 LL_HRTIM_GetADCTrigSrc\n 02313 * ADC2R ADC2TDC4 LL_HRTIM_GetADCTrigSrc\n 02314 * ADC2R ADC2TDPER LL_HRTIM_GetADCTrigSrc\n 02315 * ADC2R ADC2TDRST LL_HRTIM_GetADCTrigSrc\n 02316 * ADC2R ADC2TEC2 LL_HRTIM_GetADCTrigSrc\n 02317 * ADC2R ADC2TEC3 LL_HRTIM_GetADCTrigSrc\n 02318 * ADC2R ADC2TEC4 LL_HRTIM_GetADCTrigSrc\n 02319 * ADC2R ADC2TERST LL_HRTIM_GetADCTrigSrc\n 02320 * ADC3R ADC3MC1 LL_HRTIM_GetADCTrigSrc\n 02321 * ADC3R ADC3MC2 LL_HRTIM_GetADCTrigSrc\n 02322 * ADC3R ADC3MC3 LL_HRTIM_GetADCTrigSrc\n 02323 * ADC3R ADC3MC4 LL_HRTIM_GetADCTrigSrc\n 02324 * ADC3R ADC3MPER LL_HRTIM_GetADCTrigSrc\n 02325 * ADC3R ADC3EEV1 LL_HRTIM_GetADCTrigSrc\n 02326 * ADC3R ADC3EEV2 LL_HRTIM_GetADCTrigSrc\n 02327 * ADC3R ADC3EEV3 LL_HRTIM_GetADCTrigSrc\n 02328 * ADC3R ADC3EEV4 LL_HRTIM_GetADCTrigSrc\n 02329 * ADC3R ADC3EEV5 LL_HRTIM_GetADCTrigSrc\n 02330 * ADC3R ADC3TAC2 LL_HRTIM_GetADCTrigSrc\n 02331 * ADC3R ADC3TAC3 LL_HRTIM_GetADCTrigSrc\n 02332 * ADC3R ADC3TAC4 LL_HRTIM_GetADCTrigSrc\n 02333 * ADC3R ADC3TAPER LL_HRTIM_GetADCTrigSrc\n 02334 * ADC3R ADC3TARST LL_HRTIM_GetADCTrigSrc\n 02335 * ADC3R ADC3TBC2 LL_HRTIM_GetADCTrigSrc\n 02336 * ADC3R ADC3TBC3 LL_HRTIM_GetADCTrigSrc\n 02337 * ADC3R ADC3TBC4 LL_HRTIM_GetADCTrigSrc\n 02338 * ADC3R ADC3TBPER LL_HRTIM_GetADCTrigSrc\n 02339 * ADC3R ADC3TBRST LL_HRTIM_GetADCTrigSrc\n 02340 * ADC3R ADC3TCC2 LL_HRTIM_GetADCTrigSrc\n 02341 * ADC3R ADC3TCC3 LL_HRTIM_GetADCTrigSrc\n 02342 * ADC3R ADC3TCC4 LL_HRTIM_GetADCTrigSrc\n 02343 * ADC3R ADC3TCPER LL_HRTIM_GetADCTrigSrc\n 02344 * ADC3R ADC3TDC2 LL_HRTIM_GetADCTrigSrc\n 02345 * ADC3R ADC3TDC3 LL_HRTIM_GetADCTrigSrc\n 02346 * ADC3R ADC3TDC4 LL_HRTIM_GetADCTrigSrc\n 02347 * ADC3R ADC3TDPER LL_HRTIM_GetADCTrigSrc\n 02348 * ADC3R ADC3TEC2 LL_HRTIM_GetADCTrigSrc\n 02349 * ADC3R ADC3TEC3 LL_HRTIM_GetADCTrigSrc\n 02350 * ADC3R ADC3TEC4 LL_HRTIM_GetADCTrigSrc\n 02351 * ADC3R ADC3TEPER LL_HRTIM_GetADCTrigSrc\n 02352 * ADC4R ADC4MC1 LL_HRTIM_GetADCTrigSrc\n 02353 * ADC4R ADC4MC2 LL_HRTIM_GetADCTrigSrc\n 02354 * ADC4R ADC4MC3 LL_HRTIM_GetADCTrigSrc\n 02355 * ADC4R ADC4MC4 LL_HRTIM_GetADCTrigSrc\n 02356 * ADC4R ADC4MPER LL_HRTIM_GetADCTrigSrc\n 02357 * ADC4R ADC4EEV6 LL_HRTIM_GetADCTrigSrc\n 02358 * ADC4R ADC4EEV7 LL_HRTIM_GetADCTrigSrc\n 02359 * ADC4R ADC4EEV8 LL_HRTIM_GetADCTrigSrc\n 02360 * ADC4R ADC4EEV9 LL_HRTIM_GetADCTrigSrc\n 02361 * ADC4R ADC4EEV10 LL_HRTIM_GetADCTrigSrc\n 02362 * ADC4R ADC4TAC2 LL_HRTIM_GetADCTrigSrc\n 02363 * ADC4R ADC4TAC3 LL_HRTIM_GetADCTrigSrc\n 02364 * ADC4R ADC4TAC4 LL_HRTIM_GetADCTrigSrc\n 02365 * ADC4R ADC4TAPER LL_HRTIM_GetADCTrigSrc\n 02366 * ADC4R ADC4TBC2 LL_HRTIM_GetADCTrigSrc\n 02367 * ADC4R ADC4TBC3 LL_HRTIM_GetADCTrigSrc\n 02368 * ADC4R ADC4TBC4 LL_HRTIM_GetADCTrigSrc\n 02369 * ADC4R ADC4TBPER LL_HRTIM_GetADCTrigSrc\n 02370 * ADC4R ADC4TCC2 LL_HRTIM_GetADCTrigSrc\n 02371 * ADC4R ADC4TCC3 LL_HRTIM_GetADCTrigSrc\n 02372 * ADC4R ADC4TCC4 LL_HRTIM_GetADCTrigSrc\n 02373 * ADC4R ADC4TCPER LL_HRTIM_GetADCTrigSrc\n 02374 * ADC4R ADC4TCRST LL_HRTIM_GetADCTrigSrc\n 02375 * ADC4R ADC4TDC2 LL_HRTIM_GetADCTrigSrc\n 02376 * ADC4R ADC4TDC3 LL_HRTIM_GetADCTrigSrc\n 02377 * ADC4R ADC4TDC4 LL_HRTIM_GetADCTrigSrc\n 02378 * ADC4R ADC4TDPER LL_HRTIM_GetADCTrigSrc\n 02379 * ADC4R ADC4TDRST LL_HRTIM_GetADCTrigSrc\n 02380 * ADC4R ADC4TEC2 LL_HRTIM_GetADCTrigSrc\n 02381 * ADC4R ADC4TEC3 LL_HRTIM_GetADCTrigSrc\n 02382 * ADC4R ADC4TEC4 LL_HRTIM_GetADCTrigSrc\n 02383 * ADC4R ADC4TERST LL_HRTIM_GetADCTrigSrc 02384 * @param HRTIMx High Resolution Timer instance 02385 * @param ADCTrig This parameter can be one of the following values: 02386 * @arg @ref LL_HRTIM_ADCTRIG_1 02387 * @arg @ref LL_HRTIM_ADCTRIG_2 02388 * @arg @ref LL_HRTIM_ADCTRIG_3 02389 * @arg @ref LL_HRTIM_ADCTRIG_4 02390 * @retval Src This parameter can be a combination of the following values: 02391 * 02392 * For ADC trigger 1 and ADC trigger 3 this parameter can be a 02393 * combination of the following values: 02394 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE 02395 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1 02396 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2 02397 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3 02398 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4 02399 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER 02400 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1 02401 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2 02402 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3 02403 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4 02404 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5 02405 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2 02406 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3 02407 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4 02408 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER 02409 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST 02410 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2 02411 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3 02412 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4 02413 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER 02414 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST 02415 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2 02416 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3 02417 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4 02418 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER 02419 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2 02420 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3 02421 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4 02422 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER 02423 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2 02424 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3 02425 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4 02426 * @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER 02427 * 02428 * For ADC trigger 2 and ADC trigger 4 this parameter can be a 02429 * combination of the following values: 02430 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE 02431 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1 02432 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2 02433 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3 02434 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4 02435 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER 02436 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6 02437 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7 02438 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8 02439 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9 02440 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10 02441 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2 02442 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3 02443 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4 02444 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER 02445 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2 02446 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3 02447 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4 02448 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER 02449 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2 02450 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3 02451 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4 02452 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER 02453 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST 02454 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2 02455 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3 02456 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4 02457 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER 02458 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST 02459 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2 02460 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3 02461 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4 02462 * @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST 02463 */ 02464 __STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig) 02465 { 02466 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) + 02467 REG_OFFSET_TAB_ADCxR[ADCTrig])); 02468 return (*pReg); 02469 02470 } 02471 02472 02473 /** 02474 * @} 02475 */ 02476 02477 /** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control 02478 * @{ 02479 */ 02480 02481 /** 02482 * @brief Enable timer(s) counter. 02483 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterEnable\n 02484 * MDIER TDCEN LL_HRTIM_TIM_CounterEnable\n 02485 * MDIER TCCEN LL_HRTIM_TIM_CounterEnable\n 02486 * MDIER TBCEN LL_HRTIM_TIM_CounterEnable\n 02487 * MDIER TACEN LL_HRTIM_TIM_CounterEnable\n 02488 * MDIER MCEN LL_HRTIM_TIM_CounterEnable 02489 * @param HRTIMx High Resolution Timer instance 02490 * @param Timers This parameter can be a combination of the following values: 02491 * @arg @ref LL_HRTIM_TIMER_MASTER 02492 * @arg @ref LL_HRTIM_TIMER_A 02493 * @arg @ref LL_HRTIM_TIMER_B 02494 * @arg @ref LL_HRTIM_TIMER_C 02495 * @arg @ref LL_HRTIM_TIMER_D 02496 * @arg @ref LL_HRTIM_TIMER_E 02497 * @retval None 02498 */ 02499 __STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 02500 { 02501 SET_BIT(HRTIMx->sMasterRegs.MCR, Timers); 02502 } 02503 02504 /** 02505 * @brief Disable timer(s) counter. 02506 * @rmtoll MDIER TECEN LL_HRTIM_TIM_CounterDisable\n 02507 * MDIER TDCEN LL_HRTIM_TIM_CounterDisable\n 02508 * MDIER TCCEN LL_HRTIM_TIM_CounterDisable\n 02509 * MDIER TBCEN LL_HRTIM_TIM_CounterDisable\n 02510 * MDIER TACEN LL_HRTIM_TIM_CounterDisable\n 02511 * MDIER MCEN LL_HRTIM_TIM_CounterDisable 02512 * @param HRTIMx High Resolution Timer instance 02513 * @param Timers This parameter can be a combination of the following values: 02514 * @arg @ref LL_HRTIM_TIMER_MASTER 02515 * @arg @ref LL_HRTIM_TIMER_A 02516 * @arg @ref LL_HRTIM_TIMER_B 02517 * @arg @ref LL_HRTIM_TIMER_C 02518 * @arg @ref LL_HRTIM_TIMER_D 02519 * @arg @ref LL_HRTIM_TIMER_E 02520 * @retval None 02521 */ 02522 __STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers) 02523 { 02524 CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers); 02525 } 02526 02527 /** 02528 * @brief Indicate whether the timer counter is enabled. 02529 * @rmtoll MDIER TECEN LL_HRTIM_TIM_IsCounterEnabled\n 02530 * MDIER TDCEN LL_HRTIM_TIM_IsCounterEnabled\n 02531 * MDIER TCCEN LL_HRTIM_TIM_IsCounterEnabled\n 02532 * MDIER TBCEN LL_HRTIM_TIM_IsCounterEnabled\n 02533 * MDIER TACEN LL_HRTIM_TIM_IsCounterEnabled\n 02534 * MDIER MCEN LL_HRTIM_TIM_IsCounterEnabled 02535 * @param HRTIMx High Resolution Timer instance 02536 * @param Timer This parameter can be one of the following values: 02537 * @arg @ref LL_HRTIM_TIMER_MASTER 02538 * @arg @ref LL_HRTIM_TIMER_A 02539 * @arg @ref LL_HRTIM_TIMER_B 02540 * @arg @ref LL_HRTIM_TIMER_C 02541 * @arg @ref LL_HRTIM_TIMER_D 02542 * @arg @ref LL_HRTIM_TIMER_E 02543 * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0). 02544 */ 02545 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02546 { 02547 return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL); 02548 } 02549 02550 /** 02551 * @brief Set the timer clock prescaler ratio. 02552 * @rmtoll MCR CKPSC LL_HRTIM_TIM_SetPrescaler\n 02553 * TIMxCR CKPSC LL_HRTIM_TIM_SetPrescaler 02554 * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0]. 02555 * @note The prescaling ratio cannot be modified once the timer counter is enabled. 02556 * @param HRTIMx High Resolution Timer instance 02557 * @param Timer This parameter can be one of the following values: 02558 * @arg @ref LL_HRTIM_TIMER_MASTER 02559 * @arg @ref LL_HRTIM_TIMER_A 02560 * @arg @ref LL_HRTIM_TIMER_B 02561 * @arg @ref LL_HRTIM_TIMER_C 02562 * @arg @ref LL_HRTIM_TIMER_D 02563 * @arg @ref LL_HRTIM_TIMER_E 02564 * @param Prescaler This parameter can be one of the following values: 02565 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1 02566 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2 02567 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 02568 * @retval None 02569 */ 02570 __STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) 02571 { 02572 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02573 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02574 MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler); 02575 } 02576 02577 /** 02578 * @brief Get the timer clock prescaler ratio 02579 * @rmtoll MCR CKPSC LL_HRTIM_TIM_GetPrescaler\n 02580 * TIMxCR CKPSC LL_HRTIM_TIM_GetPrescaler 02581 * @param HRTIMx High Resolution Timer instance 02582 * @param Timer This parameter can be one of the following values: 02583 * @arg @ref LL_HRTIM_TIMER_MASTER 02584 * @arg @ref LL_HRTIM_TIMER_A 02585 * @arg @ref LL_HRTIM_TIMER_B 02586 * @arg @ref LL_HRTIM_TIMER_C 02587 * @arg @ref LL_HRTIM_TIMER_D 02588 * @arg @ref LL_HRTIM_TIMER_E 02589 * @retval Prescaler Returned value can be one of the following values: 02590 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1 02591 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2 02592 * @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4 02593 */ 02594 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02595 { 02596 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02597 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02598 return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC)); 02599 } 02600 02601 /** 02602 * @brief Set the counter operating mode mode (single-shot, continuous or re-triggerable). 02603 * @rmtoll MCR CONT LL_HRTIM_TIM_SetCounterMode\n 02604 * MCR RETRIG LL_HRTIM_TIM_SetCounterMode\n 02605 * TIMxCR CONT LL_HRTIM_TIM_SetCounterMode\n 02606 * TIMxCR RETRIG LL_HRTIM_TIM_SetCounterMode 02607 * @param HRTIMx High Resolution Timer instance 02608 * @param Timer This parameter can be one of the following values: 02609 * @arg @ref LL_HRTIM_TIMER_MASTER 02610 * @arg @ref LL_HRTIM_TIMER_A 02611 * @arg @ref LL_HRTIM_TIMER_B 02612 * @arg @ref LL_HRTIM_TIMER_C 02613 * @arg @ref LL_HRTIM_TIMER_D 02614 * @arg @ref LL_HRTIM_TIMER_E 02615 * @param Mode This parameter can be one of the following values: 02616 * @arg @ref LL_HRTIM_MODE_CONTINUOUS 02617 * @arg @ref LL_HRTIM_MODE_SINGLESHOT 02618 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE 02619 * @retval None 02620 */ 02621 __STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode) 02622 { 02623 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02624 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02625 MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode); 02626 } 02627 02628 /** 02629 * @brief Get the counter operating mode mode 02630 * @rmtoll MCR CONT LL_HRTIM_TIM_GetCounterMode\n 02631 * MCR RETRIG LL_HRTIM_TIM_GetCounterMode\n 02632 * TIMxCR CONT LL_HRTIM_TIM_GetCounterMode\n 02633 * TIMxCR RETRIG LL_HRTIM_TIM_GetCounterMode 02634 * @param HRTIMx High Resolution Timer instance 02635 * @param Timer This parameter can be one of the following values: 02636 * @arg @ref LL_HRTIM_TIMER_MASTER 02637 * @arg @ref LL_HRTIM_TIMER_A 02638 * @arg @ref LL_HRTIM_TIMER_B 02639 * @arg @ref LL_HRTIM_TIMER_C 02640 * @arg @ref LL_HRTIM_TIMER_D 02641 * @arg @ref LL_HRTIM_TIMER_E 02642 * @retval Mode Returned value can be one of the following values: 02643 * @arg @ref LL_HRTIM_MODE_CONTINUOUS 02644 * @arg @ref LL_HRTIM_MODE_SINGLESHOT 02645 * @arg @ref LL_HRTIM_MODE_RETRIGGERABLE 02646 */ 02647 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02648 { 02649 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02650 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02651 return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT))); 02652 } 02653 02654 /** 02655 * @brief Enable the half duty-cycle mode. 02656 * @rmtoll MCR HALF LL_HRTIM_TIM_EnableHalfMode\n 02657 * TIMxCR HALF LL_HRTIM_TIM_EnableHalfMode 02658 * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR) 02659 * active register is automatically updated with HRTIM_MPER/2 02660 * (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written. 02661 * @param HRTIMx High Resolution Timer instance 02662 * @param Timer This parameter can be one of the following values: 02663 * @arg @ref LL_HRTIM_TIMER_MASTER 02664 * @arg @ref LL_HRTIM_TIMER_A 02665 * @arg @ref LL_HRTIM_TIMER_B 02666 * @arg @ref LL_HRTIM_TIMER_C 02667 * @arg @ref LL_HRTIM_TIMER_D 02668 * @arg @ref LL_HRTIM_TIMER_E 02669 * @retval None 02670 */ 02671 __STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02672 { 02673 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02674 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02675 SET_BIT(*pReg, HRTIM_MCR_HALF); 02676 } 02677 02678 /** 02679 * @brief Disable the half duty-cycle mode. 02680 * @rmtoll MCR HALF LL_HRTIM_TIM_DisableHalfMode\n 02681 * TIMxCR HALF LL_HRTIM_TIM_DisableHalfMode 02682 * @param HRTIMx High Resolution Timer instance 02683 * @param Timer This parameter can be one of the following values: 02684 * @arg @ref LL_HRTIM_TIMER_MASTER 02685 * @arg @ref LL_HRTIM_TIMER_A 02686 * @arg @ref LL_HRTIM_TIMER_B 02687 * @arg @ref LL_HRTIM_TIMER_C 02688 * @arg @ref LL_HRTIM_TIMER_D 02689 * @arg @ref LL_HRTIM_TIMER_E 02690 * @retval None 02691 */ 02692 __STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02693 { 02694 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02695 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02696 CLEAR_BIT(*pReg, HRTIM_MCR_HALF); 02697 } 02698 02699 /** 02700 * @brief Indicate whether half duty-cycle mode is enabled for a given timer. 02701 * @rmtoll MCR HALF LL_HRTIM_TIM_IsEnabledHalfMode\n 02702 * TIMxCR HALF LL_HRTIM_TIM_IsEnabledHalfMode 02703 * @param HRTIMx High Resolution Timer instance 02704 * @param Timer This parameter can be one of the following values: 02705 * @arg @ref LL_HRTIM_TIMER_MASTER 02706 * @arg @ref LL_HRTIM_TIMER_A 02707 * @arg @ref LL_HRTIM_TIMER_B 02708 * @arg @ref LL_HRTIM_TIMER_C 02709 * @arg @ref LL_HRTIM_TIMER_D 02710 * @arg @ref LL_HRTIM_TIMER_E 02711 * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). 02712 */ 02713 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02714 { 02715 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02716 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02717 02718 return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL); 02719 } 02720 /** 02721 * @brief Enable the timer start when receiving a synchronization input event. 02722 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_EnableStartOnSync\n 02723 * TIMxCR SYNSTRTA LL_HRTIM_TIM_EnableStartOnSync 02724 * @param HRTIMx High Resolution Timer instance 02725 * @param Timer This parameter can be one of the following values: 02726 * @arg @ref LL_HRTIM_TIMER_MASTER 02727 * @arg @ref LL_HRTIM_TIMER_A 02728 * @arg @ref LL_HRTIM_TIMER_B 02729 * @arg @ref LL_HRTIM_TIMER_C 02730 * @arg @ref LL_HRTIM_TIMER_D 02731 * @arg @ref LL_HRTIM_TIMER_E 02732 * @retval None 02733 */ 02734 __STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02735 { 02736 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02737 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02738 SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); 02739 } 02740 02741 /** 02742 * @brief Disable the timer start when receiving a synchronization input event. 02743 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_DisableStartOnSync\n 02744 * TIMxCR SYNSTRTA LL_HRTIM_TIM_DisableStartOnSync 02745 * @param HRTIMx High Resolution Timer instance 02746 * @param Timer This parameter can be one of the following values: 02747 * @arg @ref LL_HRTIM_TIMER_MASTER 02748 * @arg @ref LL_HRTIM_TIMER_A 02749 * @arg @ref LL_HRTIM_TIMER_B 02750 * @arg @ref LL_HRTIM_TIMER_C 02751 * @arg @ref LL_HRTIM_TIMER_D 02752 * @arg @ref LL_HRTIM_TIMER_E 02753 * @retval None 02754 */ 02755 __STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02756 { 02757 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02758 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02759 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM); 02760 } 02761 02762 /** 02763 * @brief Indicate whether the timer start when receiving a synchronization input event. 02764 * @rmtoll MCR SYNCSTRTM LL_HRTIM_TIM_IsEnabledStartOnSync\n 02765 * TIMxCR SYNSTRTA LL_HRTIM_TIM_IsEnabledStartOnSync 02766 * @param HRTIMx High Resolution Timer instance 02767 * @param Timer This parameter can be one of the following values: 02768 * @arg @ref LL_HRTIM_TIMER_MASTER 02769 * @arg @ref LL_HRTIM_TIMER_A 02770 * @arg @ref LL_HRTIM_TIMER_B 02771 * @arg @ref LL_HRTIM_TIMER_C 02772 * @arg @ref LL_HRTIM_TIMER_D 02773 * @arg @ref LL_HRTIM_TIMER_E 02774 * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). 02775 */ 02776 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02777 { 02778 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02779 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02780 02781 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL); 02782 } 02783 02784 /** 02785 * @brief Enable the timer reset when receiving a synchronization input event. 02786 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_EnableResetOnSync\n 02787 * TIMxCR SYNCRSTA LL_HRTIM_TIM_EnableResetOnSync 02788 * @param HRTIMx High Resolution Timer instance 02789 * @param Timer This parameter can be one of the following values: 02790 * @arg @ref LL_HRTIM_TIMER_MASTER 02791 * @arg @ref LL_HRTIM_TIMER_A 02792 * @arg @ref LL_HRTIM_TIMER_B 02793 * @arg @ref LL_HRTIM_TIMER_C 02794 * @arg @ref LL_HRTIM_TIMER_D 02795 * @arg @ref LL_HRTIM_TIMER_E 02796 * @retval None 02797 */ 02798 __STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02799 { 02800 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02801 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02802 SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM); 02803 } 02804 02805 /** 02806 * @brief Disable the timer reset when receiving a synchronization input event. 02807 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_DisableResetOnSync\n 02808 * TIMxCR SYNCRSTA LL_HRTIM_TIM_DisableResetOnSync 02809 * @param HRTIMx High Resolution Timer instance 02810 * @param Timer This parameter can be one of the following values: 02811 * @arg @ref LL_HRTIM_TIMER_MASTER 02812 * @arg @ref LL_HRTIM_TIMER_A 02813 * @arg @ref LL_HRTIM_TIMER_B 02814 * @arg @ref LL_HRTIM_TIMER_C 02815 * @arg @ref LL_HRTIM_TIMER_D 02816 * @arg @ref LL_HRTIM_TIMER_E 02817 * @retval None 02818 */ 02819 __STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02820 { 02821 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02822 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02823 CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM); 02824 } 02825 02826 /** 02827 * @brief Indicate whether the timer reset when receiving a synchronization input event. 02828 * @rmtoll MCR SYNCRSTM LL_HRTIM_TIM_IsEnabledResetOnSync\n 02829 * TIMxCR SYNCRSTA LL_HRTIM_TIM_IsEnabledResetOnSync 02830 * @param HRTIMx High Resolution Timer instance 02831 * @param Timer This parameter can be one of the following values: 02832 * @arg @ref LL_HRTIM_TIMER_MASTER 02833 * @arg @ref LL_HRTIM_TIMER_A 02834 * @arg @ref LL_HRTIM_TIMER_B 02835 * @arg @ref LL_HRTIM_TIMER_C 02836 * @arg @ref LL_HRTIM_TIMER_D 02837 * @arg @ref LL_HRTIM_TIMER_E 02838 * @retval None 02839 */ 02840 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02841 { 02842 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02843 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02844 02845 return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL); 02846 } 02847 02848 /** 02849 * @brief Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx). 02850 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_SetDACTrig\n 02851 * TIMxCR DACSYNC LL_HRTIM_TIM_SetDACTrig 02852 * @param HRTIMx High Resolution Timer instance 02853 * @param Timer This parameter can be one of the following values: 02854 * @arg @ref LL_HRTIM_TIMER_MASTER 02855 * @arg @ref LL_HRTIM_TIMER_A 02856 * @arg @ref LL_HRTIM_TIMER_B 02857 * @arg @ref LL_HRTIM_TIMER_C 02858 * @arg @ref LL_HRTIM_TIMER_D 02859 * @arg @ref LL_HRTIM_TIMER_E 02860 * @param DACTrig This parameter can be one of the following values: 02861 * @arg @ref LL_HRTIM_DACTRIG_NONE 02862 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1 02863 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2 02864 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3 02865 * @retval None 02866 */ 02867 __STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig) 02868 { 02869 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02870 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02871 MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig); 02872 } 02873 02874 /** 02875 * @brief Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx). 02876 * @rmtoll MCR DACSYNC LL_HRTIM_TIM_GetDACTrig\n 02877 * TIMxCR DACSYNC LL_HRTIM_TIM_GetDACTrig 02878 * @param HRTIMx High Resolution Timer instance 02879 * @param Timer This parameter can be one of the following values: 02880 * @arg @ref LL_HRTIM_TIMER_MASTER 02881 * @arg @ref LL_HRTIM_TIMER_A 02882 * @arg @ref LL_HRTIM_TIMER_B 02883 * @arg @ref LL_HRTIM_TIMER_C 02884 * @arg @ref LL_HRTIM_TIMER_D 02885 * @arg @ref LL_HRTIM_TIMER_E 02886 * @retval DACTrig Returned value can be one of the following values: 02887 * @arg @ref LL_HRTIM_DACTRIG_NONE 02888 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1 02889 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2 02890 * @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3 02891 */ 02892 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02893 { 02894 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02895 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02896 return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC)); 02897 } 02898 02899 /** 02900 * @brief Enable the timer registers preload mechanism. 02901 * @rmtoll MCR PREEN LL_HRTIM_TIM_EnablePreload\n 02902 * TIMxCR PREEN LL_HRTIM_TIM_EnablePreload 02903 * @note When the preload mode is enabled, accessed registers are shadow registers. 02904 * Their content is transferred into the active register after an update request, 02905 * either software or synchronized with an event. 02906 * @param HRTIMx High Resolution Timer instance 02907 * @param Timer This parameter can be one of the following values: 02908 * @arg @ref LL_HRTIM_TIMER_MASTER 02909 * @arg @ref LL_HRTIM_TIMER_A 02910 * @arg @ref LL_HRTIM_TIMER_B 02911 * @arg @ref LL_HRTIM_TIMER_C 02912 * @arg @ref LL_HRTIM_TIMER_D 02913 * @arg @ref LL_HRTIM_TIMER_E 02914 * @retval None 02915 */ 02916 __STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02917 { 02918 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02919 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02920 SET_BIT(*pReg, HRTIM_MCR_PREEN); 02921 } 02922 02923 /** 02924 * @brief Disable the timer registers preload mechanism. 02925 * @rmtoll MCR PREEN LL_HRTIM_TIM_DisablePreload\n 02926 * TIMxCR PREEN LL_HRTIM_TIM_DisablePreload 02927 * @param HRTIMx High Resolution Timer instance 02928 * @param Timer This parameter can be one of the following values: 02929 * @arg @ref LL_HRTIM_TIMER_MASTER 02930 * @arg @ref LL_HRTIM_TIMER_A 02931 * @arg @ref LL_HRTIM_TIMER_B 02932 * @arg @ref LL_HRTIM_TIMER_C 02933 * @arg @ref LL_HRTIM_TIMER_D 02934 * @arg @ref LL_HRTIM_TIMER_E 02935 * @retval None 02936 */ 02937 __STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02938 { 02939 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02940 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02941 CLEAR_BIT(*pReg, HRTIM_MCR_PREEN); 02942 } 02943 02944 /** 02945 * @brief Indicate whether the timer registers preload mechanism is enabled. 02946 * @rmtoll MCR PREEN LL_HRTIM_TIM_IsEnabledPreload\n 02947 * TIMxCR PREEN LL_HRTIM_TIM_IsEnabledPreload 02948 * @param HRTIMx High Resolution Timer instance 02949 * @param Timer This parameter can be one of the following values: 02950 * @arg @ref LL_HRTIM_TIMER_MASTER 02951 * @arg @ref LL_HRTIM_TIMER_A 02952 * @arg @ref LL_HRTIM_TIMER_B 02953 * @arg @ref LL_HRTIM_TIMER_C 02954 * @arg @ref LL_HRTIM_TIMER_D 02955 * @arg @ref LL_HRTIM_TIMER_E 02956 * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0). 02957 */ 02958 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 02959 { 02960 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 02961 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 02962 02963 return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL); 02964 } 02965 02966 /** 02967 * @brief Set the timer register update trigger. 02968 * @rmtoll MCR MREPU LL_HRTIM_TIM_SetUpdateTrig\n 02969 * TIMxCR TAU LL_HRTIM_TIM_SetUpdateTrig\n 02970 * TIMxCR TBU LL_HRTIM_TIM_SetUpdateTrig\n 02971 * TIMxCR TCU LL_HRTIM_TIM_SetUpdateTrig\n 02972 * TIMxCR TDU LL_HRTIM_TIM_SetUpdateTrig\n 02973 * TIMxCR TEU LL_HRTIM_TIM_SetUpdateTrig\n 02974 * TIMxCR MSTU LL_HRTIM_TIM_SetUpdateTrig 02975 * @param HRTIMx High Resolution Timer instance 02976 * @param Timer This parameter can be one of the following values: 02977 * @arg @ref LL_HRTIM_TIMER_MASTER 02978 * @arg @ref LL_HRTIM_TIMER_A 02979 * @arg @ref LL_HRTIM_TIMER_B 02980 * @arg @ref LL_HRTIM_TIMER_C 02981 * @arg @ref LL_HRTIM_TIMER_D 02982 * @arg @ref LL_HRTIM_TIMER_E 02983 * @param UpdateTrig This parameter can be one of the following values: 02984 * 02985 * For the master timer this parameter can be one of the following values: 02986 * @arg @ref LL_HRTIM_UPDATETRIG_NONE 02987 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION 02988 * 02989 * For timer A..E this parameter can be: 02990 * @arg @ref LL_HRTIM_UPDATETRIG_NONE 02991 * or a combination of the following values: 02992 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER 02993 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A 02994 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B 02995 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C 02996 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D 02997 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E 02998 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION 02999 * @arg @ref LL_HRTIM_UPDATETRIG_RESET 03000 * @retval None 03001 */ 03002 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig) 03003 { 03004 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03005 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 03006 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]); 03007 } 03008 03009 /** 03010 * @brief Get the timer register update trigger. 03011 * @rmtoll MCR MREPU LL_HRTIM_TIM_GetUpdateTrig\n 03012 * TIMxCR TBU LL_HRTIM_TIM_GetUpdateTrig\n 03013 * TIMxCR TCU LL_HRTIM_TIM_GetUpdateTrig\n 03014 * TIMxCR TDU LL_HRTIM_TIM_GetUpdateTrig\n 03015 * TIMxCR TEU LL_HRTIM_TIM_GetUpdateTrig\n 03016 * TIMxCR MSTU LL_HRTIM_TIM_GetUpdateTrig 03017 * @param HRTIMx High Resolution Timer instance 03018 * @param Timer This parameter can be one of the following values: 03019 * @arg @ref LL_HRTIM_TIMER_MASTER 03020 * @arg @ref LL_HRTIM_TIMER_A 03021 * @arg @ref LL_HRTIM_TIMER_B 03022 * @arg @ref LL_HRTIM_TIMER_C 03023 * @arg @ref LL_HRTIM_TIMER_D 03024 * @arg @ref LL_HRTIM_TIMER_E 03025 * @retval UpdateTrig Returned value can be one of the following values: 03026 * 03027 * For the master timer this parameter can be one of the following values: 03028 * @arg @ref LL_HRTIM_UPDATETRIG_NONE 03029 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION 03030 * 03031 * For timer A..E this parameter can be: 03032 * @arg @ref LL_HRTIM_UPDATETRIG_NONE 03033 * or a combination of the following values: 03034 * @arg @ref LL_HRTIM_UPDATETRIG_MASTER 03035 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A 03036 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B 03037 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C 03038 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D 03039 * @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E 03040 * @arg @ref LL_HRTIM_UPDATETRIG_REPETITION 03041 * @arg @ref LL_HRTIM_UPDATETRIG_RESET 03042 */ 03043 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03044 { 03045 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03046 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 03047 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >> REG_SHIFT_TAB_UPDATETRIG[iTimer]); 03048 } 03049 03050 /** 03051 * @brief Set the timer registers update condition (how the registers update occurs relatively to the burst DMA transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])). 03052 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_SetUpdateGating\n 03053 * TIMxCR UPDGAT LL_HRTIM_TIM_SetUpdateGating 03054 * @param HRTIMx High Resolution Timer instance 03055 * @param Timer This parameter can be one of the following values: 03056 * @arg @ref LL_HRTIM_TIMER_MASTER 03057 * @arg @ref LL_HRTIM_TIMER_A 03058 * @arg @ref LL_HRTIM_TIMER_B 03059 * @arg @ref LL_HRTIM_TIMER_C 03060 * @arg @ref LL_HRTIM_TIMER_D 03061 * @arg @ref LL_HRTIM_TIMER_E 03062 * @param UpdateGating This parameter can be one of the following values: 03063 * 03064 * For the master timer this parameter can be one of the following values: 03065 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT 03066 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST 03067 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE 03068 * 03069 * For the timer A..E this parameter can be one of the following values: 03070 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT 03071 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST 03072 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE 03073 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1 03074 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2 03075 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3 03076 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE 03077 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE 03078 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE 03079 * @retval None 03080 */ 03081 __STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating) 03082 { 03083 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03084 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 03085 MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer])); 03086 } 03087 03088 /** 03089 * @brief Get the timer registers update condition. 03090 * @rmtoll MCR BRSTDMA LL_HRTIM_TIM_GetUpdateGating\n 03091 * TIMxCR UPDGAT LL_HRTIM_TIM_GetUpdateGating 03092 * @param HRTIMx High Resolution Timer instance 03093 * @param Timer This parameter can be one of the following values: 03094 * @arg @ref LL_HRTIM_TIMER_MASTER 03095 * @arg @ref LL_HRTIM_TIMER_A 03096 * @arg @ref LL_HRTIM_TIMER_B 03097 * @arg @ref LL_HRTIM_TIMER_C 03098 * @arg @ref LL_HRTIM_TIMER_D 03099 * @arg @ref LL_HRTIM_TIMER_E 03100 * @retval UpdateGating Returned value can be one of the following values: 03101 * 03102 * For the master timer this parameter can be one of the following values: 03103 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT 03104 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST 03105 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE 03106 * 03107 * For the timer A..E this parameter can be one of the following values: 03108 * @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT 03109 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST 03110 * @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE 03111 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1 03112 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2 03113 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3 03114 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE 03115 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE 03116 * @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE 03117 */ 03118 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03119 { 03120 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03121 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer])); 03122 return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >> REG_SHIFT_TAB_UPDATEGATING[iTimer]); 03123 } 03124 03125 /** 03126 * @brief Enable the push-pull mode. 03127 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_EnablePushPullMode 03128 * @param HRTIMx High Resolution Timer instance 03129 * @param Timer This parameter can be one of the following values: 03130 * @arg @ref LL_HRTIM_TIMER_A 03131 * @arg @ref LL_HRTIM_TIMER_B 03132 * @arg @ref LL_HRTIM_TIMER_C 03133 * @arg @ref LL_HRTIM_TIMER_D 03134 * @arg @ref LL_HRTIM_TIMER_E 03135 * @retval None 03136 */ 03137 __STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03138 { 03139 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03140 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 03141 REG_OFFSET_TAB_TIMER[iTimer])); 03142 SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL); 03143 } 03144 03145 /** 03146 * @brief Disable the push-pull mode. 03147 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_DisablePushPullMode 03148 * @param HRTIMx High Resolution Timer instance 03149 * @param Timer This parameter can be one of the following values: 03150 * @arg @ref LL_HRTIM_TIMER_A 03151 * @arg @ref LL_HRTIM_TIMER_B 03152 * @arg @ref LL_HRTIM_TIMER_C 03153 * @arg @ref LL_HRTIM_TIMER_D 03154 * @arg @ref LL_HRTIM_TIMER_E 03155 * @retval None 03156 */ 03157 __STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03158 { 03159 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03160 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 03161 REG_OFFSET_TAB_TIMER[iTimer])); 03162 CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL); 03163 } 03164 03165 /** 03166 * @brief Indicate whether the push-pull mode is enabled. 03167 * @rmtoll TIMxCR PSHPLL LL_HRTIM_TIM_IsEnabledPushPullMode\n 03168 * @param HRTIMx High Resolution Timer instance 03169 * @param Timer This parameter can be one of the following values: 03170 * @arg @ref LL_HRTIM_TIMER_A 03171 * @arg @ref LL_HRTIM_TIMER_B 03172 * @arg @ref LL_HRTIM_TIMER_C 03173 * @arg @ref LL_HRTIM_TIMER_D 03174 * @arg @ref LL_HRTIM_TIMER_E 03175 * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0). 03176 */ 03177 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03178 { 03179 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03180 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 03181 REG_OFFSET_TAB_TIMER[iTimer])); 03182 return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL); 03183 } 03184 03185 /** 03186 * @brief Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode). 03187 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_SetCompareMode\n 03188 * TIMxCR DELCMP4 LL_HRTIM_TIM_SetCompareMode 03189 * @note In auto-delayed mode the compare match occurs independently from the timer counter value. 03190 * @param HRTIMx High Resolution Timer instance 03191 * @param Timer This parameter can be one of the following values: 03192 * @arg @ref LL_HRTIM_TIMER_A 03193 * @arg @ref LL_HRTIM_TIMER_B 03194 * @arg @ref LL_HRTIM_TIMER_C 03195 * @arg @ref LL_HRTIM_TIMER_D 03196 * @arg @ref LL_HRTIM_TIMER_E 03197 * @param CompareUnit This parameter can be one of the following values: 03198 * @arg @ref LL_HRTIM_COMPAREUNIT_2 03199 * @arg @ref LL_HRTIM_COMPAREUNIT_4 03200 * @param Mode This parameter can be one of the following values: 03201 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR 03202 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT 03203 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1 03204 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3 03205 * @retval None 03206 */ 03207 __STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit, 03208 uint32_t Mode) 03209 { 03210 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03211 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 03212 REG_OFFSET_TAB_TIMER[iTimer])); 03213 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); 03214 MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift)); 03215 } 03216 03217 /** 03218 * @brief Get the functioning mode of the compare unit. 03219 * @rmtoll TIMxCR DELCMP2 LL_HRTIM_TIM_GetCompareMode\n 03220 * TIMxCR DELCMP4 LL_HRTIM_TIM_GetCompareMode 03221 * @param HRTIMx High Resolution Timer instance 03222 * @param Timer This parameter can be one of the following values: 03223 * @arg @ref LL_HRTIM_TIMER_A 03224 * @arg @ref LL_HRTIM_TIMER_B 03225 * @arg @ref LL_HRTIM_TIMER_C 03226 * @arg @ref LL_HRTIM_TIMER_D 03227 * @arg @ref LL_HRTIM_TIMER_E 03228 * @param CompareUnit This parameter can be one of the following values: 03229 * @arg @ref LL_HRTIM_COMPAREUNIT_2 03230 * @arg @ref LL_HRTIM_COMPAREUNIT_4 03231 * @retval Mode Returned value can be one of the following values: 03232 * @arg @ref LL_HRTIM_COMPAREMODE_REGULAR 03233 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT 03234 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1 03235 * @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3 03236 */ 03237 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit) 03238 { 03239 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03240 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) + 03241 REG_OFFSET_TAB_TIMER[iTimer])); 03242 uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU); 03243 return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >> shift); 03244 } 03245 03246 /** 03247 * @brief Set the timer counter value. 03248 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_SetCounter\n 03249 * CNTxR CNTx LL_HRTIM_TIM_SetCounter 03250 * @note This function can only be called when the timer is stopped. 03251 * @note For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least 03252 * significant bits of the counter are not significant. They cannot be 03253 * written and return 0 when read. 03254 * @note The timer behavior is not guaranteed if the counter value is set above 03255 * the period. 03256 * @param HRTIMx High Resolution Timer instance 03257 * @param Timer This parameter can be one of the following values: 03258 * @arg @ref LL_HRTIM_TIMER_MASTER 03259 * @arg @ref LL_HRTIM_TIMER_A 03260 * @arg @ref LL_HRTIM_TIMER_B 03261 * @arg @ref LL_HRTIM_TIMER_C 03262 * @arg @ref LL_HRTIM_TIMER_D 03263 * @arg @ref LL_HRTIM_TIMER_E 03264 * @param Counter Value between 0 and 0xFFFF 03265 * @retval None 03266 */ 03267 __STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter) 03268 { 03269 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03270 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + 03271 REG_OFFSET_TAB_TIMER[iTimer])); 03272 MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter); 03273 } 03274 03275 /** 03276 * @brief Get actual timer counter value. 03277 * @rmtoll MCNTR MCNT LL_HRTIM_TIM_GetCounter\n 03278 * CNTxR CNTx LL_HRTIM_TIM_GetCounter 03279 * @param HRTIMx High Resolution Timer instance 03280 * @param Timer This parameter can be one of the following values: 03281 * @arg @ref LL_HRTIM_TIMER_MASTER 03282 * @arg @ref LL_HRTIM_TIMER_A 03283 * @arg @ref LL_HRTIM_TIMER_B 03284 * @arg @ref LL_HRTIM_TIMER_C 03285 * @arg @ref LL_HRTIM_TIMER_D 03286 * @arg @ref LL_HRTIM_TIMER_E 03287 * @retval Counter Value between 0 and 0xFFFF 03288 */ 03289 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03290 { 03291 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03292 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) + 03293 REG_OFFSET_TAB_TIMER[iTimer])); 03294 return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR)); 03295 } 03296 03297 /** 03298 * @brief Set the timer period value. 03299 * @rmtoll MPER MPER LL_HRTIM_TIM_SetPeriod\n 03300 * PERxR PERx LL_HRTIM_TIM_SetPeriod 03301 * @param HRTIMx High Resolution Timer instance 03302 * @param Timer This parameter can be one of the following values: 03303 * @arg @ref LL_HRTIM_TIMER_MASTER 03304 * @arg @ref LL_HRTIM_TIMER_A 03305 * @arg @ref LL_HRTIM_TIMER_B 03306 * @arg @ref LL_HRTIM_TIMER_C 03307 * @arg @ref LL_HRTIM_TIMER_D 03308 * @arg @ref LL_HRTIM_TIMER_E 03309 * @param Period Value between 0 and 0xFFFF 03310 * @retval None 03311 */ 03312 __STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period) 03313 { 03314 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03315 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + 03316 REG_OFFSET_TAB_TIMER[iTimer])); 03317 MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period); 03318 } 03319 03320 /** 03321 * @brief Get actual timer period value. 03322 * @rmtoll MPER MPER LL_HRTIM_TIM_GetPeriod\n 03323 * PERxR PERx LL_HRTIM_TIM_GetPeriod 03324 * @param HRTIMx High Resolution Timer instance 03325 * @param Timer This parameter can be one of the following values: 03326 * @arg @ref LL_HRTIM_TIMER_MASTER 03327 * @arg @ref LL_HRTIM_TIMER_A 03328 * @arg @ref LL_HRTIM_TIMER_B 03329 * @arg @ref LL_HRTIM_TIMER_C 03330 * @arg @ref LL_HRTIM_TIMER_D 03331 * @arg @ref LL_HRTIM_TIMER_E 03332 * @retval Period Value between 0 and 0xFFFF 03333 */ 03334 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03335 { 03336 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03337 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) + 03338 REG_OFFSET_TAB_TIMER[iTimer])); 03339 return (READ_BIT(*pReg, HRTIM_MPER_MPER)); 03340 } 03341 03342 /** 03343 * @brief Set the timer repetition period value. 03344 * @rmtoll MREP MREP LL_HRTIM_TIM_SetRepetition\n 03345 * REPxR REPx LL_HRTIM_TIM_SetRepetition 03346 * @param HRTIMx High Resolution Timer instance 03347 * @param Timer This parameter can be one of the following values: 03348 * @arg @ref LL_HRTIM_TIMER_MASTER 03349 * @arg @ref LL_HRTIM_TIMER_A 03350 * @arg @ref LL_HRTIM_TIMER_B 03351 * @arg @ref LL_HRTIM_TIMER_C 03352 * @arg @ref LL_HRTIM_TIMER_D 03353 * @arg @ref LL_HRTIM_TIMER_E 03354 * @param Repetition Value between 0 and 0xFF 03355 * @retval None 03356 */ 03357 __STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition) 03358 { 03359 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03360 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + 03361 REG_OFFSET_TAB_TIMER[iTimer])); 03362 MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition); 03363 } 03364 03365 /** 03366 * @brief Get actual timer repetition period value. 03367 * @rmtoll MREP MREP LL_HRTIM_TIM_GetRepetition\n 03368 * REPxR REPx LL_HRTIM_TIM_GetRepetition 03369 * @param HRTIMx High Resolution Timer instance 03370 * @param Timer This parameter can be one of the following values: 03371 * @arg @ref LL_HRTIM_TIMER_MASTER 03372 * @arg @ref LL_HRTIM_TIMER_A 03373 * @arg @ref LL_HRTIM_TIMER_B 03374 * @arg @ref LL_HRTIM_TIMER_C 03375 * @arg @ref LL_HRTIM_TIMER_D 03376 * @arg @ref LL_HRTIM_TIMER_E 03377 * @retval Repetition Value between 0 and 0xFF 03378 */ 03379 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03380 { 03381 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03382 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) + 03383 REG_OFFSET_TAB_TIMER[iTimer])); 03384 return (READ_BIT(*pReg, HRTIM_MREP_MREP)); 03385 } 03386 03387 /** 03388 * @brief Set the compare value of the compare unit 1. 03389 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_SetCompare1\n 03390 * CMP1xR CMP1x LL_HRTIM_TIM_SetCompare1 03391 * @param HRTIMx High Resolution Timer instance 03392 * @param Timer This parameter can be one of the following values: 03393 * @arg @ref LL_HRTIM_TIMER_MASTER 03394 * @arg @ref LL_HRTIM_TIMER_A 03395 * @arg @ref LL_HRTIM_TIMER_B 03396 * @arg @ref LL_HRTIM_TIMER_C 03397 * @arg @ref LL_HRTIM_TIMER_D 03398 * @arg @ref LL_HRTIM_TIMER_E 03399 * @param CompareValue Compare value must be above or equal to 3 03400 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 03401 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 03402 * @retval None 03403 */ 03404 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) 03405 { 03406 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03407 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + 03408 REG_OFFSET_TAB_TIMER[iTimer])); 03409 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue); 03410 } 03411 03412 /** 03413 * @brief Get actual compare value of the compare unit 1. 03414 * @rmtoll MCMP1R MCMP1 LL_HRTIM_TIM_GetCompare1\n 03415 * CMP1xR CMP1x LL_HRTIM_TIM_GetCompare1 03416 * @param HRTIMx High Resolution Timer instance 03417 * @param Timer This parameter can be one of the following values: 03418 * @arg @ref LL_HRTIM_TIMER_MASTER 03419 * @arg @ref LL_HRTIM_TIMER_A 03420 * @arg @ref LL_HRTIM_TIMER_B 03421 * @arg @ref LL_HRTIM_TIMER_C 03422 * @arg @ref LL_HRTIM_TIMER_D 03423 * @arg @ref LL_HRTIM_TIMER_E 03424 * @retval CompareValue Compare value must be above or equal to 3 03425 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 03426 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 03427 */ 03428 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03429 { 03430 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03431 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) + 03432 REG_OFFSET_TAB_TIMER[iTimer])); 03433 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R)); 03434 } 03435 03436 /** 03437 * @brief Set the compare value of the compare unit 2. 03438 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_SetCompare2\n 03439 * CMP2xR CMP2x LL_HRTIM_TIM_SetCompare2 03440 * @param HRTIMx High Resolution Timer instance 03441 * @param Timer This parameter can be one of the following values: 03442 * @arg @ref LL_HRTIM_TIMER_MASTER 03443 * @arg @ref LL_HRTIM_TIMER_A 03444 * @arg @ref LL_HRTIM_TIMER_B 03445 * @arg @ref LL_HRTIM_TIMER_C 03446 * @arg @ref LL_HRTIM_TIMER_D 03447 * @arg @ref LL_HRTIM_TIMER_E 03448 * @param CompareValue Compare value must be above or equal to 3 03449 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 03450 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 03451 * @retval None 03452 */ 03453 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) 03454 { 03455 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03456 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + 03457 REG_OFFSET_TAB_TIMER[iTimer])); 03458 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue); 03459 } 03460 03461 /** 03462 * @brief Get actual compare value of the compare unit 2. 03463 * @rmtoll MCMP2R MCMP2 LL_HRTIM_TIM_GetCompare2\n 03464 * CMP2xR CMP2x LL_HRTIM_TIM_GetCompare2\n 03465 * @param HRTIMx High Resolution Timer instance 03466 * @param Timer This parameter can be one of the following values: 03467 * @arg @ref LL_HRTIM_TIMER_MASTER 03468 * @arg @ref LL_HRTIM_TIMER_A 03469 * @arg @ref LL_HRTIM_TIMER_B 03470 * @arg @ref LL_HRTIM_TIMER_C 03471 * @arg @ref LL_HRTIM_TIMER_D 03472 * @arg @ref LL_HRTIM_TIMER_E 03473 * @retval CompareValue Compare value must be above or equal to 3 03474 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 03475 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 03476 */ 03477 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03478 { 03479 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03480 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) + 03481 REG_OFFSET_TAB_TIMER[iTimer])); 03482 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R)); 03483 } 03484 03485 /** 03486 * @brief Set the compare value of the compare unit 3. 03487 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_SetCompare3\n 03488 * CMP3xR CMP3x LL_HRTIM_TIM_SetCompare3 03489 * @param HRTIMx High Resolution Timer instance 03490 * @param Timer This parameter can be one of the following values: 03491 * @arg @ref LL_HRTIM_TIMER_MASTER 03492 * @arg @ref LL_HRTIM_TIMER_A 03493 * @arg @ref LL_HRTIM_TIMER_B 03494 * @arg @ref LL_HRTIM_TIMER_C 03495 * @arg @ref LL_HRTIM_TIMER_D 03496 * @arg @ref LL_HRTIM_TIMER_E 03497 * @param CompareValue Compare value must be above or equal to 3 03498 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 03499 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 03500 * @retval None 03501 */ 03502 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) 03503 { 03504 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03505 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + 03506 REG_OFFSET_TAB_TIMER[iTimer])); 03507 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue); 03508 } 03509 03510 /** 03511 * @brief Get actual compare value of the compare unit 3. 03512 * @rmtoll MCMP3R MCMP3 LL_HRTIM_TIM_GetCompare3\n 03513 * CMP3xR CMP3x LL_HRTIM_TIM_GetCompare3 03514 * @param HRTIMx High Resolution Timer instance 03515 * @param Timer This parameter can be one of the following values: 03516 * @arg @ref LL_HRTIM_TIMER_MASTER 03517 * @arg @ref LL_HRTIM_TIMER_A 03518 * @arg @ref LL_HRTIM_TIMER_B 03519 * @arg @ref LL_HRTIM_TIMER_C 03520 * @arg @ref LL_HRTIM_TIMER_D 03521 * @arg @ref LL_HRTIM_TIMER_E 03522 * @retval CompareValue Compare value must be above or equal to 3 03523 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 03524 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 03525 */ 03526 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03527 { 03528 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03529 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) + 03530 REG_OFFSET_TAB_TIMER[iTimer])); 03531 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R)); 03532 } 03533 03534 /** 03535 * @brief Set the compare value of the compare unit 4. 03536 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_SetCompare4\n 03537 * CMP4xR CMP4x LL_HRTIM_TIM_SetCompare4 03538 * @param HRTIMx High Resolution Timer instance 03539 * @param Timer This parameter can be one of the following values: 03540 * @arg @ref LL_HRTIM_TIMER_MASTER 03541 * @arg @ref LL_HRTIM_TIMER_A 03542 * @arg @ref LL_HRTIM_TIMER_B 03543 * @arg @ref LL_HRTIM_TIMER_C 03544 * @arg @ref LL_HRTIM_TIMER_D 03545 * @arg @ref LL_HRTIM_TIMER_E 03546 * @param CompareValue Compare value must be above or equal to 3 03547 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 03548 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 03549 * @retval None 03550 */ 03551 __STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue) 03552 { 03553 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03554 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + 03555 REG_OFFSET_TAB_TIMER[iTimer])); 03556 MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue); 03557 } 03558 03559 /** 03560 * @brief Get actual compare value of the compare unit 4. 03561 * @rmtoll MCMP4R MCMP4 LL_HRTIM_TIM_GetCompare4\n 03562 * CMP4xR CMP4x LL_HRTIM_TIM_GetCompare4 03563 * @param HRTIMx High Resolution Timer instance 03564 * @param Timer This parameter can be one of the following values: 03565 * @arg @ref LL_HRTIM_TIMER_MASTER 03566 * @arg @ref LL_HRTIM_TIMER_A 03567 * @arg @ref LL_HRTIM_TIMER_B 03568 * @arg @ref LL_HRTIM_TIMER_C 03569 * @arg @ref LL_HRTIM_TIMER_D 03570 * @arg @ref LL_HRTIM_TIMER_E 03571 * @retval CompareValue Compare value must be above or equal to 3 03572 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 03573 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 03574 */ 03575 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03576 { 03577 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 03578 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) + 03579 REG_OFFSET_TAB_TIMER[iTimer])); 03580 return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R)); 03581 } 03582 03583 /** 03584 * @brief Set the reset trigger of a timer counter. 03585 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_SetResetTrig\n 03586 * RSTxR CMP2 LL_HRTIM_TIM_SetResetTrig\n 03587 * RSTxR CMP4 LL_HRTIM_TIM_SetResetTrig\n 03588 * RSTxR MSTPER LL_HRTIM_TIM_SetResetTrig\n 03589 * RSTxR MSTCMP1 LL_HRTIM_TIM_SetResetTrig\n 03590 * RSTxR MSTCMP2 LL_HRTIM_TIM_SetResetTrig\n 03591 * RSTxR MSTCMP3 LL_HRTIM_TIM_SetResetTrig\n 03592 * RSTxR MSTCMP4 LL_HRTIM_TIM_SetResetTrig\n 03593 * RSTxR EXTEVNT1 LL_HRTIM_TIM_SetResetTrig\n 03594 * RSTxR EXTEVNT2 LL_HRTIM_TIM_SetResetTrig\n 03595 * RSTxR EXTEVNT3 LL_HRTIM_TIM_SetResetTrig\n 03596 * RSTxR EXTEVNT4 LL_HRTIM_TIM_SetResetTrig\n 03597 * RSTxR EXTEVNT5 LL_HRTIM_TIM_SetResetTrig\n 03598 * RSTxR EXTEVNT6 LL_HRTIM_TIM_SetResetTrig\n 03599 * RSTxR EXTEVNT7 LL_HRTIM_TIM_SetResetTrig\n 03600 * RSTxR EXTEVNT8 LL_HRTIM_TIM_SetResetTrig\n 03601 * RSTxR EXTEVNT9 LL_HRTIM_TIM_SetResetTrig\n 03602 * RSTxR EXTEVNT10 LL_HRTIM_TIM_SetResetTrig\n 03603 * RSTxR TIMBCMP1 LL_HRTIM_TIM_SetResetTrig\n 03604 * RSTxR TIMBCMP2 LL_HRTIM_TIM_SetResetTrig\n 03605 * RSTxR TIMBCMP4 LL_HRTIM_TIM_SetResetTrig\n 03606 * RSTxR TIMCCMP1 LL_HRTIM_TIM_SetResetTrig\n 03607 * RSTxR TIMCCMP2 LL_HRTIM_TIM_SetResetTrig\n 03608 * RSTxR TIMCCMP4 LL_HRTIM_TIM_SetResetTrig\n 03609 * RSTxR TIMDCMP1 LL_HRTIM_TIM_SetResetTrig\n 03610 * RSTxR TIMDCMP2 LL_HRTIM_TIM_SetResetTrig\n 03611 * RSTxR TIMDCMP4 LL_HRTIM_TIM_SetResetTrig\n 03612 * RSTxR TIMECMP1 LL_HRTIM_TIM_SetResetTrig\n 03613 * RSTxR TIMECMP2 LL_HRTIM_TIM_SetResetTrig\n 03614 * RSTxR TIMECMP4 LL_HRTIM_TIM_SetResetTrig 03615 * @note The reset of the timer counter can be triggered by up to 30 events 03616 * that can be selected among the following sources: 03617 * @arg The timing unit: Compare 2, Compare 4 and Update (3 events). 03618 * @arg The master timer: Reset and Compare 1..4 (5 events). 03619 * @arg The external events EXTEVNT1..10 (10 events). 03620 * @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events). 03621 * @param HRTIMx High Resolution Timer instance 03622 * @param Timer This parameter can be one of the following values: 03623 * @arg @ref LL_HRTIM_TIMER_A 03624 * @arg @ref LL_HRTIM_TIMER_B 03625 * @arg @ref LL_HRTIM_TIMER_C 03626 * @arg @ref LL_HRTIM_TIMER_D 03627 * @arg @ref LL_HRTIM_TIMER_E 03628 * @param ResetTrig This parameter can be a combination of the following values: 03629 * @arg @ref LL_HRTIM_RESETTRIG_NONE 03630 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE 03631 * @arg @ref LL_HRTIM_RESETTRIG_CMP2 03632 * @arg @ref LL_HRTIM_RESETTRIG_CMP4 03633 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER 03634 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1 03635 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2 03636 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3 03637 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4 03638 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1 03639 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2 03640 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3 03641 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4 03642 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5 03643 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6 03644 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7 03645 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8 03646 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9 03647 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10 03648 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1 03649 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2 03650 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4 03651 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1 03652 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2 03653 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4 03654 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1 03655 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2 03656 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4 03657 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1 03658 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2 03659 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4 03660 * @retval None 03661 */ 03662 __STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig) 03663 { 03664 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03665 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + 03666 REG_OFFSET_TAB_TIMER[iTimer])); 03667 WRITE_REG(*pReg, ResetTrig); 03668 } 03669 03670 /** 03671 * @brief Get actual reset trigger of a timer counter. 03672 * @rmtoll RSTxR UPDT LL_HRTIM_TIM_GetResetTrig\n 03673 * RSTxR CMP2 LL_HRTIM_TIM_GetResetTrig\n 03674 * RSTxR CMP4 LL_HRTIM_TIM_GetResetTrig\n 03675 * RSTxR MSTPER LL_HRTIM_TIM_GetResetTrig\n 03676 * RSTxR MSTCMP1 LL_HRTIM_TIM_GetResetTrig\n 03677 * RSTxR MSTCMP2 LL_HRTIM_TIM_GetResetTrig\n 03678 * RSTxR MSTCMP3 LL_HRTIM_TIM_GetResetTrig\n 03679 * RSTxR MSTCMP4 LL_HRTIM_TIM_GetResetTrig\n 03680 * RSTxR EXTEVNT1 LL_HRTIM_TIM_GetResetTrig\n 03681 * RSTxR EXTEVNT2 LL_HRTIM_TIM_GetResetTrig\n 03682 * RSTxR EXTEVNT3 LL_HRTIM_TIM_GetResetTrig\n 03683 * RSTxR EXTEVNT4 LL_HRTIM_TIM_GetResetTrig\n 03684 * RSTxR EXTEVNT5 LL_HRTIM_TIM_GetResetTrig\n 03685 * RSTxR EXTEVNT6 LL_HRTIM_TIM_GetResetTrig\n 03686 * RSTxR EXTEVNT7 LL_HRTIM_TIM_GetResetTrig\n 03687 * RSTxR EXTEVNT8 LL_HRTIM_TIM_GetResetTrig\n 03688 * RSTxR EXTEVNT9 LL_HRTIM_TIM_GetResetTrig\n 03689 * RSTxR EXTEVNT10 LL_HRTIM_TIM_GetResetTrig\n 03690 * RSTxR TIMBCMP1 LL_HRTIM_TIM_GetResetTrig\n 03691 * RSTxR TIMBCMP2 LL_HRTIM_TIM_GetResetTrig\n 03692 * RSTxR TIMBCMP4 LL_HRTIM_TIM_GetResetTrig\n 03693 * RSTxR TIMCCMP1 LL_HRTIM_TIM_GetResetTrig\n 03694 * RSTxR TIMCCMP2 LL_HRTIM_TIM_GetResetTrig\n 03695 * RSTxR TIMCCMP4 LL_HRTIM_TIM_GetResetTrig\n 03696 * RSTxR TIMDCMP1 LL_HRTIM_TIM_GetResetTrig\n 03697 * RSTxR TIMDCMP2 LL_HRTIM_TIM_GetResetTrig\n 03698 * RSTxR TIMDCMP4 LL_HRTIM_TIM_GetResetTrig\n 03699 * RSTxR TIMECMP1 LL_HRTIM_TIM_GetResetTrig\n 03700 * RSTxR TIMECMP2 LL_HRTIM_TIM_GetResetTrig\n 03701 * RSTxR TIMECMP4 LL_HRTIM_TIM_GetResetTrig 03702 * @param HRTIMx High Resolution Timer instance 03703 * @param Timer This parameter can be one of the following values: 03704 * @arg @ref LL_HRTIM_TIMER_A 03705 * @arg @ref LL_HRTIM_TIMER_B 03706 * @arg @ref LL_HRTIM_TIMER_C 03707 * @arg @ref LL_HRTIM_TIMER_D 03708 * @arg @ref LL_HRTIM_TIMER_E 03709 * @retval ResetTrig Returned value can be one of the following values: 03710 * @arg @ref LL_HRTIM_RESETTRIG_NONE 03711 * @arg @ref LL_HRTIM_RESETTRIG_UPDATE 03712 * @arg @ref LL_HRTIM_RESETTRIG_CMP2 03713 * @arg @ref LL_HRTIM_RESETTRIG_CMP4 03714 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER 03715 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1 03716 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2 03717 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3 03718 * @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4 03719 * @arg @ref LL_HRTIM_RESETTRIG_EEV_1 03720 * @arg @ref LL_HRTIM_RESETTRIG_EEV_2 03721 * @arg @ref LL_HRTIM_RESETTRIG_EEV_3 03722 * @arg @ref LL_HRTIM_RESETTRIG_EEV_4 03723 * @arg @ref LL_HRTIM_RESETTRIG_EEV_5 03724 * @arg @ref LL_HRTIM_RESETTRIG_EEV_6 03725 * @arg @ref LL_HRTIM_RESETTRIG_EEV_7 03726 * @arg @ref LL_HRTIM_RESETTRIG_EEV_8 03727 * @arg @ref LL_HRTIM_RESETTRIG_EEV_9 03728 * @arg @ref LL_HRTIM_RESETTRIG_EEV_10 03729 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1 03730 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2 03731 * @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4 03732 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1 03733 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2 03734 * @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4 03735 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1 03736 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2 03737 * @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4 03738 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1 03739 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2 03740 * @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4 03741 */ 03742 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03743 { 03744 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03745 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) + 03746 REG_OFFSET_TAB_TIMER[iTimer])); 03747 return (READ_REG(*pReg)); 03748 } 03749 03750 /** 03751 * @brief Get captured value for capture unit 1. 03752 * @rmtoll CPT1xR CPT1x LL_HRTIM_TIM_GetCapture1 03753 * @param HRTIMx High Resolution Timer instance 03754 * @param Timer This parameter can be one of the following values: 03755 * @arg @ref LL_HRTIM_TIMER_A 03756 * @arg @ref LL_HRTIM_TIMER_B 03757 * @arg @ref LL_HRTIM_TIMER_C 03758 * @arg @ref LL_HRTIM_TIMER_D 03759 * @arg @ref LL_HRTIM_TIMER_E 03760 * @retval Captured value 03761 */ 03762 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03763 { 03764 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03765 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) + 03766 REG_OFFSET_TAB_TIMER[iTimer])); 03767 return (READ_REG(*pReg)); 03768 } 03769 03770 /** 03771 * @brief Get captured value for capture unit 2. 03772 * @rmtoll CPT2xR CPT2x LL_HRTIM_TIM_GetCapture2 03773 * @param HRTIMx High Resolution Timer instance 03774 * @param Timer This parameter can be one of the following values: 03775 * @arg @ref LL_HRTIM_TIMER_A 03776 * @arg @ref LL_HRTIM_TIMER_B 03777 * @arg @ref LL_HRTIM_TIMER_C 03778 * @arg @ref LL_HRTIM_TIMER_D 03779 * @arg @ref LL_HRTIM_TIMER_E 03780 * @retval Captured value 03781 */ 03782 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03783 { 03784 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03785 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) + 03786 REG_OFFSET_TAB_TIMER[iTimer])); 03787 return (READ_REG(*pReg)); 03788 } 03789 03790 /** 03791 * @brief Set the trigger of a capture unit for a given timer. 03792 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_SetCaptureTrig\n 03793 * CPT1xCR UPDCPT LL_HRTIM_TIM_SetCaptureTrig\n 03794 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_SetCaptureTrig\n 03795 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_SetCaptureTrig\n 03796 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_SetCaptureTrig\n 03797 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_SetCaptureTrig\n 03798 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_SetCaptureTrig\n 03799 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_SetCaptureTrig\n 03800 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_SetCaptureTrig\n 03801 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_SetCaptureTrig\n 03802 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_SetCaptureTrig\n 03803 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_SetCaptureTrig\n 03804 * CPT1xCR TA1SET LL_HRTIM_TIM_SetCaptureTrig\n 03805 * CPT1xCR TA1RST LL_HRTIM_TIM_SetCaptureTrig\n 03806 * CPT1xCR TACMP1 LL_HRTIM_TIM_SetCaptureTrig\n 03807 * CPT1xCR TACMP2 LL_HRTIM_TIM_SetCaptureTrig\n 03808 * CPT1xCR TB1SET LL_HRTIM_TIM_SetCaptureTrig\n 03809 * CPT1xCR TB1RST LL_HRTIM_TIM_SetCaptureTrig\n 03810 * CPT1xCR TBCMP1 LL_HRTIM_TIM_SetCaptureTrig\n 03811 * CPT1xCR TBCMP2 LL_HRTIM_TIM_SetCaptureTrig\n 03812 * CPT1xCR TC1SET LL_HRTIM_TIM_SetCaptureTrig\n 03813 * CPT1xCR TC1RST LL_HRTIM_TIM_SetCaptureTrig\n 03814 * CPT1xCR TCCMP1 LL_HRTIM_TIM_SetCaptureTrig\n 03815 * CPT1xCR TCCMP2 LL_HRTIM_TIM_SetCaptureTrig\n 03816 * CPT1xCR TD1SET LL_HRTIM_TIM_SetCaptureTrig\n 03817 * CPT1xCR TD1RST LL_HRTIM_TIM_SetCaptureTrig\n 03818 * CPT1xCR TDCMP1 LL_HRTIM_TIM_SetCaptureTrig\n 03819 * CPT1xCR TDCMP2 LL_HRTIM_TIM_SetCaptureTrig\n 03820 * CPT1xCR TE1SET LL_HRTIM_TIM_SetCaptureTrig\n 03821 * CPT1xCR TE1RST LL_HRTIM_TIM_SetCaptureTrig\n 03822 * CPT1xCR TECMP1 LL_HRTIM_TIM_SetCaptureTrig\n 03823 * CPT1xCR TECMP2 LL_HRTIM_TIM_SetCaptureTrig 03824 * @param HRTIMx High Resolution Timer instance 03825 * @param Timer This parameter can be one of the following values: 03826 * @arg @ref LL_HRTIM_TIMER_A 03827 * @arg @ref LL_HRTIM_TIMER_B 03828 * @arg @ref LL_HRTIM_TIMER_C 03829 * @arg @ref LL_HRTIM_TIMER_D 03830 * @arg @ref LL_HRTIM_TIMER_E 03831 * @param CaptureUnit This parameter can be one of the following values: 03832 * @arg @ref LL_HRTIM_CAPTUREUNIT_1 03833 * @arg @ref LL_HRTIM_CAPTUREUNIT_2 03834 * @param CaptureTrig This parameter can be a combination of the following values: 03835 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE 03836 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE 03837 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1 03838 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2 03839 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3 03840 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4 03841 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5 03842 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6 03843 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7 03844 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8 03845 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9 03846 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10 03847 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET 03848 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET 03849 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1 03850 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2 03851 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET 03852 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET 03853 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1 03854 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2 03855 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET 03856 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET 03857 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1 03858 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2 03859 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET 03860 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET 03861 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1 03862 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2 03863 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET 03864 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET 03865 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1 03866 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2 03867 * @retval None 03868 */ 03869 __STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit, 03870 uint32_t CaptureTrig) 03871 { 03872 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03873 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + 03874 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); 03875 WRITE_REG(*pReg, CaptureTrig); 03876 } 03877 03878 /** 03879 * @brief Get actual trigger of a capture unit for a given timer. 03880 * @rmtoll CPT1xCR SWCPT LL_HRTIM_TIM_GetCaptureTrig\n 03881 * CPT1xCR UPDCPT LL_HRTIM_TIM_GetCaptureTrig\n 03882 * CPT1xCR EXEV1CPT LL_HRTIM_TIM_GetCaptureTrig\n 03883 * CPT1xCR EXEV2CPT LL_HRTIM_TIM_GetCaptureTrig\n 03884 * CPT1xCR EXEV3CPT LL_HRTIM_TIM_GetCaptureTrig\n 03885 * CPT1xCR EXEV4CPT LL_HRTIM_TIM_GetCaptureTrig\n 03886 * CPT1xCR EXEV5CPT LL_HRTIM_TIM_GetCaptureTrig\n 03887 * CPT1xCR EXEV6CPT LL_HRTIM_TIM_GetCaptureTrig\n 03888 * CPT1xCR EXEV7CPT LL_HRTIM_TIM_GetCaptureTrig\n 03889 * CPT1xCR EXEV8CPT LL_HRTIM_TIM_GetCaptureTrig\n 03890 * CPT1xCR EXEV9CPT LL_HRTIM_TIM_GetCaptureTrig\n 03891 * CPT1xCR EXEV10CPT LL_HRTIM_TIM_GetCaptureTrig\n 03892 * CPT1xCR TA1SET LL_HRTIM_TIM_GetCaptureTrig\n 03893 * CPT1xCR TA1RST LL_HRTIM_TIM_GetCaptureTrig\n 03894 * CPT1xCR TACMP1 LL_HRTIM_TIM_GetCaptureTrig\n 03895 * CPT1xCR TACMP2 LL_HRTIM_TIM_GetCaptureTrig\n 03896 * CPT1xCR TB1SET LL_HRTIM_TIM_GetCaptureTrig\n 03897 * CPT1xCR TB1RST LL_HRTIM_TIM_GetCaptureTrig\n 03898 * CPT1xCR TBCMP1 LL_HRTIM_TIM_GetCaptureTrig\n 03899 * CPT1xCR TBCMP2 LL_HRTIM_TIM_GetCaptureTrig\n 03900 * CPT1xCR TC1SET LL_HRTIM_TIM_GetCaptureTrig\n 03901 * CPT1xCR TC1RST LL_HRTIM_TIM_GetCaptureTrig\n 03902 * CPT1xCR TCCMP1 LL_HRTIM_TIM_GetCaptureTrig\n 03903 * CPT1xCR TCCMP2 LL_HRTIM_TIM_GetCaptureTrig\n 03904 * CPT1xCR TD1SET LL_HRTIM_TIM_GetCaptureTrig\n 03905 * CPT1xCR TD1RST LL_HRTIM_TIM_GetCaptureTrig\n 03906 * CPT1xCR TDCMP1 LL_HRTIM_TIM_GetCaptureTrig\n 03907 * CPT1xCR TDCMP2 LL_HRTIM_TIM_GetCaptureTrig\n 03908 * CPT1xCR TE1SET LL_HRTIM_TIM_GetCaptureTrig\n 03909 * CPT1xCR TE1RST LL_HRTIM_TIM_GetCaptureTrig\n 03910 * CPT1xCR TECMP1 LL_HRTIM_TIM_GetCaptureTrig\n 03911 * CPT1xCR TECMP2 LL_HRTIM_TIM_GetCaptureTrig 03912 * @param HRTIMx High Resolution Timer instance 03913 * @param Timer This parameter can be one of the following values: 03914 * @arg @ref LL_HRTIM_TIMER_A 03915 * @arg @ref LL_HRTIM_TIMER_B 03916 * @arg @ref LL_HRTIM_TIMER_C 03917 * @arg @ref LL_HRTIM_TIMER_D 03918 * @arg @ref LL_HRTIM_TIMER_E 03919 * @param CaptureUnit This parameter can be one of the following values: 03920 * @arg @ref LL_HRTIM_CAPTUREUNIT_1 03921 * @arg @ref LL_HRTIM_CAPTUREUNIT_2 03922 * @retval CaptureTrig This parameter can be a combination of the following values: 03923 * @arg @ref LL_HRTIM_CAPTURETRIG_NONE 03924 * @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE 03925 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1 03926 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2 03927 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3 03928 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4 03929 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5 03930 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6 03931 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7 03932 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8 03933 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9 03934 * @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10 03935 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET 03936 * @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET 03937 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1 03938 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2 03939 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET 03940 * @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET 03941 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1 03942 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2 03943 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET 03944 * @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET 03945 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1 03946 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2 03947 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET 03948 * @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET 03949 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1 03950 * @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2 03951 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET 03952 * @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET 03953 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1 03954 * @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2 03955 */ 03956 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit) 03957 { 03958 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03959 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) + 03960 REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U))); 03961 return (READ_REG(*pReg)); 03962 } 03963 03964 /** 03965 * @brief Enable deadtime insertion for a given timer. 03966 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_EnableDeadTime 03967 * @param HRTIMx High Resolution Timer instance 03968 * @param Timer This parameter can be one of the following values: 03969 * @arg @ref LL_HRTIM_TIMER_A 03970 * @arg @ref LL_HRTIM_TIMER_B 03971 * @arg @ref LL_HRTIM_TIMER_C 03972 * @arg @ref LL_HRTIM_TIMER_D 03973 * @arg @ref LL_HRTIM_TIMER_E 03974 * @retval None 03975 */ 03976 __STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03977 { 03978 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03979 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 03980 REG_OFFSET_TAB_TIMER[iTimer])); 03981 SET_BIT(*pReg, HRTIM_OUTR_DTEN); 03982 } 03983 03984 /** 03985 * @brief Disable deadtime insertion for a given timer. 03986 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_DisableDeadTime 03987 * @param HRTIMx High Resolution Timer instance 03988 * @param Timer This parameter can be one of the following values: 03989 * @arg @ref LL_HRTIM_TIMER_A 03990 * @arg @ref LL_HRTIM_TIMER_B 03991 * @arg @ref LL_HRTIM_TIMER_C 03992 * @arg @ref LL_HRTIM_TIMER_D 03993 * @arg @ref LL_HRTIM_TIMER_E 03994 * @retval None 03995 */ 03996 __STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 03997 { 03998 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 03999 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 04000 REG_OFFSET_TAB_TIMER[iTimer])); 04001 CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN); 04002 } 04003 04004 /** 04005 * @brief Indicate whether deadtime insertion is enabled for a given timer. 04006 * @rmtoll OUTxR DTEN LL_HRTIM_TIM_IsEnabledDeadTime 04007 * @param HRTIMx High Resolution Timer instance 04008 * @param Timer This parameter can be one of the following values: 04009 * @arg @ref LL_HRTIM_TIMER_A 04010 * @arg @ref LL_HRTIM_TIMER_B 04011 * @arg @ref LL_HRTIM_TIMER_C 04012 * @arg @ref LL_HRTIM_TIMER_D 04013 * @arg @ref LL_HRTIM_TIMER_E 04014 * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0). 04015 */ 04016 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04017 { 04018 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04019 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 04020 REG_OFFSET_TAB_TIMER[iTimer])); 04021 04022 return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL); 04023 } 04024 04025 /** 04026 * @brief Set the delayed protection (DLYPRT) mode. 04027 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_SetDLYPRTMode\n 04028 * OUTxR DLYPRT LL_HRTIM_TIM_SetDLYPRTMode 04029 * @note This function must be called prior enabling the delayed protection 04030 * @note Balanced Idle mode is only available in push-pull mode 04031 * @param HRTIMx High Resolution Timer instance 04032 * @param Timer This parameter can be one of the following values: 04033 * @arg @ref LL_HRTIM_TIMER_A 04034 * @arg @ref LL_HRTIM_TIMER_B 04035 * @arg @ref LL_HRTIM_TIMER_C 04036 * @arg @ref LL_HRTIM_TIMER_D 04037 * @arg @ref LL_HRTIM_TIMER_E 04038 * @param DLYPRTMode Delayed protection (DLYPRT) mode 04039 * 04040 * For timers A, B and C this parameter can be one of the following values: 04041 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 04042 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 04043 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 04044 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6 04045 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 04046 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 04047 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 04048 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7 04049 * 04050 * For timers D and E this parameter can be one of the following values: 04051 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 04052 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 04053 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 04054 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8 04055 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 04056 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 04057 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 04058 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9 04059 * @retval None 04060 */ 04061 __STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode) 04062 { 04063 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04064 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 04065 REG_OFFSET_TAB_TIMER[iTimer])); 04066 MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode); 04067 } 04068 04069 /** 04070 * @brief Get the delayed protection (DLYPRT) mode. 04071 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_GetDLYPRTMode\n 04072 * OUTxR DLYPRT LL_HRTIM_TIM_GetDLYPRTMode 04073 * @param HRTIMx High Resolution Timer instance 04074 * @param Timer This parameter can be one of the following values: 04075 * @arg @ref LL_HRTIM_TIMER_A 04076 * @arg @ref LL_HRTIM_TIMER_B 04077 * @arg @ref LL_HRTIM_TIMER_C 04078 * @arg @ref LL_HRTIM_TIMER_D 04079 * @arg @ref LL_HRTIM_TIMER_E 04080 * @retval DLYPRTMode Delayed protection (DLYPRT) mode 04081 * 04082 * For timers A, B and C this parameter can be one of the following values: 04083 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6 04084 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6 04085 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6 04086 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6 04087 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7 04088 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7 04089 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7 04090 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7 04091 * 04092 * For timers D and E this parameter can be one of the following values: 04093 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8 04094 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8 04095 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8 04096 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8 04097 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9 04098 * @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9 04099 * @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9 04100 * @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9 04101 */ 04102 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04103 { 04104 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04105 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 04106 REG_OFFSET_TAB_TIMER[iTimer])); 04107 return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT)); 04108 } 04109 04110 /** 04111 * @brief Enable delayed protection (DLYPRT) for a given timer. 04112 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_EnableDLYPRT 04113 * @note This function must not be called once the concerned timer is enabled 04114 * @param HRTIMx High Resolution Timer instance 04115 * @param Timer This parameter can be one of the following values: 04116 * @arg @ref LL_HRTIM_TIMER_A 04117 * @arg @ref LL_HRTIM_TIMER_B 04118 * @arg @ref LL_HRTIM_TIMER_C 04119 * @arg @ref LL_HRTIM_TIMER_D 04120 * @arg @ref LL_HRTIM_TIMER_E 04121 * @retval None 04122 */ 04123 __STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04124 { 04125 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04126 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 04127 REG_OFFSET_TAB_TIMER[iTimer])); 04128 SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); 04129 } 04130 04131 /** 04132 * @brief Disable delayed protection (DLYPRT) for a given timer. 04133 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_DisableDLYPRT 04134 * @note This function must not be called once the concerned timer is enabled 04135 * @param HRTIMx High Resolution Timer instance 04136 * @param Timer This parameter can be one of the following values: 04137 * @arg @ref LL_HRTIM_TIMER_A 04138 * @arg @ref LL_HRTIM_TIMER_B 04139 * @arg @ref LL_HRTIM_TIMER_C 04140 * @arg @ref LL_HRTIM_TIMER_D 04141 * @arg @ref LL_HRTIM_TIMER_E 04142 * @retval None 04143 */ 04144 __STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04145 { 04146 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04147 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 04148 REG_OFFSET_TAB_TIMER[iTimer])); 04149 CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN); 04150 } 04151 04152 /** 04153 * @brief Indicate whether delayed protection (DLYPRT) is enabled for a given timer. 04154 * @rmtoll OUTxR DLYPRTEN LL_HRTIM_TIM_IsEnabledDLYPRT 04155 * @param HRTIMx High Resolution Timer instance 04156 * @param Timer This parameter can be one of the following values: 04157 * @arg @ref LL_HRTIM_TIMER_A 04158 * @arg @ref LL_HRTIM_TIMER_B 04159 * @arg @ref LL_HRTIM_TIMER_C 04160 * @arg @ref LL_HRTIM_TIMER_D 04161 * @arg @ref LL_HRTIM_TIMER_E 04162 * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0). 04163 */ 04164 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04165 { 04166 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04167 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 04168 REG_OFFSET_TAB_TIMER[iTimer])); 04169 return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL); 04170 } 04171 04172 /** 04173 * @brief Enable the fault channel(s) for a given timer. 04174 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_EnableFault\n 04175 * FLTxR FLT2EN LL_HRTIM_TIM_EnableFault\n 04176 * FLTxR FLT3EN LL_HRTIM_TIM_EnableFault\n 04177 * FLTxR FLT4EN LL_HRTIM_TIM_EnableFault\n 04178 * FLTxR FLT5EN LL_HRTIM_TIM_EnableFault 04179 * @param HRTIMx High Resolution Timer instance 04180 * @param Timer This parameter can be one of the following values: 04181 * @arg @ref LL_HRTIM_TIMER_A 04182 * @arg @ref LL_HRTIM_TIMER_B 04183 * @arg @ref LL_HRTIM_TIMER_C 04184 * @arg @ref LL_HRTIM_TIMER_D 04185 * @arg @ref LL_HRTIM_TIMER_E 04186 * @param Faults This parameter can be a combination of the following values: 04187 * @arg @ref LL_HRTIM_FAULT_1 04188 * @arg @ref LL_HRTIM_FAULT_2 04189 * @arg @ref LL_HRTIM_FAULT_3 04190 * @arg @ref LL_HRTIM_FAULT_4 04191 * @arg @ref LL_HRTIM_FAULT_5 04192 * @retval None 04193 */ 04194 __STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) 04195 { 04196 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04197 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + 04198 REG_OFFSET_TAB_TIMER[iTimer])); 04199 SET_BIT(*pReg, Faults); 04200 } 04201 04202 /** 04203 * @brief Disable the fault channel(s) for a given timer. 04204 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_DisableFault\n 04205 * FLTxR FLT2EN LL_HRTIM_TIM_DisableFault\n 04206 * FLTxR FLT3EN LL_HRTIM_TIM_DisableFault\n 04207 * FLTxR FLT4EN LL_HRTIM_TIM_DisableFault\n 04208 * FLTxR FLT5EN LL_HRTIM_TIM_DisableFault 04209 * @param HRTIMx High Resolution Timer instance 04210 * @param Timer This parameter can be one of the following values: 04211 * @arg @ref LL_HRTIM_TIMER_A 04212 * @arg @ref LL_HRTIM_TIMER_B 04213 * @arg @ref LL_HRTIM_TIMER_C 04214 * @arg @ref LL_HRTIM_TIMER_D 04215 * @arg @ref LL_HRTIM_TIMER_E 04216 * @param Faults This parameter can be a combination of the following values: 04217 * @arg @ref LL_HRTIM_FAULT_1 04218 * @arg @ref LL_HRTIM_FAULT_2 04219 * @arg @ref LL_HRTIM_FAULT_3 04220 * @arg @ref LL_HRTIM_FAULT_4 04221 * @arg @ref LL_HRTIM_FAULT_5 04222 * @retval None 04223 */ 04224 __STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults) 04225 { 04226 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04227 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + 04228 REG_OFFSET_TAB_TIMER[iTimer])); 04229 CLEAR_BIT(*pReg, Faults); 04230 } 04231 04232 /** 04233 * @brief Indicate whether the fault channel is enabled for a given timer. 04234 * @rmtoll FLTxR FLT1EN LL_HRTIM_TIM_IsEnabledFault\n 04235 * FLTxR FLT2EN LL_HRTIM_TIM_IsEnabledFault\n 04236 * FLTxR FLT3EN LL_HRTIM_TIM_IsEnabledFault\n 04237 * FLTxR FLT4EN LL_HRTIM_TIM_IsEnabledFault\n 04238 * FLTxR FLT5EN LL_HRTIM_TIM_IsEnabledFault 04239 * @param HRTIMx High Resolution Timer instance 04240 * @param Timer This parameter can be one of the following values: 04241 * @arg @ref LL_HRTIM_TIMER_A 04242 * @arg @ref LL_HRTIM_TIMER_B 04243 * @arg @ref LL_HRTIM_TIMER_C 04244 * @arg @ref LL_HRTIM_TIMER_D 04245 * @arg @ref LL_HRTIM_TIMER_E 04246 * @param Fault This parameter can be one of the following values: 04247 * @arg @ref LL_HRTIM_FAULT_1 04248 * @arg @ref LL_HRTIM_FAULT_2 04249 * @arg @ref LL_HRTIM_FAULT_3 04250 * @arg @ref LL_HRTIM_FAULT_4 04251 * @arg @ref LL_HRTIM_FAULT_5 04252 * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0). 04253 */ 04254 __STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault) 04255 { 04256 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04257 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + 04258 REG_OFFSET_TAB_TIMER[iTimer])); 04259 04260 return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL); 04261 } 04262 04263 /** 04264 * @brief Lock the fault conditioning set-up for a given timer. 04265 * @rmtoll FLTxR FLTLCK LL_HRTIM_TIM_LockFault 04266 * @note Timer fault-related set-up is frozen until the next HRTIM or system reset 04267 * @param HRTIMx High Resolution Timer instance 04268 * @param Timer This parameter can be one of the following values: 04269 * @arg @ref LL_HRTIM_TIMER_A 04270 * @arg @ref LL_HRTIM_TIMER_B 04271 * @arg @ref LL_HRTIM_TIMER_C 04272 * @arg @ref LL_HRTIM_TIMER_D 04273 * @arg @ref LL_HRTIM_TIMER_E 04274 * @retval None 04275 */ 04276 __STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04277 { 04278 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04279 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) + 04280 REG_OFFSET_TAB_TIMER[iTimer])); 04281 SET_BIT(*pReg, HRTIM_FLTR_FLTLCK); 04282 } 04283 04284 /** 04285 * @brief Define how the timer behaves during a burst mode operation. 04286 * @rmtoll BMCR MTBM LL_HRTIM_TIM_SetBurstModeOption\n 04287 * BMCR TABM LL_HRTIM_TIM_SetBurstModeOption\n 04288 * BMCR TBBM LL_HRTIM_TIM_SetBurstModeOption\n 04289 * BMCR TCBM LL_HRTIM_TIM_SetBurstModeOption\n 04290 * BMCR TDBM LL_HRTIM_TIM_SetBurstModeOption\n 04291 * BMCR TEBM LL_HRTIM_TIM_SetBurstModeOption 04292 * @note This function must not be called when the burst mode is enabled 04293 * @param HRTIMx High Resolution Timer instance 04294 * @param Timer This parameter can be one of the following values: 04295 * @arg @ref LL_HRTIM_TIMER_MASTER 04296 * @arg @ref LL_HRTIM_TIMER_A 04297 * @arg @ref LL_HRTIM_TIMER_B 04298 * @arg @ref LL_HRTIM_TIMER_C 04299 * @arg @ref LL_HRTIM_TIMER_D 04300 * @arg @ref LL_HRTIM_TIMER_E 04301 * @param BurtsModeOption This parameter can be one of the following values: 04302 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK 04303 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER 04304 * @retval None 04305 */ 04306 __STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption) 04307 { 04308 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); 04309 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer); 04310 } 04311 04312 /** 04313 * @brief Retrieve how the timer behaves during a burst mode operation. 04314 * @rmtoll BMCR MCR LL_HRTIM_TIM_GetBurstModeOption\n 04315 * BMCR TABM LL_HRTIM_TIM_GetBurstModeOption\n 04316 * BMCR TBBM LL_HRTIM_TIM_GetBurstModeOption\n 04317 * BMCR TCBM LL_HRTIM_TIM_GetBurstModeOption\n 04318 * BMCR TDBM LL_HRTIM_TIM_GetBurstModeOption\n 04319 * BMCR TEBM LL_HRTIM_TIM_GetBurstModeOption 04320 * @param HRTIMx High Resolution Timer instance 04321 * @param Timer This parameter can be one of the following values: 04322 * @arg @ref LL_HRTIM_TIMER_MASTER 04323 * @arg @ref LL_HRTIM_TIMER_A 04324 * @arg @ref LL_HRTIM_TIMER_B 04325 * @arg @ref LL_HRTIM_TIMER_C 04326 * @arg @ref LL_HRTIM_TIMER_D 04327 * @arg @ref LL_HRTIM_TIMER_E 04328 * @retval BurtsMode This parameter can be one of the following values: 04329 * @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK 04330 * @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER 04331 */ 04332 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04333 { 04334 uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU); 04335 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer); 04336 } 04337 04338 /** 04339 * @brief Program which registers are to be written by Burst DMA transfers. 04340 * @rmtoll BDMUPDR MTBM LL_HRTIM_TIM_ConfigBurstDMA\n 04341 * BDMUPDR MICR LL_HRTIM_TIM_ConfigBurstDMA\n 04342 * BDMUPDR MDIER LL_HRTIM_TIM_ConfigBurstDMA\n 04343 * BDMUPDR MCNT LL_HRTIM_TIM_ConfigBurstDMA\n 04344 * BDMUPDR MPER LL_HRTIM_TIM_ConfigBurstDMA\n 04345 * BDMUPDR MREP LL_HRTIM_TIM_ConfigBurstDMA\n 04346 * BDMUPDR MCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n 04347 * BDMUPDR MCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n 04348 * BDMUPDR MCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n 04349 * BDMUPDR MCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n 04350 * BDTxUPDR TIMxCR LL_HRTIM_TIM_ConfigBurstDMA\n 04351 * BDTxUPDR TIMxICR LL_HRTIM_TIM_ConfigBurstDMA\n 04352 * BDTxUPDR TIMxDIER LL_HRTIM_TIM_ConfigBurstDMA\n 04353 * BDTxUPDR TIMxCNT LL_HRTIM_TIM_ConfigBurstDMA\n 04354 * BDTxUPDR TIMxPER LL_HRTIM_TIM_ConfigBurstDMA\n 04355 * BDTxUPDR TIMxREP LL_HRTIM_TIM_ConfigBurstDMA\n 04356 * BDTxUPDR TIMxCMP1 LL_HRTIM_TIM_ConfigBurstDMA\n 04357 * BDTxUPDR TIMxCMP2 LL_HRTIM_TIM_ConfigBurstDMA\n 04358 * BDTxUPDR TIMxCMP3 LL_HRTIM_TIM_ConfigBurstDMA\n 04359 * BDTxUPDR TIMxCMP4 LL_HRTIM_TIM_ConfigBurstDMA\n 04360 * BDTxUPDR TIMxDTR LL_HRTIM_TIM_ConfigBurstDMA\n 04361 * BDTxUPDR TIMxSET1R LL_HRTIM_TIM_ConfigBurstDMA\n 04362 * BDTxUPDR TIMxRST1R LL_HRTIM_TIM_ConfigBurstDMA\n 04363 * BDTxUPDR TIMxSET2R LL_HRTIM_TIM_ConfigBurstDMA\n 04364 * BDTxUPDR TIMxRST2R LL_HRTIM_TIM_ConfigBurstDMA\n 04365 * BDTxUPDR TIMxEEFR1 LL_HRTIM_TIM_ConfigBurstDMA\n 04366 * BDTxUPDR TIMxEEFR2 LL_HRTIM_TIM_ConfigBurstDMA\n 04367 * BDTxUPDR TIMxRSTR LL_HRTIM_TIM_ConfigBurstDMA\n 04368 * BDTxUPDR TIMxOUTR LL_HRTIM_TIM_ConfigBurstDMA\n 04369 * BDTxUPDR TIMxLTCH LL_HRTIM_TIM_ConfigBurstDMA 04370 * @param HRTIMx High Resolution Timer instance 04371 * @param Timer This parameter can be one of the following values: 04372 * @arg @ref LL_HRTIM_TIMER_MASTER 04373 * @arg @ref LL_HRTIM_TIMER_A 04374 * @arg @ref LL_HRTIM_TIMER_B 04375 * @arg @ref LL_HRTIM_TIMER_C 04376 * @arg @ref LL_HRTIM_TIMER_D 04377 * @arg @ref LL_HRTIM_TIMER_E 04378 * @param Registers Registers to be updated by the DMA request 04379 * 04380 * For Master timer this parameter can be can be a combination of the following values: 04381 * @arg @ref LL_HRTIM_BURSTDMA_NONE 04382 * @arg @ref LL_HRTIM_BURSTDMA_MCR 04383 * @arg @ref LL_HRTIM_BURSTDMA_MICR 04384 * @arg @ref LL_HRTIM_BURSTDMA_MDIER 04385 * @arg @ref LL_HRTIM_BURSTDMA_MCNT 04386 * @arg @ref LL_HRTIM_BURSTDMA_MPER 04387 * @arg @ref LL_HRTIM_BURSTDMA_MREP 04388 * @arg @ref LL_HRTIM_BURSTDMA_MCMP1 04389 * @arg @ref LL_HRTIM_BURSTDMA_MCMP2 04390 * @arg @ref LL_HRTIM_BURSTDMA_MCMP3 04391 * @arg @ref LL_HRTIM_BURSTDMA_MCMP4 04392 * 04393 * For Timers A..E this parameter can be can be a combination of the following values: 04394 * @arg @ref LL_HRTIM_BURSTDMA_NONE 04395 * @arg @ref LL_HRTIM_BURSTDMA_TIMMCR 04396 * @arg @ref LL_HRTIM_BURSTDMA_TIMICR 04397 * @arg @ref LL_HRTIM_BURSTDMA_TIMDIER 04398 * @arg @ref LL_HRTIM_BURSTDMA_TIMCNT 04399 * @arg @ref LL_HRTIM_BURSTDMA_TIMPER 04400 * @arg @ref LL_HRTIM_BURSTDMA_TIMREP 04401 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1 04402 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2 04403 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3 04404 * @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4 04405 * @arg @ref LL_HRTIM_BURSTDMA_TIMDTR 04406 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R 04407 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R 04408 * @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R 04409 * @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R 04410 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1 04411 * @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2 04412 * @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR 04413 * @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR 04414 * @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR 04415 * @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR 04416 * @retval None 04417 */ 04418 __STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers) 04419 { 04420 04421 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 04422 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer))); 04423 WRITE_REG(*pReg, Registers); 04424 } 04425 04426 /** 04427 * @brief Indicate on which output the signal is currently applied. 04428 * @rmtoll TIMxISR CPPSTAT LL_HRTIM_TIM_GetCurrentPushPullStatus 04429 * @note Only significant when the timer operates in push-pull mode. 04430 * @param HRTIMx High Resolution Timer instance 04431 * @param Timer This parameter can be one of the following values: 04432 * @arg @ref LL_HRTIM_TIMER_A 04433 * @arg @ref LL_HRTIM_TIMER_B 04434 * @arg @ref LL_HRTIM_TIMER_C 04435 * @arg @ref LL_HRTIM_TIMER_D 04436 * @arg @ref LL_HRTIM_TIMER_E 04437 * @retval CPPSTAT This parameter can be one of the following values: 04438 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1 04439 * @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2 04440 */ 04441 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04442 { 04443 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 04444 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 04445 REG_OFFSET_TAB_TIMER[iTimer])); 04446 return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT)); 04447 } 04448 04449 /** 04450 * @brief Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered. 04451 * @rmtoll TIMxISR IPPSTAT LL_HRTIM_TIM_GetIdlePushPullStatus 04452 * @param HRTIMx High Resolution Timer instance 04453 * @param Timer This parameter can be one of the following values: 04454 * @arg @ref LL_HRTIM_TIMER_A 04455 * @arg @ref LL_HRTIM_TIMER_B 04456 * @arg @ref LL_HRTIM_TIMER_C 04457 * @arg @ref LL_HRTIM_TIMER_D 04458 * @arg @ref LL_HRTIM_TIMER_E 04459 * @retval IPPSTAT This parameter can be one of the following values: 04460 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1 04461 * @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2 04462 */ 04463 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04464 { 04465 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 04466 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 04467 REG_OFFSET_TAB_TIMER[iTimer])); 04468 return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT)); 04469 } 04470 04471 /** 04472 * @brief Set the event filter for a given timer. 04473 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventFilter\n 04474 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventFilter\n 04475 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventFilter\n 04476 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventFilter\n 04477 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventFilter\n 04478 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventFilter\n 04479 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventFilter\n 04480 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventFilter\n 04481 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventFilter\n 04482 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventFilter 04483 * @note This function must not be called when the timer counter is enabled. 04484 * @param HRTIMx High Resolution Timer instance 04485 * @param Timer This parameter can be one of the following values: 04486 * @arg @ref LL_HRTIM_TIMER_A 04487 * @arg @ref LL_HRTIM_TIMER_B 04488 * @arg @ref LL_HRTIM_TIMER_C 04489 * @arg @ref LL_HRTIM_TIMER_D 04490 * @arg @ref LL_HRTIM_TIMER_E 04491 * @param Event This parameter can be one of the following values: 04492 * @arg @ref LL_HRTIM_EVENT_1 04493 * @arg @ref LL_HRTIM_EVENT_2 04494 * @arg @ref LL_HRTIM_EVENT_3 04495 * @arg @ref LL_HRTIM_EVENT_4 04496 * @arg @ref LL_HRTIM_EVENT_5 04497 * @arg @ref LL_HRTIM_EVENT_6 04498 * @arg @ref LL_HRTIM_EVENT_7 04499 * @arg @ref LL_HRTIM_EVENT_8 04500 * @arg @ref LL_HRTIM_EVENT_9 04501 * @arg @ref LL_HRTIM_EVENT_10 04502 * @param Filter This parameter can be one of the following values: 04503 * @arg @ref LL_HRTIM_EEFLTR_NONE 04504 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1 04505 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2 04506 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3 04507 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4 04508 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1 04509 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2 04510 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3 04511 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4 04512 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5 04513 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6 04514 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7 04515 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8 04516 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2 04517 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3 04518 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM 04519 04520 * @retval None 04521 */ 04522 __STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter) 04523 { 04524 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); 04525 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 04526 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + 04527 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); 04528 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); 04529 } 04530 04531 /** 04532 * @brief Get actual event filter settings for a given timer. 04533 * @rmtoll EEFxR1 EE1FLTR LL_HRTIM_TIM_GetEventFilter\n 04534 * EEFxR1 EE2FLTR LL_HRTIM_TIM_GetEventFilter\n 04535 * EEFxR1 EE3FLTR LL_HRTIM_TIM_GetEventFilter\n 04536 * EEFxR1 EE4FLTR LL_HRTIM_TIM_GetEventFilter\n 04537 * EEFxR1 EE5FLTR LL_HRTIM_TIM_GetEventFilter\n 04538 * EEFxR2 EE6FLTR LL_HRTIM_TIM_GetEventFilter\n 04539 * EEFxR2 EE7FLTR LL_HRTIM_TIM_GetEventFilter\n 04540 * EEFxR2 EE8FLTR LL_HRTIM_TIM_GetEventFilter\n 04541 * EEFxR2 EE9FLTR LL_HRTIM_TIM_GetEventFilter\n 04542 * EEFxR2 EE10FLTR LL_HRTIM_TIM_GetEventFilter 04543 * @param HRTIMx High Resolution Timer instance 04544 * @param Timer This parameter can be one of the following values: 04545 * @arg @ref LL_HRTIM_TIMER_A 04546 * @arg @ref LL_HRTIM_TIMER_B 04547 * @arg @ref LL_HRTIM_TIMER_C 04548 * @arg @ref LL_HRTIM_TIMER_D 04549 * @arg @ref LL_HRTIM_TIMER_E 04550 * @param Event This parameter can be one of the following values: 04551 * @arg @ref LL_HRTIM_EVENT_1 04552 * @arg @ref LL_HRTIM_EVENT_2 04553 * @arg @ref LL_HRTIM_EVENT_3 04554 * @arg @ref LL_HRTIM_EVENT_4 04555 * @arg @ref LL_HRTIM_EVENT_5 04556 * @arg @ref LL_HRTIM_EVENT_6 04557 * @arg @ref LL_HRTIM_EVENT_7 04558 * @arg @ref LL_HRTIM_EVENT_8 04559 * @arg @ref LL_HRTIM_EVENT_9 04560 * @arg @ref LL_HRTIM_EVENT_10 04561 * @retval Filter This parameter can be one of the following values: 04562 * @arg @ref LL_HRTIM_EEFLTR_NONE 04563 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1 04564 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2 04565 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3 04566 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4 04567 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1 04568 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2 04569 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3 04570 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4 04571 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5 04572 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6 04573 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7 04574 * @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8 04575 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2 04576 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3 04577 * @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM 04578 */ 04579 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) 04580 { 04581 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); 04582 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 04583 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + 04584 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); 04585 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent])); 04586 } 04587 04588 /** 04589 * @brief Enable or disable event latch mechanism for a given timer. 04590 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04591 * EEFxR1 EE2LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04592 * EEFxR1 EE3LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04593 * EEFxR1 EE4LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04594 * EEFxR1 EE5LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04595 * EEFxR2 EE6LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04596 * EEFxR2 EE7LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04597 * EEFxR2 EE8LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04598 * EEFxR2 EE9LTCH LL_HRTIM_TIM_SetEventLatchStatus\n 04599 * EEFxR2 EE10LTCH LL_HRTIM_TIM_SetEventLatchStatus 04600 * @note This function must not be called when the timer counter is enabled. 04601 * @param HRTIMx High Resolution Timer instance 04602 * @param Timer This parameter can be one of the following values: 04603 * @arg @ref LL_HRTIM_TIMER_A 04604 * @arg @ref LL_HRTIM_TIMER_B 04605 * @arg @ref LL_HRTIM_TIMER_C 04606 * @arg @ref LL_HRTIM_TIMER_D 04607 * @arg @ref LL_HRTIM_TIMER_E 04608 * @param Event This parameter can be one of the following values: 04609 * @arg @ref LL_HRTIM_EVENT_1 04610 * @arg @ref LL_HRTIM_EVENT_2 04611 * @arg @ref LL_HRTIM_EVENT_3 04612 * @arg @ref LL_HRTIM_EVENT_4 04613 * @arg @ref LL_HRTIM_EVENT_5 04614 * @arg @ref LL_HRTIM_EVENT_6 04615 * @arg @ref LL_HRTIM_EVENT_7 04616 * @arg @ref LL_HRTIM_EVENT_8 04617 * @arg @ref LL_HRTIM_EVENT_9 04618 * @arg @ref LL_HRTIM_EVENT_10 04619 * @param LatchStatus This parameter can be one of the following values: 04620 * @arg @ref LL_HRTIM_EELATCH_DISABLED 04621 * @arg @ref LL_HRTIM_EELATCH_ENABLED 04622 * @retval None 04623 */ 04624 __STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, 04625 uint32_t LatchStatus) 04626 { 04627 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); 04628 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 04629 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + 04630 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); 04631 MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent])); 04632 } 04633 04634 /** 04635 * @brief Get actual event latch status for a given timer. 04636 * @rmtoll EEFxR1 EE1LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04637 * EEFxR1 EE2LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04638 * EEFxR1 EE3LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04639 * EEFxR1 EE4LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04640 * EEFxR1 EE5LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04641 * EEFxR2 EE6LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04642 * EEFxR2 EE7LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04643 * EEFxR2 EE8LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04644 * EEFxR2 EE9LTCH LL_HRTIM_TIM_GetEventLatchStatus\n 04645 * EEFxR2 EE10LTCH LL_HRTIM_TIM_GetEventLatchStatus 04646 * @param HRTIMx High Resolution Timer instance 04647 * @param Timer This parameter can be one of the following values: 04648 * @arg @ref LL_HRTIM_TIMER_A 04649 * @arg @ref LL_HRTIM_TIMER_B 04650 * @arg @ref LL_HRTIM_TIMER_C 04651 * @arg @ref LL_HRTIM_TIMER_D 04652 * @arg @ref LL_HRTIM_TIMER_E 04653 * @param Event This parameter can be one of the following values: 04654 * @arg @ref LL_HRTIM_EVENT_1 04655 * @arg @ref LL_HRTIM_EVENT_2 04656 * @arg @ref LL_HRTIM_EVENT_3 04657 * @arg @ref LL_HRTIM_EVENT_4 04658 * @arg @ref LL_HRTIM_EVENT_5 04659 * @arg @ref LL_HRTIM_EVENT_6 04660 * @arg @ref LL_HRTIM_EVENT_7 04661 * @arg @ref LL_HRTIM_EVENT_8 04662 * @arg @ref LL_HRTIM_EVENT_9 04663 * @arg @ref LL_HRTIM_EVENT_10 04664 * @retval LatchStatus This parameter can be one of the following values: 04665 * @arg @ref LL_HRTIM_EELATCH_DISABLED 04666 * @arg @ref LL_HRTIM_EELATCH_ENABLED 04667 */ 04668 __STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event) 04669 { 04670 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A)); 04671 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 04672 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) + 04673 REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent])); 04674 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent])); 04675 } 04676 04677 /** 04678 * @} 04679 */ 04680 04681 /** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration 04682 * @{ 04683 */ 04684 04685 /** 04686 * @brief Configure the dead time insertion feature for a given timer. 04687 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_Config\n 04688 * DTxR SDTF LL_HRTIM_DT_Config\n 04689 * DTxR SDRT LL_HRTIM_DT_Config 04690 * @param HRTIMx High Resolution Timer instance 04691 * @param Timer This parameter can be one of the following values: 04692 * @arg @ref LL_HRTIM_TIMER_A 04693 * @arg @ref LL_HRTIM_TIMER_B 04694 * @arg @ref LL_HRTIM_TIMER_C 04695 * @arg @ref LL_HRTIM_TIMER_D 04696 * @arg @ref LL_HRTIM_TIMER_E 04697 * @param Configuration This parameter must be a combination of all the following values: 04698 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16 04699 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE 04700 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE 04701 * @retval None 04702 */ 04703 __STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) 04704 { 04705 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04706 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04707 REG_OFFSET_TAB_TIMER[iTimer])); 04708 MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration); 04709 } 04710 04711 /** 04712 * @brief Set the deadtime prescaler value. 04713 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_SetPrescaler 04714 * @param HRTIMx High Resolution Timer instance 04715 * @param Timer This parameter can be one of the following values: 04716 * @arg @ref LL_HRTIM_TIMER_A 04717 * @arg @ref LL_HRTIM_TIMER_B 04718 * @arg @ref LL_HRTIM_TIMER_C 04719 * @arg @ref LL_HRTIM_TIMER_D 04720 * @arg @ref LL_HRTIM_TIMER_E 04721 * @param Prescaler This parameter can be one of the following values: 04722 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 04723 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4 04724 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2 04725 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1 04726 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2 04727 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4 04728 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8 04729 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16 04730 * @retval None 04731 */ 04732 __STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) 04733 { 04734 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04735 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04736 REG_OFFSET_TAB_TIMER[iTimer])); 04737 MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler); 04738 } 04739 04740 /** 04741 * @brief Get actual deadtime prescaler value. 04742 * @rmtoll DTxR DTPRSC LL_HRTIM_DT_GetPrescaler 04743 * @param HRTIMx High Resolution Timer instance 04744 * @param Timer This parameter can be one of the following values: 04745 * @arg @ref LL_HRTIM_TIMER_A 04746 * @arg @ref LL_HRTIM_TIMER_B 04747 * @arg @ref LL_HRTIM_TIMER_C 04748 * @arg @ref LL_HRTIM_TIMER_D 04749 * @arg @ref LL_HRTIM_TIMER_E 04750 * @retval Prescaler This parameter can be one of the following values: 04751 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 04752 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL4 04753 * @arg @ref LL_HRTIM_DT_PRESCALER_MUL2 04754 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV1 04755 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV2 04756 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV4 04757 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV8 04758 * @arg @ref LL_HRTIM_DT_PRESCALER_DIV16 04759 */ 04760 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04761 { 04762 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04763 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04764 REG_OFFSET_TAB_TIMER[iTimer])); 04765 return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC)); 04766 } 04767 04768 /** 04769 * @brief Set the deadtime rising value. 04770 * @rmtoll DTxR DTR LL_HRTIM_DT_SetRisingValue 04771 * @param HRTIMx High Resolution Timer instance 04772 * @param Timer This parameter can be one of the following values: 04773 * @arg @ref LL_HRTIM_TIMER_A 04774 * @arg @ref LL_HRTIM_TIMER_B 04775 * @arg @ref LL_HRTIM_TIMER_C 04776 * @arg @ref LL_HRTIM_TIMER_D 04777 * @arg @ref LL_HRTIM_TIMER_E 04778 * @param RisingValue Value between 0 and 0x1FF 04779 * @retval None 04780 */ 04781 __STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue) 04782 { 04783 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04784 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04785 REG_OFFSET_TAB_TIMER[iTimer])); 04786 MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue); 04787 } 04788 04789 /** 04790 * @brief Get actual deadtime rising value. 04791 * @rmtoll DTxR DTR LL_HRTIM_DT_GetRisingValue 04792 * @param HRTIMx High Resolution Timer instance 04793 * @param Timer This parameter can be one of the following values: 04794 * @arg @ref LL_HRTIM_TIMER_A 04795 * @arg @ref LL_HRTIM_TIMER_B 04796 * @arg @ref LL_HRTIM_TIMER_C 04797 * @arg @ref LL_HRTIM_TIMER_D 04798 * @arg @ref LL_HRTIM_TIMER_E 04799 * @retval RisingValue Value between 0 and 0x1FF 04800 */ 04801 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04802 { 04803 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04804 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04805 REG_OFFSET_TAB_TIMER[iTimer])); 04806 return (READ_BIT(*pReg, HRTIM_DTR_DTR)); 04807 } 04808 04809 /** 04810 * @brief Set the deadtime sign on rising edge. 04811 * @rmtoll DTxR SDTR LL_HRTIM_DT_SetRisingSign 04812 * @param HRTIMx High Resolution Timer instance 04813 * @param Timer This parameter can be one of the following values: 04814 * @arg @ref LL_HRTIM_TIMER_A 04815 * @arg @ref LL_HRTIM_TIMER_B 04816 * @arg @ref LL_HRTIM_TIMER_C 04817 * @arg @ref LL_HRTIM_TIMER_D 04818 * @arg @ref LL_HRTIM_TIMER_E 04819 * @param RisingSign This parameter can be one of the following values: 04820 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE 04821 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE 04822 * @retval None 04823 */ 04824 __STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign) 04825 { 04826 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04827 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04828 REG_OFFSET_TAB_TIMER[iTimer])); 04829 MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign); 04830 } 04831 04832 /** 04833 * @brief Get actual deadtime sign on rising edge. 04834 * @rmtoll DTxR SDTR LL_HRTIM_DT_GetRisingSign 04835 * @param HRTIMx High Resolution Timer instance 04836 * @param Timer This parameter can be one of the following values: 04837 * @arg @ref LL_HRTIM_TIMER_A 04838 * @arg @ref LL_HRTIM_TIMER_B 04839 * @arg @ref LL_HRTIM_TIMER_C 04840 * @arg @ref LL_HRTIM_TIMER_D 04841 * @arg @ref LL_HRTIM_TIMER_E 04842 * @retval RisingSign This parameter can be one of the following values: 04843 * @arg @ref LL_HRTIM_DT_RISING_POSITIVE 04844 * @arg @ref LL_HRTIM_DT_RISING_NEGATIVE 04845 */ 04846 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04847 { 04848 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04849 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04850 REG_OFFSET_TAB_TIMER[iTimer])); 04851 return (READ_BIT(*pReg, HRTIM_DTR_SDTR)); 04852 } 04853 04854 /** 04855 * @brief Set the deadime falling value. 04856 * @rmtoll DTxR DTF LL_HRTIM_DT_SetFallingValue 04857 * @param HRTIMx High Resolution Timer instance 04858 * @param Timer This parameter can be one of the following values: 04859 * @arg @ref LL_HRTIM_TIMER_A 04860 * @arg @ref LL_HRTIM_TIMER_B 04861 * @arg @ref LL_HRTIM_TIMER_C 04862 * @arg @ref LL_HRTIM_TIMER_D 04863 * @arg @ref LL_HRTIM_TIMER_E 04864 * @param FallingValue Value between 0 and 0x1FF 04865 * @retval None 04866 */ 04867 __STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue) 04868 { 04869 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04870 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04871 REG_OFFSET_TAB_TIMER[iTimer])); 04872 MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos); 04873 } 04874 04875 /** 04876 * @brief Get actual deadtime falling value 04877 * @rmtoll DTxR DTF LL_HRTIM_DT_GetFallingValue 04878 * @param HRTIMx High Resolution Timer instance 04879 * @param Timer This parameter can be one of the following values: 04880 * @arg @ref LL_HRTIM_TIMER_A 04881 * @arg @ref LL_HRTIM_TIMER_B 04882 * @arg @ref LL_HRTIM_TIMER_C 04883 * @arg @ref LL_HRTIM_TIMER_D 04884 * @arg @ref LL_HRTIM_TIMER_E 04885 * @retval FallingValue Value between 0 and 0x1FF 04886 */ 04887 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04888 { 04889 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04890 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04891 REG_OFFSET_TAB_TIMER[iTimer])); 04892 return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos); 04893 } 04894 04895 /** 04896 * @brief Set the deadtime sign on falling edge. 04897 * @rmtoll DTxR SDTF LL_HRTIM_DT_SetFallingSign 04898 * @param HRTIMx High Resolution Timer instance 04899 * @param Timer This parameter can be one of the following values: 04900 * @arg @ref LL_HRTIM_TIMER_A 04901 * @arg @ref LL_HRTIM_TIMER_B 04902 * @arg @ref LL_HRTIM_TIMER_C 04903 * @arg @ref LL_HRTIM_TIMER_D 04904 * @arg @ref LL_HRTIM_TIMER_E 04905 * @param FallingSign This parameter can be one of the following values: 04906 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE 04907 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE 04908 * @retval None 04909 */ 04910 __STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign) 04911 { 04912 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04913 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04914 REG_OFFSET_TAB_TIMER[iTimer])); 04915 MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign); 04916 } 04917 04918 /** 04919 * @brief Get actual deadtime sign on falling edge. 04920 * @rmtoll DTxR SDTF LL_HRTIM_DT_GetFallingSign 04921 * @param HRTIMx High Resolution Timer instance 04922 * @param Timer This parameter can be one of the following values: 04923 * @arg @ref LL_HRTIM_TIMER_A 04924 * @arg @ref LL_HRTIM_TIMER_B 04925 * @arg @ref LL_HRTIM_TIMER_C 04926 * @arg @ref LL_HRTIM_TIMER_D 04927 * @arg @ref LL_HRTIM_TIMER_E 04928 * @retval FallingSign This parameter can be one of the following values: 04929 * @arg @ref LL_HRTIM_DT_FALLING_POSITIVE 04930 * @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE 04931 */ 04932 __STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04933 { 04934 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04935 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04936 REG_OFFSET_TAB_TIMER[iTimer])); 04937 return (READ_BIT(*pReg, HRTIM_DTR_SDTF)); 04938 } 04939 04940 /** 04941 * @brief Lock the deadtime value and sign on rising edge. 04942 * @rmtoll DTxR DTRLK LL_HRTIM_DT_LockRising 04943 * @param HRTIMx High Resolution Timer instance 04944 * @param Timer This parameter can be one of the following values: 04945 * @arg @ref LL_HRTIM_TIMER_A 04946 * @arg @ref LL_HRTIM_TIMER_B 04947 * @arg @ref LL_HRTIM_TIMER_C 04948 * @arg @ref LL_HRTIM_TIMER_D 04949 * @arg @ref LL_HRTIM_TIMER_E 04950 * @retval None 04951 */ 04952 __STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04953 { 04954 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04955 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04956 REG_OFFSET_TAB_TIMER[iTimer])); 04957 SET_BIT(*pReg, HRTIM_DTR_DTRLK); 04958 } 04959 04960 /** 04961 * @brief Lock the deadtime sign on rising edge. 04962 * @rmtoll DTxR DTRSLK LL_HRTIM_DT_LockRisingSign 04963 * @param HRTIMx High Resolution Timer instance 04964 * @param Timer This parameter can be one of the following values: 04965 * @arg @ref LL_HRTIM_TIMER_A 04966 * @arg @ref LL_HRTIM_TIMER_B 04967 * @arg @ref LL_HRTIM_TIMER_C 04968 * @arg @ref LL_HRTIM_TIMER_D 04969 * @arg @ref LL_HRTIM_TIMER_E 04970 * @retval None 04971 */ 04972 __STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04973 { 04974 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04975 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04976 REG_OFFSET_TAB_TIMER[iTimer])); 04977 SET_BIT(*pReg, HRTIM_DTR_DTRSLK); 04978 } 04979 04980 /** 04981 * @brief Lock the deadtime value and sign on falling edge. 04982 * @rmtoll DTxR DTFLK LL_HRTIM_DT_LockFalling 04983 * @param HRTIMx High Resolution Timer instance 04984 * @param Timer This parameter can be one of the following values: 04985 * @arg @ref LL_HRTIM_TIMER_A 04986 * @arg @ref LL_HRTIM_TIMER_B 04987 * @arg @ref LL_HRTIM_TIMER_C 04988 * @arg @ref LL_HRTIM_TIMER_D 04989 * @arg @ref LL_HRTIM_TIMER_E 04990 * @retval None 04991 */ 04992 __STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 04993 { 04994 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 04995 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 04996 REG_OFFSET_TAB_TIMER[iTimer])); 04997 SET_BIT(*pReg, HRTIM_DTR_DTFLK); 04998 } 04999 05000 /** 05001 * @brief Lock the deadtime sign on falling edge. 05002 * @rmtoll DTxR DTFSLK LL_HRTIM_DT_LockFallingSign 05003 * @param HRTIMx High Resolution Timer instance 05004 * @param Timer This parameter can be one of the following values: 05005 * @arg @ref LL_HRTIM_TIMER_A 05006 * @arg @ref LL_HRTIM_TIMER_B 05007 * @arg @ref LL_HRTIM_TIMER_C 05008 * @arg @ref LL_HRTIM_TIMER_D 05009 * @arg @ref LL_HRTIM_TIMER_E 05010 * @retval None 05011 */ 05012 __STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 05013 { 05014 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 05015 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) + 05016 REG_OFFSET_TAB_TIMER[iTimer])); 05017 SET_BIT(*pReg, HRTIM_DTR_DTFSLK); 05018 } 05019 05020 /** 05021 * @} 05022 */ 05023 05024 /** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration 05025 * @{ 05026 */ 05027 05028 /** 05029 * @brief Configure the chopper stage for a given timer. 05030 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_Config\n 05031 * CHPxR CARDTY LL_HRTIM_CHP_Config\n 05032 * CHPxR STRTPW LL_HRTIM_CHP_Config 05033 * @note This function must not be called if the chopper mode is already 05034 * enabled for one of the timer outputs. 05035 * @param HRTIMx High Resolution Timer instance 05036 * @param Timer This parameter can be one of the following values: 05037 * @arg @ref LL_HRTIM_TIMER_A 05038 * @arg @ref LL_HRTIM_TIMER_B 05039 * @arg @ref LL_HRTIM_TIMER_C 05040 * @arg @ref LL_HRTIM_TIMER_D 05041 * @arg @ref LL_HRTIM_TIMER_E 05042 * @param Configuration This parameter must be a combination of all the following values: 05043 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256 05044 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875 05045 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256 05046 * @retval None 05047 */ 05048 __STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration) 05049 { 05050 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 05051 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 05052 REG_OFFSET_TAB_TIMER[iTimer])); 05053 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration); 05054 } 05055 05056 /** 05057 * @brief Set prescaler determining the carrier frequency to be added on top 05058 * of the timer output signals when chopper mode is enabled. 05059 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_SetPrescaler 05060 * @note This function must not be called if the chopper mode is already 05061 * enabled for one of the timer outputs. 05062 * @param HRTIMx High Resolution Timer instance 05063 * @param Timer This parameter can be one of the following values: 05064 * @arg @ref LL_HRTIM_TIMER_A 05065 * @arg @ref LL_HRTIM_TIMER_B 05066 * @arg @ref LL_HRTIM_TIMER_C 05067 * @arg @ref LL_HRTIM_TIMER_D 05068 * @arg @ref LL_HRTIM_TIMER_E 05069 * @param Prescaler This parameter can be one of the following values: 05070 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 05071 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32 05072 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48 05073 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64 05074 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80 05075 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96 05076 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112 05077 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128 05078 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144 05079 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160 05080 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176 05081 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192 05082 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208 05083 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224 05084 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240 05085 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256 05086 * @retval None 05087 */ 05088 __STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler) 05089 { 05090 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 05091 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 05092 REG_OFFSET_TAB_TIMER[iTimer])); 05093 MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler); 05094 } 05095 05096 /** 05097 * @brief Get actual chopper stage prescaler value. 05098 * @rmtoll CHPxR CARFRQ LL_HRTIM_CHP_GetPrescaler 05099 * @param HRTIMx High Resolution Timer instance 05100 * @param Timer This parameter can be one of the following values: 05101 * @arg @ref LL_HRTIM_TIMER_A 05102 * @arg @ref LL_HRTIM_TIMER_B 05103 * @arg @ref LL_HRTIM_TIMER_C 05104 * @arg @ref LL_HRTIM_TIMER_D 05105 * @arg @ref LL_HRTIM_TIMER_E 05106 * @retval Prescaler This parameter can be one of the following values: 05107 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 05108 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32 05109 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48 05110 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64 05111 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80 05112 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96 05113 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112 05114 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128 05115 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144 05116 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160 05117 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176 05118 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192 05119 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208 05120 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224 05121 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240 05122 * @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256 05123 */ 05124 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 05125 { 05126 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 05127 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 05128 REG_OFFSET_TAB_TIMER[iTimer])); 05129 return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ)); 05130 } 05131 05132 /** 05133 * @brief Set the chopper duty cycle. 05134 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_SetDutyCycle 05135 * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8) 05136 * @note This function must not be called if the chopper mode is already 05137 * enabled for one of the timer outputs. 05138 * @param HRTIMx High Resolution Timer instance 05139 * @param Timer This parameter can be one of the following values: 05140 * @arg @ref LL_HRTIM_TIMER_A 05141 * @arg @ref LL_HRTIM_TIMER_B 05142 * @arg @ref LL_HRTIM_TIMER_C 05143 * @arg @ref LL_HRTIM_TIMER_D 05144 * @arg @ref LL_HRTIM_TIMER_E 05145 * @param DutyCycle This parameter can be one of the following values: 05146 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 05147 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125 05148 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250 05149 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375 05150 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500 05151 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625 05152 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750 05153 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875 05154 * @retval None 05155 */ 05156 __STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle) 05157 { 05158 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 05159 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 05160 REG_OFFSET_TAB_TIMER[iTimer])); 05161 MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle); 05162 } 05163 05164 /** 05165 * @brief Get actual chopper duty cycle. 05166 * @rmtoll CHPxR CARDTY LL_HRTIM_CHP_GetDutyCycle 05167 * @param HRTIMx High Resolution Timer instance 05168 * @param Timer This parameter can be one of the following values: 05169 * @arg @ref LL_HRTIM_TIMER_A 05170 * @arg @ref LL_HRTIM_TIMER_B 05171 * @arg @ref LL_HRTIM_TIMER_C 05172 * @arg @ref LL_HRTIM_TIMER_D 05173 * @arg @ref LL_HRTIM_TIMER_E 05174 * @retval DutyCycle This parameter can be one of the following values: 05175 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 05176 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125 05177 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250 05178 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375 05179 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500 05180 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625 05181 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750 05182 * @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875 05183 */ 05184 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 05185 { 05186 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 05187 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 05188 REG_OFFSET_TAB_TIMER[iTimer])); 05189 return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY)); 05190 } 05191 05192 /** 05193 * @brief Set the start pulse width. 05194 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_SetPulseWidth 05195 * @note This function must not be called if the chopper mode is already 05196 * enabled for one of the timer outputs. 05197 * @param HRTIMx High Resolution Timer instance 05198 * @param Timer This parameter can be one of the following values: 05199 * @arg @ref LL_HRTIM_TIMER_A 05200 * @arg @ref LL_HRTIM_TIMER_B 05201 * @arg @ref LL_HRTIM_TIMER_C 05202 * @arg @ref LL_HRTIM_TIMER_D 05203 * @arg @ref LL_HRTIM_TIMER_E 05204 * @param PulseWidth This parameter can be one of the following values: 05205 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 05206 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32 05207 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48 05208 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64 05209 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80 05210 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96 05211 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112 05212 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128 05213 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144 05214 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160 05215 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176 05216 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192 05217 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208 05218 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224 05219 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240 05220 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256 05221 * @retval None 05222 */ 05223 __STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth) 05224 { 05225 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 05226 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 05227 REG_OFFSET_TAB_TIMER[iTimer])); 05228 MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth); 05229 } 05230 05231 /** 05232 * @brief Get actual start pulse width. 05233 * @rmtoll CHPxR STRPW LL_HRTIM_CHP_GetPulseWidth 05234 * @param HRTIMx High Resolution Timer instance 05235 * @param Timer This parameter can be one of the following values: 05236 * @arg @ref LL_HRTIM_TIMER_A 05237 * @arg @ref LL_HRTIM_TIMER_B 05238 * @arg @ref LL_HRTIM_TIMER_C 05239 * @arg @ref LL_HRTIM_TIMER_D 05240 * @arg @ref LL_HRTIM_TIMER_E 05241 * @retval PulseWidth This parameter can be one of the following values: 05242 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 05243 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32 05244 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48 05245 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64 05246 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80 05247 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96 05248 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112 05249 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128 05250 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144 05251 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160 05252 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176 05253 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192 05254 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208 05255 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224 05256 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240 05257 * @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256 05258 */ 05259 __STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 05260 { 05261 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos); 05262 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) + 05263 REG_OFFSET_TAB_TIMER[iTimer])); 05264 return (READ_BIT(*pReg, HRTIM_CHPR_STRPW)); 05265 } 05266 05267 /** 05268 * @} 05269 */ 05270 05271 /** @defgroup HRTIM_LL_EF_Output_Management Output_Management 05272 * @{ 05273 */ 05274 05275 /** 05276 * @brief Set the timer output set source. 05277 * @rmtoll SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n 05278 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n 05279 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n 05280 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n 05281 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n 05282 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n 05283 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n 05284 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n 05285 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n 05286 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n 05287 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n 05288 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n 05289 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n 05290 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n 05291 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n 05292 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n 05293 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n 05294 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n 05295 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n 05296 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n 05297 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n 05298 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n 05299 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n 05300 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n 05301 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n 05302 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n 05303 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n 05304 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n 05305 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n 05306 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n 05307 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n 05308 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc\n 05309 * SETx1R SST LL_HRTIM_OUT_SetOutputSetSrc\n 05310 * SETx1R RESYNC LL_HRTIM_OUT_SetOutputSetSrc\n 05311 * SETx1R PER LL_HRTIM_OUT_SetOutputSetSrc\n 05312 * SETx1R CMP1 LL_HRTIM_OUT_SetOutputSetSrc\n 05313 * SETx1R CMP2 LL_HRTIM_OUT_SetOutputSetSrc\n 05314 * SETx1R CMP3 LL_HRTIM_OUT_SetOutputSetSrc\n 05315 * SETx1R CMP4 LL_HRTIM_OUT_SetOutputSetSrc\n 05316 * SETx1R MSTPER LL_HRTIM_OUT_SetOutputSetSrc\n 05317 * SETx1R MSTCMP1 LL_HRTIM_OUT_SetOutputSetSrc\n 05318 * SETx1R MSTCMP2 LL_HRTIM_OUT_SetOutputSetSrc\n 05319 * SETx1R MSTCMP3 LL_HRTIM_OUT_SetOutputSetSrc\n 05320 * SETx1R MSTCMP4 LL_HRTIM_OUT_SetOutputSetSrc\n 05321 * SETx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n 05322 * SETx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n 05323 * SETx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n 05324 * SETx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n 05325 * SETx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n 05326 * SETx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n 05327 * SETx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n 05328 * SETx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n 05329 * SETx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n 05330 * SETx1R EXEVNT1 LL_HRTIM_OUT_SetOutputSetSrc\n 05331 * SETx1R EXEVNT2 LL_HRTIM_OUT_SetOutputSetSrc\n 05332 * SETx1R EXEVNT3 LL_HRTIM_OUT_SetOutputSetSrc\n 05333 * SETx1R EXEVNT4 LL_HRTIM_OUT_SetOutputSetSrc\n 05334 * SETx1R EXEVNT5 LL_HRTIM_OUT_SetOutputSetSrc\n 05335 * SETx1R EXEVNT6 LL_HRTIM_OUT_SetOutputSetSrc\n 05336 * SETx1R EXEVNT7 LL_HRTIM_OUT_SetOutputSetSrc\n 05337 * SETx1R EXEVNT8 LL_HRTIM_OUT_SetOutputSetSrc\n 05338 * SETx1R EXEVNT9 LL_HRTIM_OUT_SetOutputSetSrc\n 05339 * SETx1R EXEVNT10 LL_HRTIM_OUT_SetOutputSetSrc\n 05340 * SETx1R UPDATE LL_HRTIM_OUT_SetOutputSetSrc 05341 * @param HRTIMx High Resolution Timer instance 05342 * @param Output This parameter can be one of the following values: 05343 * @arg @ref LL_HRTIM_OUTPUT_TA1 05344 * @arg @ref LL_HRTIM_OUTPUT_TA2 05345 * @arg @ref LL_HRTIM_OUTPUT_TB1 05346 * @arg @ref LL_HRTIM_OUTPUT_TB2 05347 * @arg @ref LL_HRTIM_OUTPUT_TC1 05348 * @arg @ref LL_HRTIM_OUTPUT_TC2 05349 * @arg @ref LL_HRTIM_OUTPUT_TD1 05350 * @arg @ref LL_HRTIM_OUTPUT_TD2 05351 * @arg @ref LL_HRTIM_OUTPUT_TE1 05352 * @arg @ref LL_HRTIM_OUTPUT_TE2 05353 * @param SetSrc This parameter can be a combination of the following values: 05354 * @arg @ref LL_HRTIM_CROSSBAR_NONE 05355 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC 05356 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER 05357 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 05358 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 05359 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 05360 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 05361 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER 05362 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 05363 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 05364 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 05365 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 05366 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 05367 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 05368 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 05369 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 05370 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 05371 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 05372 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 05373 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 05374 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 05375 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 05376 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 05377 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 05378 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 05379 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 05380 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 05381 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 05382 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 05383 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 05384 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 05385 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE 05386 * @retval None 05387 */ 05388 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc) 05389 { 05390 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05391 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + 05392 REG_OFFSET_TAB_SETxR[iOutput])); 05393 WRITE_REG(*pReg, SetSrc); 05394 } 05395 05396 /** 05397 * @brief Get the timer output set source. 05398 * @rmtoll SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n 05399 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n 05400 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n 05401 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n 05402 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n 05403 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n 05404 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n 05405 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n 05406 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n 05407 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n 05408 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n 05409 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n 05410 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n 05411 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n 05412 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n 05413 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n 05414 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n 05415 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n 05416 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n 05417 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n 05418 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n 05419 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n 05420 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n 05421 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n 05422 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n 05423 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n 05424 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n 05425 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n 05426 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n 05427 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n 05428 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n 05429 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc\n 05430 * SETx1R SST LL_HRTIM_OUT_GetOutputSetSrc\n 05431 * SETx1R RESYNC LL_HRTIM_OUT_GetOutputSetSrc\n 05432 * SETx1R PER LL_HRTIM_OUT_GetOutputSetSrc\n 05433 * SETx1R CMP1 LL_HRTIM_OUT_GetOutputSetSrc\n 05434 * SETx1R CMP2 LL_HRTIM_OUT_GetOutputSetSrc\n 05435 * SETx1R CMP3 LL_HRTIM_OUT_GetOutputSetSrc\n 05436 * SETx1R CMP4 LL_HRTIM_OUT_GetOutputSetSrc\n 05437 * SETx1R MSTPER LL_HRTIM_OUT_GetOutputSetSrc\n 05438 * SETx1R MSTCMP1 LL_HRTIM_OUT_GetOutputSetSrc\n 05439 * SETx1R MSTCMP2 LL_HRTIM_OUT_GetOutputSetSrc\n 05440 * SETx1R MSTCMP3 LL_HRTIM_OUT_GetOutputSetSrc\n 05441 * SETx1R MSTCMP4 LL_HRTIM_OUT_GetOutputSetSrc\n 05442 * SETx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n 05443 * SETx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n 05444 * SETx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n 05445 * SETx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n 05446 * SETx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n 05447 * SETx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n 05448 * SETx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n 05449 * SETx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n 05450 * SETx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n 05451 * SETx1R EXEVNT1 LL_HRTIM_OUT_GetOutputSetSrc\n 05452 * SETx1R EXEVNT2 LL_HRTIM_OUT_GetOutputSetSrc\n 05453 * SETx1R EXEVNT3 LL_HRTIM_OUT_GetOutputSetSrc\n 05454 * SETx1R EXEVNT4 LL_HRTIM_OUT_GetOutputSetSrc\n 05455 * SETx1R EXEVNT5 LL_HRTIM_OUT_GetOutputSetSrc\n 05456 * SETx1R EXEVNT6 LL_HRTIM_OUT_GetOutputSetSrc\n 05457 * SETx1R EXEVNT7 LL_HRTIM_OUT_GetOutputSetSrc\n 05458 * SETx1R EXEVNT8 LL_HRTIM_OUT_GetOutputSetSrc\n 05459 * SETx1R EXEVNT9 LL_HRTIM_OUT_GetOutputSetSrc\n 05460 * SETx1R EXEVNT10 LL_HRTIM_OUT_GetOutputSetSrc\n 05461 * SETx1R UPDATE LL_HRTIM_OUT_GetOutputSetSrc 05462 * @param HRTIMx High Resolution Timer instance 05463 * @param Output This parameter can be one of the following values: 05464 * @arg @ref LL_HRTIM_OUTPUT_TA1 05465 * @arg @ref LL_HRTIM_OUTPUT_TA2 05466 * @arg @ref LL_HRTIM_OUTPUT_TB1 05467 * @arg @ref LL_HRTIM_OUTPUT_TB2 05468 * @arg @ref LL_HRTIM_OUTPUT_TC1 05469 * @arg @ref LL_HRTIM_OUTPUT_TC2 05470 * @arg @ref LL_HRTIM_OUTPUT_TD1 05471 * @arg @ref LL_HRTIM_OUTPUT_TD2 05472 * @arg @ref LL_HRTIM_OUTPUT_TE1 05473 * @arg @ref LL_HRTIM_OUTPUT_TE2 05474 * @retval SetSrc This parameter can be a combination of the following values: 05475 * @arg @ref LL_HRTIM_CROSSBAR_NONE 05476 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC 05477 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER 05478 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 05479 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 05480 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 05481 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 05482 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER 05483 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 05484 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 05485 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 05486 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 05487 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 05488 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 05489 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 05490 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 05491 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 05492 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 05493 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 05494 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 05495 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 05496 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 05497 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 05498 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 05499 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 05500 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 05501 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 05502 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 05503 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 05504 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 05505 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 05506 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE 05507 */ 05508 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) 05509 { 05510 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05511 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + 05512 REG_OFFSET_TAB_SETxR[iOutput])); 05513 return (uint32_t) READ_REG(*pReg); 05514 } 05515 05516 /** 05517 * @brief Set the timer output reset source. 05518 * @rmtoll RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n 05519 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n 05520 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n 05521 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n 05522 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n 05523 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n 05524 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n 05525 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n 05526 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n 05527 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n 05528 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n 05529 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n 05530 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n 05531 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n 05532 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n 05533 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n 05534 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n 05535 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n 05536 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n 05537 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n 05538 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n 05539 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n 05540 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n 05541 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n 05542 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n 05543 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n 05544 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n 05545 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n 05546 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n 05547 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n 05548 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n 05549 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc\n 05550 * RSTx1R RST LL_HRTIM_OUT_SetOutputResetSrc\n 05551 * RSTx1R RESYNC LL_HRTIM_OUT_SetOutputResetSrc\n 05552 * RSTx1R PER LL_HRTIM_OUT_SetOutputResetSrc\n 05553 * RSTx1R CMP1 LL_HRTIM_OUT_SetOutputResetSrc\n 05554 * RSTx1R CMP2 LL_HRTIM_OUT_SetOutputResetSrc\n 05555 * RSTx1R CMP3 LL_HRTIM_OUT_SetOutputResetSrc\n 05556 * RSTx1R CMP4 LL_HRTIM_OUT_SetOutputResetSrc\n 05557 * RSTx1R MSTPER LL_HRTIM_OUT_SetOutputResetSrc\n 05558 * RSTx1R MSTCMP1 LL_HRTIM_OUT_SetOutputResetSrc\n 05559 * RSTx1R MSTCMP2 LL_HRTIM_OUT_SetOutputResetSrc\n 05560 * RSTx1R MSTCMP3 LL_HRTIM_OUT_SetOutputResetSrc\n 05561 * RSTx1R MSTCMP4 LL_HRTIM_OUT_SetOutputResetSrc\n 05562 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n 05563 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n 05564 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n 05565 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n 05566 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n 05567 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n 05568 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n 05569 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n 05570 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n 05571 * RSTx1R EXEVNT1 LL_HRTIM_OUT_SetOutputResetSrc\n 05572 * RSTx1R EXEVNT2 LL_HRTIM_OUT_SetOutputResetSrc\n 05573 * RSTx1R EXEVNT3 LL_HRTIM_OUT_SetOutputResetSrc\n 05574 * RSTx1R EXEVNT4 LL_HRTIM_OUT_SetOutputResetSrc\n 05575 * RSTx1R EXEVNT5 LL_HRTIM_OUT_SetOutputResetSrc\n 05576 * RSTx1R EXEVNT6 LL_HRTIM_OUT_SetOutputResetSrc\n 05577 * RSTx1R EXEVNT7 LL_HRTIM_OUT_SetOutputResetSrc\n 05578 * RSTx1R EXEVNT8 LL_HRTIM_OUT_SetOutputResetSrc\n 05579 * RSTx1R EXEVNT9 LL_HRTIM_OUT_SetOutputResetSrc\n 05580 * RSTx1R EXEVNT10 LL_HRTIM_OUT_SetOutputResetSrc\n 05581 * RSTx1R UPDATE LL_HRTIM_OUT_SetOutputResetSrc 05582 * @param HRTIMx High Resolution Timer instance 05583 * @param Output This parameter can be one of the following values: 05584 * @arg @ref LL_HRTIM_OUTPUT_TA1 05585 * @arg @ref LL_HRTIM_OUTPUT_TA2 05586 * @arg @ref LL_HRTIM_OUTPUT_TB1 05587 * @arg @ref LL_HRTIM_OUTPUT_TB2 05588 * @arg @ref LL_HRTIM_OUTPUT_TC1 05589 * @arg @ref LL_HRTIM_OUTPUT_TC2 05590 * @arg @ref LL_HRTIM_OUTPUT_TD1 05591 * @arg @ref LL_HRTIM_OUTPUT_TD2 05592 * @arg @ref LL_HRTIM_OUTPUT_TE1 05593 * @arg @ref LL_HRTIM_OUTPUT_TE2 05594 * @param ResetSrc This parameter can be a combination of the following values: 05595 * @arg @ref LL_HRTIM_CROSSBAR_NONE 05596 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC 05597 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER 05598 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 05599 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 05600 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 05601 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 05602 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER 05603 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 05604 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 05605 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 05606 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 05607 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 05608 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 05609 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 05610 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 05611 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 05612 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 05613 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 05614 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 05615 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 05616 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 05617 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 05618 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 05619 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 05620 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 05621 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 05622 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 05623 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 05624 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 05625 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 05626 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE 05627 * @retval None 05628 */ 05629 __STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc) 05630 { 05631 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05632 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + 05633 REG_OFFSET_TAB_SETxR[iOutput])); 05634 WRITE_REG(*pReg, ResetSrc); 05635 } 05636 05637 /** 05638 * @brief Get the timer output set source. 05639 * @rmtoll RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n 05640 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n 05641 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n 05642 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n 05643 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n 05644 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n 05645 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n 05646 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n 05647 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n 05648 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n 05649 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n 05650 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n 05651 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n 05652 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n 05653 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n 05654 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n 05655 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n 05656 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n 05657 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n 05658 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n 05659 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n 05660 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n 05661 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n 05662 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n 05663 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n 05664 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n 05665 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n 05666 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n 05667 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n 05668 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n 05669 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n 05670 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc\n 05671 * RSTx1R RST LL_HRTIM_OUT_GetOutputResetSrc\n 05672 * RSTx1R RESYNC LL_HRTIM_OUT_GetOutputResetSrc\n 05673 * RSTx1R PER LL_HRTIM_OUT_GetOutputResetSrc\n 05674 * RSTx1R CMP1 LL_HRTIM_OUT_GetOutputResetSrc\n 05675 * RSTx1R CMP2 LL_HRTIM_OUT_GetOutputResetSrc\n 05676 * RSTx1R CMP3 LL_HRTIM_OUT_GetOutputResetSrc\n 05677 * RSTx1R CMP4 LL_HRTIM_OUT_GetOutputResetSrc\n 05678 * RSTx1R MSTPER LL_HRTIM_OUT_GetOutputResetSrc\n 05679 * RSTx1R MSTCMP1 LL_HRTIM_OUT_GetOutputResetSrc\n 05680 * RSTx1R MSTCMP2 LL_HRTIM_OUT_GetOutputResetSrc\n 05681 * RSTx1R MSTCMP3 LL_HRTIM_OUT_GetOutputResetSrc\n 05682 * RSTx1R MSTCMP4 LL_HRTIM_OUT_GetOutputResetSrc\n 05683 * RSTx1R TIMEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n 05684 * RSTx1R TIMEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n 05685 * RSTx1R TIMEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n 05686 * RSTx1R TIMEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n 05687 * RSTx1R TIMEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n 05688 * RSTx1R TIMEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n 05689 * RSTx1R TIMEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n 05690 * RSTx1R TIMEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n 05691 * RSTx1R TIMEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n 05692 * RSTx1R EXEVNT1 LL_HRTIM_OUT_GetOutputResetSrc\n 05693 * RSTx1R EXEVNT2 LL_HRTIM_OUT_GetOutputResetSrc\n 05694 * RSTx1R EXEVNT3 LL_HRTIM_OUT_GetOutputResetSrc\n 05695 * RSTx1R EXEVNT4 LL_HRTIM_OUT_GetOutputResetSrc\n 05696 * RSTx1R EXEVNT5 LL_HRTIM_OUT_GetOutputResetSrc\n 05697 * RSTx1R EXEVNT6 LL_HRTIM_OUT_GetOutputResetSrc\n 05698 * RSTx1R EXEVNT7 LL_HRTIM_OUT_GetOutputResetSrc\n 05699 * RSTx1R EXEVNT8 LL_HRTIM_OUT_GetOutputResetSrc\n 05700 * RSTx1R EXEVNT9 LL_HRTIM_OUT_GetOutputResetSrc\n 05701 * RSTx1R EXEVNT10 LL_HRTIM_OUT_GetOutputResetSrc\n 05702 * RSTx1R UPDATE LL_HRTIM_OUT_GetOutputResetSrc 05703 * @param HRTIMx High Resolution Timer instance 05704 * @param Output This parameter can be one of the following values: 05705 * @arg @ref LL_HRTIM_OUTPUT_TA1 05706 * @arg @ref LL_HRTIM_OUTPUT_TA2 05707 * @arg @ref LL_HRTIM_OUTPUT_TB1 05708 * @arg @ref LL_HRTIM_OUTPUT_TB2 05709 * @arg @ref LL_HRTIM_OUTPUT_TC1 05710 * @arg @ref LL_HRTIM_OUTPUT_TC2 05711 * @arg @ref LL_HRTIM_OUTPUT_TD1 05712 * @arg @ref LL_HRTIM_OUTPUT_TD2 05713 * @arg @ref LL_HRTIM_OUTPUT_TE1 05714 * @arg @ref LL_HRTIM_OUTPUT_TE2 05715 * @retval ResetSrc This parameter can be a combination of the following values: 05716 * @arg @ref LL_HRTIM_CROSSBAR_NONE 05717 * @arg @ref LL_HRTIM_CROSSBAR_RESYNC 05718 * @arg @ref LL_HRTIM_CROSSBAR_TIMPER 05719 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1 05720 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2 05721 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3 05722 * @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4 05723 * @arg @ref LL_HRTIM_CROSSBAR_MASTERPER 05724 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1 05725 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2 05726 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3 05727 * @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4 05728 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1 05729 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2 05730 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3 05731 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4 05732 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5 05733 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6 05734 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7 05735 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8 05736 * @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9 05737 * @arg @ref LL_HRTIM_CROSSBAR_EEV_1 05738 * @arg @ref LL_HRTIM_CROSSBAR_EEV_2 05739 * @arg @ref LL_HRTIM_CROSSBAR_EEV_3 05740 * @arg @ref LL_HRTIM_CROSSBAR_EEV_4 05741 * @arg @ref LL_HRTIM_CROSSBAR_EEV_5 05742 * @arg @ref LL_HRTIM_CROSSBAR_EEV_6 05743 * @arg @ref LL_HRTIM_CROSSBAR_EEV_7 05744 * @arg @ref LL_HRTIM_CROSSBAR_EEV_8 05745 * @arg @ref LL_HRTIM_CROSSBAR_EEV_9 05746 * @arg @ref LL_HRTIM_CROSSBAR_EEV_10 05747 * @arg @ref LL_HRTIM_CROSSBAR_UPDATE 05748 */ 05749 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output) 05750 { 05751 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05752 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) + 05753 REG_OFFSET_TAB_SETxR[iOutput])); 05754 return (uint32_t) READ_REG(*pReg); 05755 } 05756 05757 /** 05758 * @brief Configure a timer output. 05759 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_Config\n 05760 * OUTxR IDLEM1 LL_HRTIM_OUT_Config\n 05761 * OUTxR IDLES1 LL_HRTIM_OUT_Config\n 05762 * OUTxR FAULT1 LL_HRTIM_OUT_Config\n 05763 * OUTxR CHP1 LL_HRTIM_OUT_Config\n 05764 * OUTxR DIDL1 LL_HRTIM_OUT_Config\n 05765 * OUTxR POL2 LL_HRTIM_OUT_Config\n 05766 * OUTxR IDLEM2 LL_HRTIM_OUT_Config\n 05767 * OUTxR IDLES2 LL_HRTIM_OUT_Config\n 05768 * OUTxR FAULT2 LL_HRTIM_OUT_Config\n 05769 * OUTxR CHP2 LL_HRTIM_OUT_Config\n 05770 * OUTxR DIDL2 LL_HRTIM_OUT_Config 05771 * @param HRTIMx High Resolution Timer instance 05772 * @param Output This parameter can be one of the following values: 05773 * @arg @ref LL_HRTIM_OUTPUT_TA1 05774 * @arg @ref LL_HRTIM_OUTPUT_TA2 05775 * @arg @ref LL_HRTIM_OUTPUT_TB1 05776 * @arg @ref LL_HRTIM_OUTPUT_TB2 05777 * @arg @ref LL_HRTIM_OUTPUT_TC1 05778 * @arg @ref LL_HRTIM_OUTPUT_TC2 05779 * @arg @ref LL_HRTIM_OUTPUT_TD1 05780 * @arg @ref LL_HRTIM_OUTPUT_TD2 05781 * @arg @ref LL_HRTIM_OUTPUT_TE1 05782 * @arg @ref LL_HRTIM_OUTPUT_TE2 05783 * @param Configuration This parameter must be a combination of all the following values: 05784 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY 05785 * @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST 05786 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE 05787 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ 05788 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED 05789 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED 05790 * @retval None 05791 */ 05792 __STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration) 05793 { 05794 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05795 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 05796 REG_OFFSET_TAB_OUTxR[iOutput])); 05797 MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]), 05798 (Configuration << REG_SHIFT_TAB_OUTxR[iOutput])); 05799 } 05800 05801 /** 05802 * @brief Set the polarity of a timer output. 05803 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_SetPolarity\n 05804 * OUTxR POL2 LL_HRTIM_OUT_SetPolarity 05805 * @param HRTIMx High Resolution Timer instance 05806 * @param Output This parameter can be one of the following values: 05807 * @arg @ref LL_HRTIM_OUTPUT_TA1 05808 * @arg @ref LL_HRTIM_OUTPUT_TA2 05809 * @arg @ref LL_HRTIM_OUTPUT_TB1 05810 * @arg @ref LL_HRTIM_OUTPUT_TB2 05811 * @arg @ref LL_HRTIM_OUTPUT_TC1 05812 * @arg @ref LL_HRTIM_OUTPUT_TC2 05813 * @arg @ref LL_HRTIM_OUTPUT_TD1 05814 * @arg @ref LL_HRTIM_OUTPUT_TD2 05815 * @arg @ref LL_HRTIM_OUTPUT_TE1 05816 * @arg @ref LL_HRTIM_OUTPUT_TE2 05817 * @param Polarity This parameter can be one of the following values: 05818 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY 05819 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY 05820 * @retval None 05821 */ 05822 __STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity) 05823 { 05824 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05825 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 05826 REG_OFFSET_TAB_OUTxR[iOutput])); 05827 MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput])); 05828 } 05829 05830 /** 05831 * @brief Get actual polarity of the timer output. 05832 * @rmtoll OUTxR POL1 LL_HRTIM_OUT_GetPolarity\n 05833 * OUTxR POL2 LL_HRTIM_OUT_GetPolarity 05834 * @param HRTIMx High Resolution Timer instance 05835 * @param Output This parameter can be one of the following values: 05836 * @arg @ref LL_HRTIM_OUTPUT_TA1 05837 * @arg @ref LL_HRTIM_OUTPUT_TA2 05838 * @arg @ref LL_HRTIM_OUTPUT_TB1 05839 * @arg @ref LL_HRTIM_OUTPUT_TB2 05840 * @arg @ref LL_HRTIM_OUTPUT_TC1 05841 * @arg @ref LL_HRTIM_OUTPUT_TC2 05842 * @arg @ref LL_HRTIM_OUTPUT_TD1 05843 * @arg @ref LL_HRTIM_OUTPUT_TD2 05844 * @arg @ref LL_HRTIM_OUTPUT_TE1 05845 * @arg @ref LL_HRTIM_OUTPUT_TE2 05846 * @retval Polarity This parameter can be one of the following values: 05847 * @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY 05848 * @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY 05849 */ 05850 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output) 05851 { 05852 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05853 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 05854 REG_OFFSET_TAB_OUTxR[iOutput])); 05855 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 05856 } 05857 05858 /** 05859 * @brief Set the output IDLE mode. 05860 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_SetIdleMode\n 05861 * OUTxR IDLEM2 LL_HRTIM_OUT_SetIdleMode 05862 * @note This function must not be called when the burst mode is active 05863 * @param HRTIMx High Resolution Timer instance 05864 * @param Output This parameter can be one of the following values: 05865 * @arg @ref LL_HRTIM_OUTPUT_TA1 05866 * @arg @ref LL_HRTIM_OUTPUT_TA2 05867 * @arg @ref LL_HRTIM_OUTPUT_TB1 05868 * @arg @ref LL_HRTIM_OUTPUT_TB2 05869 * @arg @ref LL_HRTIM_OUTPUT_TC1 05870 * @arg @ref LL_HRTIM_OUTPUT_TC2 05871 * @arg @ref LL_HRTIM_OUTPUT_TD1 05872 * @arg @ref LL_HRTIM_OUTPUT_TD2 05873 * @arg @ref LL_HRTIM_OUTPUT_TE1 05874 * @arg @ref LL_HRTIM_OUTPUT_TE2 05875 * @param IdleMode This parameter can be one of the following values: 05876 * @arg @ref LL_HRTIM_OUT_NO_IDLE 05877 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST 05878 * @retval None 05879 */ 05880 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode) 05881 { 05882 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05883 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 05884 REG_OFFSET_TAB_OUTxR[iOutput])); 05885 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput]))); 05886 } 05887 05888 /** 05889 * @brief Get actual output IDLE mode. 05890 * @rmtoll OUTxR IDLEM1 LL_HRTIM_OUT_GetIdleMode\n 05891 * OUTxR IDLEM2 LL_HRTIM_OUT_GetIdleMode 05892 * @param HRTIMx High Resolution Timer instance 05893 * @param Output This parameter can be one of the following values: 05894 * @arg @ref LL_HRTIM_OUTPUT_TA1 05895 * @arg @ref LL_HRTIM_OUTPUT_TA2 05896 * @arg @ref LL_HRTIM_OUTPUT_TB1 05897 * @arg @ref LL_HRTIM_OUTPUT_TB2 05898 * @arg @ref LL_HRTIM_OUTPUT_TC1 05899 * @arg @ref LL_HRTIM_OUTPUT_TC2 05900 * @arg @ref LL_HRTIM_OUTPUT_TD1 05901 * @arg @ref LL_HRTIM_OUTPUT_TD2 05902 * @arg @ref LL_HRTIM_OUTPUT_TE1 05903 * @arg @ref LL_HRTIM_OUTPUT_TE2 05904 * @retval IdleMode This parameter can be one of the following values: 05905 * @arg @ref LL_HRTIM_OUT_NO_IDLE 05906 * @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST 05907 */ 05908 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) 05909 { 05910 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05911 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 05912 REG_OFFSET_TAB_OUTxR[iOutput])); 05913 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 05914 } 05915 05916 /** 05917 * @brief Set the output IDLE level. 05918 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_SetIdleLevel\n 05919 * OUTxR IDLES2 LL_HRTIM_OUT_SetIdleLevel 05920 * @note This function must be called prior enabling the timer. 05921 * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE. 05922 * @param HRTIMx High Resolution Timer instance 05923 * @param Output This parameter can be one of the following values: 05924 * @arg @ref LL_HRTIM_OUTPUT_TA1 05925 * @arg @ref LL_HRTIM_OUTPUT_TA2 05926 * @arg @ref LL_HRTIM_OUTPUT_TB1 05927 * @arg @ref LL_HRTIM_OUTPUT_TB2 05928 * @arg @ref LL_HRTIM_OUTPUT_TC1 05929 * @arg @ref LL_HRTIM_OUTPUT_TC2 05930 * @arg @ref LL_HRTIM_OUTPUT_TD1 05931 * @arg @ref LL_HRTIM_OUTPUT_TD2 05932 * @arg @ref LL_HRTIM_OUTPUT_TE1 05933 * @arg @ref LL_HRTIM_OUTPUT_TE2 05934 * @param IdleLevel This parameter can be one of the following values: 05935 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE 05936 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE 05937 * @retval None 05938 */ 05939 __STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel) 05940 { 05941 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05942 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 05943 REG_OFFSET_TAB_OUTxR[iOutput])); 05944 MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput])); 05945 } 05946 05947 /** 05948 * @brief Get actual output IDLE level. 05949 * @rmtoll OUTxR IDLES1 LL_HRTIM_OUT_GetIdleLevel\n 05950 * OUTxR IDLES2 LL_HRTIM_OUT_GetIdleLevel 05951 * @param HRTIMx High Resolution Timer instance 05952 * @param Output This parameter can be one of the following values: 05953 * @arg @ref LL_HRTIM_OUTPUT_TA1 05954 * @arg @ref LL_HRTIM_OUTPUT_TA2 05955 * @arg @ref LL_HRTIM_OUTPUT_TB1 05956 * @arg @ref LL_HRTIM_OUTPUT_TB2 05957 * @arg @ref LL_HRTIM_OUTPUT_TC1 05958 * @arg @ref LL_HRTIM_OUTPUT_TC2 05959 * @arg @ref LL_HRTIM_OUTPUT_TD1 05960 * @arg @ref LL_HRTIM_OUTPUT_TD2 05961 * @arg @ref LL_HRTIM_OUTPUT_TE1 05962 * @arg @ref LL_HRTIM_OUTPUT_TE2 05963 * @retval IdleLevel This parameter can be one of the following values: 05964 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE 05965 * @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE 05966 */ 05967 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) 05968 { 05969 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 05970 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 05971 REG_OFFSET_TAB_OUTxR[iOutput])); 05972 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 05973 } 05974 05975 /** 05976 * @brief Set the output FAULT state. 05977 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_SetFaultState\n 05978 * OUTxR FAULT2 LL_HRTIM_OUT_SetFaultState 05979 * @note This function must not called when the timer is enabled and a fault 05980 * channel is enabled at timer level. 05981 * @param HRTIMx High Resolution Timer instance 05982 * @param Output This parameter can be one of the following values: 05983 * @arg @ref LL_HRTIM_OUTPUT_TA1 05984 * @arg @ref LL_HRTIM_OUTPUT_TA2 05985 * @arg @ref LL_HRTIM_OUTPUT_TB1 05986 * @arg @ref LL_HRTIM_OUTPUT_TB2 05987 * @arg @ref LL_HRTIM_OUTPUT_TC1 05988 * @arg @ref LL_HRTIM_OUTPUT_TC2 05989 * @arg @ref LL_HRTIM_OUTPUT_TD1 05990 * @arg @ref LL_HRTIM_OUTPUT_TD2 05991 * @arg @ref LL_HRTIM_OUTPUT_TE1 05992 * @arg @ref LL_HRTIM_OUTPUT_TE2 05993 * @param FaultState This parameter can be one of the following values: 05994 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 05995 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE 05996 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE 05997 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ 05998 * @retval None 05999 */ 06000 __STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState) 06001 { 06002 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06003 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 06004 REG_OFFSET_TAB_OUTxR[iOutput])); 06005 MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput])); 06006 } 06007 06008 /** 06009 * @brief Get actual FAULT state. 06010 * @rmtoll OUTxR FAULT1 LL_HRTIM_OUT_GetFaultState\n 06011 * OUTxR FAULT2 LL_HRTIM_OUT_GetFaultState 06012 * @param HRTIMx High Resolution Timer instance 06013 * @param Output This parameter can be one of the following values: 06014 * @arg @ref LL_HRTIM_OUTPUT_TA1 06015 * @arg @ref LL_HRTIM_OUTPUT_TA2 06016 * @arg @ref LL_HRTIM_OUTPUT_TB1 06017 * @arg @ref LL_HRTIM_OUTPUT_TB2 06018 * @arg @ref LL_HRTIM_OUTPUT_TC1 06019 * @arg @ref LL_HRTIM_OUTPUT_TC2 06020 * @arg @ref LL_HRTIM_OUTPUT_TD1 06021 * @arg @ref LL_HRTIM_OUTPUT_TD2 06022 * @arg @ref LL_HRTIM_OUTPUT_TE1 06023 * @arg @ref LL_HRTIM_OUTPUT_TE2 06024 * @retval FaultState This parameter can be one of the following values: 06025 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 06026 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE 06027 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE 06028 * @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ 06029 */ 06030 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output) 06031 { 06032 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06033 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 06034 REG_OFFSET_TAB_OUTxR[iOutput])); 06035 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 06036 } 06037 06038 /** 06039 * @brief Set the output chopper mode. 06040 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_SetChopperMode\n 06041 * OUTxR CHP2 LL_HRTIM_OUT_SetChopperMode 06042 * @note This function must not called when the timer is enabled. 06043 * @param HRTIMx High Resolution Timer instance 06044 * @param Output This parameter can be one of the following values: 06045 * @arg @ref LL_HRTIM_OUTPUT_TA1 06046 * @arg @ref LL_HRTIM_OUTPUT_TA2 06047 * @arg @ref LL_HRTIM_OUTPUT_TB1 06048 * @arg @ref LL_HRTIM_OUTPUT_TB2 06049 * @arg @ref LL_HRTIM_OUTPUT_TC1 06050 * @arg @ref LL_HRTIM_OUTPUT_TC2 06051 * @arg @ref LL_HRTIM_OUTPUT_TD1 06052 * @arg @ref LL_HRTIM_OUTPUT_TD2 06053 * @arg @ref LL_HRTIM_OUTPUT_TE1 06054 * @arg @ref LL_HRTIM_OUTPUT_TE2 06055 * @param ChopperMode This parameter can be one of the following values: 06056 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED 06057 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED 06058 * @retval None 06059 */ 06060 __STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode) 06061 { 06062 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06063 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 06064 REG_OFFSET_TAB_OUTxR[iOutput])); 06065 MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput])); 06066 } 06067 06068 /** 06069 * @brief Get actual output chopper mode 06070 * @rmtoll OUTxR CHP1 LL_HRTIM_OUT_GetChopperMode\n 06071 * OUTxR CHP2 LL_HRTIM_OUT_GetChopperMode 06072 * @param HRTIMx High Resolution Timer instance 06073 * @param Output This parameter can be one of the following values: 06074 * @arg @ref LL_HRTIM_OUTPUT_TA1 06075 * @arg @ref LL_HRTIM_OUTPUT_TA2 06076 * @arg @ref LL_HRTIM_OUTPUT_TB1 06077 * @arg @ref LL_HRTIM_OUTPUT_TB2 06078 * @arg @ref LL_HRTIM_OUTPUT_TC1 06079 * @arg @ref LL_HRTIM_OUTPUT_TC2 06080 * @arg @ref LL_HRTIM_OUTPUT_TD1 06081 * @arg @ref LL_HRTIM_OUTPUT_TD2 06082 * @arg @ref LL_HRTIM_OUTPUT_TE1 06083 * @arg @ref LL_HRTIM_OUTPUT_TE2 06084 * @retval ChopperMode This parameter can be one of the following values: 06085 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED 06086 * @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED 06087 */ 06088 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) 06089 { 06090 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06091 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 06092 REG_OFFSET_TAB_OUTxR[iOutput])); 06093 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 06094 } 06095 06096 /** 06097 * @brief Set the output burst mode entry mode. 06098 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_SetBMEntryMode\n 06099 * OUTxR DIDL2 LL_HRTIM_OUT_SetBMEntryMode 06100 * @note This function must not called when the timer is enabled. 06101 * @param HRTIMx High Resolution Timer instance 06102 * @param Output This parameter can be one of the following values: 06103 * @arg @ref LL_HRTIM_OUTPUT_TA1 06104 * @arg @ref LL_HRTIM_OUTPUT_TA2 06105 * @arg @ref LL_HRTIM_OUTPUT_TB1 06106 * @arg @ref LL_HRTIM_OUTPUT_TB2 06107 * @arg @ref LL_HRTIM_OUTPUT_TC1 06108 * @arg @ref LL_HRTIM_OUTPUT_TC2 06109 * @arg @ref LL_HRTIM_OUTPUT_TD1 06110 * @arg @ref LL_HRTIM_OUTPUT_TD2 06111 * @arg @ref LL_HRTIM_OUTPUT_TE1 06112 * @arg @ref LL_HRTIM_OUTPUT_TE2 06113 * @param BMEntryMode This parameter can be one of the following values: 06114 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 06115 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED 06116 * @retval None 06117 */ 06118 __STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode) 06119 { 06120 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06121 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 06122 REG_OFFSET_TAB_OUTxR[iOutput])); 06123 MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput])); 06124 } 06125 06126 /** 06127 * @brief Get actual output burst mode entry mode. 06128 * @rmtoll OUTxR DIDL1 LL_HRTIM_OUT_GetBMEntryMode\n 06129 * OUTxR DIDL2 LL_HRTIM_OUT_GetBMEntryMode 06130 * @param HRTIMx High Resolution Timer instance 06131 * @param Output This parameter can be one of the following values: 06132 * @arg @ref LL_HRTIM_OUTPUT_TA1 06133 * @arg @ref LL_HRTIM_OUTPUT_TA2 06134 * @arg @ref LL_HRTIM_OUTPUT_TB1 06135 * @arg @ref LL_HRTIM_OUTPUT_TB2 06136 * @arg @ref LL_HRTIM_OUTPUT_TC1 06137 * @arg @ref LL_HRTIM_OUTPUT_TC2 06138 * @arg @ref LL_HRTIM_OUTPUT_TD1 06139 * @arg @ref LL_HRTIM_OUTPUT_TD2 06140 * @arg @ref LL_HRTIM_OUTPUT_TE1 06141 * @arg @ref LL_HRTIM_OUTPUT_TE2 06142 * @retval BMEntryMode This parameter can be one of the following values: 06143 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR 06144 * @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED 06145 */ 06146 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output) 06147 { 06148 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06149 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) + 06150 REG_OFFSET_TAB_OUTxR[iOutput])); 06151 return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]); 06152 } 06153 06154 /** 06155 * @brief Get the level (active or inactive) of the designated output when the 06156 * delayed protection was triggered. 06157 * @rmtoll TIMxISR O1SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus\n 06158 * TIMxISR O2SRSR LL_HRTIM_OUT_GetDLYPRTOutStatus 06159 * @param HRTIMx High Resolution Timer instance 06160 * @param Output This parameter can be one of the following values: 06161 * @arg @ref LL_HRTIM_OUTPUT_TA1 06162 * @arg @ref LL_HRTIM_OUTPUT_TA2 06163 * @arg @ref LL_HRTIM_OUTPUT_TB1 06164 * @arg @ref LL_HRTIM_OUTPUT_TB2 06165 * @arg @ref LL_HRTIM_OUTPUT_TC1 06166 * @arg @ref LL_HRTIM_OUTPUT_TC2 06167 * @arg @ref LL_HRTIM_OUTPUT_TD1 06168 * @arg @ref LL_HRTIM_OUTPUT_TD2 06169 * @arg @ref LL_HRTIM_OUTPUT_TE1 06170 * @arg @ref LL_HRTIM_OUTPUT_TE2 06171 * @retval OutputLevel This parameter can be one of the following values: 06172 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE 06173 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE 06174 */ 06175 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output) 06176 { 06177 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06178 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + 06179 REG_OFFSET_TAB_OUTxR[iOutput])); 06180 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> 06181 HRTIM_TIMISR_O1STAT_Pos); 06182 } 06183 06184 /** 06185 * @brief Force the timer output to its active or inactive level. 06186 * @rmtoll SETx1R SST LL_HRTIM_OUT_ForceLevel\n 06187 * RSTx1R SRT LL_HRTIM_OUT_ForceLevel\n 06188 * SETx2R SST LL_HRTIM_OUT_ForceLevel\n 06189 * RSTx2R SRT LL_HRTIM_OUT_ForceLevel 06190 * @param HRTIMx High Resolution Timer instance 06191 * @param Output This parameter can be one of the following values: 06192 * @arg @ref LL_HRTIM_OUTPUT_TA1 06193 * @arg @ref LL_HRTIM_OUTPUT_TA2 06194 * @arg @ref LL_HRTIM_OUTPUT_TB1 06195 * @arg @ref LL_HRTIM_OUTPUT_TB2 06196 * @arg @ref LL_HRTIM_OUTPUT_TC1 06197 * @arg @ref LL_HRTIM_OUTPUT_TC2 06198 * @arg @ref LL_HRTIM_OUTPUT_TD1 06199 * @arg @ref LL_HRTIM_OUTPUT_TD2 06200 * @arg @ref LL_HRTIM_OUTPUT_TE1 06201 * @arg @ref LL_HRTIM_OUTPUT_TE2 06202 * @param OutputLevel This parameter can be one of the following values: 06203 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE 06204 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE 06205 * @retval None 06206 */ 06207 __STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel) 06208 { 06209 const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] = 06210 { 06211 0x04U, /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE */ 06212 0x00U /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE */ 06213 }; 06214 06215 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06216 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) + 06217 REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel])); 06218 SET_BIT(*pReg, HRTIM_SET1R_SST); 06219 } 06220 06221 /** 06222 * @brief Get actual output level, before the output stage (chopper, polarity). 06223 * @rmtoll TIMxISR O1CPY LL_HRTIM_OUT_GetLevel\n 06224 * TIMxISR O2CPY LL_HRTIM_OUT_GetLevel 06225 * @param HRTIMx High Resolution Timer instance 06226 * @param Output This parameter can be one of the following values: 06227 * @arg @ref LL_HRTIM_OUTPUT_TA1 06228 * @arg @ref LL_HRTIM_OUTPUT_TA2 06229 * @arg @ref LL_HRTIM_OUTPUT_TB1 06230 * @arg @ref LL_HRTIM_OUTPUT_TB2 06231 * @arg @ref LL_HRTIM_OUTPUT_TC1 06232 * @arg @ref LL_HRTIM_OUTPUT_TC2 06233 * @arg @ref LL_HRTIM_OUTPUT_TD1 06234 * @arg @ref LL_HRTIM_OUTPUT_TD2 06235 * @arg @ref LL_HRTIM_OUTPUT_TE1 06236 * @arg @ref LL_HRTIM_OUTPUT_TE2 06237 * @retval OutputLevel This parameter can be one of the following values: 06238 * @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE 06239 * @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE 06240 */ 06241 __STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output) 06242 { 06243 uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1)); 06244 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) + 06245 REG_OFFSET_TAB_OUTxR[iOutput])); 06246 return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >> 06247 HRTIM_TIMISR_O1CPY_Pos); 06248 } 06249 06250 /** 06251 * @} 06252 */ 06253 06254 /** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management 06255 * @{ 06256 */ 06257 06258 /** 06259 * @brief Configure external event conditioning. 06260 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_Config\n 06261 * EECR1 EE1POL LL_HRTIM_EE_Config\n 06262 * EECR1 EE1SNS LL_HRTIM_EE_Config\n 06263 * EECR1 EE1FAST LL_HRTIM_EE_Config\n 06264 * EECR1 EE2SRC LL_HRTIM_EE_Config\n 06265 * EECR1 EE2POL LL_HRTIM_EE_Config\n 06266 * EECR1 EE2SNS LL_HRTIM_EE_Config\n 06267 * EECR1 EE2FAST LL_HRTIM_EE_Config\n 06268 * EECR1 EE3SRC LL_HRTIM_EE_Config\n 06269 * EECR1 EE3POL LL_HRTIM_EE_Config\n 06270 * EECR1 EE3SNS LL_HRTIM_EE_Config\n 06271 * EECR1 EE3FAST LL_HRTIM_EE_Config\n 06272 * EECR1 EE4SRC LL_HRTIM_EE_Config\n 06273 * EECR1 EE4POL LL_HRTIM_EE_Config\n 06274 * EECR1 EE4SNS LL_HRTIM_EE_Config\n 06275 * EECR1 EE4FAST LL_HRTIM_EE_Config\n 06276 * EECR1 EE5SRC LL_HRTIM_EE_Config\n 06277 * EECR1 EE5POL LL_HRTIM_EE_Config\n 06278 * EECR1 EE5SNS LL_HRTIM_EE_Config\n 06279 * EECR1 EE5FAST LL_HRTIM_EE_Config\n 06280 * EECR2 EE6SRC LL_HRTIM_EE_Config\n 06281 * EECR2 EE6POL LL_HRTIM_EE_Config\n 06282 * EECR2 EE6SNS LL_HRTIM_EE_Config\n 06283 * EECR2 EE6FAST LL_HRTIM_EE_Config\n 06284 * EECR2 EE7SRC LL_HRTIM_EE_Config\n 06285 * EECR2 EE7POL LL_HRTIM_EE_Config\n 06286 * EECR2 EE7SNS LL_HRTIM_EE_Config\n 06287 * EECR2 EE7FAST LL_HRTIM_EE_Config\n 06288 * EECR2 EE8SRC LL_HRTIM_EE_Config\n 06289 * EECR2 EE8POL LL_HRTIM_EE_Config\n 06290 * EECR2 EE8SNS LL_HRTIM_EE_Config\n 06291 * EECR2 EE8FAST LL_HRTIM_EE_Config\n 06292 * EECR2 EE9SRC LL_HRTIM_EE_Config\n 06293 * EECR2 EE9POL LL_HRTIM_EE_Config\n 06294 * EECR2 EE9SNS LL_HRTIM_EE_Config\n 06295 * EECR2 EE9FAST LL_HRTIM_EE_Config\n 06296 * EECR2 EE10SRC LL_HRTIM_EE_Config\n 06297 * EECR2 EE10POL LL_HRTIM_EE_Config\n 06298 * EECR2 EE10SNS LL_HRTIM_EE_Config\n 06299 * EECR2 EE10FAST LL_HRTIM_EE_Config 06300 * @note This function must not be called when the timer counter is enabled. 06301 * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel. 06302 * @note Fast mode is available only for LL_HRTIM_EVENT_1..5. 06303 * @param HRTIMx High Resolution Timer instance 06304 * @param Event This parameter can be one of the following values: 06305 * @arg @ref LL_HRTIM_EVENT_1 06306 * @arg @ref LL_HRTIM_EVENT_2 06307 * @arg @ref LL_HRTIM_EVENT_3 06308 * @arg @ref LL_HRTIM_EVENT_4 06309 * @arg @ref LL_HRTIM_EVENT_5 06310 * @arg @ref LL_HRTIM_EVENT_6 06311 * @arg @ref LL_HRTIM_EVENT_7 06312 * @arg @ref LL_HRTIM_EVENT_8 06313 * @arg @ref LL_HRTIM_EVENT_9 06314 * @arg @ref LL_HRTIM_EVENT_10 06315 * @param Configuration This parameter must be a combination of all the following values: 06316 * @arg External event source 1 or External event source 2 or External event source 3 or External event source 4 06317 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW 06318 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES 06319 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE 06320 * @retval None 06321 */ 06322 __STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration) 06323 { 06324 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06325 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06326 REG_OFFSET_TAB_EECR[iEvent])); 06327 MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]), 06328 (Configuration << REG_SHIFT_TAB_EExSRC[iEvent])); 06329 } 06330 06331 /** 06332 * @brief Set the external event source. 06333 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_SetSrc\n 06334 * EECR1 EE2SRC LL_HRTIM_EE_SetSrc\n 06335 * EECR1 EE3SRC LL_HRTIM_EE_SetSrc\n 06336 * EECR1 EE4SRC LL_HRTIM_EE_SetSrc\n 06337 * EECR1 EE5SRC LL_HRTIM_EE_SetSrc\n 06338 * EECR2 EE6SRC LL_HRTIM_EE_SetSrc\n 06339 * EECR2 EE7SRC LL_HRTIM_EE_SetSrc\n 06340 * EECR2 EE8SRC LL_HRTIM_EE_SetSrc\n 06341 * EECR2 EE9SRC LL_HRTIM_EE_SetSrc\n 06342 * EECR2 EE10SRC LL_HRTIM_EE_SetSrc 06343 * @param HRTIMx High Resolution Timer instance 06344 * @param Event This parameter can be one of the following values: 06345 * @arg @ref LL_HRTIM_EVENT_1 06346 * @arg @ref LL_HRTIM_EVENT_2 06347 * @arg @ref LL_HRTIM_EVENT_3 06348 * @arg @ref LL_HRTIM_EVENT_4 06349 * @arg @ref LL_HRTIM_EVENT_5 06350 * @arg @ref LL_HRTIM_EVENT_6 06351 * @arg @ref LL_HRTIM_EVENT_7 06352 * @arg @ref LL_HRTIM_EVENT_8 06353 * @arg @ref LL_HRTIM_EVENT_9 06354 * @arg @ref LL_HRTIM_EVENT_10 06355 * @param Src This parameter can be one of the following values: 06356 * @arg External event source 1 06357 * @arg External event source 2 06358 * @arg External event source 3 06359 * @arg External event source 4 06360 * @retval None 06361 */ 06362 __STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src) 06363 { 06364 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06365 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06366 REG_OFFSET_TAB_EECR[iEvent])); 06367 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent])); 06368 } 06369 06370 /** 06371 * @brief Get actual external event source. 06372 * @rmtoll EECR1 EE1SRC LL_HRTIM_EE_GetSrc\n 06373 * EECR1 EE2SRC LL_HRTIM_EE_GetSrc\n 06374 * EECR1 EE3SRC LL_HRTIM_EE_GetSrc\n 06375 * EECR1 EE4SRC LL_HRTIM_EE_GetSrc\n 06376 * EECR1 EE5SRC LL_HRTIM_EE_GetSrc\n 06377 * EECR2 EE6SRC LL_HRTIM_EE_GetSrc\n 06378 * EECR2 EE7SRC LL_HRTIM_EE_GetSrc\n 06379 * EECR2 EE8SRC LL_HRTIM_EE_GetSrc\n 06380 * EECR2 EE9SRC LL_HRTIM_EE_GetSrc\n 06381 * EECR2 EE10SRC LL_HRTIM_EE_GetSrc 06382 * @param HRTIMx High Resolution Timer instance 06383 * @param Event This parameter can be one of the following values: 06384 * @arg @ref LL_HRTIM_EVENT_1 06385 * @arg @ref LL_HRTIM_EVENT_2 06386 * @arg @ref LL_HRTIM_EVENT_3 06387 * @arg @ref LL_HRTIM_EVENT_4 06388 * @arg @ref LL_HRTIM_EVENT_5 06389 * @arg @ref LL_HRTIM_EVENT_6 06390 * @arg @ref LL_HRTIM_EVENT_7 06391 * @arg @ref LL_HRTIM_EVENT_8 06392 * @arg @ref LL_HRTIM_EVENT_9 06393 * @arg @ref LL_HRTIM_EVENT_10 06394 * @retval EventSrc This parameter can be one of the following values: 06395 * @arg External event source 1 06396 * @arg External event source 2 06397 * @arg External event source 3 06398 * @arg External event source 4 06399 */ 06400 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event) 06401 { 06402 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06403 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06404 REG_OFFSET_TAB_EECR[iEvent])); 06405 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 06406 } 06407 06408 /** 06409 * @brief Set the polarity of an external event. 06410 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_SetPolarity\n 06411 * EECR1 EE2POL LL_HRTIM_EE_SetPolarity\n 06412 * EECR1 EE3POL LL_HRTIM_EE_SetPolarity\n 06413 * EECR1 EE4POL LL_HRTIM_EE_SetPolarity\n 06414 * EECR1 EE5POL LL_HRTIM_EE_SetPolarity\n 06415 * EECR2 EE6POL LL_HRTIM_EE_SetPolarity\n 06416 * EECR2 EE7POL LL_HRTIM_EE_SetPolarity\n 06417 * EECR2 EE8POL LL_HRTIM_EE_SetPolarity\n 06418 * EECR2 EE9POL LL_HRTIM_EE_SetPolarity\n 06419 * EECR2 EE10POL LL_HRTIM_EE_SetPolarity 06420 * @note This function must not be called when the timer counter is enabled. 06421 * @note Event polarity is only significant when event detection is level-sensitive. 06422 * @param HRTIMx High Resolution Timer instance 06423 * @param Event This parameter can be one of the following values: 06424 * @arg @ref LL_HRTIM_EVENT_1 06425 * @arg @ref LL_HRTIM_EVENT_2 06426 * @arg @ref LL_HRTIM_EVENT_3 06427 * @arg @ref LL_HRTIM_EVENT_4 06428 * @arg @ref LL_HRTIM_EVENT_5 06429 * @arg @ref LL_HRTIM_EVENT_6 06430 * @arg @ref LL_HRTIM_EVENT_7 06431 * @arg @ref LL_HRTIM_EVENT_8 06432 * @arg @ref LL_HRTIM_EVENT_9 06433 * @arg @ref LL_HRTIM_EVENT_10 06434 * @param Polarity This parameter can be one of the following values: 06435 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH 06436 * @arg @ref LL_HRTIM_EE_POLARITY_LOW 06437 * @retval None 06438 */ 06439 __STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity) 06440 { 06441 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06442 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06443 REG_OFFSET_TAB_EECR[iEvent])); 06444 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent])); 06445 } 06446 06447 /** 06448 * @brief Get actual polarity setting of an external event. 06449 * @rmtoll EECR1 EE1POL LL_HRTIM_EE_GetPolarity\n 06450 * EECR1 EE2POL LL_HRTIM_EE_GetPolarity\n 06451 * EECR1 EE3POL LL_HRTIM_EE_GetPolarity\n 06452 * EECR1 EE4POL LL_HRTIM_EE_GetPolarity\n 06453 * EECR1 EE5POL LL_HRTIM_EE_GetPolarity\n 06454 * EECR2 EE6POL LL_HRTIM_EE_GetPolarity\n 06455 * EECR2 EE7POL LL_HRTIM_EE_GetPolarity\n 06456 * EECR2 EE8POL LL_HRTIM_EE_GetPolarity\n 06457 * EECR2 EE9POL LL_HRTIM_EE_GetPolarity\n 06458 * EECR2 EE10POL LL_HRTIM_EE_GetPolarity 06459 * @param HRTIMx High Resolution Timer instance 06460 * @param Event This parameter can be one of the following values: 06461 * @arg @ref LL_HRTIM_EVENT_1 06462 * @arg @ref LL_HRTIM_EVENT_2 06463 * @arg @ref LL_HRTIM_EVENT_3 06464 * @arg @ref LL_HRTIM_EVENT_4 06465 * @arg @ref LL_HRTIM_EVENT_5 06466 * @arg @ref LL_HRTIM_EVENT_6 06467 * @arg @ref LL_HRTIM_EVENT_7 06468 * @arg @ref LL_HRTIM_EVENT_8 06469 * @arg @ref LL_HRTIM_EVENT_9 06470 * @arg @ref LL_HRTIM_EVENT_10 06471 * @retval Polarity This parameter can be one of the following values: 06472 * @arg @ref LL_HRTIM_EE_POLARITY_HIGH 06473 * @arg @ref LL_HRTIM_EE_POLARITY_LOW 06474 */ 06475 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event) 06476 { 06477 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06478 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06479 REG_OFFSET_TAB_EECR[iEvent])); 06480 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 06481 } 06482 06483 /** 06484 * @brief Set the sensitivity of an external event. 06485 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_SetSensitivity\n 06486 * EECR1 EE2SNS LL_HRTIM_EE_SetSensitivity\n 06487 * EECR1 EE3SNS LL_HRTIM_EE_SetSensitivity\n 06488 * EECR1 EE4SNS LL_HRTIM_EE_SetSensitivity\n 06489 * EECR1 EE5SNS LL_HRTIM_EE_SetSensitivity\n 06490 * EECR2 EE6SNS LL_HRTIM_EE_SetSensitivity\n 06491 * EECR2 EE7SNS LL_HRTIM_EE_SetSensitivity\n 06492 * EECR2 EE8SNS LL_HRTIM_EE_SetSensitivity\n 06493 * EECR2 EE9SNS LL_HRTIM_EE_SetSensitivity\n 06494 * EECR2 EE10SNS LL_HRTIM_EE_SetSensitivity 06495 * @param HRTIMx High Resolution Timer instance 06496 * @param Event This parameter can be one of the following values: 06497 * @arg @ref LL_HRTIM_EVENT_1 06498 * @arg @ref LL_HRTIM_EVENT_2 06499 * @arg @ref LL_HRTIM_EVENT_3 06500 * @arg @ref LL_HRTIM_EVENT_4 06501 * @arg @ref LL_HRTIM_EVENT_5 06502 * @arg @ref LL_HRTIM_EVENT_6 06503 * @arg @ref LL_HRTIM_EVENT_7 06504 * @arg @ref LL_HRTIM_EVENT_8 06505 * @arg @ref LL_HRTIM_EVENT_9 06506 * @arg @ref LL_HRTIM_EVENT_10 06507 * @param Sensitivity This parameter can be one of the following values: 06508 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL 06509 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE 06510 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE 06511 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES 06512 * @retval None 06513 */ 06514 06515 __STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity) 06516 { 06517 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06518 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06519 REG_OFFSET_TAB_EECR[iEvent])); 06520 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent])); 06521 } 06522 06523 /** 06524 * @brief Get actual sensitivity setting of an external event. 06525 * @rmtoll EECR1 EE1SNS LL_HRTIM_EE_GetSensitivity\n 06526 * EECR1 EE2SNS LL_HRTIM_EE_GetSensitivity\n 06527 * EECR1 EE3SNS LL_HRTIM_EE_GetSensitivity\n 06528 * EECR1 EE4SNS LL_HRTIM_EE_GetSensitivity\n 06529 * EECR1 EE5SNS LL_HRTIM_EE_GetSensitivity\n 06530 * EECR2 EE6SNS LL_HRTIM_EE_GetSensitivity\n 06531 * EECR2 EE7SNS LL_HRTIM_EE_GetSensitivity\n 06532 * EECR2 EE8SNS LL_HRTIM_EE_GetSensitivity\n 06533 * EECR2 EE9SNS LL_HRTIM_EE_GetSensitivity\n 06534 * EECR2 EE10SNS LL_HRTIM_EE_GetSensitivity 06535 * @param HRTIMx High Resolution Timer instance 06536 * @param Event This parameter can be one of the following values: 06537 * @arg @ref LL_HRTIM_EVENT_1 06538 * @arg @ref LL_HRTIM_EVENT_2 06539 * @arg @ref LL_HRTIM_EVENT_3 06540 * @arg @ref LL_HRTIM_EVENT_4 06541 * @arg @ref LL_HRTIM_EVENT_5 06542 * @arg @ref LL_HRTIM_EVENT_6 06543 * @arg @ref LL_HRTIM_EVENT_7 06544 * @arg @ref LL_HRTIM_EVENT_8 06545 * @arg @ref LL_HRTIM_EVENT_9 06546 * @arg @ref LL_HRTIM_EVENT_10 06547 * @retval Polarity This parameter can be one of the following values: 06548 * @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL 06549 * @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE 06550 * @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE 06551 * @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES 06552 */ 06553 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event) 06554 { 06555 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06556 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06557 REG_OFFSET_TAB_EECR[iEvent])); 06558 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 06559 } 06560 06561 /** 06562 * @brief Set the fast mode of an external event. 06563 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_SetFastMode\n 06564 * EECR1 EE2FAST LL_HRTIM_EE_SetFastMode\n 06565 * EECR1 EE3FAST LL_HRTIM_EE_SetFastMode\n 06566 * EECR1 EE4FAST LL_HRTIM_EE_SetFastMode\n 06567 * EECR1 EE5FAST LL_HRTIM_EE_SetFastMode\n 06568 * EECR2 EE6FAST LL_HRTIM_EE_SetFastMode\n 06569 * EECR2 EE7FAST LL_HRTIM_EE_SetFastMode\n 06570 * EECR2 EE8FAST LL_HRTIM_EE_SetFastMode\n 06571 * EECR2 EE9FAST LL_HRTIM_EE_SetFastMode\n 06572 * EECR2 EE10FAST LL_HRTIM_EE_SetFastMode 06573 * @note This function must not be called when the timer counter is enabled. 06574 * @param HRTIMx High Resolution Timer instance 06575 * @param Event This parameter can be one of the following values: 06576 * @arg @ref LL_HRTIM_EVENT_1 06577 * @arg @ref LL_HRTIM_EVENT_2 06578 * @arg @ref LL_HRTIM_EVENT_3 06579 * @arg @ref LL_HRTIM_EVENT_4 06580 * @arg @ref LL_HRTIM_EVENT_5 06581 * @param FastMode This parameter can be one of the following values: 06582 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE 06583 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE 06584 * @retval None 06585 */ 06586 __STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode) 06587 { 06588 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06589 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06590 REG_OFFSET_TAB_EECR[iEvent])); 06591 MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent])); 06592 } 06593 06594 /** 06595 * @brief Get actual fast mode setting of an external event. 06596 * @rmtoll EECR1 EE1FAST LL_HRTIM_EE_GetFastMode\n 06597 * EECR1 EE2FAST LL_HRTIM_EE_GetFastMode\n 06598 * EECR1 EE3FAST LL_HRTIM_EE_GetFastMode\n 06599 * EECR1 EE4FAST LL_HRTIM_EE_GetFastMode\n 06600 * EECR1 EE5FAST LL_HRTIM_EE_GetFastMode\n 06601 * EECR2 EE6FAST LL_HRTIM_EE_GetFastMode\n 06602 * EECR2 EE7FAST LL_HRTIM_EE_GetFastMode\n 06603 * EECR2 EE8FAST LL_HRTIM_EE_GetFastMode\n 06604 * EECR2 EE9FAST LL_HRTIM_EE_GetFastMode\n 06605 * EECR2 EE10FAST LL_HRTIM_EE_GetFastMode 06606 * @param HRTIMx High Resolution Timer instance 06607 * @param Event This parameter can be one of the following values: 06608 * @arg @ref LL_HRTIM_EVENT_1 06609 * @arg @ref LL_HRTIM_EVENT_2 06610 * @arg @ref LL_HRTIM_EVENT_3 06611 * @arg @ref LL_HRTIM_EVENT_4 06612 * @arg @ref LL_HRTIM_EVENT_5 06613 * @retval FastMode This parameter can be one of the following values: 06614 * @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE 06615 * @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE 06616 */ 06617 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event) 06618 { 06619 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06620 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) + 06621 REG_OFFSET_TAB_EECR[iEvent])); 06622 return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 06623 } 06624 06625 /** 06626 * @brief Set the digital noise filter of a external event. 06627 * @rmtoll EECR3 EE6F LL_HRTIM_EE_SetFilter\n 06628 * EECR3 EE7F LL_HRTIM_EE_SetFilter\n 06629 * EECR3 EE8F LL_HRTIM_EE_SetFilter\n 06630 * EECR3 EE9F LL_HRTIM_EE_SetFilter\n 06631 * EECR3 EE10F LL_HRTIM_EE_SetFilter 06632 * @param HRTIMx High Resolution Timer instance 06633 * @param Event This parameter can be one of the following values: 06634 * @arg @ref LL_HRTIM_EVENT_6 06635 * @arg @ref LL_HRTIM_EVENT_7 06636 * @arg @ref LL_HRTIM_EVENT_8 06637 * @arg @ref LL_HRTIM_EVENT_9 06638 * @arg @ref LL_HRTIM_EVENT_10 06639 * @param Filter This parameter can be one of the following values: 06640 * @arg @ref LL_HRTIM_EE_FILTER_NONE 06641 * @arg @ref LL_HRTIM_EE_FILTER_1 06642 * @arg @ref LL_HRTIM_EE_FILTER_2 06643 * @arg @ref LL_HRTIM_EE_FILTER_3 06644 * @arg @ref LL_HRTIM_EE_FILTER_4 06645 * @arg @ref LL_HRTIM_EE_FILTER_5 06646 * @arg @ref LL_HRTIM_EE_FILTER_6 06647 * @arg @ref LL_HRTIM_EE_FILTER_7 06648 * @arg @ref LL_HRTIM_EE_FILTER_8 06649 * @arg @ref LL_HRTIM_EE_FILTER_9 06650 * @arg @ref LL_HRTIM_EE_FILTER_10 06651 * @arg @ref LL_HRTIM_EE_FILTER_11 06652 * @arg @ref LL_HRTIM_EE_FILTER_12 06653 * @arg @ref LL_HRTIM_EE_FILTER_13 06654 * @arg @ref LL_HRTIM_EE_FILTER_14 06655 * @arg @ref LL_HRTIM_EE_FILTER_15 06656 * @retval None 06657 */ 06658 __STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter) 06659 { 06660 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1)); 06661 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]), 06662 (Filter << REG_SHIFT_TAB_EExSRC[iEvent])); 06663 } 06664 06665 /** 06666 * @brief Get actual digital noise filter setting of a external event. 06667 * @rmtoll EECR3 EE6F LL_HRTIM_EE_GetFilter\n 06668 * EECR3 EE7F LL_HRTIM_EE_GetFilter\n 06669 * EECR3 EE8F LL_HRTIM_EE_GetFilter\n 06670 * EECR3 EE9F LL_HRTIM_EE_GetFilter\n 06671 * EECR3 EE10F LL_HRTIM_EE_GetFilter 06672 * @param HRTIMx High Resolution Timer instance 06673 * @param Event This parameter can be one of the following values: 06674 * @arg @ref LL_HRTIM_EVENT_6 06675 * @arg @ref LL_HRTIM_EVENT_7 06676 * @arg @ref LL_HRTIM_EVENT_8 06677 * @arg @ref LL_HRTIM_EVENT_9 06678 * @arg @ref LL_HRTIM_EVENT_10 06679 * @retval Filter This parameter can be one of the following values: 06680 * @arg @ref LL_HRTIM_EE_FILTER_NONE 06681 * @arg @ref LL_HRTIM_EE_FILTER_1 06682 * @arg @ref LL_HRTIM_EE_FILTER_2 06683 * @arg @ref LL_HRTIM_EE_FILTER_3 06684 * @arg @ref LL_HRTIM_EE_FILTER_4 06685 * @arg @ref LL_HRTIM_EE_FILTER_5 06686 * @arg @ref LL_HRTIM_EE_FILTER_6 06687 * @arg @ref LL_HRTIM_EE_FILTER_7 06688 * @arg @ref LL_HRTIM_EE_FILTER_8 06689 * @arg @ref LL_HRTIM_EE_FILTER_9 06690 * @arg @ref LL_HRTIM_EE_FILTER_10 06691 * @arg @ref LL_HRTIM_EE_FILTER_11 06692 * @arg @ref LL_HRTIM_EE_FILTER_12 06693 * @arg @ref LL_HRTIM_EE_FILTER_13 06694 * @arg @ref LL_HRTIM_EE_FILTER_14 06695 * @arg @ref LL_HRTIM_EE_FILTER_15 06696 */ 06697 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event) 06698 { 06699 uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6)); 06700 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, 06701 (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >> REG_SHIFT_TAB_EExSRC[iEvent]); 06702 } 06703 06704 /** 06705 * @brief Set the external event prescaler. 06706 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_SetPrescaler 06707 * @param HRTIMx High Resolution Timer instance 06708 * @param Prescaler This parameter can be one of the following values: 06709 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1 06710 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2 06711 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4 06712 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8 06713 * @retval None 06714 */ 06715 06716 __STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler) 06717 { 06718 MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler); 06719 } 06720 06721 /** 06722 * @brief Get actual external event prescaler setting. 06723 * @rmtoll EECR3 EEVSD LL_HRTIM_EE_GetPrescaler 06724 * @param HRTIMx High Resolution Timer instance 06725 * @retval Prescaler This parameter can be one of the following values: 06726 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV1 06727 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV2 06728 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV4 06729 * @arg @ref LL_HRTIM_EE_PRESCALER_DIV8 06730 */ 06731 06732 __STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx) 06733 { 06734 return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD)); 06735 } 06736 06737 /** 06738 * @} 06739 */ 06740 06741 /** @defgroup HRTIM_LL_EF_Fault_management Fault_management 06742 * @{ 06743 */ 06744 /** 06745 * @brief Configure fault signal conditioning Polarity and Source. 06746 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_Config\n 06747 * FLTINR1 FLT1SRC LL_HRTIM_FLT_Config\n 06748 * FLTINR1 FLT2P LL_HRTIM_FLT_Config\n 06749 * FLTINR1 FLT2SRC LL_HRTIM_FLT_Config\n 06750 * FLTINR1 FLT3P LL_HRTIM_FLT_Config\n 06751 * FLTINR1 FLT3SRC LL_HRTIM_FLT_Config\n 06752 * FLTINR1 FLT4P LL_HRTIM_FLT_Config\n 06753 * FLTINR1 FLT4SRC LL_HRTIM_FLT_Config\n 06754 * FLTINR2 FLT5P LL_HRTIM_FLT_Config\n 06755 * FLTINR2 FLT5SRC LL_HRTIM_FLT_Config 06756 * @note This function must not be called when the fault channel is enabled. 06757 * @param HRTIMx High Resolution Timer instance 06758 * @param Fault This parameter can be one of the following values: 06759 * @arg @ref LL_HRTIM_FAULT_1 06760 * @arg @ref LL_HRTIM_FAULT_2 06761 * @arg @ref LL_HRTIM_FAULT_3 06762 * @arg @ref LL_HRTIM_FAULT_4 06763 * @arg @ref LL_HRTIM_FAULT_5 06764 * @param Configuration This parameter must be a combination of all the following values: 06765 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_INTERNAL 06766 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH 06767 * @retval None 06768 */ 06769 __STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration) 06770 { 06771 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 06772 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 06773 REG_OFFSET_TAB_FLTINR[iFault])); 06774 MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]), 06775 (Configuration << REG_SHIFT_TAB_FLTxE[iFault])); 06776 } 06777 06778 /** 06779 * @brief Set the source of a fault signal. 06780 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_SetSrc\n 06781 * FLTINR1 FLT2SRC LL_HRTIM_FLT_SetSrc\n 06782 * FLTINR1 FLT3SRC LL_HRTIM_FLT_SetSrc\n 06783 * FLTINR1 FLT4SRC LL_HRTIM_FLT_SetSrc\n 06784 * FLTINR2 FLT5SRC LL_HRTIM_FLT_SetSrc 06785 * @note This function must not be called when the fault channel is enabled. 06786 * @param HRTIMx High Resolution Timer instance 06787 * @param Fault This parameter can be one of the following values: 06788 * @arg @ref LL_HRTIM_FAULT_1 06789 * @arg @ref LL_HRTIM_FAULT_2 06790 * @arg @ref LL_HRTIM_FAULT_3 06791 * @arg @ref LL_HRTIM_FAULT_4 06792 * @arg @ref LL_HRTIM_FAULT_5 06793 * @param Src This parameter can be one of the following values: 06794 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT 06795 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL 06796 * @retval None 06797 */ 06798 __STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src) 06799 { 06800 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 06801 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 06802 REG_OFFSET_TAB_FLTINR[iFault])); 06803 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault])); 06804 } 06805 06806 /** 06807 * @brief Get actual source of a fault signal. 06808 * @rmtoll FLTINR1 FLT1SRC LL_HRTIM_FLT_GetSrc\n 06809 * FLTINR1 FLT2SRC LL_HRTIM_FLT_GetSrc\n 06810 * FLTINR1 FLT3SRC LL_HRTIM_FLT_GetSrc\n 06811 * FLTINR1 FLT4SRC LL_HRTIM_FLT_GetSrc\n 06812 * FLTINR2 FLT5SRC LL_HRTIM_FLT_GetSrc 06813 * @param HRTIMx High Resolution Timer instance 06814 * @param Fault This parameter can be one of the following values: 06815 * @arg @ref LL_HRTIM_FAULT_1 06816 * @arg @ref LL_HRTIM_FAULT_2 06817 * @arg @ref LL_HRTIM_FAULT_3 06818 * @arg @ref LL_HRTIM_FAULT_4 06819 * @arg @ref LL_HRTIM_FAULT_5 06820 * @retval Source This parameter can be one of the following values: 06821 * @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT 06822 * @arg @ref LL_HRTIM_FLT_SRC_INTERNAL 06823 */ 06824 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 06825 { 06826 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 06827 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 06828 REG_OFFSET_TAB_FLTINR[iFault])); 06829 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); 06830 } 06831 06832 /** 06833 * @brief Set the polarity of a fault signal. 06834 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_SetPolarity\n 06835 * FLTINR1 FLT2P LL_HRTIM_FLT_SetPolarity\n 06836 * FLTINR1 FLT3P LL_HRTIM_FLT_SetPolarity\n 06837 * FLTINR1 FLT4P LL_HRTIM_FLT_SetPolarity\n 06838 * FLTINR2 FLT5P LL_HRTIM_FLT_SetPolarity 06839 * @note This function must not be called when the fault channel is enabled. 06840 * @param HRTIMx High Resolution Timer instance 06841 * @param Fault This parameter can be one of the following values: 06842 * @arg @ref LL_HRTIM_FAULT_1 06843 * @arg @ref LL_HRTIM_FAULT_2 06844 * @arg @ref LL_HRTIM_FAULT_3 06845 * @arg @ref LL_HRTIM_FAULT_4 06846 * @arg @ref LL_HRTIM_FAULT_5 06847 * @param Polarity This parameter can be one of the following values: 06848 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW 06849 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH 06850 * @retval None 06851 */ 06852 __STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity) 06853 { 06854 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 06855 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 06856 REG_OFFSET_TAB_FLTINR[iFault])); 06857 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault])); 06858 } 06859 06860 /** 06861 * @brief Get actual polarity of a fault signal. 06862 * @rmtoll FLTINR1 FLT1P LL_HRTIM_FLT_GetPolarity\n 06863 * FLTINR1 FLT2P LL_HRTIM_FLT_GetPolarity\n 06864 * FLTINR1 FLT3P LL_HRTIM_FLT_GetPolarity\n 06865 * FLTINR1 FLT4P LL_HRTIM_FLT_GetPolarity\n 06866 * FLTINR2 FLT5P LL_HRTIM_FLT_GetPolarity 06867 * @param HRTIMx High Resolution Timer instance 06868 * @param Fault This parameter can be one of the following values: 06869 * @arg @ref LL_HRTIM_FAULT_1 06870 * @arg @ref LL_HRTIM_FAULT_2 06871 * @arg @ref LL_HRTIM_FAULT_3 06872 * @arg @ref LL_HRTIM_FAULT_4 06873 * @arg @ref LL_HRTIM_FAULT_5 06874 * @retval Polarity This parameter can be one of the following values: 06875 * @arg @ref LL_HRTIM_FLT_POLARITY_LOW 06876 * @arg @ref LL_HRTIM_FLT_POLARITY_HIGH 06877 */ 06878 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 06879 { 06880 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 06881 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 06882 REG_OFFSET_TAB_FLTINR[iFault])); 06883 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); 06884 } 06885 06886 /** 06887 * @brief Set the digital noise filter of a fault signal. 06888 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_SetFilter\n 06889 * FLTINR1 FLT2F LL_HRTIM_FLT_SetFilter\n 06890 * FLTINR1 FLT3F LL_HRTIM_FLT_SetFilter\n 06891 * FLTINR1 FLT4F LL_HRTIM_FLT_SetFilter\n 06892 * FLTINR2 FLT5F LL_HRTIM_FLT_SetFilter 06893 * @note This function must not be called when the fault channel is enabled. 06894 * @param HRTIMx High Resolution Timer instance 06895 * @param Fault This parameter can be one of the following values: 06896 * @arg @ref LL_HRTIM_FAULT_1 06897 * @arg @ref LL_HRTIM_FAULT_2 06898 * @arg @ref LL_HRTIM_FAULT_3 06899 * @arg @ref LL_HRTIM_FAULT_4 06900 * @arg @ref LL_HRTIM_FAULT_5 06901 * @param Filter This parameter can be one of the following values: 06902 * @arg @ref LL_HRTIM_FLT_FILTER_NONE 06903 * @arg @ref LL_HRTIM_FLT_FILTER_1 06904 * @arg @ref LL_HRTIM_FLT_FILTER_2 06905 * @arg @ref LL_HRTIM_FLT_FILTER_3 06906 * @arg @ref LL_HRTIM_FLT_FILTER_4 06907 * @arg @ref LL_HRTIM_FLT_FILTER_5 06908 * @arg @ref LL_HRTIM_FLT_FILTER_6 06909 * @arg @ref LL_HRTIM_FLT_FILTER_7 06910 * @arg @ref LL_HRTIM_FLT_FILTER_8 06911 * @arg @ref LL_HRTIM_FLT_FILTER_9 06912 * @arg @ref LL_HRTIM_FLT_FILTER_10 06913 * @arg @ref LL_HRTIM_FLT_FILTER_11 06914 * @arg @ref LL_HRTIM_FLT_FILTER_12 06915 * @arg @ref LL_HRTIM_FLT_FILTER_13 06916 * @arg @ref LL_HRTIM_FLT_FILTER_14 06917 * @arg @ref LL_HRTIM_FLT_FILTER_15 06918 * @retval None 06919 */ 06920 __STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter) 06921 { 06922 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 06923 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 06924 REG_OFFSET_TAB_FLTINR[iFault])); 06925 MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault])); 06926 } 06927 06928 /** 06929 * @brief Get actual digital noise filter setting of a fault signal. 06930 * @rmtoll FLTINR1 FLT1F LL_HRTIM_FLT_GetFilter\n 06931 * FLTINR1 FLT2F LL_HRTIM_FLT_GetFilter\n 06932 * FLTINR1 FLT3F LL_HRTIM_FLT_GetFilter\n 06933 * FLTINR1 FLT4F LL_HRTIM_FLT_GetFilter\n 06934 * FLTINR2 FLT5F LL_HRTIM_FLT_GetFilter 06935 * @param HRTIMx High Resolution Timer instance 06936 * @param Fault This parameter can be one of the following values: 06937 * @arg @ref LL_HRTIM_FAULT_1 06938 * @arg @ref LL_HRTIM_FAULT_2 06939 * @arg @ref LL_HRTIM_FAULT_3 06940 * @arg @ref LL_HRTIM_FAULT_4 06941 * @arg @ref LL_HRTIM_FAULT_5 06942 * @retval Filter This parameter can be one of the following values: 06943 * @arg @ref LL_HRTIM_FLT_FILTER_NONE 06944 * @arg @ref LL_HRTIM_FLT_FILTER_1 06945 * @arg @ref LL_HRTIM_FLT_FILTER_2 06946 * @arg @ref LL_HRTIM_FLT_FILTER_3 06947 * @arg @ref LL_HRTIM_FLT_FILTER_4 06948 * @arg @ref LL_HRTIM_FLT_FILTER_5 06949 * @arg @ref LL_HRTIM_FLT_FILTER_6 06950 * @arg @ref LL_HRTIM_FLT_FILTER_7 06951 * @arg @ref LL_HRTIM_FLT_FILTER_8 06952 * @arg @ref LL_HRTIM_FLT_FILTER_9 06953 * @arg @ref LL_HRTIM_FLT_FILTER_10 06954 * @arg @ref LL_HRTIM_FLT_FILTER_11 06955 * @arg @ref LL_HRTIM_FLT_FILTER_12 06956 * @arg @ref LL_HRTIM_FLT_FILTER_13 06957 * @arg @ref LL_HRTIM_FLT_FILTER_14 06958 * @arg @ref LL_HRTIM_FLT_FILTER_15 06959 */ 06960 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 06961 { 06962 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 06963 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 06964 REG_OFFSET_TAB_FLTINR[iFault])); 06965 return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]); 06966 06967 } 06968 06969 /** 06970 * @brief Set the fault circuitry prescaler. 06971 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_SetPrescaler 06972 * @param HRTIMx High Resolution Timer instance 06973 * @param Prescaler This parameter can be one of the following values: 06974 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1 06975 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2 06976 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4 06977 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8 06978 * @retval None 06979 */ 06980 __STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler) 06981 { 06982 MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler); 06983 } 06984 06985 /** 06986 * @brief Get actual fault circuitry prescaler setting. 06987 * @rmtoll FLTINR2 FLTSD LL_HRTIM_FLT_GetPrescaler 06988 * @param HRTIMx High Resolution Timer instance 06989 * @retval Prescaler This parameter can be one of the following values: 06990 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1 06991 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2 06992 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4 06993 * @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8 06994 */ 06995 __STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx) 06996 { 06997 return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD)); 06998 } 06999 07000 /** 07001 * @brief Lock the fault signal conditioning settings. 07002 * @rmtoll FLTINR1 FLT1LCK LL_HRTIM_FLT_Lock\n 07003 * FLTINR1 FLT2LCK LL_HRTIM_FLT_Lock\n 07004 * FLTINR1 FLT3LCK LL_HRTIM_FLT_Lock\n 07005 * FLTINR1 FLT4LCK LL_HRTIM_FLT_Lock\n 07006 * FLTINR2 FLT5LCK LL_HRTIM_FLT_Lock 07007 * @param HRTIMx High Resolution Timer instance 07008 * @param Fault This parameter can be one of the following values: 07009 * @arg @ref LL_HRTIM_FAULT_1 07010 * @arg @ref LL_HRTIM_FAULT_2 07011 * @arg @ref LL_HRTIM_FAULT_3 07012 * @arg @ref LL_HRTIM_FAULT_4 07013 * @arg @ref LL_HRTIM_FAULT_5 07014 * @retval None 07015 */ 07016 __STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 07017 { 07018 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 07019 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 07020 REG_OFFSET_TAB_FLTINR[iFault])); 07021 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault])); 07022 } 07023 07024 /** 07025 * @brief Enable the fault circuitry for the designated fault input. 07026 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Enable\n 07027 * FLTINR1 FLT2E LL_HRTIM_FLT_Enable\n 07028 * FLTINR1 FLT3E LL_HRTIM_FLT_Enable\n 07029 * FLTINR1 FLT4E LL_HRTIM_FLT_Enable\n 07030 * FLTINR2 FLT5E LL_HRTIM_FLT_Enable 07031 * @param HRTIMx High Resolution Timer instance 07032 * @param Fault This parameter can be one of the following values: 07033 * @arg @ref LL_HRTIM_FAULT_1 07034 * @arg @ref LL_HRTIM_FAULT_2 07035 * @arg @ref LL_HRTIM_FAULT_3 07036 * @arg @ref LL_HRTIM_FAULT_4 07037 * @arg @ref LL_HRTIM_FAULT_5 07038 * @retval None 07039 */ 07040 __STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 07041 { 07042 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 07043 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 07044 REG_OFFSET_TAB_FLTINR[iFault])); 07045 SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); 07046 } 07047 07048 /** 07049 * @brief Disable the fault circuitry for for the designated fault input. 07050 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_Disable\n 07051 * FLTINR1 FLT2E LL_HRTIM_FLT_Disable\n 07052 * FLTINR1 FLT3E LL_HRTIM_FLT_Disable\n 07053 * FLTINR1 FLT4E LL_HRTIM_FLT_Disable\n 07054 * FLTINR2 FLT5E LL_HRTIM_FLT_Disable 07055 * @param HRTIMx High Resolution Timer instance 07056 * @param Fault This parameter can be one of the following values: 07057 * @arg @ref LL_HRTIM_FAULT_1 07058 * @arg @ref LL_HRTIM_FAULT_2 07059 * @arg @ref LL_HRTIM_FAULT_3 07060 * @arg @ref LL_HRTIM_FAULT_4 07061 * @arg @ref LL_HRTIM_FAULT_5 07062 * @retval None 07063 */ 07064 __STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 07065 { 07066 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 07067 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 07068 REG_OFFSET_TAB_FLTINR[iFault])); 07069 CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])); 07070 } 07071 07072 /** 07073 * @brief Indicate whether the fault circuitry is enabled for a given fault input. 07074 * @rmtoll FLTINR1 FLT1E LL_HRTIM_FLT_IsEnabled\n 07075 * FLTINR1 FLT2E LL_HRTIM_FLT_IsEnabled\n 07076 * FLTINR1 FLT3E LL_HRTIM_FLT_IsEnabled\n 07077 * FLTINR1 FLT4E LL_HRTIM_FLT_IsEnabled\n 07078 * FLTINR2 FLT5E LL_HRTIM_FLT_IsEnabled 07079 * @param HRTIMx High Resolution Timer instance 07080 * @param Fault This parameter can be one of the following values: 07081 * @arg @ref LL_HRTIM_FAULT_1 07082 * @arg @ref LL_HRTIM_FAULT_2 07083 * @arg @ref LL_HRTIM_FAULT_3 07084 * @arg @ref LL_HRTIM_FAULT_4 07085 * @arg @ref LL_HRTIM_FAULT_5 07086 * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0). 07087 */ 07088 __STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault) 07089 { 07090 uint32_t iFault = (uint8_t)POSITION_VAL(Fault); 07091 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) + 07092 REG_OFFSET_TAB_FLTINR[iFault])); 07093 return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) == 07094 (HRTIM_IER_FLT1)) ? 1UL : 0UL); 07095 } 07096 07097 /** 07098 * @} 07099 */ 07100 07101 /** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management 07102 * @{ 07103 */ 07104 07105 /** 07106 * @brief Configure the burst mode controller. 07107 * @rmtoll BMCR BMOM LL_HRTIM_BM_Config\n 07108 * BMCR BMCLK LL_HRTIM_BM_Config\n 07109 * BMCR BMPRSC LL_HRTIM_BM_Config 07110 * @param HRTIMx High Resolution Timer instance 07111 * @param Configuration This parameter must be a combination of all the following values: 07112 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS 07113 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM 07114 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768 07115 * @retval None 07116 */ 07117 __STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration) 07118 { 07119 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration); 07120 } 07121 07122 /** 07123 * @brief Set the burst mode controller operating mode. 07124 * @rmtoll BMCR BMOM LL_HRTIM_BM_SetMode 07125 * @param HRTIMx High Resolution Timer instance 07126 * @param Mode This parameter can be one of the following values: 07127 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT 07128 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS 07129 * @retval None 07130 */ 07131 __STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode) 07132 { 07133 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode); 07134 } 07135 07136 /** 07137 * @brief Get actual burst mode controller operating mode. 07138 * @rmtoll BMCR BMOM LL_HRTIM_BM_GetMode 07139 * @param HRTIMx High Resolution Timer instance 07140 * @retval Mode This parameter can be one of the following values: 07141 * @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT 07142 * @arg @ref LL_HRTIM_BM_MODE_CONTINOUS 07143 */ 07144 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx) 07145 { 07146 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM); 07147 } 07148 07149 /** 07150 * @brief Set the burst mode controller clock source. 07151 * @rmtoll BMCR BMCLK LL_HRTIM_BM_SetClockSrc 07152 * @param HRTIMx High Resolution Timer instance 07153 * @param ClockSrc This parameter can be one of the following values: 07154 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER 07155 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A 07156 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B 07157 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C 07158 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D 07159 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E 07160 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC 07161 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC 07162 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO 07163 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM 07164 * @retval None 07165 */ 07166 __STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc) 07167 { 07168 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc); 07169 } 07170 07171 /** 07172 * @brief Get actual burst mode controller clock source. 07173 * @rmtoll BMCR BMCLK LL_HRTIM_BM_GetClockSrc 07174 * @param HRTIMx High Resolution Timer instance 07175 * @retval ClockSrc This parameter can be one of the following values: 07176 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER 07177 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A 07178 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B 07179 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C 07180 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D 07181 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E 07182 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC 07183 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC 07184 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO 07185 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM 07186 * @retval ClockSrc This parameter can be one of the following values: 07187 * @arg @ref LL_HRTIM_BM_CLKSRC_MASTER 07188 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A 07189 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B 07190 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C 07191 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D 07192 * @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E 07193 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC 07194 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC 07195 * @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO 07196 * @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM 07197 */ 07198 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx) 07199 { 07200 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK); 07201 } 07202 07203 /** 07204 * @brief Set the burst mode controller prescaler. 07205 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_SetPrescaler 07206 * @param HRTIMx High Resolution Timer instance 07207 * @param Prescaler This parameter can be one of the following values: 07208 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 07209 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2 07210 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4 07211 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8 07212 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16 07213 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32 07214 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64 07215 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128 07216 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256 07217 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512 07218 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024 07219 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048 07220 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096 07221 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192 07222 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384 07223 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768 07224 * @retval None 07225 */ 07226 __STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler) 07227 { 07228 MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler); 07229 } 07230 07231 /** 07232 * @brief Get actual burst mode controller prescaler setting. 07233 * @rmtoll BMCR BMPRSC LL_HRTIM_BM_GetPrescaler 07234 * @param HRTIMx High Resolution Timer instance 07235 * @retval Prescaler This parameter can be one of the following values: 07236 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 07237 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2 07238 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4 07239 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8 07240 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16 07241 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32 07242 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV64 07243 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV128 07244 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV256 07245 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV512 07246 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024 07247 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048 07248 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096 07249 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192 07250 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384 07251 * @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768 07252 */ 07253 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx) 07254 { 07255 return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC); 07256 } 07257 07258 /** 07259 * @brief Enable burst mode compare and period registers preload. 07260 * @rmtoll BMCR BMPREN LL_HRTIM_BM_EnablePreload 07261 * @param HRTIMx High Resolution Timer instance 07262 * @retval None 07263 */ 07264 __STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx) 07265 { 07266 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); 07267 } 07268 07269 /** 07270 * @brief Disable burst mode compare and period registers preload. 07271 * @rmtoll BMCR BMPREN LL_HRTIM_BM_DisablePreload 07272 * @param HRTIMx High Resolution Timer instance 07273 * @retval None 07274 */ 07275 __STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx) 07276 { 07277 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); 07278 } 07279 07280 /** 07281 * @brief Indicate whether burst mode compare and period registers are preloaded. 07282 * @rmtoll BMCR BMPREN LL_HRTIM_BM_IsEnabledPreload 07283 * @param HRTIMx High Resolution Timer instance 07284 * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0). 07285 */ 07286 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx) 07287 { 07288 uint32_t temp; /* MISRAC-2012 compliance */ 07289 temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN); 07290 07291 return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL); 07292 } 07293 07294 /** 07295 * @brief Set the burst mode controller trigger 07296 * @rmtoll BMTRGR SW LL_HRTIM_BM_SetTrig\n 07297 * BMTRGR MSTRST LL_HRTIM_BM_SetTrig\n 07298 * BMTRGR MSTREP LL_HRTIM_BM_SetTrig\n 07299 * BMTRGR MSTCMP1 LL_HRTIM_BM_SetTrig\n 07300 * BMTRGR MSTCMP2 LL_HRTIM_BM_SetTrig\n 07301 * BMTRGR MSTCMP3 LL_HRTIM_BM_SetTrig\n 07302 * BMTRGR MSTCMP4 LL_HRTIM_BM_SetTrig\n 07303 * BMTRGR TARST LL_HRTIM_BM_SetTrig\n 07304 * BMTRGR TAREP LL_HRTIM_BM_SetTrig\n 07305 * BMTRGR TACMP1 LL_HRTIM_BM_SetTrig\n 07306 * BMTRGR TACMP2 LL_HRTIM_BM_SetTrig\n 07307 * BMTRGR TBRST LL_HRTIM_BM_SetTrig\n 07308 * BMTRGR TBREP LL_HRTIM_BM_SetTrig\n 07309 * BMTRGR TBCMP1 LL_HRTIM_BM_SetTrig\n 07310 * BMTRGR TBCMP2 LL_HRTIM_BM_SetTrig\n 07311 * BMTRGR TCRST LL_HRTIM_BM_SetTrig\n 07312 * BMTRGR TCREP LL_HRTIM_BM_SetTrig\n 07313 * BMTRGR TCCMP1 LL_HRTIM_BM_SetTrig\n 07314 * BMTRGR TCCMP2 LL_HRTIM_BM_SetTrig\n 07315 * BMTRGR TDRST LL_HRTIM_BM_SetTrig\n 07316 * BMTRGR TDREP LL_HRTIM_BM_SetTrig\n 07317 * BMTRGR TDCMP1 LL_HRTIM_BM_SetTrig\n 07318 * BMTRGR TDCMP2 LL_HRTIM_BM_SetTrig\n 07319 * BMTRGR TERST LL_HRTIM_BM_SetTrig\n 07320 * BMTRGR TEREP LL_HRTIM_BM_SetTrig\n 07321 * BMTRGR TECMP1 LL_HRTIM_BM_SetTrig\n 07322 * BMTRGR TECMP2 LL_HRTIM_BM_SetTrig\n 07323 * BMTRGR TAEEV7 LL_HRTIM_BM_SetTrig\n 07324 * BMTRGR TAEEV8 LL_HRTIM_BM_SetTrig\n 07325 * BMTRGR EEV7 LL_HRTIM_BM_SetTrig\n 07326 * BMTRGR EEV8 LL_HRTIM_BM_SetTrig\n 07327 * BMTRGR OCHIPEV LL_HRTIM_BM_SetTrig 07328 * @param HRTIMx High Resolution Timer instance 07329 * @param Trig This parameter can be a combination of the following values: 07330 * @arg @ref LL_HRTIM_BM_TRIG_NONE 07331 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET 07332 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION 07333 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1 07334 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2 07335 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3 07336 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4 07337 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET 07338 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION 07339 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1 07340 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2 07341 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET 07342 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION 07343 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1 07344 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2 07345 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET 07346 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION 07347 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1 07348 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2 07349 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET 07350 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION 07351 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1 07352 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2 07353 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET 07354 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION 07355 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1 07356 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2 07357 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7 07358 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8 07359 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7 07360 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8 07361 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP 07362 * @retval None 07363 */ 07364 __STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig) 07365 { 07366 WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig); 07367 } 07368 07369 /** 07370 * @brief Get actual burst mode controller trigger. 07371 * @rmtoll BMTRGR SW LL_HRTIM_BM_GetTrig\n 07372 * BMTRGR MSTRST LL_HRTIM_BM_GetTrig\n 07373 * BMTRGR MSTREP LL_HRTIM_BM_GetTrig\n 07374 * BMTRGR MSTCMP1 LL_HRTIM_BM_GetTrig\n 07375 * BMTRGR MSTCMP2 LL_HRTIM_BM_GetTrig\n 07376 * BMTRGR MSTCMP3 LL_HRTIM_BM_GetTrig\n 07377 * BMTRGR MSTCMP4 LL_HRTIM_BM_GetTrig\n 07378 * BMTRGR TARST LL_HRTIM_BM_GetTrig\n 07379 * BMTRGR TAREP LL_HRTIM_BM_GetTrig\n 07380 * BMTRGR TACMP1 LL_HRTIM_BM_GetTrig\n 07381 * BMTRGR TACMP2 LL_HRTIM_BM_GetTrig\n 07382 * BMTRGR TBRST LL_HRTIM_BM_GetTrig\n 07383 * BMTRGR TBREP LL_HRTIM_BM_GetTrig\n 07384 * BMTRGR TBCMP1 LL_HRTIM_BM_GetTrig\n 07385 * BMTRGR TBCMP2 LL_HRTIM_BM_GetTrig\n 07386 * BMTRGR TCRST LL_HRTIM_BM_GetTrig\n 07387 * BMTRGR TCREP LL_HRTIM_BM_GetTrig\n 07388 * BMTRGR TCCMP1 LL_HRTIM_BM_GetTrig\n 07389 * BMTRGR TCCMP2 LL_HRTIM_BM_GetTrig\n 07390 * BMTRGR TDRST LL_HRTIM_BM_GetTrig\n 07391 * BMTRGR TDREP LL_HRTIM_BM_GetTrig\n 07392 * BMTRGR TDCMP1 LL_HRTIM_BM_GetTrig\n 07393 * BMTRGR TDCMP2 LL_HRTIM_BM_GetTrig\n 07394 * BMTRGR TERST LL_HRTIM_BM_GetTrig\n 07395 * BMTRGR TEREP LL_HRTIM_BM_GetTrig\n 07396 * BMTRGR TECMP1 LL_HRTIM_BM_GetTrig\n 07397 * BMTRGR TECMP2 LL_HRTIM_BM_GetTrig\n 07398 * BMTRGR TAEEV7 LL_HRTIM_BM_GetTrig\n 07399 * BMTRGR TAEEV8 LL_HRTIM_BM_GetTrig\n 07400 * BMTRGR EEV7 LL_HRTIM_BM_GetTrig\n 07401 * BMTRGR EEV8 LL_HRTIM_BM_GetTrig\n 07402 * BMTRGR OCHIPEV LL_HRTIM_BM_GetTrig 07403 * @param HRTIMx High Resolution Timer instance 07404 * @retval Trig This parameter can be a combination of the following values: 07405 * @arg @ref LL_HRTIM_BM_TRIG_NONE 07406 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET 07407 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION 07408 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1 07409 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2 07410 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3 07411 * @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4 07412 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET 07413 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION 07414 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1 07415 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2 07416 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET 07417 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION 07418 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1 07419 * @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2 07420 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET 07421 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION 07422 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1 07423 * @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2 07424 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET 07425 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION 07426 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1 07427 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2 07428 * @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET 07429 * @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION 07430 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1 07431 * @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2 07432 * @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7 07433 * @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8 07434 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_7 07435 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_8 07436 * @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP 07437 */ 07438 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx) 07439 { 07440 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR); 07441 } 07442 07443 /** 07444 * @brief Set the burst mode controller compare value. 07445 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_SetCompare 07446 * @param HRTIMx High Resolution Timer instance 07447 * @param CompareValue Compare value must be above or equal to 3 07448 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 07449 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 07450 * @retval None 07451 */ 07452 __STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue) 07453 { 07454 WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue); 07455 } 07456 07457 /** 07458 * @brief Get actual burst mode controller compare value. 07459 * @rmtoll BMCMPR BMCMP LL_HRTIM_BM_GetCompare 07460 * @param HRTIMx High Resolution Timer instance 07461 * @retval CompareValue Compare value must be above or equal to 3 07462 * periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0, 07463 * 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 07464 */ 07465 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx) 07466 { 07467 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR); 07468 } 07469 07470 /** 07471 * @brief Set the burst mode controller period. 07472 * @rmtoll BMPER BMPER LL_HRTIM_BM_SetPeriod 07473 * @param HRTIMx High Resolution Timer instance 07474 * @param Period The period value must be above or equal to 3 periods of the fHRTIM clock, 07475 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 07476 * The maximum value is 0x0000 FFDF. 07477 * @retval None 07478 */ 07479 __STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period) 07480 { 07481 WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period); 07482 } 07483 07484 /** 07485 * @brief Get actual burst mode controller period. 07486 * @rmtoll BMPER BMPER LL_HRTIM_BM_GetPeriod 07487 * @param HRTIMx High Resolution Timer instance 07488 * @retval The period value must be above or equal to 3 periods of the fHRTIM clock, 07489 * that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,... 07490 * The maximum value is 0x0000 FFDF. 07491 */ 07492 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx) 07493 { 07494 return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER); 07495 } 07496 07497 /** 07498 * @brief Enable the burst mode controller 07499 * @rmtoll BMCR BME LL_HRTIM_BM_Enable 07500 * @param HRTIMx High Resolution Timer instance 07501 * @retval None 07502 */ 07503 __STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx) 07504 { 07505 SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME); 07506 } 07507 07508 /** 07509 * @brief Disable the burst mode controller 07510 * @rmtoll BMCR BME LL_HRTIM_BM_Disable 07511 * @param HRTIMx High Resolution Timer instance 07512 * @retval None 07513 */ 07514 __STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx) 07515 { 07516 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME); 07517 } 07518 07519 /** 07520 * @brief Indicate whether the burst mode controller is enabled. 07521 * @rmtoll BMCR BME LL_HRTIM_BM_IsEnabled 07522 * @param HRTIMx High Resolution Timer instance 07523 * @retval State of BME bit in HRTIM_BMCR register (1 or 0). 07524 */ 07525 __STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx) 07526 { 07527 return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL); 07528 } 07529 07530 /** 07531 * @brief Trigger the burst operation (software trigger) 07532 * @rmtoll BMTRGR SW LL_HRTIM_BM_Start 07533 * @param HRTIMx High Resolution Timer instance 07534 * @retval None 07535 */ 07536 __STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx) 07537 { 07538 SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW); 07539 } 07540 07541 /** 07542 * @brief Stop the burst mode operation. 07543 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_Stop 07544 * @note Causes a burst mode early termination. 07545 * @param HRTIMx High Resolution Timer instance 07546 * @retval None 07547 */ 07548 __STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx) 07549 { 07550 CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT); 07551 } 07552 07553 /** 07554 * @brief Get actual burst mode status 07555 * @rmtoll BMCR BMSTAT LL_HRTIM_BM_GetStatus 07556 * @param HRTIMx High Resolution Timer instance 07557 * @retval Status This parameter can be one of the following values: 07558 * @arg @ref LL_HRTIM_BM_STATUS_NORMAL 07559 * @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING 07560 */ 07561 __STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx) 07562 { 07563 return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT)); 07564 } 07565 07566 /** 07567 * @} 07568 */ 07569 07570 /** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management 07571 * @{ 07572 */ 07573 07574 /** 07575 * @brief Clear the Fault 1 interrupt flag. 07576 * @rmtoll ICR FLT1C LL_HRTIM_ClearFlag_FLT1 07577 * @param HRTIMx High Resolution Timer instance 07578 * @retval None 07579 */ 07580 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx) 07581 { 07582 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C); 07583 } 07584 07585 /** 07586 * @brief Indicate whether Fault 1 interrupt occurred. 07587 * @rmtoll ICR FLT1 LL_HRTIM_IsActiveFlag_FLT1 07588 * @param HRTIMx High Resolution Timer instance 07589 * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0). 07590 */ 07591 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx) 07592 { 07593 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL); 07594 } 07595 07596 /** 07597 * @brief Clear the Fault 2 interrupt flag. 07598 * @rmtoll ICR FLT2C LL_HRTIM_ClearFlag_FLT2 07599 * @param HRTIMx High Resolution Timer instance 07600 * @retval None 07601 */ 07602 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx) 07603 { 07604 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C); 07605 } 07606 07607 /** 07608 * @brief Indicate whether Fault 2 interrupt occurred. 07609 * @rmtoll ICR FLT2 LL_HRTIM_IsActiveFlag_FLT2 07610 * @param HRTIMx High Resolution Timer instance 07611 * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0). 07612 */ 07613 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx) 07614 { 07615 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL); 07616 } 07617 07618 /** 07619 * @brief Clear the Fault 3 interrupt flag. 07620 * @rmtoll ICR FLT3C LL_HRTIM_ClearFlag_FLT3 07621 * @param HRTIMx High Resolution Timer instance 07622 * @retval None 07623 */ 07624 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx) 07625 { 07626 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C); 07627 } 07628 07629 /** 07630 * @brief Indicate whether Fault 3 interrupt occurred. 07631 * @rmtoll ICR FLT3 LL_HRTIM_IsActiveFlag_FLT3 07632 * @param HRTIMx High Resolution Timer instance 07633 * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0). 07634 */ 07635 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx) 07636 { 07637 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL); 07638 } 07639 07640 /** 07641 * @brief Clear the Fault 4 interrupt flag. 07642 * @rmtoll ICR FLT4C LL_HRTIM_ClearFlag_FLT4 07643 * @param HRTIMx High Resolution Timer instance 07644 * @retval None 07645 */ 07646 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx) 07647 { 07648 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C); 07649 } 07650 07651 /** 07652 * @brief Indicate whether Fault 4 interrupt occurred. 07653 * @rmtoll ICR FLT4 LL_HRTIM_IsActiveFlag_FLT4 07654 * @param HRTIMx High Resolution Timer instance 07655 * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0). 07656 */ 07657 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx) 07658 { 07659 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL); 07660 } 07661 07662 /** 07663 * @brief Clear the Fault 5 interrupt flag. 07664 * @rmtoll ICR FLT5C LL_HRTIM_ClearFlag_FLT5 07665 * @param HRTIMx High Resolution Timer instance 07666 * @retval None 07667 */ 07668 __STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx) 07669 { 07670 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C); 07671 } 07672 07673 /** 07674 * @brief Indicate whether Fault 5 interrupt occurred. 07675 * @rmtoll ICR FLT5 LL_HRTIM_IsActiveFlag_FLT5 07676 * @param HRTIMx High Resolution Timer instance 07677 * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0). 07678 */ 07679 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx) 07680 { 07681 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL); 07682 } 07683 07684 /** 07685 * @brief Clear the System Fault interrupt flag. 07686 * @rmtoll ICR SYSFLTC LL_HRTIM_ClearFlag_SYSFLT 07687 * @param HRTIMx High Resolution Timer instance 07688 * @retval None 07689 */ 07690 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx) 07691 { 07692 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC); 07693 } 07694 07695 /** 07696 * @brief Indicate whether System Fault interrupt occurred. 07697 * @rmtoll ISR SYSFLT LL_HRTIM_IsActiveFlag_SYSFLT 07698 * @param HRTIMx High Resolution Timer instance 07699 * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0). 07700 */ 07701 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx) 07702 { 07703 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL); 07704 } 07705 07706 /** 07707 * @brief Clear the Burst Mode period interrupt flag. 07708 * @rmtoll ICR BMPERC LL_HRTIM_ClearFlag_BMPER 07709 * @param HRTIMx High Resolution Timer instance 07710 * @retval None 07711 */ 07712 __STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx) 07713 { 07714 SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC); 07715 } 07716 07717 /** 07718 * @brief Indicate whether Burst Mode period interrupt occurred. 07719 * @rmtoll ISR BMPER LL_HRTIM_IsActiveFlag_BMPER 07720 * @param HRTIMx High Resolution Timer instance 07721 * @retval State of BMPER bit in HRTIM_ISR register (1 or 0). 07722 */ 07723 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx) 07724 { 07725 return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL); 07726 } 07727 07728 /** 07729 * @brief Clear the Synchronization Input interrupt flag. 07730 * @rmtoll MICR SYNCC LL_HRTIM_ClearFlag_SYNC 07731 * @param HRTIMx High Resolution Timer instance 07732 * @retval None 07733 */ 07734 __STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx) 07735 { 07736 SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC); 07737 } 07738 07739 /** 07740 * @brief Indicate whether the Synchronization Input interrupt occurred. 07741 * @rmtoll MISR SYNC LL_HRTIM_IsActiveFlag_SYNC 07742 * @param HRTIMx High Resolution Timer instance 07743 * @retval State of SYNC bit in HRTIM_MISR register (1 or 0). 07744 */ 07745 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx) 07746 { 07747 return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL); 07748 } 07749 07750 /** 07751 * @brief Clear the update interrupt flag for a given timer (including the master timer) . 07752 * @rmtoll MICR MUPDC LL_HRTIM_ClearFlag_UPDATE\n 07753 * TIMxICR UPDC LL_HRTIM_ClearFlag_UPDATE 07754 * @param HRTIMx High Resolution Timer instance 07755 * @param Timer This parameter can be one of the following values: 07756 * @arg @ref LL_HRTIM_TIMER_MASTER 07757 * @arg @ref LL_HRTIM_TIMER_A 07758 * @arg @ref LL_HRTIM_TIMER_B 07759 * @arg @ref LL_HRTIM_TIMER_C 07760 * @arg @ref LL_HRTIM_TIMER_D 07761 * @arg @ref LL_HRTIM_TIMER_E 07762 * @retval None 07763 */ 07764 __STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07765 { 07766 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07767 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 07768 REG_OFFSET_TAB_TIMER[iTimer])); 07769 SET_BIT(*pReg, HRTIM_MICR_MUPD); 07770 } 07771 07772 /** 07773 * @brief Indicate whether the update interrupt has occurred for a given timer (including the master timer) . 07774 * @rmtoll MISR MUPD LL_HRTIM_IsActiveFlag_UPDATE\n 07775 * TIMxISR UPD LL_HRTIM_IsActiveFlag_UPDATE 07776 * @param HRTIMx High Resolution Timer instance 07777 * @param Timer This parameter can be one of the following values: 07778 * @arg @ref LL_HRTIM_TIMER_MASTER 07779 * @arg @ref LL_HRTIM_TIMER_A 07780 * @arg @ref LL_HRTIM_TIMER_B 07781 * @arg @ref LL_HRTIM_TIMER_C 07782 * @arg @ref LL_HRTIM_TIMER_D 07783 * @arg @ref LL_HRTIM_TIMER_E 07784 * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 07785 */ 07786 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07787 { 07788 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07789 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 07790 REG_OFFSET_TAB_TIMER[iTimer])); 07791 07792 return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL); 07793 } 07794 07795 /** 07796 * @brief Clear the repetition interrupt flag for a given timer (including the master timer) . 07797 * @rmtoll MICR MREPC LL_HRTIM_ClearFlag_REP\n 07798 * TIMxICR REPC LL_HRTIM_ClearFlag_REP 07799 * @param HRTIMx High Resolution Timer instance 07800 * @param Timer This parameter can be one of the following values: 07801 * @arg @ref LL_HRTIM_TIMER_MASTER 07802 * @arg @ref LL_HRTIM_TIMER_A 07803 * @arg @ref LL_HRTIM_TIMER_B 07804 * @arg @ref LL_HRTIM_TIMER_C 07805 * @arg @ref LL_HRTIM_TIMER_D 07806 * @arg @ref LL_HRTIM_TIMER_E 07807 * @retval None 07808 */ 07809 __STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07810 { 07811 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07812 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 07813 REG_OFFSET_TAB_TIMER[iTimer])); 07814 SET_BIT(*pReg, HRTIM_MICR_MREP); 07815 07816 } 07817 07818 /** 07819 * @brief Indicate whether the repetition interrupt has occurred for a given timer (including the master timer) . 07820 * @rmtoll MISR MREP LL_HRTIM_IsActiveFlag_REP\n 07821 * TIMxISR REP LL_HRTIM_IsActiveFlag_REP 07822 * @param HRTIMx High Resolution Timer instance 07823 * @param Timer This parameter can be one of the following values: 07824 * @arg @ref LL_HRTIM_TIMER_MASTER 07825 * @arg @ref LL_HRTIM_TIMER_A 07826 * @arg @ref LL_HRTIM_TIMER_B 07827 * @arg @ref LL_HRTIM_TIMER_C 07828 * @arg @ref LL_HRTIM_TIMER_D 07829 * @arg @ref LL_HRTIM_TIMER_E 07830 * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 07831 */ 07832 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07833 { 07834 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07835 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 07836 REG_OFFSET_TAB_TIMER[iTimer])); 07837 07838 return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL); 07839 } 07840 07841 /** 07842 * @brief Clear the compare 1 match interrupt for a given timer (including the master timer). 07843 * @rmtoll MICR MCMP1C LL_HRTIM_ClearFlag_CMP1\n 07844 * TIMxICR CMP1C LL_HRTIM_ClearFlag_CMP1 07845 * @param HRTIMx High Resolution Timer instance 07846 * @param Timer This parameter can be one of the following values: 07847 * @arg @ref LL_HRTIM_TIMER_MASTER 07848 * @arg @ref LL_HRTIM_TIMER_A 07849 * @arg @ref LL_HRTIM_TIMER_B 07850 * @arg @ref LL_HRTIM_TIMER_C 07851 * @arg @ref LL_HRTIM_TIMER_D 07852 * @arg @ref LL_HRTIM_TIMER_E 07853 * @retval None 07854 */ 07855 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07856 { 07857 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07858 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 07859 REG_OFFSET_TAB_TIMER[iTimer])); 07860 SET_BIT(*pReg, HRTIM_MICR_MCMP1); 07861 } 07862 07863 /** 07864 * @brief Indicate whether the compare match 1 interrupt has occurred for a given timer (including the master timer) . 07865 * @rmtoll MISR MCMP1 LL_HRTIM_IsActiveFlag_CMP1\n 07866 * TIMxISR CMP1 LL_HRTIM_IsActiveFlag_CMP1 07867 * @param HRTIMx High Resolution Timer instance 07868 * @param Timer This parameter can be one of the following values: 07869 * @arg @ref LL_HRTIM_TIMER_MASTER 07870 * @arg @ref LL_HRTIM_TIMER_A 07871 * @arg @ref LL_HRTIM_TIMER_B 07872 * @arg @ref LL_HRTIM_TIMER_C 07873 * @arg @ref LL_HRTIM_TIMER_D 07874 * @arg @ref LL_HRTIM_TIMER_E 07875 * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 07876 */ 07877 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07878 { 07879 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07880 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 07881 REG_OFFSET_TAB_TIMER[iTimer])); 07882 07883 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL); 07884 } 07885 07886 /** 07887 * @brief Clear the compare 2 match interrupt for a given timer (including the master timer). 07888 * @rmtoll MICR MCMP2C LL_HRTIM_ClearFlag_CMP2\n 07889 * TIMxICR CMP2C LL_HRTIM_ClearFlag_CMP2 07890 * @param HRTIMx High Resolution Timer instance 07891 * @param Timer This parameter can be one of the following values: 07892 * @arg @ref LL_HRTIM_TIMER_MASTER 07893 * @arg @ref LL_HRTIM_TIMER_A 07894 * @arg @ref LL_HRTIM_TIMER_B 07895 * @arg @ref LL_HRTIM_TIMER_C 07896 * @arg @ref LL_HRTIM_TIMER_D 07897 * @arg @ref LL_HRTIM_TIMER_E 07898 * @retval None 07899 */ 07900 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07901 { 07902 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07903 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 07904 REG_OFFSET_TAB_TIMER[iTimer])); 07905 SET_BIT(*pReg, HRTIM_MICR_MCMP2); 07906 } 07907 07908 /** 07909 * @brief Indicate whether the compare match 2 interrupt has occurred for a given timer (including the master timer) . 07910 * @rmtoll MISR MCMP2 LL_HRTIM_IsActiveFlag_CMP2\n 07911 * TIMxISR CMP2 LL_HRTIM_IsActiveFlag_CMP2 07912 * @param HRTIMx High Resolution Timer instance 07913 * @param Timer This parameter can be one of the following values: 07914 * @arg @ref LL_HRTIM_TIMER_MASTER 07915 * @arg @ref LL_HRTIM_TIMER_A 07916 * @arg @ref LL_HRTIM_TIMER_B 07917 * @arg @ref LL_HRTIM_TIMER_C 07918 * @arg @ref LL_HRTIM_TIMER_D 07919 * @arg @ref LL_HRTIM_TIMER_E 07920 * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 07921 */ 07922 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07923 { 07924 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07925 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 07926 REG_OFFSET_TAB_TIMER[iTimer])); 07927 07928 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL); 07929 } 07930 07931 /** 07932 * @brief Clear the compare 3 match interrupt for a given timer (including the master timer). 07933 * @rmtoll MICR MCMP3C LL_HRTIM_ClearFlag_CMP3\n 07934 * TIMxICR CMP3C LL_HRTIM_ClearFlag_CMP3 07935 * @param HRTIMx High Resolution Timer instance 07936 * @param Timer This parameter can be one of the following values: 07937 * @arg @ref LL_HRTIM_TIMER_MASTER 07938 * @arg @ref LL_HRTIM_TIMER_A 07939 * @arg @ref LL_HRTIM_TIMER_B 07940 * @arg @ref LL_HRTIM_TIMER_C 07941 * @arg @ref LL_HRTIM_TIMER_D 07942 * @arg @ref LL_HRTIM_TIMER_E 07943 * @retval None 07944 */ 07945 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07946 { 07947 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07948 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 07949 REG_OFFSET_TAB_TIMER[iTimer])); 07950 SET_BIT(*pReg, HRTIM_MICR_MCMP3); 07951 } 07952 07953 /** 07954 * @brief Indicate whether the compare match 3 interrupt has occurred for a given timer (including the master timer) . 07955 * @rmtoll MISR MCMP3 LL_HRTIM_IsActiveFlag_CMP3\n 07956 * TIMxISR CMP3 LL_HRTIM_IsActiveFlag_CMP3 07957 * @param HRTIMx High Resolution Timer instance 07958 * @param Timer This parameter can be one of the following values: 07959 * @arg @ref LL_HRTIM_TIMER_MASTER 07960 * @arg @ref LL_HRTIM_TIMER_A 07961 * @arg @ref LL_HRTIM_TIMER_B 07962 * @arg @ref LL_HRTIM_TIMER_C 07963 * @arg @ref LL_HRTIM_TIMER_D 07964 * @arg @ref LL_HRTIM_TIMER_E 07965 * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 07966 */ 07967 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07968 { 07969 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07970 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 07971 REG_OFFSET_TAB_TIMER[iTimer])); 07972 07973 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL); 07974 } 07975 07976 /** 07977 * @brief Clear the compare 4 match interrupt for a given timer (including the master timer). 07978 * @rmtoll MICR MCMP4C LL_HRTIM_ClearFlag_CMP4\n 07979 * TIMxICR CMP4C LL_HRTIM_ClearFlag_CMP4 07980 * @param HRTIMx High Resolution Timer instance 07981 * @param Timer This parameter can be one of the following values: 07982 * @arg @ref LL_HRTIM_TIMER_MASTER 07983 * @arg @ref LL_HRTIM_TIMER_A 07984 * @arg @ref LL_HRTIM_TIMER_B 07985 * @arg @ref LL_HRTIM_TIMER_C 07986 * @arg @ref LL_HRTIM_TIMER_D 07987 * @arg @ref LL_HRTIM_TIMER_E 07988 * @retval None 07989 */ 07990 __STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 07991 { 07992 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 07993 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 07994 REG_OFFSET_TAB_TIMER[iTimer])); 07995 SET_BIT(*pReg, HRTIM_MICR_MCMP4); 07996 } 07997 07998 /** 07999 * @brief Indicate whether the compare match 4 interrupt has occurred for a given timer (including the master timer) . 08000 * @rmtoll MISR MCMP4 LL_HRTIM_IsActiveFlag_CMP4\n 08001 * TIMxISR CMP4 LL_HRTIM_IsActiveFlag_CMP4 08002 * @param HRTIMx High Resolution Timer instance 08003 * @param Timer This parameter can be one of the following values: 08004 * @arg @ref LL_HRTIM_TIMER_MASTER 08005 * @arg @ref LL_HRTIM_TIMER_A 08006 * @arg @ref LL_HRTIM_TIMER_B 08007 * @arg @ref LL_HRTIM_TIMER_C 08008 * @arg @ref LL_HRTIM_TIMER_D 08009 * @arg @ref LL_HRTIM_TIMER_E 08010 * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0). 08011 */ 08012 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08013 { 08014 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08015 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08016 REG_OFFSET_TAB_TIMER[iTimer])); 08017 08018 return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL); 08019 } 08020 08021 /** 08022 * @brief Clear the capture 1 interrupt flag for a given timer. 08023 * @rmtoll TIMxICR CPT1C LL_HRTIM_ClearFlag_CPT1 08024 * @param HRTIMx High Resolution Timer instance 08025 * @param Timer This parameter can be one of the following values: 08026 * @arg @ref LL_HRTIM_TIMER_A 08027 * @arg @ref LL_HRTIM_TIMER_B 08028 * @arg @ref LL_HRTIM_TIMER_C 08029 * @arg @ref LL_HRTIM_TIMER_D 08030 * @arg @ref LL_HRTIM_TIMER_E 08031 * @retval None 08032 */ 08033 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08034 { 08035 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08036 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 08037 REG_OFFSET_TAB_TIMER[iTimer])); 08038 SET_BIT(*pReg, HRTIM_TIMICR_CPT1C); 08039 } 08040 08041 /** 08042 * @brief Indicate whether the capture 1 interrupt occurred for a given timer. 08043 * @rmtoll TIMxISR CPT1 LL_HRTIM_IsActiveFlag_CPT1 08044 * @param HRTIMx High Resolution Timer instance 08045 * @param Timer This parameter can be one of the following values: 08046 * @arg @ref LL_HRTIM_TIMER_A 08047 * @arg @ref LL_HRTIM_TIMER_B 08048 * @arg @ref LL_HRTIM_TIMER_C 08049 * @arg @ref LL_HRTIM_TIMER_D 08050 * @arg @ref LL_HRTIM_TIMER_E 08051 * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0). 08052 */ 08053 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08054 { 08055 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08056 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08057 REG_OFFSET_TAB_TIMER[iTimer])); 08058 08059 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL); 08060 } 08061 08062 /** 08063 * @brief Clear the capture 2 interrupt flag for a given timer. 08064 * @rmtoll TIMxICR CPT2C LL_HRTIM_ClearFlag_CPT2 08065 * @param HRTIMx High Resolution Timer instance 08066 * @param Timer This parameter can be one of the following values: 08067 * @arg @ref LL_HRTIM_TIMER_A 08068 * @arg @ref LL_HRTIM_TIMER_B 08069 * @arg @ref LL_HRTIM_TIMER_C 08070 * @arg @ref LL_HRTIM_TIMER_D 08071 * @arg @ref LL_HRTIM_TIMER_E 08072 * @retval None 08073 */ 08074 __STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08075 { 08076 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08077 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 08078 REG_OFFSET_TAB_TIMER[iTimer])); 08079 SET_BIT(*pReg, HRTIM_TIMICR_CPT2C); 08080 } 08081 08082 /** 08083 * @brief Indicate whether the capture 2 interrupt occurred for a given timer. 08084 * @rmtoll TIMxISR CPT2 LL_HRTIM_IsActiveFlag_CPT2 08085 * @param HRTIMx High Resolution Timer instance 08086 * @param Timer This parameter can be one of the following values: 08087 * @arg @ref LL_HRTIM_TIMER_A 08088 * @arg @ref LL_HRTIM_TIMER_B 08089 * @arg @ref LL_HRTIM_TIMER_C 08090 * @arg @ref LL_HRTIM_TIMER_D 08091 * @arg @ref LL_HRTIM_TIMER_E 08092 * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0). 08093 */ 08094 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08095 { 08096 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08097 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08098 REG_OFFSET_TAB_TIMER[iTimer])); 08099 08100 return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL); 08101 } 08102 08103 /** 08104 * @brief Clear the output 1 set interrupt flag for a given timer. 08105 * @rmtoll TIMxICR SET1C LL_HRTIM_ClearFlag_SET1 08106 * @param HRTIMx High Resolution Timer instance 08107 * @param Timer This parameter can be one of the following values: 08108 * @arg @ref LL_HRTIM_TIMER_A 08109 * @arg @ref LL_HRTIM_TIMER_B 08110 * @arg @ref LL_HRTIM_TIMER_C 08111 * @arg @ref LL_HRTIM_TIMER_D 08112 * @arg @ref LL_HRTIM_TIMER_E 08113 * @retval None 08114 */ 08115 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08116 { 08117 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08118 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 08119 REG_OFFSET_TAB_TIMER[iTimer])); 08120 SET_BIT(*pReg, HRTIM_TIMICR_SET1C); 08121 } 08122 08123 /** 08124 * @brief Indicate whether the output 1 set interrupt occurred for a given timer. 08125 * @rmtoll TIMxISR SET1 LL_HRTIM_IsActiveFlag_SET1 08126 * @param HRTIMx High Resolution Timer instance 08127 * @param Timer This parameter can be one of the following values: 08128 * @arg @ref LL_HRTIM_TIMER_A 08129 * @arg @ref LL_HRTIM_TIMER_B 08130 * @arg @ref LL_HRTIM_TIMER_C 08131 * @arg @ref LL_HRTIM_TIMER_D 08132 * @arg @ref LL_HRTIM_TIMER_E 08133 * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0). 08134 */ 08135 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08136 { 08137 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08138 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08139 REG_OFFSET_TAB_TIMER[iTimer])); 08140 08141 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL); 08142 } 08143 08144 /** 08145 * @brief Clear the output 1 reset interrupt flag for a given timer. 08146 * @rmtoll TIMxICR RST1C LL_HRTIM_ClearFlag_RST1 08147 * @param HRTIMx High Resolution Timer instance 08148 * @param Timer This parameter can be one of the following values: 08149 * @arg @ref LL_HRTIM_TIMER_A 08150 * @arg @ref LL_HRTIM_TIMER_B 08151 * @arg @ref LL_HRTIM_TIMER_C 08152 * @arg @ref LL_HRTIM_TIMER_D 08153 * @arg @ref LL_HRTIM_TIMER_E 08154 * @retval None 08155 */ 08156 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08157 { 08158 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08159 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 08160 REG_OFFSET_TAB_TIMER[iTimer])); 08161 SET_BIT(*pReg, HRTIM_TIMICR_RST1C); 08162 } 08163 08164 /** 08165 * @brief Indicate whether the output 1 reset interrupt occurred for a given timer. 08166 * @rmtoll TIMxISR RST1 LL_HRTIM_IsActiveFlag_RST1 08167 * @param HRTIMx High Resolution Timer instance 08168 * @param Timer This parameter can be one of the following values: 08169 * @arg @ref LL_HRTIM_TIMER_A 08170 * @arg @ref LL_HRTIM_TIMER_B 08171 * @arg @ref LL_HRTIM_TIMER_C 08172 * @arg @ref LL_HRTIM_TIMER_D 08173 * @arg @ref LL_HRTIM_TIMER_E 08174 * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0). 08175 */ 08176 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08177 { 08178 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08179 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08180 REG_OFFSET_TAB_TIMER[iTimer])); 08181 08182 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL); 08183 } 08184 08185 /** 08186 * @brief Clear the output 2 set interrupt flag for a given timer. 08187 * @rmtoll TIMxICR SET2C LL_HRTIM_ClearFlag_SET2 08188 * @param HRTIMx High Resolution Timer instance 08189 * @param Timer This parameter can be one of the following values: 08190 * @arg @ref LL_HRTIM_TIMER_A 08191 * @arg @ref LL_HRTIM_TIMER_B 08192 * @arg @ref LL_HRTIM_TIMER_C 08193 * @arg @ref LL_HRTIM_TIMER_D 08194 * @arg @ref LL_HRTIM_TIMER_E 08195 * @retval None 08196 */ 08197 __STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08198 { 08199 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08200 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 08201 REG_OFFSET_TAB_TIMER[iTimer])); 08202 SET_BIT(*pReg, HRTIM_TIMICR_SET2C); 08203 } 08204 08205 /** 08206 * @brief Indicate whether the output 2 set interrupt occurred for a given timer. 08207 * @rmtoll TIMxISR SET2 LL_HRTIM_IsActiveFlag_SET2 08208 * @param HRTIMx High Resolution Timer instance 08209 * @param Timer This parameter can be one of the following values: 08210 * @arg @ref LL_HRTIM_TIMER_A 08211 * @arg @ref LL_HRTIM_TIMER_B 08212 * @arg @ref LL_HRTIM_TIMER_C 08213 * @arg @ref LL_HRTIM_TIMER_D 08214 * @arg @ref LL_HRTIM_TIMER_E 08215 * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0). 08216 */ 08217 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08218 { 08219 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08220 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08221 REG_OFFSET_TAB_TIMER[iTimer])); 08222 08223 return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL); 08224 } 08225 08226 /** 08227 * @brief Clear the output 2reset interrupt flag for a given timer. 08228 * @rmtoll TIMxICR RST2C LL_HRTIM_ClearFlag_RST2 08229 * @param HRTIMx High Resolution Timer instance 08230 * @param Timer This parameter can be one of the following values: 08231 * @arg @ref LL_HRTIM_TIMER_A 08232 * @arg @ref LL_HRTIM_TIMER_B 08233 * @arg @ref LL_HRTIM_TIMER_C 08234 * @arg @ref LL_HRTIM_TIMER_D 08235 * @arg @ref LL_HRTIM_TIMER_E 08236 * @retval None 08237 */ 08238 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08239 { 08240 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08241 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 08242 REG_OFFSET_TAB_TIMER[iTimer])); 08243 SET_BIT(*pReg, HRTIM_TIMICR_RST2C); 08244 } 08245 08246 /** 08247 * @brief Indicate whether the output 2 reset interrupt occurred for a given timer. 08248 * @rmtoll TIMxISR RST2 LL_HRTIM_IsActiveFlag_RST2 08249 * @param HRTIMx High Resolution Timer instance 08250 * @param Timer This parameter can be one of the following values: 08251 * @arg @ref LL_HRTIM_TIMER_A 08252 * @arg @ref LL_HRTIM_TIMER_B 08253 * @arg @ref LL_HRTIM_TIMER_C 08254 * @arg @ref LL_HRTIM_TIMER_D 08255 * @arg @ref LL_HRTIM_TIMER_E 08256 * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0). 08257 */ 08258 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08259 { 08260 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08261 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08262 REG_OFFSET_TAB_TIMER[iTimer])); 08263 08264 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL); 08265 } 08266 08267 /** 08268 * @brief Clear the reset and/or roll-over interrupt flag for a given timer. 08269 * @rmtoll TIMxICR RSTC LL_HRTIM_ClearFlag_RST 08270 * @param HRTIMx High Resolution Timer instance 08271 * @param Timer This parameter can be one of the following values: 08272 * @arg @ref LL_HRTIM_TIMER_A 08273 * @arg @ref LL_HRTIM_TIMER_B 08274 * @arg @ref LL_HRTIM_TIMER_C 08275 * @arg @ref LL_HRTIM_TIMER_D 08276 * @arg @ref LL_HRTIM_TIMER_E 08277 * @retval None 08278 */ 08279 __STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08280 { 08281 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08282 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 08283 REG_OFFSET_TAB_TIMER[iTimer])); 08284 SET_BIT(*pReg, HRTIM_TIMICR_RSTC); 08285 } 08286 08287 /** 08288 * @brief Indicate whether the reset and/or roll-over interrupt occurred for a given timer. 08289 * @rmtoll TIMxISR RST LL_HRTIM_IsActiveFlag_RST 08290 * @param HRTIMx High Resolution Timer instance 08291 * @param Timer This parameter can be one of the following values: 08292 * @arg @ref LL_HRTIM_TIMER_A 08293 * @arg @ref LL_HRTIM_TIMER_B 08294 * @arg @ref LL_HRTIM_TIMER_C 08295 * @arg @ref LL_HRTIM_TIMER_D 08296 * @arg @ref LL_HRTIM_TIMER_E 08297 * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0). 08298 */ 08299 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08300 { 08301 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08302 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08303 REG_OFFSET_TAB_TIMER[iTimer])); 08304 08305 return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL); 08306 } 08307 08308 /** 08309 * @brief Clear the delayed protection interrupt flag for a given timer. 08310 * @rmtoll TIMxICR DLYPRTC LL_HRTIM_ClearFlag_DLYPRT 08311 * @param HRTIMx High Resolution Timer instance 08312 * @param Timer This parameter can be one of the following values: 08313 * @arg @ref LL_HRTIM_TIMER_A 08314 * @arg @ref LL_HRTIM_TIMER_B 08315 * @arg @ref LL_HRTIM_TIMER_C 08316 * @arg @ref LL_HRTIM_TIMER_D 08317 * @arg @ref LL_HRTIM_TIMER_E 08318 * @retval None 08319 */ 08320 __STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08321 { 08322 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08323 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) + 08324 REG_OFFSET_TAB_TIMER[iTimer])); 08325 SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC); 08326 } 08327 08328 /** 08329 * @brief Indicate whether the delayed protection interrupt occurred for a given timer. 08330 * @rmtoll TIMxISR DLYPRT LL_HRTIM_IsActiveFlag_DLYPRT 08331 * @param HRTIMx High Resolution Timer instance 08332 * @param Timer This parameter can be one of the following values: 08333 * @arg @ref LL_HRTIM_TIMER_A 08334 * @arg @ref LL_HRTIM_TIMER_B 08335 * @arg @ref LL_HRTIM_TIMER_C 08336 * @arg @ref LL_HRTIM_TIMER_D 08337 * @arg @ref LL_HRTIM_TIMER_E 08338 * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0). 08339 */ 08340 __STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08341 { 08342 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08343 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) + 08344 REG_OFFSET_TAB_TIMER[iTimer])); 08345 08346 return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL); 08347 } 08348 08349 /** 08350 * @} 08351 */ 08352 08353 /** @defgroup HRTIM_LL_EF_IT_Management IT_Management 08354 * @{ 08355 */ 08356 08357 /** 08358 * @brief Enable the fault 1 interrupt. 08359 * @rmtoll IER FLT1IE LL_HRTIM_EnableIT_FLT1 08360 * @param HRTIMx High Resolution Timer instance 08361 * @retval None 08362 */ 08363 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx) 08364 { 08365 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1); 08366 } 08367 08368 /** 08369 * @brief Disable the fault 1 interrupt. 08370 * @rmtoll IER FLT1IE LL_HRTIM_DisableIT_FLT1 08371 * @param HRTIMx High Resolution Timer instance 08372 * @retval None 08373 */ 08374 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx) 08375 { 08376 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1); 08377 } 08378 08379 /** 08380 * @brief Indicate whether the fault 1 interrupt is enabled. 08381 * @rmtoll IER FLT1IE LL_HRTIM_IsEnabledIT_FLT1 08382 * @param HRTIMx High Resolution Timer instance 08383 * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0). 08384 */ 08385 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx) 08386 { 08387 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL); 08388 } 08389 08390 /** 08391 * @brief Enable the fault 2 interrupt. 08392 * @rmtoll IER FLT2IE LL_HRTIM_EnableIT_FLT2 08393 * @param HRTIMx High Resolution Timer instance 08394 * @retval None 08395 */ 08396 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx) 08397 { 08398 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2); 08399 } 08400 08401 /** 08402 * @brief Disable the fault 2 interrupt. 08403 * @rmtoll IER FLT2IE LL_HRTIM_DisableIT_FLT2 08404 * @param HRTIMx High Resolution Timer instance 08405 * @retval None 08406 */ 08407 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx) 08408 { 08409 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2); 08410 } 08411 08412 /** 08413 * @brief Indicate whether the fault 2 interrupt is enabled. 08414 * @rmtoll IER FLT2IE LL_HRTIM_IsEnabledIT_FLT2 08415 * @param HRTIMx High Resolution Timer instance 08416 * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0). 08417 */ 08418 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx) 08419 { 08420 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL); 08421 } 08422 08423 /** 08424 * @brief Enable the fault 3 interrupt. 08425 * @rmtoll IER FLT3IE LL_HRTIM_EnableIT_FLT3 08426 * @param HRTIMx High Resolution Timer instance 08427 * @retval None 08428 */ 08429 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx) 08430 { 08431 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3); 08432 } 08433 08434 /** 08435 * @brief Disable the fault 3 interrupt. 08436 * @rmtoll IER FLT3IE LL_HRTIM_DisableIT_FLT3 08437 * @param HRTIMx High Resolution Timer instance 08438 * @retval None 08439 */ 08440 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx) 08441 { 08442 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3); 08443 } 08444 08445 /** 08446 * @brief Indicate whether the fault 3 interrupt is enabled. 08447 * @rmtoll IER FLT3IE LL_HRTIM_IsEnabledIT_FLT3 08448 * @param HRTIMx High Resolution Timer instance 08449 * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0). 08450 */ 08451 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx) 08452 { 08453 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL); 08454 } 08455 08456 /** 08457 * @brief Enable the fault 4 interrupt. 08458 * @rmtoll IER FLT4IE LL_HRTIM_EnableIT_FLT4 08459 * @param HRTIMx High Resolution Timer instance 08460 * @retval None 08461 */ 08462 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx) 08463 { 08464 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4); 08465 } 08466 08467 /** 08468 * @brief Disable the fault 4 interrupt. 08469 * @rmtoll IER FLT4IE LL_HRTIM_DisableIT_FLT4 08470 * @param HRTIMx High Resolution Timer instance 08471 * @retval None 08472 */ 08473 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx) 08474 { 08475 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4); 08476 } 08477 08478 /** 08479 * @brief Indicate whether the fault 4 interrupt is enabled. 08480 * @rmtoll IER FLT4IE LL_HRTIM_IsEnabledIT_FLT4 08481 * @param HRTIMx High Resolution Timer instance 08482 * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0). 08483 */ 08484 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx) 08485 { 08486 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL); 08487 } 08488 08489 /** 08490 * @brief Enable the fault 5 interrupt. 08491 * @rmtoll IER FLT5IE LL_HRTIM_EnableIT_FLT5 08492 * @param HRTIMx High Resolution Timer instance 08493 * @retval None 08494 */ 08495 __STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx) 08496 { 08497 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5); 08498 } 08499 08500 /** 08501 * @brief Disable the fault 5 interrupt. 08502 * @rmtoll IER FLT5IE LL_HRTIM_DisableIT_FLT5 08503 * @param HRTIMx High Resolution Timer instance 08504 * @retval None 08505 */ 08506 __STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx) 08507 { 08508 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5); 08509 } 08510 08511 /** 08512 * @brief Indicate whether the fault 5 interrupt is enabled. 08513 * @rmtoll IER FLT5IE LL_HRTIM_IsEnabledIT_FLT5 08514 * @param HRTIMx High Resolution Timer instance 08515 * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0). 08516 */ 08517 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx) 08518 { 08519 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL); 08520 } 08521 08522 /** 08523 * @brief Enable the system fault interrupt. 08524 * @rmtoll IER SYSFLTIE LL_HRTIM_EnableIT_SYSFLT 08525 * @param HRTIMx High Resolution Timer instance 08526 * @retval None 08527 */ 08528 __STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx) 08529 { 08530 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT); 08531 } 08532 08533 /** 08534 * @brief Disable the system fault interrupt. 08535 * @rmtoll IER SYSFLTIE LL_HRTIM_DisableIT_SYSFLT 08536 * @param HRTIMx High Resolution Timer instance 08537 * @retval None 08538 */ 08539 __STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx) 08540 { 08541 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT); 08542 } 08543 08544 /** 08545 * @brief Indicate whether the system fault interrupt is enabled. 08546 * @rmtoll IER SYSFLTIE LL_HRTIM_IsEnabledIT_SYSFLT 08547 * @param HRTIMx High Resolution Timer instance 08548 * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0). 08549 */ 08550 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx) 08551 { 08552 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL); 08553 } 08554 08555 /** 08556 * @brief Enable the burst mode period interrupt. 08557 * @rmtoll IER BMPERIE LL_HRTIM_EnableIT_BMPER 08558 * @param HRTIMx High Resolution Timer instance 08559 * @retval None 08560 */ 08561 __STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx) 08562 { 08563 SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER); 08564 } 08565 08566 /** 08567 * @brief Disable the burst mode period interrupt. 08568 * @rmtoll IER BMPERIE LL_HRTIM_DisableIT_BMPER 08569 * @param HRTIMx High Resolution Timer instance 08570 * @retval None 08571 */ 08572 __STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx) 08573 { 08574 CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER); 08575 } 08576 08577 /** 08578 * @brief Indicate whether the burst mode period interrupt is enabled. 08579 * @rmtoll IER BMPERIE LL_HRTIM_IsEnabledIT_BMPER 08580 * @param HRTIMx High Resolution Timer instance 08581 * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0). 08582 */ 08583 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx) 08584 { 08585 return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL); 08586 } 08587 08588 /** 08589 * @brief Enable the synchronization input interrupt. 08590 * @rmtoll MDIER SYNCIE LL_HRTIM_EnableIT_SYNC 08591 * @param HRTIMx High Resolution Timer instance 08592 * @retval None 08593 */ 08594 __STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx) 08595 { 08596 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); 08597 } 08598 08599 /** 08600 * @brief Disable the synchronization input interrupt. 08601 * @rmtoll MDIER SYNCIE LL_HRTIM_DisableIT_SYNC 08602 * @param HRTIMx High Resolution Timer instance 08603 * @retval None 08604 */ 08605 __STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx) 08606 { 08607 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE); 08608 } 08609 08610 /** 08611 * @brief Indicate whether the synchronization input interrupt is enabled. 08612 * @rmtoll MDIER SYNCIE LL_HRTIM_IsEnabledIT_SYNC 08613 * @param HRTIMx High Resolution Timer instance 08614 * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0). 08615 */ 08616 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx) 08617 { 08618 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL); 08619 } 08620 08621 /** 08622 * @brief Enable the update interrupt for a given timer. 08623 * @rmtoll MDIER MUPDIE LL_HRTIM_EnableIT_UPDATE\n 08624 * TIMxDIER UPDIE LL_HRTIM_EnableIT_UPDATE 08625 * @param HRTIMx High Resolution Timer instance 08626 * @param Timer This parameter can be one of the following values: 08627 * @arg @ref LL_HRTIM_TIMER_MASTER 08628 * @arg @ref LL_HRTIM_TIMER_A 08629 * @arg @ref LL_HRTIM_TIMER_B 08630 * @arg @ref LL_HRTIM_TIMER_C 08631 * @arg @ref LL_HRTIM_TIMER_D 08632 * @arg @ref LL_HRTIM_TIMER_E 08633 * @retval None 08634 */ 08635 __STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08636 { 08637 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08638 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08639 REG_OFFSET_TAB_TIMER[iTimer])); 08640 SET_BIT(*pReg, HRTIM_MDIER_MUPDIE); 08641 } 08642 08643 /** 08644 * @brief Disable the update interrupt for a given timer. 08645 * @rmtoll MDIER MUPDIE LL_HRTIM_DisableIT_UPDATE\n 08646 * TIMxDIER UPDIE LL_HRTIM_DisableIT_UPDATE 08647 * @param HRTIMx High Resolution Timer instance 08648 * @param Timer This parameter can be one of the following values: 08649 * @arg @ref LL_HRTIM_TIMER_MASTER 08650 * @arg @ref LL_HRTIM_TIMER_A 08651 * @arg @ref LL_HRTIM_TIMER_B 08652 * @arg @ref LL_HRTIM_TIMER_C 08653 * @arg @ref LL_HRTIM_TIMER_D 08654 * @arg @ref LL_HRTIM_TIMER_E 08655 * @retval None 08656 */ 08657 __STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08658 { 08659 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08660 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08661 REG_OFFSET_TAB_TIMER[iTimer])); 08662 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE); 08663 } 08664 08665 /** 08666 * @brief Indicate whether the update interrupt is enabled for a given timer. 08667 * @rmtoll MDIER MUPDIE LL_HRTIM_IsEnabledIT_UPDATE\n 08668 * TIMxDIER UPDIE LL_HRTIM_IsEnabledIT_UPDATE 08669 * @param HRTIMx High Resolution Timer instance 08670 * @param Timer This parameter can be one of the following values: 08671 * @arg @ref LL_HRTIM_TIMER_MASTER 08672 * @arg @ref LL_HRTIM_TIMER_A 08673 * @arg @ref LL_HRTIM_TIMER_B 08674 * @arg @ref LL_HRTIM_TIMER_C 08675 * @arg @ref LL_HRTIM_TIMER_D 08676 * @arg @ref LL_HRTIM_TIMER_E 08677 * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 08678 */ 08679 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08680 { 08681 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08682 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08683 REG_OFFSET_TAB_TIMER[iTimer])); 08684 08685 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL); 08686 } 08687 08688 /** 08689 * @brief Enable the repetition interrupt for a given timer. 08690 * @rmtoll MDIER MREPIE LL_HRTIM_EnableIT_REP\n 08691 * TIMxDIER REPIE LL_HRTIM_EnableIT_REP 08692 * @param HRTIMx High Resolution Timer instance 08693 * @param Timer This parameter can be one of the following values: 08694 * @arg @ref LL_HRTIM_TIMER_MASTER 08695 * @arg @ref LL_HRTIM_TIMER_A 08696 * @arg @ref LL_HRTIM_TIMER_B 08697 * @arg @ref LL_HRTIM_TIMER_C 08698 * @arg @ref LL_HRTIM_TIMER_D 08699 * @arg @ref LL_HRTIM_TIMER_E 08700 * @retval None 08701 */ 08702 __STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08703 { 08704 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08705 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08706 REG_OFFSET_TAB_TIMER[iTimer])); 08707 SET_BIT(*pReg, HRTIM_MDIER_MREPIE); 08708 } 08709 08710 /** 08711 * @brief Disable the repetition interrupt for a given timer. 08712 * @rmtoll MDIER MREPIE LL_HRTIM_DisableIT_REP\n 08713 * TIMxDIER REPIE LL_HRTIM_DisableIT_REP 08714 * @param HRTIMx High Resolution Timer instance 08715 * @param Timer This parameter can be one of the following values: 08716 * @arg @ref LL_HRTIM_TIMER_MASTER 08717 * @arg @ref LL_HRTIM_TIMER_A 08718 * @arg @ref LL_HRTIM_TIMER_B 08719 * @arg @ref LL_HRTIM_TIMER_C 08720 * @arg @ref LL_HRTIM_TIMER_D 08721 * @arg @ref LL_HRTIM_TIMER_E 08722 * @retval None 08723 */ 08724 __STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08725 { 08726 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08727 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08728 REG_OFFSET_TAB_TIMER[iTimer])); 08729 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE); 08730 } 08731 08732 /** 08733 * @brief Indicate whether the repetition interrupt is enabled for a given timer. 08734 * @rmtoll MDIER MREPIE LL_HRTIM_IsEnabledIT_REP\n 08735 * TIMxDIER REPIE LL_HRTIM_IsEnabledIT_REP 08736 * @param HRTIMx High Resolution Timer instance 08737 * @param Timer This parameter can be one of the following values: 08738 * @arg @ref LL_HRTIM_TIMER_MASTER 08739 * @arg @ref LL_HRTIM_TIMER_A 08740 * @arg @ref LL_HRTIM_TIMER_B 08741 * @arg @ref LL_HRTIM_TIMER_C 08742 * @arg @ref LL_HRTIM_TIMER_D 08743 * @arg @ref LL_HRTIM_TIMER_E 08744 * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 08745 */ 08746 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08747 { 08748 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08749 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08750 REG_OFFSET_TAB_TIMER[iTimer])); 08751 08752 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL); 08753 } 08754 08755 /** 08756 * @brief Enable the compare 1 interrupt for a given timer. 08757 * @rmtoll MDIER MCMP1IE LL_HRTIM_EnableIT_CMP1\n 08758 * TIMxDIER CMP1IE LL_HRTIM_EnableIT_CMP1 08759 * @param HRTIMx High Resolution Timer instance 08760 * @param Timer This parameter can be one of the following values: 08761 * @arg @ref LL_HRTIM_TIMER_MASTER 08762 * @arg @ref LL_HRTIM_TIMER_A 08763 * @arg @ref LL_HRTIM_TIMER_B 08764 * @arg @ref LL_HRTIM_TIMER_C 08765 * @arg @ref LL_HRTIM_TIMER_D 08766 * @arg @ref LL_HRTIM_TIMER_E 08767 * @retval None 08768 */ 08769 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08770 { 08771 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08772 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08773 REG_OFFSET_TAB_TIMER[iTimer])); 08774 SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE); 08775 } 08776 08777 /** 08778 * @brief Disable the compare 1 interrupt for a given timer. 08779 * @rmtoll MDIER MCMP1IE LL_HRTIM_DisableIT_CMP1\n 08780 * TIMxDIER CMP1IE LL_HRTIM_DisableIT_CMP1 08781 * @param HRTIMx High Resolution Timer instance 08782 * @param Timer This parameter can be one of the following values: 08783 * @arg @ref LL_HRTIM_TIMER_MASTER 08784 * @arg @ref LL_HRTIM_TIMER_A 08785 * @arg @ref LL_HRTIM_TIMER_B 08786 * @arg @ref LL_HRTIM_TIMER_C 08787 * @arg @ref LL_HRTIM_TIMER_D 08788 * @arg @ref LL_HRTIM_TIMER_E 08789 * @retval None 08790 */ 08791 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08792 { 08793 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08794 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08795 REG_OFFSET_TAB_TIMER[iTimer])); 08796 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE); 08797 } 08798 08799 /** 08800 * @brief Indicate whether the compare 1 interrupt is enabled for a given timer. 08801 * @rmtoll MDIER MCMP1IE LL_HRTIM_IsEnabledIT_CMP1\n 08802 * TIMxDIER CMP1IE LL_HRTIM_IsEnabledIT_CMP1 08803 * @param HRTIMx High Resolution Timer instance 08804 * @param Timer This parameter can be one of the following values: 08805 * @arg @ref LL_HRTIM_TIMER_MASTER 08806 * @arg @ref LL_HRTIM_TIMER_A 08807 * @arg @ref LL_HRTIM_TIMER_B 08808 * @arg @ref LL_HRTIM_TIMER_C 08809 * @arg @ref LL_HRTIM_TIMER_D 08810 * @arg @ref LL_HRTIM_TIMER_E 08811 * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 08812 */ 08813 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08814 { 08815 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08816 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08817 REG_OFFSET_TAB_TIMER[iTimer])); 08818 08819 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL); 08820 } 08821 08822 /** 08823 * @brief Enable the compare 2 interrupt for a given timer. 08824 * @rmtoll MDIER MCMP2IE LL_HRTIM_EnableIT_CMP2\n 08825 * TIMxDIER CMP2IE LL_HRTIM_EnableIT_CMP2 08826 * @param HRTIMx High Resolution Timer instance 08827 * @param Timer This parameter can be one of the following values: 08828 * @arg @ref LL_HRTIM_TIMER_MASTER 08829 * @arg @ref LL_HRTIM_TIMER_A 08830 * @arg @ref LL_HRTIM_TIMER_B 08831 * @arg @ref LL_HRTIM_TIMER_C 08832 * @arg @ref LL_HRTIM_TIMER_D 08833 * @arg @ref LL_HRTIM_TIMER_E 08834 * @retval None 08835 */ 08836 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08837 { 08838 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08839 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08840 REG_OFFSET_TAB_TIMER[iTimer])); 08841 SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE); 08842 } 08843 08844 /** 08845 * @brief Disable the compare 2 interrupt for a given timer. 08846 * @rmtoll MDIER MCMP2IE LL_HRTIM_DisableIT_CMP2\n 08847 * TIMxDIER CMP2IE LL_HRTIM_DisableIT_CMP2 08848 * @param HRTIMx High Resolution Timer instance 08849 * @param Timer This parameter can be one of the following values: 08850 * @arg @ref LL_HRTIM_TIMER_MASTER 08851 * @arg @ref LL_HRTIM_TIMER_A 08852 * @arg @ref LL_HRTIM_TIMER_B 08853 * @arg @ref LL_HRTIM_TIMER_C 08854 * @arg @ref LL_HRTIM_TIMER_D 08855 * @arg @ref LL_HRTIM_TIMER_E 08856 * @retval None 08857 */ 08858 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08859 { 08860 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08861 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08862 REG_OFFSET_TAB_TIMER[iTimer])); 08863 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE); 08864 } 08865 08866 /** 08867 * @brief Indicate whether the compare 2 interrupt is enabled for a given timer. 08868 * @rmtoll MDIER MCMP2IE LL_HRTIM_IsEnabledIT_CMP2\n 08869 * TIMxDIER CMP2IE LL_HRTIM_IsEnabledIT_CMP2 08870 * @param HRTIMx High Resolution Timer instance 08871 * @param Timer This parameter can be one of the following values: 08872 * @arg @ref LL_HRTIM_TIMER_MASTER 08873 * @arg @ref LL_HRTIM_TIMER_A 08874 * @arg @ref LL_HRTIM_TIMER_B 08875 * @arg @ref LL_HRTIM_TIMER_C 08876 * @arg @ref LL_HRTIM_TIMER_D 08877 * @arg @ref LL_HRTIM_TIMER_E 08878 * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 08879 */ 08880 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08881 { 08882 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08883 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08884 REG_OFFSET_TAB_TIMER[iTimer])); 08885 08886 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL); 08887 } 08888 08889 /** 08890 * @brief Enable the compare 3 interrupt for a given timer. 08891 * @rmtoll MDIER MCMP3IE LL_HRTIM_EnableIT_CMP3\n 08892 * TIMxDIER CMP3IE LL_HRTIM_EnableIT_CMP3 08893 * @param HRTIMx High Resolution Timer instance 08894 * @param Timer This parameter can be one of the following values: 08895 * @arg @ref LL_HRTIM_TIMER_MASTER 08896 * @arg @ref LL_HRTIM_TIMER_A 08897 * @arg @ref LL_HRTIM_TIMER_B 08898 * @arg @ref LL_HRTIM_TIMER_C 08899 * @arg @ref LL_HRTIM_TIMER_D 08900 * @arg @ref LL_HRTIM_TIMER_E 08901 * @retval None 08902 */ 08903 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08904 { 08905 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08906 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08907 REG_OFFSET_TAB_TIMER[iTimer])); 08908 SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE); 08909 } 08910 08911 /** 08912 * @brief Disable the compare 3 interrupt for a given timer. 08913 * @rmtoll MDIER MCMP3IE LL_HRTIM_DisableIT_CMP3\n 08914 * TIMxDIER CMP3IE LL_HRTIM_DisableIT_CMP3 08915 * @param HRTIMx High Resolution Timer instance 08916 * @param Timer This parameter can be one of the following values: 08917 * @arg @ref LL_HRTIM_TIMER_MASTER 08918 * @arg @ref LL_HRTIM_TIMER_A 08919 * @arg @ref LL_HRTIM_TIMER_B 08920 * @arg @ref LL_HRTIM_TIMER_C 08921 * @arg @ref LL_HRTIM_TIMER_D 08922 * @arg @ref LL_HRTIM_TIMER_E 08923 * @retval None 08924 */ 08925 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08926 { 08927 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08928 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08929 REG_OFFSET_TAB_TIMER[iTimer])); 08930 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE); 08931 } 08932 08933 /** 08934 * @brief Indicate whether the compare 3 interrupt is enabled for a given timer. 08935 * @rmtoll MDIER MCMP3IE LL_HRTIM_IsEnabledIT_CMP3\n 08936 * TIMxDIER CMP3IE LL_HRTIM_IsEnabledIT_CMP3 08937 * @param HRTIMx High Resolution Timer instance 08938 * @param Timer This parameter can be one of the following values: 08939 * @arg @ref LL_HRTIM_TIMER_MASTER 08940 * @arg @ref LL_HRTIM_TIMER_A 08941 * @arg @ref LL_HRTIM_TIMER_B 08942 * @arg @ref LL_HRTIM_TIMER_C 08943 * @arg @ref LL_HRTIM_TIMER_D 08944 * @arg @ref LL_HRTIM_TIMER_E 08945 * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 08946 */ 08947 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08948 { 08949 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08950 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08951 REG_OFFSET_TAB_TIMER[iTimer])); 08952 08953 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL); 08954 } 08955 08956 /** 08957 * @brief Enable the compare 4 interrupt for a given timer. 08958 * @rmtoll MDIER MCMP4IE LL_HRTIM_EnableIT_CMP4\n 08959 * TIMxDIER CMP4IE LL_HRTIM_EnableIT_CMP4 08960 * @param HRTIMx High Resolution Timer instance 08961 * @param Timer This parameter can be one of the following values: 08962 * @arg @ref LL_HRTIM_TIMER_MASTER 08963 * @arg @ref LL_HRTIM_TIMER_A 08964 * @arg @ref LL_HRTIM_TIMER_B 08965 * @arg @ref LL_HRTIM_TIMER_C 08966 * @arg @ref LL_HRTIM_TIMER_D 08967 * @arg @ref LL_HRTIM_TIMER_E 08968 * @retval None 08969 */ 08970 __STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08971 { 08972 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08973 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08974 REG_OFFSET_TAB_TIMER[iTimer])); 08975 SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE); 08976 } 08977 08978 /** 08979 * @brief Disable the compare 4 interrupt for a given timer. 08980 * @rmtoll MDIER MCMP4IE LL_HRTIM_DisableIT_CMP4\n 08981 * TIMxDIER CMP4IE LL_HRTIM_DisableIT_CMP4 08982 * @param HRTIMx High Resolution Timer instance 08983 * @param Timer This parameter can be one of the following values: 08984 * @arg @ref LL_HRTIM_TIMER_MASTER 08985 * @arg @ref LL_HRTIM_TIMER_A 08986 * @arg @ref LL_HRTIM_TIMER_B 08987 * @arg @ref LL_HRTIM_TIMER_C 08988 * @arg @ref LL_HRTIM_TIMER_D 08989 * @arg @ref LL_HRTIM_TIMER_E 08990 * @retval None 08991 */ 08992 __STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 08993 { 08994 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 08995 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 08996 REG_OFFSET_TAB_TIMER[iTimer])); 08997 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE); 08998 } 08999 09000 /** 09001 * @brief Indicate whether the compare 4 interrupt is enabled for a given timer. 09002 * @rmtoll MDIER MCMP4IE LL_HRTIM_IsEnabledIT_CMP4\n 09003 * TIMxDIER CMP4IE LL_HRTIM_IsEnabledIT_CMP4 09004 * @param HRTIMx High Resolution Timer instance 09005 * @param Timer This parameter can be one of the following values: 09006 * @arg @ref LL_HRTIM_TIMER_MASTER 09007 * @arg @ref LL_HRTIM_TIMER_A 09008 * @arg @ref LL_HRTIM_TIMER_B 09009 * @arg @ref LL_HRTIM_TIMER_C 09010 * @arg @ref LL_HRTIM_TIMER_D 09011 * @arg @ref LL_HRTIM_TIMER_E 09012 * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 09013 */ 09014 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09015 { 09016 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09017 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09018 REG_OFFSET_TAB_TIMER[iTimer])); 09019 09020 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL); 09021 } 09022 09023 /** 09024 * @brief Enable the capture 1 interrupt for a given timer. 09025 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_EnableIT_CPT1 09026 * @param HRTIMx High Resolution Timer instance 09027 * @param Timer This parameter can be one of the following values: 09028 * @arg @ref LL_HRTIM_TIMER_A 09029 * @arg @ref LL_HRTIM_TIMER_B 09030 * @arg @ref LL_HRTIM_TIMER_C 09031 * @arg @ref LL_HRTIM_TIMER_D 09032 * @arg @ref LL_HRTIM_TIMER_E 09033 * @retval None 09034 */ 09035 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09036 { 09037 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09038 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09039 REG_OFFSET_TAB_TIMER[iTimer])); 09040 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); 09041 } 09042 09043 /** 09044 * @brief Enable the capture 1 interrupt for a given timer. 09045 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_DisableIT_CPT1 09046 * @param HRTIMx High Resolution Timer instance 09047 * @param Timer This parameter can be one of the following values: 09048 * @arg @ref LL_HRTIM_TIMER_A 09049 * @arg @ref LL_HRTIM_TIMER_B 09050 * @arg @ref LL_HRTIM_TIMER_C 09051 * @arg @ref LL_HRTIM_TIMER_D 09052 * @arg @ref LL_HRTIM_TIMER_E 09053 * @retval None 09054 */ 09055 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09056 { 09057 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09058 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09059 REG_OFFSET_TAB_TIMER[iTimer])); 09060 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE); 09061 } 09062 09063 /** 09064 * @brief Indicate whether the capture 1 interrupt is enabled for a given timer. 09065 * @rmtoll TIMxDIER CPT1IE LL_HRTIM_IsEnabledIT_CPT1 09066 * @param HRTIMx High Resolution Timer instance 09067 * @param Timer This parameter can be one of the following values: 09068 * @arg @ref LL_HRTIM_TIMER_A 09069 * @arg @ref LL_HRTIM_TIMER_B 09070 * @arg @ref LL_HRTIM_TIMER_C 09071 * @arg @ref LL_HRTIM_TIMER_D 09072 * @arg @ref LL_HRTIM_TIMER_E 09073 * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0). 09074 */ 09075 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09076 { 09077 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09078 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09079 REG_OFFSET_TAB_TIMER[iTimer])); 09080 09081 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL); 09082 } 09083 09084 /** 09085 * @brief Enable the capture 2 interrupt for a given timer. 09086 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_EnableIT_CPT2 09087 * @param HRTIMx High Resolution Timer instance 09088 * @param Timer This parameter can be one of the following values: 09089 * @arg @ref LL_HRTIM_TIMER_A 09090 * @arg @ref LL_HRTIM_TIMER_B 09091 * @arg @ref LL_HRTIM_TIMER_C 09092 * @arg @ref LL_HRTIM_TIMER_D 09093 * @arg @ref LL_HRTIM_TIMER_E 09094 * @retval None 09095 */ 09096 __STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09097 { 09098 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09099 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09100 REG_OFFSET_TAB_TIMER[iTimer])); 09101 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); 09102 } 09103 09104 /** 09105 * @brief Enable the capture 2 interrupt for a given timer. 09106 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_DisableIT_CPT2 09107 * @param HRTIMx High Resolution Timer instance 09108 * @param Timer This parameter can be one of the following values: 09109 * @arg @ref LL_HRTIM_TIMER_A 09110 * @arg @ref LL_HRTIM_TIMER_B 09111 * @arg @ref LL_HRTIM_TIMER_C 09112 * @arg @ref LL_HRTIM_TIMER_D 09113 * @arg @ref LL_HRTIM_TIMER_E 09114 * @retval None 09115 */ 09116 __STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09117 { 09118 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09119 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09120 REG_OFFSET_TAB_TIMER[iTimer])); 09121 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE); 09122 } 09123 09124 /** 09125 * @brief Indicate whether the capture 2 interrupt is enabled for a given timer. 09126 * @rmtoll TIMxDIER CPT2IE LL_HRTIM_IsEnabledIT_CPT2 09127 * @param HRTIMx High Resolution Timer instance 09128 * @param Timer This parameter can be one of the following values: 09129 * @arg @ref LL_HRTIM_TIMER_A 09130 * @arg @ref LL_HRTIM_TIMER_B 09131 * @arg @ref LL_HRTIM_TIMER_C 09132 * @arg @ref LL_HRTIM_TIMER_D 09133 * @arg @ref LL_HRTIM_TIMER_E 09134 * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0). 09135 */ 09136 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09137 { 09138 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09139 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09140 REG_OFFSET_TAB_TIMER[iTimer])); 09141 09142 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL); 09143 } 09144 09145 /** 09146 * @brief Enable the output 1 set interrupt for a given timer. 09147 * @rmtoll TIMxDIER SET1IE LL_HRTIM_EnableIT_SET1 09148 * @param HRTIMx High Resolution Timer instance 09149 * @param Timer This parameter can be one of the following values: 09150 * @arg @ref LL_HRTIM_TIMER_A 09151 * @arg @ref LL_HRTIM_TIMER_B 09152 * @arg @ref LL_HRTIM_TIMER_C 09153 * @arg @ref LL_HRTIM_TIMER_D 09154 * @arg @ref LL_HRTIM_TIMER_E 09155 * @retval None 09156 */ 09157 __STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09158 { 09159 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09160 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09161 REG_OFFSET_TAB_TIMER[iTimer])); 09162 SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE); 09163 } 09164 09165 /** 09166 * @brief Disable the output 1 set interrupt for a given timer. 09167 * @rmtoll TIMxDIER SET1IE LL_HRTIM_DisableIT_SET1 09168 * @param HRTIMx High Resolution Timer instance 09169 * @param Timer This parameter can be one of the following values: 09170 * @arg @ref LL_HRTIM_TIMER_A 09171 * @arg @ref LL_HRTIM_TIMER_B 09172 * @arg @ref LL_HRTIM_TIMER_C 09173 * @arg @ref LL_HRTIM_TIMER_D 09174 * @arg @ref LL_HRTIM_TIMER_E 09175 * @retval None 09176 */ 09177 __STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09178 { 09179 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09180 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09181 REG_OFFSET_TAB_TIMER[iTimer])); 09182 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE); 09183 } 09184 09185 /** 09186 * @brief Indicate whether the output 1 set interrupt is enabled for a given timer. 09187 * @rmtoll TIMxDIER SET1IE LL_HRTIM_IsEnabledIT_SET1 09188 * @param HRTIMx High Resolution Timer instance 09189 * @param Timer This parameter can be one of the following values: 09190 * @arg @ref LL_HRTIM_TIMER_A 09191 * @arg @ref LL_HRTIM_TIMER_B 09192 * @arg @ref LL_HRTIM_TIMER_C 09193 * @arg @ref LL_HRTIM_TIMER_D 09194 * @arg @ref LL_HRTIM_TIMER_E 09195 * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0). 09196 */ 09197 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09198 { 09199 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09200 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09201 REG_OFFSET_TAB_TIMER[iTimer])); 09202 09203 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL); 09204 } 09205 09206 /** 09207 * @brief Enable the output 1 reset interrupt for a given timer. 09208 * @rmtoll TIMxDIER RST1IE LL_HRTIM_EnableIT_RST1 09209 * @param HRTIMx High Resolution Timer instance 09210 * @param Timer This parameter can be one of the following values: 09211 * @arg @ref LL_HRTIM_TIMER_A 09212 * @arg @ref LL_HRTIM_TIMER_B 09213 * @arg @ref LL_HRTIM_TIMER_C 09214 * @arg @ref LL_HRTIM_TIMER_D 09215 * @arg @ref LL_HRTIM_TIMER_E 09216 * @retval None 09217 */ 09218 __STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09219 { 09220 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09221 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09222 REG_OFFSET_TAB_TIMER[iTimer])); 09223 SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE); 09224 } 09225 09226 /** 09227 * @brief Disable the output 1 reset interrupt for a given timer. 09228 * @rmtoll TIMxDIER RST1IE LL_HRTIM_DisableIT_RST1 09229 * @param HRTIMx High Resolution Timer instance 09230 * @param Timer This parameter can be one of the following values: 09231 * @arg @ref LL_HRTIM_TIMER_A 09232 * @arg @ref LL_HRTIM_TIMER_B 09233 * @arg @ref LL_HRTIM_TIMER_C 09234 * @arg @ref LL_HRTIM_TIMER_D 09235 * @arg @ref LL_HRTIM_TIMER_E 09236 * @retval None 09237 */ 09238 __STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09239 { 09240 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09241 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09242 REG_OFFSET_TAB_TIMER[iTimer])); 09243 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE); 09244 } 09245 09246 /** 09247 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer. 09248 * @rmtoll TIMxDIER RST1IE LL_HRTIM_IsEnabledIT_RST1 09249 * @param HRTIMx High Resolution Timer instance 09250 * @param Timer This parameter can be one of the following values: 09251 * @arg @ref LL_HRTIM_TIMER_A 09252 * @arg @ref LL_HRTIM_TIMER_B 09253 * @arg @ref LL_HRTIM_TIMER_C 09254 * @arg @ref LL_HRTIM_TIMER_D 09255 * @arg @ref LL_HRTIM_TIMER_E 09256 * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0). 09257 */ 09258 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09259 { 09260 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09261 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09262 REG_OFFSET_TAB_TIMER[iTimer])); 09263 09264 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL); 09265 } 09266 09267 /** 09268 * @brief Enable the output 2 set interrupt for a given timer. 09269 * @rmtoll TIMxDIER SET2IE LL_HRTIM_EnableIT_SET2 09270 * @param HRTIMx High Resolution Timer instance 09271 * @param Timer This parameter can be one of the following values: 09272 * @arg @ref LL_HRTIM_TIMER_A 09273 * @arg @ref LL_HRTIM_TIMER_B 09274 * @arg @ref LL_HRTIM_TIMER_C 09275 * @arg @ref LL_HRTIM_TIMER_D 09276 * @arg @ref LL_HRTIM_TIMER_E 09277 * @retval None 09278 */ 09279 __STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09280 { 09281 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09282 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09283 REG_OFFSET_TAB_TIMER[iTimer])); 09284 SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE); 09285 } 09286 09287 /** 09288 * @brief Disable the output 2 set interrupt for a given timer. 09289 * @rmtoll TIMxDIER SET2IE LL_HRTIM_DisableIT_SET2 09290 * @param HRTIMx High Resolution Timer instance 09291 * @param Timer This parameter can be one of the following values: 09292 * @arg @ref LL_HRTIM_TIMER_A 09293 * @arg @ref LL_HRTIM_TIMER_B 09294 * @arg @ref LL_HRTIM_TIMER_C 09295 * @arg @ref LL_HRTIM_TIMER_D 09296 * @arg @ref LL_HRTIM_TIMER_E 09297 * @retval None 09298 */ 09299 __STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09300 { 09301 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09302 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09303 REG_OFFSET_TAB_TIMER[iTimer])); 09304 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE); 09305 } 09306 09307 /** 09308 * @brief Indicate whether the output 2 set interrupt is enabled for a given timer. 09309 * @rmtoll TIMxDIER SET2IE LL_HRTIM_IsEnabledIT_SET2 09310 * @param HRTIMx High Resolution Timer instance 09311 * @param Timer This parameter can be one of the following values: 09312 * @arg @ref LL_HRTIM_TIMER_A 09313 * @arg @ref LL_HRTIM_TIMER_B 09314 * @arg @ref LL_HRTIM_TIMER_C 09315 * @arg @ref LL_HRTIM_TIMER_D 09316 * @arg @ref LL_HRTIM_TIMER_E 09317 * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0). 09318 */ 09319 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09320 { 09321 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09322 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09323 REG_OFFSET_TAB_TIMER[iTimer])); 09324 09325 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL); 09326 } 09327 09328 /** 09329 * @brief Enable the output 2 reset interrupt for a given timer. 09330 * @rmtoll TIMxDIER RST2IE LL_HRTIM_EnableIT_RST2 09331 * @param HRTIMx High Resolution Timer instance 09332 * @param Timer This parameter can be one of the following values: 09333 * @arg @ref LL_HRTIM_TIMER_A 09334 * @arg @ref LL_HRTIM_TIMER_B 09335 * @arg @ref LL_HRTIM_TIMER_C 09336 * @arg @ref LL_HRTIM_TIMER_D 09337 * @arg @ref LL_HRTIM_TIMER_E 09338 * @retval None 09339 */ 09340 __STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09341 { 09342 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09343 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09344 REG_OFFSET_TAB_TIMER[iTimer])); 09345 SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE); 09346 } 09347 09348 /** 09349 * @brief Disable the output 2 reset interrupt for a given timer. 09350 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2 09351 * @param HRTIMx High Resolution Timer instance 09352 * @param Timer This parameter can be one of the following values: 09353 * @arg @ref LL_HRTIM_TIMER_A 09354 * @arg @ref LL_HRTIM_TIMER_B 09355 * @arg @ref LL_HRTIM_TIMER_C 09356 * @arg @ref LL_HRTIM_TIMER_D 09357 * @arg @ref LL_HRTIM_TIMER_E 09358 * @retval None 09359 */ 09360 __STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09361 { 09362 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09363 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09364 REG_OFFSET_TAB_TIMER[iTimer])); 09365 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE); 09366 } 09367 09368 /** 09369 * @brief Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer. 09370 * @rmtoll TIMxDIER RST2IE LL_HRTIM_DisableIT_RST2 09371 * @param HRTIMx High Resolution Timer instance 09372 * @param Timer This parameter can be one of the following values: 09373 * @arg @ref LL_HRTIM_TIMER_A 09374 * @arg @ref LL_HRTIM_TIMER_B 09375 * @arg @ref LL_HRTIM_TIMER_C 09376 * @arg @ref LL_HRTIM_TIMER_D 09377 * @arg @ref LL_HRTIM_TIMER_E 09378 * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0). 09379 */ 09380 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09381 { 09382 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09383 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09384 REG_OFFSET_TAB_TIMER[iTimer])); 09385 09386 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL); 09387 } 09388 09389 /** 09390 * @brief Enable the reset/roll-over interrupt for a given timer. 09391 * @rmtoll TIMxDIER RSTIE LL_HRTIM_EnableIT_RST 09392 * @param HRTIMx High Resolution Timer instance 09393 * @param Timer This parameter can be one of the following values: 09394 * @arg @ref LL_HRTIM_TIMER_A 09395 * @arg @ref LL_HRTIM_TIMER_B 09396 * @arg @ref LL_HRTIM_TIMER_C 09397 * @arg @ref LL_HRTIM_TIMER_D 09398 * @arg @ref LL_HRTIM_TIMER_E 09399 * @retval None 09400 */ 09401 __STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09402 { 09403 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09404 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09405 REG_OFFSET_TAB_TIMER[iTimer])); 09406 SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE); 09407 } 09408 09409 /** 09410 * @brief Disable the reset/roll-over interrupt for a given timer. 09411 * @rmtoll TIMxDIER RSTIE LL_HRTIM_DisableIT_RST 09412 * @param HRTIMx High Resolution Timer instance 09413 * @param Timer This parameter can be one of the following values: 09414 * @arg @ref LL_HRTIM_TIMER_A 09415 * @arg @ref LL_HRTIM_TIMER_B 09416 * @arg @ref LL_HRTIM_TIMER_C 09417 * @arg @ref LL_HRTIM_TIMER_D 09418 * @arg @ref LL_HRTIM_TIMER_E 09419 * @retval None 09420 */ 09421 __STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09422 { 09423 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09424 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09425 REG_OFFSET_TAB_TIMER[iTimer])); 09426 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE); 09427 } 09428 09429 /** 09430 * @brief Indicate whether the reset/roll-over interrupt is enabled for a given timer. 09431 * @rmtoll TIMxDIER RSTIE LL_HRTIM_IsEnabledIT_RST 09432 * @param HRTIMx High Resolution Timer instance 09433 * @param Timer This parameter can be one of the following values: 09434 * @arg @ref LL_HRTIM_TIMER_A 09435 * @arg @ref LL_HRTIM_TIMER_B 09436 * @arg @ref LL_HRTIM_TIMER_C 09437 * @arg @ref LL_HRTIM_TIMER_D 09438 * @arg @ref LL_HRTIM_TIMER_E 09439 * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0). 09440 */ 09441 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09442 { 09443 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09444 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09445 REG_OFFSET_TAB_TIMER[iTimer])); 09446 09447 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL); 09448 } 09449 09450 /** 09451 * @brief Enable the delayed protection interrupt for a given timer. 09452 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_EnableIT_DLYPRT 09453 * @param HRTIMx High Resolution Timer instance 09454 * @param Timer This parameter can be one of the following values: 09455 * @arg @ref LL_HRTIM_TIMER_A 09456 * @arg @ref LL_HRTIM_TIMER_B 09457 * @arg @ref LL_HRTIM_TIMER_C 09458 * @arg @ref LL_HRTIM_TIMER_D 09459 * @arg @ref LL_HRTIM_TIMER_E 09460 * @retval None 09461 */ 09462 __STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09463 { 09464 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09465 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09466 REG_OFFSET_TAB_TIMER[iTimer])); 09467 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); 09468 } 09469 09470 /** 09471 * @brief Disable the delayed protection interrupt for a given timer. 09472 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_DisableIT_DLYPRT 09473 * @param HRTIMx High Resolution Timer instance 09474 * @param Timer This parameter can be one of the following values: 09475 * @arg @ref LL_HRTIM_TIMER_A 09476 * @arg @ref LL_HRTIM_TIMER_B 09477 * @arg @ref LL_HRTIM_TIMER_C 09478 * @arg @ref LL_HRTIM_TIMER_D 09479 * @arg @ref LL_HRTIM_TIMER_E 09480 * @retval None 09481 */ 09482 __STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09483 { 09484 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09485 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09486 REG_OFFSET_TAB_TIMER[iTimer])); 09487 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE); 09488 } 09489 09490 /** 09491 * @brief Indicate whether the delayed protection interrupt is enabled for a given timer. 09492 * @rmtoll TIMxDIER DLYPRTIE LL_HRTIM_IsEnabledIT_DLYPRT 09493 * @param HRTIMx High Resolution Timer instance 09494 * @param Timer This parameter can be one of the following values: 09495 * @arg @ref LL_HRTIM_TIMER_A 09496 * @arg @ref LL_HRTIM_TIMER_B 09497 * @arg @ref LL_HRTIM_TIMER_C 09498 * @arg @ref LL_HRTIM_TIMER_D 09499 * @arg @ref LL_HRTIM_TIMER_E 09500 * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0). 09501 */ 09502 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09503 { 09504 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09505 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09506 REG_OFFSET_TAB_TIMER[iTimer])); 09507 09508 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL); 09509 } 09510 09511 /** 09512 * @} 09513 */ 09514 09515 /** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management 09516 * @{ 09517 */ 09518 09519 /** 09520 * @brief Enable the synchronization input DMA request. 09521 * @rmtoll MDIER SYNCDE LL_HRTIM_EnableDMAReq_SYNC 09522 * @param HRTIMx High Resolution Timer instance 09523 * @retval None 09524 */ 09525 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) 09526 { 09527 SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE); 09528 } 09529 09530 /** 09531 * @brief Disable the synchronization input DMA request 09532 * @rmtoll MDIER SYNCDE LL_HRTIM_DisableDMAReq_SYNC 09533 * @param HRTIMx High Resolution Timer instance 09534 * @retval None 09535 */ 09536 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) 09537 { 09538 CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE); 09539 } 09540 09541 /** 09542 * @brief Indicate whether the synchronization input DMA request is enabled. 09543 * @rmtoll MDIER SYNCDE LL_HRTIM_IsEnabledDMAReq_SYNC 09544 * @param HRTIMx High Resolution Timer instance 09545 * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0). 09546 */ 09547 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx) 09548 { 09549 return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL); 09550 } 09551 09552 /** 09553 * @brief Enable the update DMA request for a given timer. 09554 * @rmtoll MDIER MUPDDE LL_HRTIM_EnableDMAReq_UPDATE\n 09555 * TIMxDIER UPDDE LL_HRTIM_EnableDMAReq_UPDATE 09556 * @param HRTIMx High Resolution Timer instance 09557 * @param Timer This parameter can be one of the following values: 09558 * @arg @ref LL_HRTIM_TIMER_MASTER 09559 * @arg @ref LL_HRTIM_TIMER_A 09560 * @arg @ref LL_HRTIM_TIMER_B 09561 * @arg @ref LL_HRTIM_TIMER_C 09562 * @arg @ref LL_HRTIM_TIMER_D 09563 * @arg @ref LL_HRTIM_TIMER_E 09564 * @retval None 09565 */ 09566 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09567 { 09568 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09569 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09570 REG_OFFSET_TAB_TIMER[iTimer])); 09571 SET_BIT(*pReg, HRTIM_MDIER_MUPDDE); 09572 } 09573 09574 /** 09575 * @brief Disable the update DMA request for a given timer. 09576 * @rmtoll MDIER MUPDDE LL_HRTIM_DisableDMAReq_UPDATE\n 09577 * TIMxDIER UPDDE LL_HRTIM_DisableDMAReq_UPDATE 09578 * @param HRTIMx High Resolution Timer instance 09579 * @param Timer This parameter can be one of the following values: 09580 * @arg @ref LL_HRTIM_TIMER_MASTER 09581 * @arg @ref LL_HRTIM_TIMER_A 09582 * @arg @ref LL_HRTIM_TIMER_B 09583 * @arg @ref LL_HRTIM_TIMER_C 09584 * @arg @ref LL_HRTIM_TIMER_D 09585 * @arg @ref LL_HRTIM_TIMER_E 09586 * @retval None 09587 */ 09588 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09589 { 09590 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09591 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09592 REG_OFFSET_TAB_TIMER[iTimer])); 09593 CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE); 09594 } 09595 09596 /** 09597 * @brief Indicate whether the update DMA request is enabled for a given timer. 09598 * @rmtoll MDIER MUPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE\n 09599 * TIMxDIER UPDDE LL_HRTIM_IsEnabledDMAReq_UPDATE 09600 * @param HRTIMx High Resolution Timer instance 09601 * @param Timer This parameter can be one of the following values: 09602 * @arg @ref LL_HRTIM_TIMER_MASTER 09603 * @arg @ref LL_HRTIM_TIMER_A 09604 * @arg @ref LL_HRTIM_TIMER_B 09605 * @arg @ref LL_HRTIM_TIMER_C 09606 * @arg @ref LL_HRTIM_TIMER_D 09607 * @arg @ref LL_HRTIM_TIMER_E 09608 * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 09609 */ 09610 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09611 { 09612 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09613 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09614 REG_OFFSET_TAB_TIMER[iTimer])); 09615 09616 return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL); 09617 } 09618 09619 /** 09620 * @brief Enable the repetition DMA request for a given timer. 09621 * @rmtoll MDIER MREPDE LL_HRTIM_EnableDMAReq_REP\n 09622 * TIMxDIER REPDE LL_HRTIM_EnableDMAReq_REP 09623 * @param HRTIMx High Resolution Timer instance 09624 * @param Timer This parameter can be one of the following values: 09625 * @arg @ref LL_HRTIM_TIMER_MASTER 09626 * @arg @ref LL_HRTIM_TIMER_A 09627 * @arg @ref LL_HRTIM_TIMER_B 09628 * @arg @ref LL_HRTIM_TIMER_C 09629 * @arg @ref LL_HRTIM_TIMER_D 09630 * @arg @ref LL_HRTIM_TIMER_E 09631 * @retval None 09632 */ 09633 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09634 { 09635 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09636 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09637 REG_OFFSET_TAB_TIMER[iTimer])); 09638 SET_BIT(*pReg, HRTIM_MDIER_MREPDE); 09639 } 09640 09641 /** 09642 * @brief Disable the repetition DMA request for a given timer. 09643 * @rmtoll MDIER MREPDE LL_HRTIM_DisableDMAReq_REP\n 09644 * TIMxDIER REPDE LL_HRTIM_DisableDMAReq_REP 09645 * @param HRTIMx High Resolution Timer instance 09646 * @param Timer This parameter can be one of the following values: 09647 * @arg @ref LL_HRTIM_TIMER_MASTER 09648 * @arg @ref LL_HRTIM_TIMER_A 09649 * @arg @ref LL_HRTIM_TIMER_B 09650 * @arg @ref LL_HRTIM_TIMER_C 09651 * @arg @ref LL_HRTIM_TIMER_D 09652 * @arg @ref LL_HRTIM_TIMER_E 09653 * @retval None 09654 */ 09655 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09656 { 09657 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09658 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09659 REG_OFFSET_TAB_TIMER[iTimer])); 09660 CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE); 09661 } 09662 09663 /** 09664 * @brief Indicate whether the repetition DMA request is enabled for a given timer. 09665 * @rmtoll MDIER MREPDE LL_HRTIM_IsEnabledDMAReq_REP\n 09666 * TIMxDIER REPDE LL_HRTIM_IsEnabledDMAReq_REP 09667 * @param HRTIMx High Resolution Timer instance 09668 * @param Timer This parameter can be one of the following values: 09669 * @arg @ref LL_HRTIM_TIMER_MASTER 09670 * @arg @ref LL_HRTIM_TIMER_A 09671 * @arg @ref LL_HRTIM_TIMER_B 09672 * @arg @ref LL_HRTIM_TIMER_C 09673 * @arg @ref LL_HRTIM_TIMER_D 09674 * @arg @ref LL_HRTIM_TIMER_E 09675 * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 09676 */ 09677 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09678 { 09679 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09680 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09681 REG_OFFSET_TAB_TIMER[iTimer])); 09682 09683 return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL); 09684 } 09685 09686 /** 09687 * @brief Enable the compare 1 DMA request for a given timer. 09688 * @rmtoll MDIER MCMP1DE LL_HRTIM_EnableDMAReq_CMP1\n 09689 * TIMxDIER CMP1DE LL_HRTIM_EnableDMAReq_CMP1 09690 * @param HRTIMx High Resolution Timer instance 09691 * @param Timer This parameter can be one of the following values: 09692 * @arg @ref LL_HRTIM_TIMER_MASTER 09693 * @arg @ref LL_HRTIM_TIMER_A 09694 * @arg @ref LL_HRTIM_TIMER_B 09695 * @arg @ref LL_HRTIM_TIMER_C 09696 * @arg @ref LL_HRTIM_TIMER_D 09697 * @arg @ref LL_HRTIM_TIMER_E 09698 * @retval None 09699 */ 09700 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09701 { 09702 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09703 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09704 REG_OFFSET_TAB_TIMER[iTimer])); 09705 SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE); 09706 } 09707 09708 /** 09709 * @brief Disable the compare 1 DMA request for a given timer. 09710 * @rmtoll MDIER MCMP1DE LL_HRTIM_DisableDMAReq_CMP1\n 09711 * TIMxDIER CMP1DE LL_HRTIM_DisableDMAReq_CMP1 09712 * @param HRTIMx High Resolution Timer instance 09713 * @param Timer This parameter can be one of the following values: 09714 * @arg @ref LL_HRTIM_TIMER_MASTER 09715 * @arg @ref LL_HRTIM_TIMER_A 09716 * @arg @ref LL_HRTIM_TIMER_B 09717 * @arg @ref LL_HRTIM_TIMER_C 09718 * @arg @ref LL_HRTIM_TIMER_D 09719 * @arg @ref LL_HRTIM_TIMER_E 09720 * @retval None 09721 */ 09722 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09723 { 09724 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09725 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09726 REG_OFFSET_TAB_TIMER[iTimer])); 09727 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE); 09728 } 09729 09730 /** 09731 * @brief Indicate whether the compare 1 DMA request is enabled for a given timer. 09732 * @rmtoll MDIER MCMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1\n 09733 * TIMxDIER CMP1DE LL_HRTIM_IsEnabledDMAReq_CMP1 09734 * @param HRTIMx High Resolution Timer instance 09735 * @param Timer This parameter can be one of the following values: 09736 * @arg @ref LL_HRTIM_TIMER_MASTER 09737 * @arg @ref LL_HRTIM_TIMER_A 09738 * @arg @ref LL_HRTIM_TIMER_B 09739 * @arg @ref LL_HRTIM_TIMER_C 09740 * @arg @ref LL_HRTIM_TIMER_D 09741 * @arg @ref LL_HRTIM_TIMER_E 09742 * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 09743 */ 09744 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09745 { 09746 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09747 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09748 REG_OFFSET_TAB_TIMER[iTimer])); 09749 09750 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL); 09751 } 09752 09753 /** 09754 * @brief Enable the compare 2 DMA request for a given timer. 09755 * @rmtoll MDIER MCMP2DE LL_HRTIM_EnableDMAReq_CMP2\n 09756 * TIMxDIER CMP2DE LL_HRTIM_EnableDMAReq_CMP2 09757 * @param HRTIMx High Resolution Timer instance 09758 * @param Timer This parameter can be one of the following values: 09759 * @arg @ref LL_HRTIM_TIMER_MASTER 09760 * @arg @ref LL_HRTIM_TIMER_A 09761 * @arg @ref LL_HRTIM_TIMER_B 09762 * @arg @ref LL_HRTIM_TIMER_C 09763 * @arg @ref LL_HRTIM_TIMER_D 09764 * @arg @ref LL_HRTIM_TIMER_E 09765 * @retval None 09766 */ 09767 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09768 { 09769 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09770 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09771 REG_OFFSET_TAB_TIMER[iTimer])); 09772 SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE); 09773 } 09774 09775 /** 09776 * @brief Disable the compare 2 DMA request for a given timer. 09777 * @rmtoll MDIER MCMP2DE LL_HRTIM_DisableDMAReq_CMP2\n 09778 * TIMxDIER CMP2DE LL_HRTIM_DisableDMAReq_CMP2 09779 * @param HRTIMx High Resolution Timer instance 09780 * @param Timer This parameter can be one of the following values: 09781 * @arg @ref LL_HRTIM_TIMER_MASTER 09782 * @arg @ref LL_HRTIM_TIMER_A 09783 * @arg @ref LL_HRTIM_TIMER_B 09784 * @arg @ref LL_HRTIM_TIMER_C 09785 * @arg @ref LL_HRTIM_TIMER_D 09786 * @arg @ref LL_HRTIM_TIMER_E 09787 * @retval None 09788 */ 09789 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09790 { 09791 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09792 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09793 REG_OFFSET_TAB_TIMER[iTimer])); 09794 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE); 09795 } 09796 09797 /** 09798 * @brief Indicate whether the compare 2 DMA request is enabled for a given timer. 09799 * @rmtoll MDIER MCMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2\n 09800 * TIMxDIER CMP2DE LL_HRTIM_IsEnabledDMAReq_CMP2 09801 * @param HRTIMx High Resolution Timer instance 09802 * @param Timer This parameter can be one of the following values: 09803 * @arg @ref LL_HRTIM_TIMER_MASTER 09804 * @arg @ref LL_HRTIM_TIMER_A 09805 * @arg @ref LL_HRTIM_TIMER_B 09806 * @arg @ref LL_HRTIM_TIMER_C 09807 * @arg @ref LL_HRTIM_TIMER_D 09808 * @arg @ref LL_HRTIM_TIMER_E 09809 * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 09810 */ 09811 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09812 { 09813 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09814 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09815 REG_OFFSET_TAB_TIMER[iTimer])); 09816 09817 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL); 09818 } 09819 09820 /** 09821 * @brief Enable the compare 3 DMA request for a given timer. 09822 * @rmtoll MDIER MCMP3DE LL_HRTIM_EnableDMAReq_CMP3\n 09823 * TIMxDIER CMP3DE LL_HRTIM_EnableDMAReq_CMP3 09824 * @param HRTIMx High Resolution Timer instance 09825 * @param Timer This parameter can be one of the following values: 09826 * @arg @ref LL_HRTIM_TIMER_MASTER 09827 * @arg @ref LL_HRTIM_TIMER_A 09828 * @arg @ref LL_HRTIM_TIMER_B 09829 * @arg @ref LL_HRTIM_TIMER_C 09830 * @arg @ref LL_HRTIM_TIMER_D 09831 * @arg @ref LL_HRTIM_TIMER_E 09832 * @retval None 09833 */ 09834 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09835 { 09836 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09837 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09838 REG_OFFSET_TAB_TIMER[iTimer])); 09839 SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE); 09840 } 09841 09842 /** 09843 * @brief Disable the compare 3 DMA request for a given timer. 09844 * @rmtoll MDIER MCMP3DE LL_HRTIM_DisableDMAReq_CMP3\n 09845 * TIMxDIER CMP3DE LL_HRTIM_DisableDMAReq_CMP3 09846 * @param HRTIMx High Resolution Timer instance 09847 * @param Timer This parameter can be one of the following values: 09848 * @arg @ref LL_HRTIM_TIMER_MASTER 09849 * @arg @ref LL_HRTIM_TIMER_A 09850 * @arg @ref LL_HRTIM_TIMER_B 09851 * @arg @ref LL_HRTIM_TIMER_C 09852 * @arg @ref LL_HRTIM_TIMER_D 09853 * @arg @ref LL_HRTIM_TIMER_E 09854 * @retval None 09855 */ 09856 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09857 { 09858 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09859 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09860 REG_OFFSET_TAB_TIMER[iTimer])); 09861 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE); 09862 } 09863 09864 /** 09865 * @brief Indicate whether the compare 3 DMA request is enabled for a given timer. 09866 * @rmtoll MDIER MCMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3\n 09867 * TIMxDIER CMP3DE LL_HRTIM_IsEnabledDMAReq_CMP3 09868 * @param HRTIMx High Resolution Timer instance 09869 * @param Timer This parameter can be one of the following values: 09870 * @arg @ref LL_HRTIM_TIMER_MASTER 09871 * @arg @ref LL_HRTIM_TIMER_A 09872 * @arg @ref LL_HRTIM_TIMER_B 09873 * @arg @ref LL_HRTIM_TIMER_C 09874 * @arg @ref LL_HRTIM_TIMER_D 09875 * @arg @ref LL_HRTIM_TIMER_E 09876 * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 09877 */ 09878 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09879 { 09880 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09881 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09882 REG_OFFSET_TAB_TIMER[iTimer])); 09883 09884 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL); 09885 } 09886 09887 /** 09888 * @brief Enable the compare 4 DMA request for a given timer. 09889 * @rmtoll MDIER MCMP4DE LL_HRTIM_EnableDMAReq_CMP4\n 09890 * TIMxDIER CMP4DE LL_HRTIM_EnableDMAReq_CMP4 09891 * @param HRTIMx High Resolution Timer instance 09892 * @param Timer This parameter can be one of the following values: 09893 * @arg @ref LL_HRTIM_TIMER_MASTER 09894 * @arg @ref LL_HRTIM_TIMER_A 09895 * @arg @ref LL_HRTIM_TIMER_B 09896 * @arg @ref LL_HRTIM_TIMER_C 09897 * @arg @ref LL_HRTIM_TIMER_D 09898 * @arg @ref LL_HRTIM_TIMER_E 09899 * @retval None 09900 */ 09901 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09902 { 09903 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09904 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09905 REG_OFFSET_TAB_TIMER[iTimer])); 09906 SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE); 09907 } 09908 09909 /** 09910 * @brief Disable the compare 4 DMA request for a given timer. 09911 * @rmtoll MDIER MCMP4DE LL_HRTIM_DisableDMAReq_CMP4\n 09912 * TIMxDIER CMP4DE LL_HRTIM_DisableDMAReq_CMP4 09913 * @param HRTIMx High Resolution Timer instance 09914 * @param Timer This parameter can be one of the following values: 09915 * @arg @ref LL_HRTIM_TIMER_MASTER 09916 * @arg @ref LL_HRTIM_TIMER_A 09917 * @arg @ref LL_HRTIM_TIMER_B 09918 * @arg @ref LL_HRTIM_TIMER_C 09919 * @arg @ref LL_HRTIM_TIMER_D 09920 * @arg @ref LL_HRTIM_TIMER_E 09921 * @retval None 09922 */ 09923 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09924 { 09925 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09926 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09927 REG_OFFSET_TAB_TIMER[iTimer])); 09928 CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE); 09929 } 09930 09931 /** 09932 * @brief Indicate whether the compare 4 DMA request is enabled for a given timer. 09933 * @rmtoll MDIER MCMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4\n 09934 * TIMxDIER CMP4DE LL_HRTIM_IsEnabledDMAReq_CMP4 09935 * @param HRTIMx High Resolution Timer instance 09936 * @param Timer This parameter can be one of the following values: 09937 * @arg @ref LL_HRTIM_TIMER_MASTER 09938 * @arg @ref LL_HRTIM_TIMER_A 09939 * @arg @ref LL_HRTIM_TIMER_B 09940 * @arg @ref LL_HRTIM_TIMER_C 09941 * @arg @ref LL_HRTIM_TIMER_D 09942 * @arg @ref LL_HRTIM_TIMER_E 09943 * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0). 09944 */ 09945 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09946 { 09947 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09948 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09949 REG_OFFSET_TAB_TIMER[iTimer])); 09950 09951 return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL); 09952 } 09953 09954 /** 09955 * @brief Enable the capture 1 DMA request for a given timer. 09956 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_EnableDMAReq_CPT1 09957 * @param HRTIMx High Resolution Timer instance 09958 * @param Timer This parameter can be one of the following values: 09959 * @arg @ref LL_HRTIM_TIMER_A 09960 * @arg @ref LL_HRTIM_TIMER_B 09961 * @arg @ref LL_HRTIM_TIMER_C 09962 * @arg @ref LL_HRTIM_TIMER_D 09963 * @arg @ref LL_HRTIM_TIMER_E 09964 * @retval None 09965 */ 09966 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09967 { 09968 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09969 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09970 REG_OFFSET_TAB_TIMER[iTimer])); 09971 SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); 09972 } 09973 09974 /** 09975 * @brief Disable the capture 1 DMA request for a given timer. 09976 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_DisableDMAReq_CPT1 09977 * @param HRTIMx High Resolution Timer instance 09978 * @param Timer This parameter can be one of the following values: 09979 * @arg @ref LL_HRTIM_TIMER_A 09980 * @arg @ref LL_HRTIM_TIMER_B 09981 * @arg @ref LL_HRTIM_TIMER_C 09982 * @arg @ref LL_HRTIM_TIMER_D 09983 * @arg @ref LL_HRTIM_TIMER_E 09984 * @retval None 09985 */ 09986 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 09987 { 09988 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 09989 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 09990 REG_OFFSET_TAB_TIMER[iTimer])); 09991 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE); 09992 } 09993 09994 /** 09995 * @brief Indicate whether the capture 1 DMA request is enabled for a given timer. 09996 * @rmtoll TIMxDIER CPT1DE LL_HRTIM_IsEnabledDMAReq_CPT1 09997 * @param HRTIMx High Resolution Timer instance 09998 * @param Timer This parameter can be one of the following values: 09999 * @arg @ref LL_HRTIM_TIMER_A 10000 * @arg @ref LL_HRTIM_TIMER_B 10001 * @arg @ref LL_HRTIM_TIMER_C 10002 * @arg @ref LL_HRTIM_TIMER_D 10003 * @arg @ref LL_HRTIM_TIMER_E 10004 * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0). 10005 */ 10006 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10007 { 10008 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10009 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10010 REG_OFFSET_TAB_TIMER[iTimer])); 10011 10012 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL); 10013 } 10014 10015 /** 10016 * @brief Enable the capture 2 DMA request for a given timer. 10017 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_EnableDMAReq_CPT2 10018 * @param HRTIMx High Resolution Timer instance 10019 * @param Timer This parameter can be one of the following values: 10020 * @arg @ref LL_HRTIM_TIMER_A 10021 * @arg @ref LL_HRTIM_TIMER_B 10022 * @arg @ref LL_HRTIM_TIMER_C 10023 * @arg @ref LL_HRTIM_TIMER_D 10024 * @arg @ref LL_HRTIM_TIMER_E 10025 * @retval None 10026 */ 10027 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10028 { 10029 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10030 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10031 REG_OFFSET_TAB_TIMER[iTimer])); 10032 SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); 10033 } 10034 10035 /** 10036 * @brief Disable the capture 2 DMA request for a given timer. 10037 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_DisableDMAReq_CPT2 10038 * @param HRTIMx High Resolution Timer instance 10039 * @param Timer This parameter can be one of the following values: 10040 * @arg @ref LL_HRTIM_TIMER_A 10041 * @arg @ref LL_HRTIM_TIMER_B 10042 * @arg @ref LL_HRTIM_TIMER_C 10043 * @arg @ref LL_HRTIM_TIMER_D 10044 * @arg @ref LL_HRTIM_TIMER_E 10045 * @retval None 10046 */ 10047 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10048 { 10049 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10050 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10051 REG_OFFSET_TAB_TIMER[iTimer])); 10052 CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE); 10053 } 10054 10055 /** 10056 * @brief Indicate whether the capture 2 DMA request is enabled for a given timer. 10057 * @rmtoll TIMxDIER CPT2DE LL_HRTIM_IsEnabledDMAReq_CPT2 10058 * @param HRTIMx High Resolution Timer instance 10059 * @param Timer This parameter can be one of the following values: 10060 * @arg @ref LL_HRTIM_TIMER_A 10061 * @arg @ref LL_HRTIM_TIMER_B 10062 * @arg @ref LL_HRTIM_TIMER_C 10063 * @arg @ref LL_HRTIM_TIMER_D 10064 * @arg @ref LL_HRTIM_TIMER_E 10065 * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0). 10066 */ 10067 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10068 { 10069 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10070 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10071 REG_OFFSET_TAB_TIMER[iTimer])); 10072 10073 return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL); 10074 } 10075 10076 /** 10077 * @brief Enable the output 1 set DMA request for a given timer. 10078 * @rmtoll TIMxDIER SET1DE LL_HRTIM_EnableDMAReq_SET1 10079 * @param HRTIMx High Resolution Timer instance 10080 * @param Timer This parameter can be one of the following values: 10081 * @arg @ref LL_HRTIM_TIMER_A 10082 * @arg @ref LL_HRTIM_TIMER_B 10083 * @arg @ref LL_HRTIM_TIMER_C 10084 * @arg @ref LL_HRTIM_TIMER_D 10085 * @arg @ref LL_HRTIM_TIMER_E 10086 * @retval None 10087 */ 10088 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10089 { 10090 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10091 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10092 REG_OFFSET_TAB_TIMER[iTimer])); 10093 SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE); 10094 } 10095 10096 /** 10097 * @brief Disable the output 1 set DMA request for a given timer. 10098 * @rmtoll TIMxDIER SET1DE LL_HRTIM_DisableDMAReq_SET1 10099 * @param HRTIMx High Resolution Timer instance 10100 * @param Timer This parameter can be one of the following values: 10101 * @arg @ref LL_HRTIM_TIMER_A 10102 * @arg @ref LL_HRTIM_TIMER_B 10103 * @arg @ref LL_HRTIM_TIMER_C 10104 * @arg @ref LL_HRTIM_TIMER_D 10105 * @arg @ref LL_HRTIM_TIMER_E 10106 * @retval None 10107 */ 10108 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10109 { 10110 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10111 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10112 REG_OFFSET_TAB_TIMER[iTimer])); 10113 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE); 10114 } 10115 10116 /** 10117 * @brief Indicate whether the output 1 set DMA request is enabled for a given timer. 10118 * @rmtoll TIMxDIER SET1DE LL_HRTIM_IsEnabledDMAReq_SET1 10119 * @param HRTIMx High Resolution Timer instance 10120 * @param Timer This parameter can be one of the following values: 10121 * @arg @ref LL_HRTIM_TIMER_A 10122 * @arg @ref LL_HRTIM_TIMER_B 10123 * @arg @ref LL_HRTIM_TIMER_C 10124 * @arg @ref LL_HRTIM_TIMER_D 10125 * @arg @ref LL_HRTIM_TIMER_E 10126 * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0). 10127 */ 10128 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10129 { 10130 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10131 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10132 REG_OFFSET_TAB_TIMER[iTimer])); 10133 10134 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL); 10135 } 10136 10137 /** 10138 * @brief Enable the output 1 reset DMA request for a given timer. 10139 * @rmtoll TIMxDIER RST1DE LL_HRTIM_EnableDMAReq_RST1 10140 * @param HRTIMx High Resolution Timer instance 10141 * @param Timer This parameter can be one of the following values: 10142 * @arg @ref LL_HRTIM_TIMER_A 10143 * @arg @ref LL_HRTIM_TIMER_B 10144 * @arg @ref LL_HRTIM_TIMER_C 10145 * @arg @ref LL_HRTIM_TIMER_D 10146 * @arg @ref LL_HRTIM_TIMER_E 10147 * @retval None 10148 */ 10149 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10150 { 10151 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10152 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10153 REG_OFFSET_TAB_TIMER[iTimer])); 10154 SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE); 10155 } 10156 10157 /** 10158 * @brief Disable the output 1 reset DMA request for a given timer. 10159 * @rmtoll TIMxDIER RST1DE LL_HRTIM_DisableDMAReq_RST1 10160 * @param HRTIMx High Resolution Timer instance 10161 * @param Timer This parameter can be one of the following values: 10162 * @arg @ref LL_HRTIM_TIMER_A 10163 * @arg @ref LL_HRTIM_TIMER_B 10164 * @arg @ref LL_HRTIM_TIMER_C 10165 * @arg @ref LL_HRTIM_TIMER_D 10166 * @arg @ref LL_HRTIM_TIMER_E 10167 * @retval None 10168 */ 10169 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10170 { 10171 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10172 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10173 REG_OFFSET_TAB_TIMER[iTimer])); 10174 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE); 10175 } 10176 10177 /** 10178 * @brief Indicate whether the output 1 reset interrupt is enabled for a given timer. 10179 * @rmtoll TIMxDIER RST1DE LL_HRTIM_IsEnabledDMAReq_RST1 10180 * @param HRTIMx High Resolution Timer instance 10181 * @param Timer This parameter can be one of the following values: 10182 * @arg @ref LL_HRTIM_TIMER_A 10183 * @arg @ref LL_HRTIM_TIMER_B 10184 * @arg @ref LL_HRTIM_TIMER_C 10185 * @arg @ref LL_HRTIM_TIMER_D 10186 * @arg @ref LL_HRTIM_TIMER_E 10187 * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0). 10188 */ 10189 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10190 { 10191 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10192 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10193 REG_OFFSET_TAB_TIMER[iTimer])); 10194 10195 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL); 10196 } 10197 10198 /** 10199 * @brief Enable the output 2 set DMA request for a given timer. 10200 * @rmtoll TIMxDIER SET2DE LL_HRTIM_EnableDMAReq_SET2 10201 * @param HRTIMx High Resolution Timer instance 10202 * @param Timer This parameter can be one of the following values: 10203 * @arg @ref LL_HRTIM_TIMER_A 10204 * @arg @ref LL_HRTIM_TIMER_B 10205 * @arg @ref LL_HRTIM_TIMER_C 10206 * @arg @ref LL_HRTIM_TIMER_D 10207 * @arg @ref LL_HRTIM_TIMER_E 10208 * @retval None 10209 */ 10210 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10211 { 10212 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10213 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10214 REG_OFFSET_TAB_TIMER[iTimer])); 10215 SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE); 10216 } 10217 10218 /** 10219 * @brief Disable the output 2 set DMA request for a given timer. 10220 * @rmtoll TIMxDIER SET2DE LL_HRTIM_DisableDMAReq_SET2 10221 * @param HRTIMx High Resolution Timer instance 10222 * @param Timer This parameter can be one of the following values: 10223 * @arg @ref LL_HRTIM_TIMER_A 10224 * @arg @ref LL_HRTIM_TIMER_B 10225 * @arg @ref LL_HRTIM_TIMER_C 10226 * @arg @ref LL_HRTIM_TIMER_D 10227 * @arg @ref LL_HRTIM_TIMER_E 10228 * @retval None 10229 */ 10230 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10231 { 10232 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10233 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10234 REG_OFFSET_TAB_TIMER[iTimer])); 10235 CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE); 10236 } 10237 10238 /** 10239 * @brief Indicate whether the output 2 set DMA request is enabled for a given timer. 10240 * @rmtoll TIMxDIER SET2DE LL_HRTIM_IsEnabledDMAReq_SET2 10241 * @param HRTIMx High Resolution Timer instance 10242 * @param Timer This parameter can be one of the following values: 10243 * @arg @ref LL_HRTIM_TIMER_A 10244 * @arg @ref LL_HRTIM_TIMER_B 10245 * @arg @ref LL_HRTIM_TIMER_C 10246 * @arg @ref LL_HRTIM_TIMER_D 10247 * @arg @ref LL_HRTIM_TIMER_E 10248 * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0). 10249 */ 10250 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10251 { 10252 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10253 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10254 REG_OFFSET_TAB_TIMER[iTimer])); 10255 10256 return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL); 10257 } 10258 10259 /** 10260 * @brief Enable the output 2 reset DMA request for a given timer. 10261 * @rmtoll TIMxDIER RST2DE LL_HRTIM_EnableDMAReq_RST2 10262 * @param HRTIMx High Resolution Timer instance 10263 * @param Timer This parameter can be one of the following values: 10264 * @arg @ref LL_HRTIM_TIMER_A 10265 * @arg @ref LL_HRTIM_TIMER_B 10266 * @arg @ref LL_HRTIM_TIMER_C 10267 * @arg @ref LL_HRTIM_TIMER_D 10268 * @arg @ref LL_HRTIM_TIMER_E 10269 * @retval None 10270 */ 10271 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10272 { 10273 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10274 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10275 REG_OFFSET_TAB_TIMER[iTimer])); 10276 SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE); 10277 } 10278 10279 /** 10280 * @brief Disable the output 2 reset DMA request for a given timer. 10281 * @rmtoll TIMxDIER RST2DE LL_HRTIM_DisableDMAReq_RST2 10282 * @param HRTIMx High Resolution Timer instance 10283 * @param Timer This parameter can be one of the following values: 10284 * @arg @ref LL_HRTIM_TIMER_A 10285 * @arg @ref LL_HRTIM_TIMER_B 10286 * @arg @ref LL_HRTIM_TIMER_C 10287 * @arg @ref LL_HRTIM_TIMER_D 10288 * @arg @ref LL_HRTIM_TIMER_E 10289 * @retval None 10290 */ 10291 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10292 { 10293 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10294 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10295 REG_OFFSET_TAB_TIMER[iTimer])); 10296 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE); 10297 } 10298 10299 /** 10300 * @brief Indicate whether the output 2 reset DMA request is enabled for a given timer. 10301 * @rmtoll TIMxDIER RST2DE LL_HRTIM_IsEnabledDMAReq_RST2 10302 * @param HRTIMx High Resolution Timer instance 10303 * @param Timer This parameter can be one of the following values: 10304 * @arg @ref LL_HRTIM_TIMER_A 10305 * @arg @ref LL_HRTIM_TIMER_B 10306 * @arg @ref LL_HRTIM_TIMER_C 10307 * @arg @ref LL_HRTIM_TIMER_D 10308 * @arg @ref LL_HRTIM_TIMER_E 10309 * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0). 10310 */ 10311 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10312 { 10313 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10314 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10315 REG_OFFSET_TAB_TIMER[iTimer])); 10316 10317 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL); 10318 } 10319 10320 /** 10321 * @brief Enable the reset/roll-over DMA request for a given timer. 10322 * @rmtoll TIMxDIER RSTDE LL_HRTIM_EnableDMAReq_RST 10323 * @param HRTIMx High Resolution Timer instance 10324 * @param Timer This parameter can be one of the following values: 10325 * @arg @ref LL_HRTIM_TIMER_A 10326 * @arg @ref LL_HRTIM_TIMER_B 10327 * @arg @ref LL_HRTIM_TIMER_C 10328 * @arg @ref LL_HRTIM_TIMER_D 10329 * @arg @ref LL_HRTIM_TIMER_E 10330 * @retval None 10331 */ 10332 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10333 { 10334 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10335 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10336 REG_OFFSET_TAB_TIMER[iTimer])); 10337 SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE); 10338 } 10339 10340 /** 10341 * @brief Disable the reset/roll-over DMA request for a given timer. 10342 * @rmtoll TIMxDIER RSTDE LL_HRTIM_DisableDMAReq_RST 10343 * @param HRTIMx High Resolution Timer instance 10344 * @param Timer This parameter can be one of the following values: 10345 * @arg @ref LL_HRTIM_TIMER_A 10346 * @arg @ref LL_HRTIM_TIMER_B 10347 * @arg @ref LL_HRTIM_TIMER_C 10348 * @arg @ref LL_HRTIM_TIMER_D 10349 * @arg @ref LL_HRTIM_TIMER_E 10350 * @retval None 10351 */ 10352 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10353 { 10354 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10355 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10356 REG_OFFSET_TAB_TIMER[iTimer])); 10357 CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE); 10358 } 10359 10360 /** 10361 * @brief Indicate whether the reset/roll-over DMA request is enabled for a given timer. 10362 * @rmtoll TIMxDIER RSTDE LL_HRTIM_IsEnabledDMAReq_RST 10363 * @param HRTIMx High Resolution Timer instance 10364 * @param Timer This parameter can be one of the following values: 10365 * @arg @ref LL_HRTIM_TIMER_A 10366 * @arg @ref LL_HRTIM_TIMER_B 10367 * @arg @ref LL_HRTIM_TIMER_C 10368 * @arg @ref LL_HRTIM_TIMER_D 10369 * @arg @ref LL_HRTIM_TIMER_E 10370 * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0). 10371 */ 10372 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10373 { 10374 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10375 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10376 REG_OFFSET_TAB_TIMER[iTimer])); 10377 10378 return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL); 10379 } 10380 10381 /** 10382 * @brief Enable the delayed protection DMA request for a given timer. 10383 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_EnableDMAReq_DLYPRT 10384 * @param HRTIMx High Resolution Timer instance 10385 * @param Timer This parameter can be one of the following values: 10386 * @arg @ref LL_HRTIM_TIMER_A 10387 * @arg @ref LL_HRTIM_TIMER_B 10388 * @arg @ref LL_HRTIM_TIMER_C 10389 * @arg @ref LL_HRTIM_TIMER_D 10390 * @arg @ref LL_HRTIM_TIMER_E 10391 * @retval None 10392 */ 10393 __STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10394 { 10395 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10396 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10397 REG_OFFSET_TAB_TIMER[iTimer])); 10398 SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); 10399 } 10400 10401 /** 10402 * @brief Disable the delayed protection DMA request for a given timer. 10403 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_DisableDMAReq_DLYPRT 10404 * @param HRTIMx High Resolution Timer instance 10405 * @param Timer This parameter can be one of the following values: 10406 * @arg @ref LL_HRTIM_TIMER_A 10407 * @arg @ref LL_HRTIM_TIMER_B 10408 * @arg @ref LL_HRTIM_TIMER_C 10409 * @arg @ref LL_HRTIM_TIMER_D 10410 * @arg @ref LL_HRTIM_TIMER_E 10411 * @retval None 10412 */ 10413 __STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10414 { 10415 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10416 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10417 REG_OFFSET_TAB_TIMER[iTimer])); 10418 CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE); 10419 } 10420 10421 /** 10422 * @brief Indicate whether the delayed protection DMA request is enabled for a given timer. 10423 * @rmtoll TIMxDIER DLYPRTDE LL_HRTIM_IsEnabledDMAReq_DLYPRT 10424 * @param HRTIMx High Resolution Timer instance 10425 * @param Timer This parameter can be one of the following values: 10426 * @arg @ref LL_HRTIM_TIMER_A 10427 * @arg @ref LL_HRTIM_TIMER_B 10428 * @arg @ref LL_HRTIM_TIMER_C 10429 * @arg @ref LL_HRTIM_TIMER_D 10430 * @arg @ref LL_HRTIM_TIMER_E 10431 * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0). 10432 */ 10433 __STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer) 10434 { 10435 uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos); 10436 const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) + 10437 REG_OFFSET_TAB_TIMER[iTimer])); 10438 10439 return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL); 10440 } 10441 10442 /** 10443 * @} 10444 */ 10445 10446 #if defined(USE_FULL_LL_DRIVER) 10447 /** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions 10448 * @{ 10449 */ 10450 ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx); 10451 /** 10452 * @} 10453 */ 10454 #endif /* USE_FULL_LL_DRIVER */ 10455 10456 /** 10457 * @} 10458 */ 10459 10460 /** 10461 * @} 10462 */ 10463 10464 #endif /* HRTIM1 */ 10465 10466 /** 10467 * @} 10468 */ 10469 10470 #ifdef __cplusplus 10471 } 10472 #endif 10473 10474 #endif /* STM32H7xx_LL_HRTIM_H */ 10475 10476
1.7.6.1