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STM32H735xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32h7xx_ll_pwr.h 00004 * @author MCD Application Team 00005 * @brief Header file of PWR LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32H7xx_LL_PWR_H 00021 #define STM32H7xx_LL_PWR_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32h7xx.h" 00029 00030 /** @addtogroup STM32H7xx_LL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (PWR) 00035 00036 /** @defgroup PWR_LL PWR 00037 * @{ 00038 */ 00039 00040 /* Private types -------------------------------------------------------------*/ 00041 /* Private variables ---------------------------------------------------------*/ 00042 /* Private constants ---------------------------------------------------------*/ 00043 /** @defgroup PWR_LL_Private_Constants PWR Private Constants 00044 * @{ 00045 */ 00046 00047 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines 00048 * @brief Flags defines which can be used with LL_PWR_WriteReg function 00049 * @{ 00050 */ 00051 /* Wake-Up Pins PWR register offsets */ 00052 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL 00053 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU 00054 /** 00055 * @} 00056 */ 00057 /** 00058 * @} 00059 */ 00060 /* Private macros ------------------------------------------------------------*/ 00061 /* Exported types ------------------------------------------------------------*/ 00062 /* Exported constants --------------------------------------------------------*/ 00063 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants 00064 * @{ 00065 */ 00066 00067 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines 00068 * @brief Flags defines which can be used with LL_PWR_WriteReg function 00069 * @{ 00070 */ 00071 #define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */ 00072 #if defined (DUAL_CORE) 00073 #define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */ 00074 #endif /* DUAL_CORE */ 00075 #define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */ 00076 #if defined (PWR_WKUPCR_WKUPC5) 00077 #define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */ 00078 #endif /* defined (PWR_WKUPCR_WKUPC5) */ 00079 #define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */ 00080 #if defined (PWR_WKUPCR_WKUPC3) 00081 #define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */ 00082 #endif /* defined (PWR_WKUPCR_WKUPC3) */ 00083 #define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */ 00084 #define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */ 00085 /** 00086 * @} 00087 */ 00088 00089 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines 00090 * @brief Flags defines which can be used with LL_PWR_ReadReg function 00091 * @{ 00092 */ 00093 #define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog voltage detector output on VDDA flag */ 00094 #define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Programmable voltage detect output flag */ 00095 #define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /*!< Current VOS applied for VCORE voltage scaling flag */ 00096 #define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */ 00097 #if defined (PWR_CSR1_MMCVDO) 00098 #define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO /*!< Voltage detector output on VDDMMC flag */ 00099 #endif /* PWR_CSR1_MMCVDO */ 00100 00101 #define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */ 00102 #define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */ 00103 #define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */ 00104 #define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */ 00105 #define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */ 00106 00107 #define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */ 00108 #define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY /*!< SMPS External supply ready flag */ 00109 00110 #if defined (PWR_CPUCR_SBF_D2) 00111 #define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ 00112 #endif /* PWR_CPUCR_SBF_D2 */ 00113 #if defined (PWR_CPUCR_SBF_D1) 00114 #define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ 00115 #endif /* PWR_CPUCR_SBF_D1 */ 00116 #define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /*!< System STANDBY Flag */ 00117 #define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /*!< STOP Flag */ 00118 #if defined (DUAL_CORE) 00119 #define LL_PWR_FLAG_CPU_HOLD2F PWR_CPUCR_HOLD2F /*!< CPU2 in hold wakeup flag */ 00120 #endif /* DUAL_CORE */ 00121 00122 #if defined (DUAL_CORE) 00123 #define LL_PWR_FLAG_CPU2_SBF_D2 PWR_CPU2CR_SBF_D2 /*!< D2 domain DSTANDBY Flag */ 00124 #define LL_PWR_FLAG_CPU2_SBF_D1 PWR_CPU2CR_SBF_D1 /*!< D1 domain DSTANDBY Flag */ 00125 #define LL_PWR_FLAG_CPU2_SBF PWR_CPU2CR_SBF /*!< System STANDBY Flag */ 00126 #define LL_PWR_FLAG_CPU2_STOPF PWR_CPU2CR_STOPF /*!< STOP Flag */ 00127 #define LL_PWR_FLAG_CPU2_HOLD1F PWR_CPU2CR_HOLD1F /*!< CPU1 in hold wakeup flag */ 00128 #endif /* DUAL_CORE */ 00129 00130 #if defined (PWR_CPUCR_PDDS_D2) 00131 #define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /*!< Voltage scaling ready flag */ 00132 #else 00133 #define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY /*!< Voltage scaling ready flag */ 00134 #endif /* PWR_CPUCR_PDDS_D2 */ 00135 00136 #define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */ 00137 #if defined (PWR_WKUPFR_WKUPF5) 00138 #define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */ 00139 #endif /* defined (PWR_WKUPFR_WKUPF5) */ 00140 #define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */ 00141 #if defined (PWR_WKUPFR_WKUPF3) 00142 #define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */ 00143 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 00144 #define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */ 00145 #define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */ 00146 /** 00147 * @} 00148 */ 00149 00150 /** @defgroup PWR_LL_EC_MODE_PWR Power mode 00151 * @{ 00152 */ 00153 #if defined (PWR_CPUCR_PDDS_D2) 00154 #define LL_PWR_CPU_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep */ 00155 #define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep */ 00156 #else 00157 #define LL_PWR_CPU_MODE_CDSTOP 0x00000000U /*!< Enter CD domain to Stop mode when the CPU enters deepsleep */ 00158 #define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep */ 00159 #endif /* PWR_CPUCR_PDDS_D2 */ 00160 00161 #if defined (PWR_CPUCR_PDDS_D2) 00162 #define LL_PWR_CPU_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep */ 00163 #define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep */ 00164 #endif /* PWR_CPUCR_PDDS_D2 */ 00165 00166 #if defined (PWR_CPUCR_PDDS_D2) 00167 #define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep */ 00168 #define LL_PWR_CPU_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep */ 00169 #define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep */ 00170 #else 00171 #define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep */ 00172 #define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep */ 00173 #define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep */ 00174 #endif /* PWR_CPUCR_PDDS_D2 */ 00175 00176 #if defined (DUAL_CORE) 00177 #define LL_PWR_CPU2_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep */ 00178 #define LL_PWR_CPU2_MODE_D1STANDBY PWR_CPU2CR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep */ 00179 #define LL_PWR_CPU2_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep */ 00180 #define LL_PWR_CPU2_MODE_D2STANDBY PWR_CPU2CR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep */ 00181 #define LL_PWR_CPU2_MODE_D3RUN PWR_CPU2CR_RUN_D3 /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep */ 00182 #define LL_PWR_CPU2_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep */ 00183 #define LL_PWR_CPU2_MODE_D3STANDBY PWR_CPU2CR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep */ 00184 #endif /* DUAL_CORE */ 00185 /** 00186 * @} 00187 */ 00188 00189 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling 00190 * @{ 00191 */ 00192 #if defined (PWR_CPUCR_PDDS_D2) 00193 #define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */ 00194 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */ 00195 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */ 00196 #if defined (SYSCFG_PWRCR_ODEN) /* STM32H74xxx and STM32H75xxx lines */ 00197 #define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ 00198 #else 00199 #define LL_PWR_REGU_VOLTAGE_SCALE0 0x00000000U /*!< Select voltage scale 0 */ 00200 #endif /* defined (SYSCFG_PWRCR_ODEN) */ 00201 #else 00202 #define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */ 00203 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */ 00204 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */ 00205 #define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */ 00206 #endif /* PWR_CPUCR_PDDS_D2 */ 00207 /** 00208 * @} 00209 */ 00210 00211 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling 00212 * @{ 00213 */ 00214 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */ 00215 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */ 00216 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */ 00217 /** 00218 * @} 00219 */ 00220 00221 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode 00222 * @{ 00223 */ 00224 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */ 00225 #define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */ 00226 /** 00227 * @} 00228 */ 00229 00230 /** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector 00231 * @{ 00232 */ 00233 #define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */ 00234 #define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */ 00235 #define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */ 00236 #define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */ 00237 #define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */ 00238 #define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */ 00239 #define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */ 00240 #define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */ 00241 /** 00242 * @} 00243 */ 00244 00245 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector 00246 * @{ 00247 */ 00248 #define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */ 00249 #define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */ 00250 #define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */ 00251 #define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */ 00252 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor 00258 * @{ 00259 */ 00260 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge the Battery through a 5 kO resistor */ 00261 #define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge the Battery through a 1.5 kO resistor */ 00262 /** 00263 * @} 00264 */ 00265 00266 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins 00267 * @{ 00268 */ 00269 #define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */ 00270 #define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */ 00271 #if defined (PWR_WKUPEPR_WKUPEN3) 00272 #define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */ 00273 #endif /* defined (PWR_WKUPEPR_WKUPEN3) */ 00274 #define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */ 00275 #if defined (PWR_WKUPEPR_WKUPEN5) 00276 #define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */ 00277 #endif /* defined (PWR_WKUPEPR_WKUPEN5) */ 00278 #define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */ 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration 00284 * @{ 00285 */ 00286 #define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */ 00287 #define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */ 00288 #define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */ 00289 /** 00290 * @} 00291 */ 00292 00293 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration 00294 * @{ 00295 */ 00296 #define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are supplied from the LDO */ 00297 #if defined (SMPS) 00298 #define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are supplied from the SMPS */ 00299 #define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */ 00300 #define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */ 00301 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 00302 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are supplied from the LDO */ 00303 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */ 00304 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */ 00305 #endif /* SMPS */ 00306 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */ 00307 /** 00308 * @} 00309 */ 00310 00311 /** 00312 * @} 00313 */ 00314 /* Exported macro ------------------------------------------------------------*/ 00315 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros 00316 * @{ 00317 */ 00318 00319 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros 00320 * @{ 00321 */ 00322 00323 /** 00324 * @brief Write a value in PWR register 00325 * @param __REG__ Register to be written 00326 * @param __VALUE__ Value to be written in the register 00327 * @retval None 00328 */ 00329 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) 00330 00331 /** 00332 * @brief Read a value in PWR register 00333 * @param __REG__ Register to be read 00334 * @retval Register value 00335 */ 00336 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) 00337 /** 00338 * @} 00339 */ 00340 00341 /** 00342 * @} 00343 */ 00344 /* Exported functions --------------------------------------------------------*/ 00345 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions 00346 * @{ 00347 */ 00348 00349 /** @defgroup PWR_LL_EF_Configuration Configuration 00350 * @{ 00351 */ 00352 00353 /** 00354 * @brief Set the voltage Regulator mode during deep sleep mode 00355 * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS 00356 * @param RegulMode This parameter can be one of the following values: 00357 * @arg @ref LL_PWR_REGU_DSMODE_MAIN 00358 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER 00359 * @retval None 00360 */ 00361 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode) 00362 { 00363 MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode); 00364 } 00365 00366 /** 00367 * @brief Get the voltage Regulator mode during deep sleep mode 00368 * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS 00369 * @retval Returned value can be one of the following values: 00370 * @arg @ref LL_PWR_REGU_DSMODE_MAIN 00371 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER 00372 */ 00373 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void) 00374 { 00375 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS)); 00376 } 00377 00378 /** 00379 * @brief Enable Power Voltage Detector 00380 * @rmtoll CR1 PVDEN LL_PWR_EnablePVD 00381 * @retval None 00382 */ 00383 __STATIC_INLINE void LL_PWR_EnablePVD(void) 00384 { 00385 SET_BIT(PWR->CR1, PWR_CR1_PVDEN); 00386 } 00387 00388 /** 00389 * @brief Disable Power Voltage Detector 00390 * @rmtoll CR1 PVDEN LL_PWR_DisablePVD 00391 * @retval None 00392 */ 00393 __STATIC_INLINE void LL_PWR_DisablePVD(void) 00394 { 00395 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN); 00396 } 00397 00398 /** 00399 * @brief Check if Power Voltage Detector is enabled 00400 * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD 00401 * @retval State of bit (1 or 0). 00402 */ 00403 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) 00404 { 00405 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL); 00406 } 00407 00408 /** 00409 * @brief Configure the voltage threshold detected by the Power Voltage Detector 00410 * @rmtoll CR1 PLS LL_PWR_SetPVDLevel 00411 * @param PVDLevel This parameter can be one of the following values: 00412 * @arg @ref LL_PWR_PVDLEVEL_0 00413 * @arg @ref LL_PWR_PVDLEVEL_1 00414 * @arg @ref LL_PWR_PVDLEVEL_2 00415 * @arg @ref LL_PWR_PVDLEVEL_3 00416 * @arg @ref LL_PWR_PVDLEVEL_4 00417 * @arg @ref LL_PWR_PVDLEVEL_5 00418 * @arg @ref LL_PWR_PVDLEVEL_6 00419 * @arg @ref LL_PWR_PVDLEVEL_7 00420 * @retval None 00421 */ 00422 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) 00423 { 00424 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); 00425 } 00426 00427 /** 00428 * @brief Get the voltage threshold detection 00429 * @rmtoll CR1 PLS LL_PWR_GetPVDLevel 00430 * @retval Returned value can be one of the following values: 00431 * @arg @ref LL_PWR_PVDLEVEL_0 00432 * @arg @ref LL_PWR_PVDLEVEL_1 00433 * @arg @ref LL_PWR_PVDLEVEL_2 00434 * @arg @ref LL_PWR_PVDLEVEL_3 00435 * @arg @ref LL_PWR_PVDLEVEL_4 00436 * @arg @ref LL_PWR_PVDLEVEL_5 00437 * @arg @ref LL_PWR_PVDLEVEL_6 00438 * @arg @ref LL_PWR_PVDLEVEL_7 00439 */ 00440 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) 00441 { 00442 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS)); 00443 } 00444 00445 /** 00446 * @brief Enable access to the backup domain 00447 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess 00448 * @retval None 00449 */ 00450 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) 00451 { 00452 SET_BIT(PWR->CR1, PWR_CR1_DBP); 00453 } 00454 00455 /** 00456 * @brief Disable access to the backup domain 00457 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess 00458 * @retval None 00459 */ 00460 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) 00461 { 00462 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); 00463 } 00464 00465 /** 00466 * @brief Check if the backup domain is enabled 00467 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess 00468 * @retval State of bit (1 or 0). 00469 */ 00470 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) 00471 { 00472 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); 00473 } 00474 00475 /** 00476 * @brief Enable the Flash Power Down in Stop Mode 00477 * @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown 00478 * @retval None 00479 */ 00480 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void) 00481 { 00482 SET_BIT(PWR->CR1, PWR_CR1_FLPS); 00483 } 00484 00485 /** 00486 * @brief Disable the Flash Power Down in Stop Mode 00487 * @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown 00488 * @retval None 00489 */ 00490 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void) 00491 { 00492 CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); 00493 } 00494 00495 /** 00496 * @brief Check if the Flash Power Down in Stop Mode is enabled 00497 * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown 00498 * @retval State of bit (1 or 0). 00499 */ 00500 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void) 00501 { 00502 return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL); 00503 } 00504 00505 #if defined (PWR_CR1_BOOSTE) 00506 /** 00507 * @brief Enable the Analog Voltage Booster (VDDA) 00508 * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster 00509 * @retval None 00510 */ 00511 __STATIC_INLINE void LL_PWR_EnableAnalogBooster(void) 00512 { 00513 SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); 00514 } 00515 00516 /** 00517 * @brief Disable the Analog Voltage Booster (VDDA) 00518 * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster 00519 * @retval None 00520 */ 00521 __STATIC_INLINE void LL_PWR_DisableAnalogBooster(void) 00522 { 00523 CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); 00524 } 00525 00526 /** 00527 * @brief Check if the Analog Voltage Booster (VDDA) is enabled 00528 * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster 00529 * @retval State of bit (1 or 0). 00530 */ 00531 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void) 00532 { 00533 return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL); 00534 } 00535 #endif /* PWR_CR1_BOOSTE */ 00536 00537 #if defined (PWR_CR1_AVD_READY) 00538 /** 00539 * @brief Enable the Analog Voltage Ready to isolate the BOOST IP until VDDA will be ready 00540 * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady 00541 * @retval None 00542 */ 00543 __STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void) 00544 { 00545 SET_BIT(PWR->CR1, PWR_CR1_AVD_READY); 00546 } 00547 00548 /** 00549 * @brief Disable the Analog Voltage Ready (VDDA) 00550 * @rmtoll CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady 00551 * @retval None 00552 */ 00553 __STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void) 00554 { 00555 CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY); 00556 } 00557 00558 /** 00559 * @brief Check if the Analog Voltage Booster (VDDA) is enabled 00560 * @rmtoll CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady 00561 * @retval State of bit (1 or 0). 00562 */ 00563 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void) 00564 { 00565 return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL); 00566 } 00567 #endif /* PWR_CR1_AVD_READY */ 00568 00569 /** 00570 * @brief Set the internal Regulator output voltage in STOP mode 00571 * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling 00572 * @param VoltageScaling This parameter can be one of the following values: 00573 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 00574 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 00575 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 00576 * @retval None 00577 */ 00578 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling) 00579 { 00580 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); 00581 } 00582 00583 /** 00584 * @brief Get the internal Regulator output voltage in STOP mode 00585 * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling 00586 * @retval Returned value can be one of the following values: 00587 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 00588 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 00589 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 00590 */ 00591 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void) 00592 { 00593 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS)); 00594 } 00595 00596 /** 00597 * @brief Enable Analog Power Voltage Detector 00598 * @rmtoll CR1 AVDEN LL_PWR_EnableAVD 00599 * @retval None 00600 */ 00601 __STATIC_INLINE void LL_PWR_EnableAVD(void) 00602 { 00603 SET_BIT(PWR->CR1, PWR_CR1_AVDEN); 00604 } 00605 00606 /** 00607 * @brief Disable Analog Power Voltage Detector 00608 * @rmtoll CR1 AVDEN LL_PWR_DisableAVD 00609 * @retval None 00610 */ 00611 __STATIC_INLINE void LL_PWR_DisableAVD(void) 00612 { 00613 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); 00614 } 00615 00616 /** 00617 * @brief Check if Analog Power Voltage Detector is enabled 00618 * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD 00619 * @retval State of bit (1 or 0). 00620 */ 00621 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void) 00622 { 00623 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL); 00624 } 00625 00626 /** 00627 * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector 00628 * @rmtoll CR1 ALS LL_PWR_SetAVDLevel 00629 * @param AVDLevel This parameter can be one of the following values: 00630 * @arg @ref LL_PWR_AVDLEVEL_0 00631 * @arg @ref LL_PWR_AVDLEVEL_1 00632 * @arg @ref LL_PWR_AVDLEVEL_2 00633 * @arg @ref LL_PWR_AVDLEVEL_3 00634 * @retval None 00635 */ 00636 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel) 00637 { 00638 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); 00639 } 00640 00641 /** 00642 * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector 00643 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel 00644 * @retval Returned value can be one of the following values: 00645 * @arg @ref LL_PWR_AVDLEVEL_0 00646 * @arg @ref LL_PWR_AVDLEVEL_1 00647 * @arg @ref LL_PWR_AVDLEVEL_2 00648 * @arg @ref LL_PWR_AVDLEVEL_3 00649 */ 00650 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void) 00651 { 00652 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS)); 00653 } 00654 00655 #if defined (PWR_CR1_AXIRAM1SO) 00656 /** 00657 * @brief Enable the AXI RAM1 shut-off in DStop/DStop2 mode 00658 * @rmtoll CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff 00659 * @retval None 00660 */ 00661 __STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void) 00662 { 00663 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); 00664 } 00665 00666 /** 00667 * @brief Disable the AXI RAM1 shut-off in DStop/DStop2 mode 00668 * @rmtoll CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff 00669 * @retval None 00670 */ 00671 __STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void) 00672 { 00673 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO); 00674 } 00675 00676 /** 00677 * @brief Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled 00678 * @rmtoll CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff 00679 * @retval State of bit (1 or 0). 00680 */ 00681 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void) 00682 { 00683 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL); 00684 } 00685 #endif /* PWR_CR1_AXIRAM1SO */ 00686 00687 #if defined (PWR_CR1_AXIRAM2SO) 00688 /** 00689 * @brief Enable the AXI RAM2 shut-off in DStop/DStop2 mode 00690 * @rmtoll CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff 00691 * @retval None 00692 */ 00693 __STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void) 00694 { 00695 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); 00696 } 00697 00698 /** 00699 * @brief Disable the AXI RAM2 shut-off in DStop/DStop2 mode 00700 * @rmtoll CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff 00701 * @retval None 00702 */ 00703 __STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void) 00704 { 00705 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO); 00706 } 00707 00708 /** 00709 * @brief Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled 00710 * @rmtoll CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff 00711 * @retval State of bit (1 or 0). 00712 */ 00713 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void) 00714 { 00715 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL); 00716 } 00717 #endif /* PWR_CR1_AXIRAM2SO */ 00718 00719 #if defined (PWR_CR1_AXIRAM3SO) 00720 /** 00721 * @brief Enable the AXI RAM3 shut-off in DStop/DStop2 mode 00722 * @rmtoll CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff 00723 * @retval None 00724 */ 00725 __STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void) 00726 { 00727 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); 00728 } 00729 00730 /** 00731 * @brief Disable the AXI RAM3 shut-off in DStop/DStop2 mode 00732 * @rmtoll CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff 00733 * @retval None 00734 */ 00735 __STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void) 00736 { 00737 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO); 00738 } 00739 00740 /** 00741 * @brief Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled 00742 * @rmtoll CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff 00743 * @retval State of bit (1 or 0). 00744 */ 00745 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void) 00746 { 00747 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL); 00748 } 00749 #endif /* PWR_CR1_AXIRAM3SO */ 00750 00751 #if defined (PWR_CR1_AHBRAM1SO) 00752 /** 00753 * @brief Enable the AHB RAM1 shut-off in DStop/DStop2 mode 00754 * @rmtoll CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff 00755 * @retval None 00756 */ 00757 __STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void) 00758 { 00759 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); 00760 } 00761 00762 /** 00763 * @brief Disable the AHB RAM1 shut-off in DStop/DStop2 mode 00764 * @rmtoll CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff 00765 * @retval None 00766 */ 00767 __STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void) 00768 { 00769 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO); 00770 } 00771 00772 /** 00773 * @brief Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled 00774 * @rmtoll CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff 00775 * @retval State of bit (1 or 0). 00776 */ 00777 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void) 00778 { 00779 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL); 00780 } 00781 #endif /* PWR_CR1_AHBRAM1SO */ 00782 00783 #if defined (PWR_CR1_AHBRAM2SO) 00784 /** 00785 * @brief Enable the AHB RAM2 shut-off in DStop/DStop2 mode 00786 * @rmtoll CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff 00787 * @retval None 00788 */ 00789 __STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void) 00790 { 00791 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); 00792 } 00793 00794 /** 00795 * @brief Disable the AHB RAM2 shut-off in DStop/DStop2 mode 00796 * @rmtoll CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff 00797 * @retval None 00798 */ 00799 __STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void) 00800 { 00801 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO); 00802 } 00803 00804 /** 00805 * @brief Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled 00806 * @rmtoll CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff 00807 * @retval State of bit (1 or 0). 00808 */ 00809 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void) 00810 { 00811 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL); 00812 } 00813 #endif /* PWR_CR1_AHBRAM2SO */ 00814 00815 #if defined (PWR_CR1_ITCMSO) 00816 /** 00817 * @brief Enable the ITCM shut-off in DStop/DStop2 mode 00818 * @rmtoll CR1 ITCMSO LL_PWR_EnableITCMSOShutOff 00819 * @retval None 00820 */ 00821 __STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void) 00822 { 00823 SET_BIT(PWR->CR1, PWR_CR1_ITCMSO); 00824 } 00825 00826 /** 00827 * @brief Disable the ITCM shut-off in DStop/DStop2 mode 00828 * @rmtoll CR1 ITCMSO LL_PWR_DisableITCMSOShutOff 00829 * @retval None 00830 */ 00831 __STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void) 00832 { 00833 CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO); 00834 } 00835 00836 /** 00837 * @brief Check if the ITCM shut-off in DStop/DStop2 mode is enabled 00838 * @rmtoll CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff 00839 * @retval State of bit (1 or 0). 00840 */ 00841 __STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void) 00842 { 00843 return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL); 00844 } 00845 #endif /* PWR_CR1_ITCMSO */ 00846 00847 #if defined (PWR_CR1_HSITFSO) 00848 /** 00849 * @brief Enable the USB and FDCAN shut-off in DStop/DStop2 mode 00850 * @rmtoll CR1 HSITFSO LL_PWR_EnableHSITFShutOff 00851 * @retval None 00852 */ 00853 __STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void) 00854 { 00855 SET_BIT(PWR->CR1, PWR_CR1_HSITFSO); 00856 } 00857 00858 /** 00859 * @brief Disable the USB and FDCAN shut-off in DStop/DStop2 mode 00860 * @rmtoll CR1 HSITFSO LL_PWR_DisableHSITFShutOff 00861 * @retval None 00862 */ 00863 __STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void) 00864 { 00865 CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO); 00866 } 00867 00868 /** 00869 * @brief Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled 00870 * @rmtoll CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff 00871 * @retval State of bit (1 or 0). 00872 */ 00873 __STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void) 00874 { 00875 return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL); 00876 } 00877 #endif /* PWR_CR1_HSITFSO */ 00878 00879 #if defined (PWR_CR1_SRDRAMSO) 00880 /** 00881 * @brief Enable the SRD AHB RAM shut-off in DStop/DStop2 mode 00882 * @rmtoll CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff 00883 * @retval None 00884 */ 00885 __STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void) 00886 { 00887 SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); 00888 } 00889 00890 /** 00891 * @brief Disable the SRD AHB RAM shut-off in DStop/DStop2 mode 00892 * @rmtoll CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff 00893 * @retval None 00894 */ 00895 __STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void) 00896 { 00897 CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO); 00898 } 00899 00900 /** 00901 * @brief Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled 00902 * @rmtoll CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff 00903 * @retval State of bit (1 or 0). 00904 */ 00905 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void) 00906 { 00907 return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL); 00908 } 00909 #endif /* PWR_CR1_SRDRAMSO */ 00910 00911 /** 00912 * @brief Enable Backup Regulator 00913 * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator 00914 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and 00915 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup 00916 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set, 00917 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that 00918 * the data written into the RAM will be maintained in the Standby and VBAT modes. 00919 * @retval None 00920 */ 00921 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) 00922 { 00923 SET_BIT(PWR->CR2, PWR_CR2_BREN); 00924 } 00925 00926 /** 00927 * @brief Disable Backup Regulator 00928 * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator 00929 * @retval None 00930 */ 00931 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) 00932 { 00933 CLEAR_BIT(PWR->CR2, PWR_CR2_BREN); 00934 } 00935 00936 /** 00937 * @brief Check if the backup Regulator is enabled 00938 * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator 00939 * @retval State of bit (1 or 0). 00940 */ 00941 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) 00942 { 00943 return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL); 00944 } 00945 00946 /** 00947 * @brief Enable VBAT and Temperature monitoring 00948 * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring 00949 * @retval None 00950 */ 00951 __STATIC_INLINE void LL_PWR_EnableMonitoring(void) 00952 { 00953 SET_BIT(PWR->CR2, PWR_CR2_MONEN); 00954 } 00955 00956 /** 00957 * @brief Disable VBAT and Temperature monitoring 00958 * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring 00959 * @retval None 00960 */ 00961 __STATIC_INLINE void LL_PWR_DisableMonitoring(void) 00962 { 00963 CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN); 00964 } 00965 00966 /** 00967 * @brief Check if the VBAT and Temperature monitoring is enabled 00968 * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring 00969 * @retval State of bit (1 or 0). 00970 */ 00971 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) 00972 { 00973 return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL); 00974 } 00975 00976 #if defined (SMPS) 00977 /** 00978 * @brief Configure the PWR supply 00979 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply 00980 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply 00981 * @rmtoll CR3 SMPSEN LL_PWR_ConfigSupply 00982 * @rmtoll CR3 SMPSEXTHP LL_PWR_ConfigSupply 00983 * @rmtoll CR3 SMPSLEVEL LL_PWR_ConfigSupply 00984 * @param SupplySource This parameter can be one of the following values: 00985 * @arg @ref LL_PWR_LDO_SUPPLY 00986 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY 00987 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO 00988 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO 00989 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO 00990 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO 00991 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT 00992 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT 00993 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY 00994 * @retval None 00995 */ 00996 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) 00997 { 00998 /* Set the power supply configuration */ 00999 MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); 01000 } 01001 #else 01002 /** 01003 * @brief Configure the PWR supply 01004 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply 01005 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply 01006 * @rmtoll CR3 SCUEN LL_PWR_ConfigSupply 01007 * @param SupplySource This parameter can be one of the following values: 01008 * @arg @ref LL_PWR_LDO_SUPPLY 01009 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY 01010 * @retval None 01011 */ 01012 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource) 01013 { 01014 /* Set the power supply configuration */ 01015 MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource); 01016 } 01017 #endif /* defined (SMPS) */ 01018 01019 #if defined (SMPS) 01020 /** 01021 * @brief Get the PWR supply 01022 * @rmtoll CR3 BYPASS LL_PWR_GetSupply 01023 * @rmtoll CR3 LDOEN LL_PWR_GetSupply 01024 * @rmtoll CR3 SMPSEN LL_PWR_GetSupply 01025 * @rmtoll CR3 SMPSEXTHP LL_PWR_GetSupply 01026 * @rmtoll CR3 SMPSLEVEL LL_PWR_GetSupply 01027 * @retval Returned value can be one of the following values: 01028 * @arg @ref LL_PWR_LDO_SUPPLY 01029 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY 01030 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO 01031 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO 01032 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO 01033 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO 01034 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT 01035 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT 01036 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY 01037 */ 01038 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void) 01039 { 01040 /* Get the power supply configuration */ 01041 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); 01042 } 01043 #else 01044 /** 01045 * @brief Get the PWR supply 01046 * @rmtoll CR3 BYPASS LL_PWR_GetSupply 01047 * @rmtoll CR3 LDOEN LL_PWR_GetSupply 01048 * @rmtoll CR3 SCUEN LL_PWR_GetSupply 01049 * @retval Returned value can be one of the following values: 01050 * @arg @ref LL_PWR_LDO_SUPPLY 01051 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY 01052 */ 01053 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void) 01054 { 01055 /* Get the power supply configuration */ 01056 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS))); 01057 } 01058 #endif /* defined (SMPS) */ 01059 01060 /** 01061 * @brief Enable battery charging 01062 * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging 01063 * @retval None 01064 */ 01065 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) 01066 { 01067 SET_BIT(PWR->CR3, PWR_CR3_VBE); 01068 } 01069 01070 /** 01071 * @brief Disable battery charging 01072 * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging 01073 * @retval None 01074 */ 01075 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) 01076 { 01077 CLEAR_BIT(PWR->CR3, PWR_CR3_VBE); 01078 } 01079 01080 /** 01081 * @brief Check if battery charging is enabled 01082 * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging 01083 * @retval State of bit (1 or 0). 01084 */ 01085 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) 01086 { 01087 return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL); 01088 } 01089 01090 /** 01091 * @brief Set the Battery charge resistor impedance 01092 * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor 01093 * @param Resistor This parameter can be one of the following values: 01094 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 01095 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 01096 * @retval None 01097 */ 01098 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) 01099 { 01100 MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor); 01101 } 01102 01103 /** 01104 * @brief Get the Battery charge resistor impedance 01105 * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor 01106 * @retval Returned value can be one of the following values: 01107 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 01108 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 01109 */ 01110 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) 01111 { 01112 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS)); 01113 } 01114 01115 /** 01116 * @brief Enable the USB regulator 01117 * @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg 01118 * @retval None 01119 */ 01120 __STATIC_INLINE void LL_PWR_EnableUSBReg(void) 01121 { 01122 SET_BIT(PWR->CR3, PWR_CR3_USBREGEN); 01123 } 01124 01125 /** 01126 * @brief Disable the USB regulator 01127 * @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg 01128 * @retval None 01129 */ 01130 __STATIC_INLINE void LL_PWR_DisableUSBReg(void) 01131 { 01132 CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN); 01133 } 01134 01135 /** 01136 * @brief Check if the USB regulator is enabled 01137 * @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg 01138 * @retval State of bit (1 or 0). 01139 */ 01140 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void) 01141 { 01142 return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL); 01143 } 01144 01145 /** 01146 * @brief Enable the USB voltage detector 01147 * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector 01148 * @retval None 01149 */ 01150 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void) 01151 { 01152 SET_BIT(PWR->CR3, PWR_CR3_USB33DEN); 01153 } 01154 01155 /** 01156 * @brief Disable the USB voltage detector 01157 * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector 01158 * @retval None 01159 */ 01160 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void) 01161 { 01162 CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN); 01163 } 01164 01165 /** 01166 * @brief Check if the USB voltage detector is enabled 01167 * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector 01168 * @retval State of bit (1 or 0). 01169 */ 01170 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void) 01171 { 01172 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL); 01173 } 01174 01175 #if defined (PWR_CPUCR_PDDS_D2) 01176 /** 01177 * @brief Set the D1 domain Power Down mode when the CPU enters deepsleep 01178 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode 01179 * @param PDMode This parameter can be one of the following values: 01180 * @arg @ref LL_PWR_CPU_MODE_D1STOP 01181 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY 01182 * @retval None 01183 */ 01184 __STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode) 01185 { 01186 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode); 01187 } 01188 #else 01189 /** 01190 * @brief Set the CPU domain Power Down mode when the CPU enters deepsleep 01191 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode 01192 * @param PDMode This parameter can be one of the following values: 01193 * @arg @ref LL_PWR_CPU_MODE_CDSTOP 01194 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 01195 * @retval None 01196 */ 01197 __STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode) 01198 { 01199 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode); 01200 } 01201 #endif /* PWR_CPUCR_PDDS_D2 */ 01202 01203 #if defined (DUAL_CORE) 01204 /** 01205 * @brief Set the D1 domain Power Down mode when the CPU2 enters deepsleep 01206 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_SetD1PowerMode 01207 * @param PDMode This parameter can be one of the following values: 01208 * @arg @ref LL_PWR_CPU2_MODE_D1STOP 01209 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY 01210 * @retval None 01211 */ 01212 __STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode) 01213 { 01214 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode); 01215 } 01216 #endif /* DUAL_CORE */ 01217 01218 #if defined (PWR_CPUCR_PDDS_D2) 01219 /** 01220 * @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep 01221 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode 01222 * @retval Returned value can be one of the following values: 01223 * @arg @ref LL_PWR_CPU_MODE_D1STOP 01224 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY 01225 */ 01226 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void) 01227 { 01228 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1)); 01229 } 01230 #else 01231 /** 01232 * @brief Get the CD Domain Power Down mode when the CPU enters deepsleep 01233 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode 01234 * @retval Returned value can be one of the following values: 01235 * @arg @ref LL_PWR_CPU_MODE_CDSTOP 01236 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2 01237 */ 01238 __STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void) 01239 { 01240 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD)); 01241 } 01242 #endif /* PWR_CPUCR_PDDS_D2 */ 01243 01244 #if defined (DUAL_CORE) 01245 /** 01246 * @brief Get the D1 Domain Power Down mode when the CPU2 enters deepsleep 01247 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_GetD1PowerMode 01248 * @retval Returned value can be one of the following values: 01249 * @arg @ref LL_PWR_CPU2_MODE_D1STOP 01250 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY 01251 */ 01252 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void) 01253 { 01254 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1)); 01255 } 01256 #endif /* DUAL_CORE */ 01257 01258 #if defined (PWR_CPUCR_PDDS_D2) 01259 /** 01260 * @brief Set the D2 domain Power Down mode when the CPU enters deepsleep 01261 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode 01262 * @param PDMode This parameter can be one of the following values: 01263 * @arg @ref LL_PWR_CPU_MODE_D2STOP 01264 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY 01265 * @retval None 01266 */ 01267 __STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode) 01268 { 01269 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode); 01270 } 01271 #endif /* PWR_CPUCR_PDDS_D2 */ 01272 01273 #if defined (DUAL_CORE) 01274 /** 01275 * @brief Set the D2 domain Power Down mode when the CPU2 enters deepsleep 01276 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_SetD2PowerMode 01277 * @param PDMode This parameter can be one of the following values: 01278 * @arg @ref LL_PWR_CPU2_MODE_D2STOP 01279 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY 01280 * @retval None 01281 */ 01282 __STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode) 01283 { 01284 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode); 01285 } 01286 #endif /* DUAL_CORE */ 01287 01288 #if defined (PWR_CPUCR_PDDS_D2) 01289 /** 01290 * @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep 01291 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode 01292 * @retval Returned value can be one of the following values: 01293 * @arg @ref LL_PWR_CPU_MODE_D2STOP 01294 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY 01295 */ 01296 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void) 01297 { 01298 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2)); 01299 } 01300 #endif /* PWR_CPUCR_PDDS_D2 */ 01301 01302 #if defined (DUAL_CORE) 01303 /** 01304 * @brief Get the D2 Domain Power Down mode when the CPU2 enters deepsleep 01305 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_GetD2PowerMode 01306 * @retval Returned value can be one of the following values: 01307 * @arg @ref LL_PWR_CPU2_MODE_D2STOP 01308 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY 01309 */ 01310 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void) 01311 { 01312 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2)); 01313 } 01314 #endif /* DUAL_CORE */ 01315 01316 #if defined (PWR_CPUCR_PDDS_D2) 01317 /** 01318 * @brief Set the D3 domain Power Down mode when the CPU enters deepsleep 01319 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode 01320 * @param PDMode This parameter can be one of the following values: 01321 * @arg @ref LL_PWR_CPU_MODE_D3STOP 01322 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY 01323 * @retval None 01324 */ 01325 __STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode) 01326 { 01327 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode); 01328 } 01329 #else 01330 /** 01331 * @brief Set the SRD domain Power Down mode when the CPU enters deepsleep 01332 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode 01333 * @param PDMode This parameter can be one of the following values: 01334 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP 01335 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY 01336 * @retval None 01337 */ 01338 __STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode) 01339 { 01340 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode); 01341 } 01342 #endif /* PWR_CPUCR_PDDS_D2 */ 01343 01344 #if defined (DUAL_CORE) 01345 /** 01346 * @brief Set the D3 domain Power Down mode when the CPU2 enters deepsleep 01347 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_SetD3PowerMode 01348 * @param PDMode This parameter can be one of the following values: 01349 * @arg @ref LL_PWR_CPU2_MODE_D3STOP 01350 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY 01351 * @retval None 01352 */ 01353 __STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode) 01354 { 01355 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode); 01356 } 01357 #endif /* DUAL_CORE */ 01358 01359 #if defined (PWR_CPUCR_PDDS_D2) 01360 /** 01361 * @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep 01362 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode 01363 * @retval Returned value can be one of the following values: 01364 * @arg @ref LL_PWR_CPU_MODE_D3STOP 01365 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY 01366 */ 01367 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void) 01368 { 01369 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3)); 01370 } 01371 #else 01372 /** 01373 * @brief Get the SRD Domain Power Down mode when the CPU enters deepsleep 01374 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_GetSRDPowerMode 01375 * @retval Returned value can be one of the following values: 01376 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP 01377 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY 01378 */ 01379 __STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void) 01380 { 01381 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD)); 01382 } 01383 #endif /* PWR_CPUCR_PDDS_D2 */ 01384 01385 #if defined (DUAL_CORE) 01386 /** 01387 * @brief Get the D3 Domain Power Down mode when the CPU2 enters deepsleep 01388 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_GetD3PowerMode 01389 * @retval Returned value can be one of the following values: 01390 * @arg @ref LL_PWR_CPU2_MODE_D3STOP 01391 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY 01392 */ 01393 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void) 01394 { 01395 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3)); 01396 } 01397 #endif /* DUAL_CORE */ 01398 01399 #if defined (DUAL_CORE) 01400 /** 01401 * @brief Hold the CPU1 and allocated peripherals when exiting from STOP mode 01402 * @rmtoll CPU2CR HOLD1 LL_PWR_HoldCPU1 01403 * @retval None 01404 */ 01405 __STATIC_INLINE void LL_PWR_HoldCPU1(void) 01406 { 01407 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); 01408 } 01409 01410 /** 01411 * @brief Release the CPU1 and allocated peripherals 01412 * @rmtoll CPU2CR HOLD1 LL_PWR_ReleaseCPU1 01413 * @retval None 01414 */ 01415 __STATIC_INLINE void LL_PWR_ReleaseCPU1(void) 01416 { 01417 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1); 01418 } 01419 01420 /** 01421 * @brief Ckeck if the CPU1 and allocated peripherals are held 01422 * @rmtoll CPU2CR HOLD1 LL_PWR_IsCPU1Held 01423 * @retval State of bit (1 or 0). 01424 */ 01425 __STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void) 01426 { 01427 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL); 01428 } 01429 01430 /** 01431 * @brief Hold the CPU2 and allocated peripherals when exiting from STOP mode 01432 * @rmtoll CPUCR HOLD2 LL_PWR_HoldCPU2 01433 * @retval None 01434 */ 01435 __STATIC_INLINE void LL_PWR_HoldCPU2(void) 01436 { 01437 SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); 01438 } 01439 01440 /** 01441 * @brief Release the CPU2 and allocated peripherals 01442 * @rmtoll CPUCR HOLD2 LL_PWR_ReleaseCPU2 01443 * @retval None 01444 */ 01445 __STATIC_INLINE void LL_PWR_ReleaseCPU2(void) 01446 { 01447 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2); 01448 } 01449 01450 /** 01451 * @brief Ckeck if the CPU2 and allocated peripherals are held 01452 * @rmtoll CPUCR HOLD2 LL_PWR_IsCPU2Held 01453 * @retval State of bit (1 or 0). 01454 */ 01455 __STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void) 01456 { 01457 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL); 01458 } 01459 #endif /* DUAL_CORE */ 01460 01461 #if defined (PWR_CPUCR_PDDS_D2) 01462 /** 01463 * @brief D3 domain remains in Run mode regardless of CPU subsystem modes 01464 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode 01465 * @retval None 01466 */ 01467 __STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void) 01468 { 01469 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); 01470 } 01471 #else 01472 /** 01473 * @brief SRD domain remains in Run mode regardless of CPU subsystem modes 01474 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode 01475 * @retval None 01476 */ 01477 __STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void) 01478 { 01479 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); 01480 } 01481 #endif /* PWR_CPUCR_PDDS_D2 */ 01482 01483 #if defined (DUAL_CORE) 01484 /** 01485 * @brief D3 domain remains in Run mode regardless of CPU2 subsystem modes 01486 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_EnableD3RunInLowPowerMode 01487 * @retval None 01488 */ 01489 __STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void) 01490 { 01491 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); 01492 } 01493 #endif /* DUAL_CORE */ 01494 01495 #if defined (PWR_CPUCR_PDDS_D2) 01496 /** 01497 * @brief D3 domain follows CPU subsystem modes 01498 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode 01499 * @retval None 01500 */ 01501 __STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void) 01502 { 01503 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3); 01504 } 01505 #else 01506 /** 01507 * @brief SRD domain follows CPU subsystem modes 01508 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode 01509 * @retval None 01510 */ 01511 __STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void) 01512 { 01513 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD); 01514 } 01515 #endif /* PWR_CPUCR_PDDS_D2 */ 01516 01517 #if defined (DUAL_CORE) 01518 /** 01519 * @brief D3 domain follows CPU2 subsystem modes 01520 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_DisableD3RunInLowPowerMode 01521 * @retval None 01522 */ 01523 __STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void) 01524 { 01525 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3); 01526 } 01527 #endif /* DUAL_CORE */ 01528 01529 #if defined (PWR_CPUCR_PDDS_D2) 01530 /** 01531 * @brief Check if D3 is kept in Run mode when CPU enters low power mode 01532 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode 01533 * @retval State of bit (1 or 0). 01534 */ 01535 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void) 01536 { 01537 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL); 01538 } 01539 #else 01540 /** 01541 * @brief Check if SRD is kept in Run mode when CPU enters low power mode 01542 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode 01543 * @retval State of bit (1 or 0). 01544 */ 01545 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void) 01546 { 01547 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL); 01548 } 01549 #endif /* PWR_CPUCR_PDDS_D2 */ 01550 01551 #if defined (DUAL_CORE) 01552 /** 01553 * @brief Check if D3 is kept in Run mode when CPU2 enters low power mode 01554 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode 01555 * @retval State of bit (1 or 0). 01556 */ 01557 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void) 01558 { 01559 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL); 01560 } 01561 #endif /* DUAL_CORE */ 01562 01563 /** 01564 * @brief Set the main internal Regulator output voltage 01565 * @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling 01566 * @param VoltageScaling This parameter can be one of the following values: 01567 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 01568 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 01569 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 01570 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 01571 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 01572 * is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1. 01573 * @retval None 01574 */ 01575 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) 01576 { 01577 #if defined (PWR_CPUCR_PDDS_D2) 01578 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling); 01579 #else 01580 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling); 01581 #endif /* PWR_CPUCR_PDDS_D2 */ 01582 } 01583 01584 /** 01585 * @brief Get the main internal Regulator output voltage 01586 * @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling 01587 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking 01588 * VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit. 01589 * @retval Returned value can be one of the following values: 01590 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0 01591 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 01592 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 01593 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 01594 */ 01595 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) 01596 { 01597 #if defined (PWR_CPUCR_PDDS_D2) 01598 return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS)); 01599 #else 01600 return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS)); 01601 #endif /* PWR_CPUCR_PDDS_D2 */ 01602 } 01603 01604 /** 01605 * @brief Enable the WakeUp PINx functionality 01606 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n 01607 * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n 01608 * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n 01609 * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n 01610 * WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n 01611 * WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin 01612 * @param WakeUpPin This parameter can be one of the following values: 01613 * @arg @ref LL_PWR_WAKEUP_PIN1 01614 * @arg @ref LL_PWR_WAKEUP_PIN2 01615 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01616 * @arg @ref LL_PWR_WAKEUP_PIN4 01617 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01618 * @arg @ref LL_PWR_WAKEUP_PIN6 01619 * 01620 * (*) value not defined in all devices. 01621 * 01622 * @retval None 01623 */ 01624 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) 01625 { 01626 SET_BIT(PWR->WKUPEPR, WakeUpPin); 01627 } 01628 01629 /** 01630 * @brief Disable the WakeUp PINx functionality 01631 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n 01632 * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n 01633 * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n 01634 * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n 01635 * WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n 01636 * WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin 01637 * @param WakeUpPin This parameter can be one of the following values: 01638 * @arg @ref LL_PWR_WAKEUP_PIN1 01639 * @arg @ref LL_PWR_WAKEUP_PIN2 01640 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01641 * @arg @ref LL_PWR_WAKEUP_PIN4 01642 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01643 * @arg @ref LL_PWR_WAKEUP_PIN6 01644 * 01645 * (*) value not defined in all devices. 01646 * 01647 * @retval None 01648 */ 01649 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) 01650 { 01651 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); 01652 } 01653 01654 /** 01655 * @brief Check if the WakeUp PINx functionality is enabled 01656 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n 01657 * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n 01658 * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n 01659 * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n 01660 * WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n 01661 * WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin 01662 * @param WakeUpPin This parameter can be one of the following values: 01663 * @arg @ref LL_PWR_WAKEUP_PIN1 01664 * @arg @ref LL_PWR_WAKEUP_PIN2 01665 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01666 * @arg @ref LL_PWR_WAKEUP_PIN4 01667 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01668 * @arg @ref LL_PWR_WAKEUP_PIN6 01669 * 01670 * (*) value not defined in all devices. 01671 * 01672 * @retval State of bit (1 or 0). 01673 */ 01674 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) 01675 { 01676 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); 01677 } 01678 01679 /** 01680 * @brief Set the Wake-Up pin polarity low for the event detection 01681 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n 01682 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n 01683 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n 01684 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n 01685 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n 01686 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow 01687 * @param WakeUpPin This parameter can be one of the following values: 01688 * @arg @ref LL_PWR_WAKEUP_PIN1 01689 * @arg @ref LL_PWR_WAKEUP_PIN2 01690 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01691 * @arg @ref LL_PWR_WAKEUP_PIN4 01692 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01693 * @arg @ref LL_PWR_WAKEUP_PIN6 01694 * 01695 * (*) value not defined in all devices. 01696 * 01697 * @retval None 01698 */ 01699 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) 01700 { 01701 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); 01702 } 01703 01704 /** 01705 * @brief Set the Wake-Up pin polarity high for the event detection 01706 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n 01707 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n 01708 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n 01709 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n 01710 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n 01711 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh 01712 * @param WakeUpPin This parameter can be one of the following values: 01713 * @arg @ref LL_PWR_WAKEUP_PIN1 01714 * @arg @ref LL_PWR_WAKEUP_PIN2 01715 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01716 * @arg @ref LL_PWR_WAKEUP_PIN4 01717 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01718 * @arg @ref LL_PWR_WAKEUP_PIN6 01719 * 01720 * (*) value not defined in all devices. 01721 * 01722 * @retval None 01723 */ 01724 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) 01725 { 01726 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); 01727 } 01728 01729 /** 01730 * @brief Get the Wake-Up pin polarity for the event detection 01731 * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n 01732 * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n 01733 * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n 01734 * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n 01735 * WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n 01736 * WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow 01737 * @param WakeUpPin This parameter can be one of the following values: 01738 * @arg @ref LL_PWR_WAKEUP_PIN1 01739 * @arg @ref LL_PWR_WAKEUP_PIN2 01740 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01741 * @arg @ref LL_PWR_WAKEUP_PIN4 01742 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01743 * @arg @ref LL_PWR_WAKEUP_PIN6 01744 * 01745 * (*) value not defined in all devices. 01746 * 01747 * @retval State of bit (1 or 0). 01748 */ 01749 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) 01750 { 01751 return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL); 01752 } 01753 01754 /** 01755 * @brief Set the Wake-Up pin Pull None 01756 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n 01757 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n 01758 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n 01759 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n 01760 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n 01761 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone 01762 * @param WakeUpPin This parameter can be one of the following values: 01763 * @arg @ref LL_PWR_WAKEUP_PIN1 01764 * @arg @ref LL_PWR_WAKEUP_PIN2 01765 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01766 * @arg @ref LL_PWR_WAKEUP_PIN4 01767 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01768 * @arg @ref LL_PWR_WAKEUP_PIN6 01769 * 01770 * (*) value not defined in all devices. 01771 * 01772 * @retval None 01773 */ 01774 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin) 01775 { 01776 MODIFY_REG(PWR->WKUPEPR, \ 01777 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ 01778 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); 01779 } 01780 01781 /** 01782 * @brief Set the Wake-Up pin Pull Up 01783 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n 01784 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n 01785 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n 01786 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n 01787 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n 01788 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp 01789 * @param WakeUpPin This parameter can be one of the following values: 01790 * @arg @ref LL_PWR_WAKEUP_PIN1 01791 * @arg @ref LL_PWR_WAKEUP_PIN2 01792 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01793 * @arg @ref LL_PWR_WAKEUP_PIN4 01794 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01795 * @arg @ref LL_PWR_WAKEUP_PIN6 01796 * 01797 * (*) value not defined in all devices. 01798 * 01799 * @retval None 01800 */ 01801 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin) 01802 { 01803 MODIFY_REG(PWR->WKUPEPR, \ 01804 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ 01805 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); 01806 } 01807 01808 /** 01809 * @brief Set the Wake-Up pin Pull Down 01810 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n 01811 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n 01812 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n 01813 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n 01814 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n 01815 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown 01816 * @param WakeUpPin This parameter can be one of the following values: 01817 * @arg @ref LL_PWR_WAKEUP_PIN1 01818 * @arg @ref LL_PWR_WAKEUP_PIN2 01819 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01820 * @arg @ref LL_PWR_WAKEUP_PIN4 01821 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01822 * @arg @ref LL_PWR_WAKEUP_PIN6 01823 * 01824 * (*) value not defined in all devices. 01825 * 01826 * @retval None 01827 */ 01828 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin) 01829 { 01830 MODIFY_REG(PWR->WKUPEPR, \ 01831 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \ 01832 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); 01833 } 01834 01835 /** 01836 * @brief Get the Wake-Up pin pull 01837 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n 01838 * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n 01839 * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n 01840 * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n 01841 * WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n 01842 * WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull 01843 * @param WakeUpPin This parameter can be one of the following values: 01844 * @arg @ref LL_PWR_WAKEUP_PIN1 01845 * @arg @ref LL_PWR_WAKEUP_PIN2 01846 * @arg @ref LL_PWR_WAKEUP_PIN3 (*) 01847 * @arg @ref LL_PWR_WAKEUP_PIN4 01848 * @arg @ref LL_PWR_WAKEUP_PIN5 (*) 01849 * @arg @ref LL_PWR_WAKEUP_PIN6 01850 * 01851 * (*) value not defined in all devices. 01852 * 01853 * @retval Returned value can be one of the following values: 01854 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL 01855 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP 01856 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN 01857 */ 01858 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin) 01859 { 01860 uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK))); 01861 01862 return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)); 01863 } 01864 01865 /** 01866 * @} 01867 */ 01868 01869 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management 01870 * @{ 01871 */ 01872 01873 /** 01874 * @brief Indicate whether VDD voltage is below the selected PVD threshold 01875 * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO 01876 * @retval State of bit (1 or 0). 01877 */ 01878 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) 01879 { 01880 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL); 01881 } 01882 01883 /** 01884 * @brief Indicate whether the voltage level is ready for current actual used VOS 01885 * @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS 01886 * @retval State of bit (1 or 0). 01887 */ 01888 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) 01889 { 01890 return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL); 01891 } 01892 01893 /** 01894 * @brief Indicate whether VDDA voltage is below the selected AVD threshold 01895 * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO 01896 * @retval State of bit (1 or 0). 01897 */ 01898 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void) 01899 { 01900 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL); 01901 } 01902 01903 #if defined (PWR_CSR1_MMCVDO) 01904 /** 01905 * @brief Indicate whether VDDMMC voltage is below 1V2 01906 * @rmtoll CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO 01907 * @retval State of bit (1 or 0). 01908 */ 01909 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void) 01910 { 01911 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL); 01912 } 01913 #endif /* PWR_CSR1_MMCVDO */ 01914 01915 /** 01916 * @brief Get Backup Regulator ready Flag 01917 * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR 01918 * @retval State of bit (1 or 0). 01919 */ 01920 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void) 01921 { 01922 return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL); 01923 } 01924 01925 /** 01926 * @brief Indicate whether the VBAT level is above or below low threshold 01927 * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL 01928 * @retval State of bit (1 or 0). 01929 */ 01930 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void) 01931 { 01932 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL); 01933 } 01934 01935 /** 01936 * @brief Indicate whether the VBAT level is above or below high threshold 01937 * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH 01938 * @retval State of bit (1 or 0). 01939 */ 01940 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) 01941 { 01942 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL); 01943 } 01944 01945 /** 01946 * @brief Indicate whether the CPU temperature level is above or below low threshold 01947 * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL 01948 * @retval State of bit (1 or 0). 01949 */ 01950 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) 01951 { 01952 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL); 01953 } 01954 01955 /** 01956 * @brief Indicate whether the CPU temperature level is above or below high threshold 01957 * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH 01958 * @retval State of bit (1 or 0). 01959 */ 01960 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) 01961 { 01962 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL); 01963 } 01964 01965 #if defined (SMPS) 01966 /** 01967 * @brief Indicate whether the SMPS external supply is ready or not 01968 * @rmtoll CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT 01969 * @retval State of bit (1 or 0). 01970 */ 01971 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void) 01972 { 01973 return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL); 01974 } 01975 #endif /* SMPS */ 01976 01977 /** 01978 * @brief Indicate whether the USB supply is ready or not 01979 * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB 01980 * @retval State of bit (1 or 0). 01981 */ 01982 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void) 01983 { 01984 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL); 01985 } 01986 01987 #if defined (DUAL_CORE) 01988 /** 01989 * @brief Get HOLD2 Flag 01990 * @rmtoll CPUCR HOLD2F LL_PWR_IsActiveFlag_HOLD2 01991 * @retval State of bit (1 or 0). 01992 */ 01993 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void) 01994 { 01995 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL); 01996 } 01997 01998 /** 01999 * @brief Get HOLD1 Flag 02000 * @rmtoll CPU2CR HOLD1F LL_PWR_IsActiveFlag_HOLD1 02001 * @retval State of bit (1 or 0). 02002 */ 02003 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void) 02004 { 02005 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL); 02006 } 02007 #endif /* DUAL_CORE */ 02008 02009 /** 02010 * @brief Get CPU System Stop Flag 02011 * @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP 02012 * @retval State of bit (1 or 0). 02013 */ 02014 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void) 02015 { 02016 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL); 02017 } 02018 02019 #if defined (DUAL_CORE) 02020 /** 02021 * @brief Get CPU2 System Stop Flag 02022 * @rmtoll CPU2CR STOPF LL_PWR_CPU2_IsActiveFlag_STOP 02023 * @retval State of bit (1 or 0). 02024 */ 02025 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void) 02026 { 02027 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL); 02028 } 02029 #endif /* DUAL_CORE */ 02030 02031 /** 02032 * @brief Get CPU System Standby Flag 02033 * @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB 02034 * @retval State of bit (1 or 0). 02035 */ 02036 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void) 02037 { 02038 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL); 02039 } 02040 02041 #if defined (DUAL_CORE) 02042 /** 02043 * @brief Get CPU2 System Standby Flag 02044 * @rmtoll CPU2CR SBF LL_PWR_CPU2_IsActiveFlag_SB 02045 * @retval State of bit (1 or 0). 02046 */ 02047 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void) 02048 { 02049 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL); 02050 } 02051 #endif /* DUAL_CORE */ 02052 02053 #if defined (PWR_CPUCR_SBF_D1) 02054 /** 02055 * @brief Get CPU D1 Domain Standby Flag 02056 * @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1 02057 * @retval State of bit (1 or 0). 02058 */ 02059 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void) 02060 { 02061 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL); 02062 } 02063 #endif /* PWR_CPUCR_SBF_D1 */ 02064 02065 #if defined (DUAL_CORE) 02066 /** 02067 * @brief Get CPU2 D1 Domain Standby Flag 02068 * @rmtoll CPU2CR SBF_D1 LL_PWR_CPU2_IsActiveFlag_SB_D1 02069 * @retval State of bit (1 or 0). 02070 */ 02071 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void) 02072 { 02073 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL); 02074 } 02075 #endif /* DUAL_CORE */ 02076 02077 #if defined (PWR_CPUCR_SBF_D2) 02078 /** 02079 * @brief Get CPU D2 Domain Standby Flag 02080 * @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2 02081 * @retval State of bit (1 or 0). 02082 */ 02083 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void) 02084 { 02085 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL); 02086 } 02087 #endif /* PWR_CPUCR_SBF_D2 */ 02088 02089 #if defined (DUAL_CORE) 02090 /** 02091 * @brief Get CPU2 D2 Domain Standby Flag 02092 * @rmtoll CPU2CR SBF_D2 LL_PWR_CPU2_IsActiveFlag_SB_D2 02093 * @retval State of bit (1 or 0). 02094 */ 02095 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void) 02096 { 02097 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL); 02098 } 02099 #endif /* DUAL_CORE */ 02100 02101 02102 /** 02103 * @brief Indicate whether the Regulator is ready in the selected voltage range 02104 * or if its output voltage is still changing to the required voltage level 02105 * @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS 02106 * @retval State of bit (1 or 0). 02107 */ 02108 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) 02109 { 02110 #if defined (PWR_CPUCR_PDDS_D2) 02111 return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL); 02112 #else 02113 return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL); 02114 #endif /* PWR_CPUCR_PDDS_D2 */ 02115 } 02116 02117 /** 02118 * @brief Get Wake-up Flag 6 02119 * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6 02120 * @retval State of bit (1 or 0). 02121 */ 02122 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) 02123 { 02124 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL); 02125 } 02126 02127 #if defined (PWR_WKUPFR_WKUPF5) 02128 /** 02129 * @brief Get Wake-up Flag 5 02130 * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5 02131 * @retval State of bit (1 or 0). 02132 */ 02133 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) 02134 { 02135 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL); 02136 } 02137 #endif /* defined (PWR_WKUPFR_WKUPF5) */ 02138 02139 /** 02140 * @brief Get Wake-up Flag 4 02141 * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4 02142 * @retval State of bit (1 or 0). 02143 */ 02144 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) 02145 { 02146 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL); 02147 } 02148 02149 #if defined (PWR_WKUPFR_WKUPF3) 02150 /** 02151 * @brief Get Wake-up Flag 3 02152 * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3 02153 * @retval State of bit (1 or 0). 02154 */ 02155 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) 02156 { 02157 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL); 02158 } 02159 #endif /* defined (PWR_WKUPFR_WKUPF3) */ 02160 02161 /** 02162 * @brief Get Wake-up Flag 2 02163 * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2 02164 * @retval State of bit (1 or 0). 02165 */ 02166 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) 02167 { 02168 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL); 02169 } 02170 02171 /** 02172 * @brief Get Wake-up Flag 1 02173 * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1 02174 * @retval State of bit (1 or 0). 02175 */ 02176 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) 02177 { 02178 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL); 02179 } 02180 02181 /** 02182 * @brief Clear CPU STANDBY, STOP and HOLD flags 02183 * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU 02184 * @retval None 02185 */ 02186 __STATIC_INLINE void LL_PWR_ClearFlag_CPU(void) 02187 { 02188 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF); 02189 } 02190 02191 #if defined (DUAL_CORE) 02192 /** 02193 * @brief Clear CPU2 STANDBY, STOP and HOLD flags 02194 * @rmtoll CPU2CR CSSF LL_PWR_ClearFlag_CPU2 02195 * @retval None 02196 */ 02197 __STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void) 02198 { 02199 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); 02200 } 02201 #endif /* DUAL_CORE */ 02202 02203 /** 02204 * @brief Clear Wake-up Flag 6 02205 * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6 02206 * @retval None 02207 */ 02208 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) 02209 { 02210 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6); 02211 } 02212 02213 #if defined (PWR_WKUPCR_WKUPC5) 02214 /** 02215 * @brief Clear Wake-up Flag 5 02216 * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5 02217 * @retval None 02218 */ 02219 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) 02220 { 02221 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5); 02222 } 02223 #endif /* defined (PWR_WKUPCR_WKUPC5) */ 02224 02225 /** 02226 * @brief Clear Wake-up Flag 4 02227 * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4 02228 * @retval None 02229 */ 02230 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) 02231 { 02232 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); 02233 } 02234 02235 #if defined (PWR_WKUPCR_WKUPC3) 02236 /** 02237 * @brief Clear Wake-up Flag 3 02238 * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3 02239 * @retval None 02240 */ 02241 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) 02242 { 02243 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); 02244 } 02245 #endif /* defined (PWR_WKUPCR_WKUPC3) */ 02246 02247 /** 02248 * @brief Clear Wake-up Flag 2 02249 * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2 02250 * @retval None 02251 */ 02252 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) 02253 { 02254 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); 02255 } 02256 02257 /** 02258 * @brief Clear Wake-up Flag 1 02259 * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1 02260 * @retval None 02261 */ 02262 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) 02263 { 02264 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); 02265 } 02266 02267 #if defined (USE_FULL_LL_DRIVER) 02268 /** @defgroup PWR_LL_EF_Init De-initialization function 02269 * @{ 02270 */ 02271 ErrorStatus LL_PWR_DeInit(void); 02272 /** 02273 * @} 02274 */ 02275 #endif /* defined (USE_FULL_LL_DRIVER) */ 02276 02277 02278 /** 02279 * @} 02280 */ 02281 02282 /** 02283 * @} 02284 */ 02285 02286 /** 02287 * @} 02288 */ 02289 02290 #endif /* defined (PWR) */ 02291 02292 /** 02293 * @} 02294 */ 02295 02296 #ifdef __cplusplus 02297 } 02298 #endif 02299 02300 #endif /* STM32H7xx_LL_PWR_H */ 02301
1.7.6.1