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STM32H735xx HAL User Manual
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Header file of SPI LL module. More...
#include "stm32h7xx.h"Go to the source code of this file.
Data Structures | |
| struct | LL_SPI_InitTypeDef |
| SPI Init structures definition. More... | |
| struct | LL_I2S_InitTypeDef |
| I2S Init structure definition. More... | |
Defines | |
| #define | LL_SPI_SR_RXP (SPI_SR_RXP) |
| #define | LL_SPI_SR_TXP (SPI_SR_TXP) |
| #define | LL_SPI_SR_DXP (SPI_SR_DXP) |
| #define | LL_SPI_SR_EOT (SPI_SR_EOT) |
| #define | LL_SPI_SR_TXTF (SPI_SR_TXTF) |
| #define | LL_SPI_SR_UDR (SPI_SR_UDR) |
| #define | LL_SPI_SR_CRCE (SPI_SR_CRCE) |
| #define | LL_SPI_SR_MODF (SPI_SR_MODF) |
| #define | LL_SPI_SR_OVR (SPI_SR_OVR) |
| #define | LL_SPI_SR_TIFRE (SPI_SR_TIFRE) |
| #define | LL_SPI_SR_TSERF (SPI_SR_TSERF) |
| #define | LL_SPI_SR_SUSP (SPI_SR_SUSP) |
| #define | LL_SPI_SR_TXC (SPI_SR_TXC) |
| #define | LL_SPI_SR_RXWNE (SPI_SR_RXWNE) |
| #define | LL_SPI_IER_RXPIE (SPI_IER_RXPIE) |
| #define | LL_SPI_IER_TXPIE (SPI_IER_TXPIE) |
| #define | LL_SPI_IER_DXPIE (SPI_IER_DXPIE) |
| #define | LL_SPI_IER_EOTIE (SPI_IER_EOTIE) |
| #define | LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE) |
| #define | LL_SPI_IER_UDRIE (SPI_IER_UDRIE) |
| #define | LL_SPI_IER_OVRIE (SPI_IER_OVRIE) |
| #define | LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE) |
| #define | LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE) |
| #define | LL_SPI_IER_MODFIE (SPI_IER_MODFIE) |
| #define | LL_SPI_IER_TSERFIE (SPI_IER_TSERFIE) |
| #define | LL_SPI_MODE_MASTER (SPI_CFG2_MASTER) |
| #define | LL_SPI_MODE_SLAVE (0x00000000UL) |
| #define | LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI) |
| #define | LL_SPI_SS_LEVEL_LOW (0x00000000UL) |
| #define | LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL) |
| #define | LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0) |
| #define | LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1) |
| #define | LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1) |
| #define | LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2) |
| #define | LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) |
| #define | LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) |
| #define | LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) |
| #define | LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3) |
| #define | LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0) |
| #define | LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1) |
| #define | LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) |
| #define | LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2) |
| #define | LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) |
| #define | LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) |
| #define | LL_SPI_SS_IDLENESS_15CYCLE |
| #define | LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL) |
| #define | LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0) |
| #define | LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1) |
| #define | LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1) |
| #define | LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2) |
| #define | LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) |
| #define | LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) |
| #define | LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) |
| #define | LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3) |
| #define | LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0) |
| #define | LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1) |
| #define | LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) |
| #define | LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2) |
| #define | LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) |
| #define | LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) |
| #define | LL_SPI_ID_IDLENESS_15CYCLE |
| #define | LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) |
| #define | LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI) |
| #define | LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) |
| #define | LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI) |
| #define | LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL) |
| #define | LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG_0) |
| #define | LL_SPI_UDR_CONFIG_LAST_TRANSMITTED (SPI_CFG1_UDRCFG_1) |
| #define | LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME (0x00000000UL) |
| #define | LL_SPI_UDR_DETECT_END_DATA_FRAME (SPI_CFG1_UDRDET_0) |
| #define | LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS (SPI_CFG1_UDRDET_1) |
| #define | LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL) |
| #define | LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0) |
| #define | LL_SPI_PHASE_1EDGE (0x00000000UL) |
| #define | LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA) |
| #define | LL_SPI_POLARITY_LOW (0x00000000UL) |
| #define | LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL) |
| #define | LL_SPI_NSS_POLARITY_LOW (0x00000000UL) |
| #define | LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP) |
| #define | LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL) |
| #define | LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0) |
| #define | LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1) |
| #define | LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) |
| #define | LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2) |
| #define | LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0) |
| #define | LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1) |
| #define | LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) |
| #define | LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST) |
| #define | LL_SPI_MSB_FIRST (0x00000000UL) |
| #define | LL_SPI_FULL_DUPLEX (0x00000000UL) |
| #define | LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0) |
| #define | LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1) |
| #define | LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1) |
| #define | LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR) |
| #define | LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) |
| #define | LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2) |
| #define | LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) |
| #define | LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) |
| #define | LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) |
| #define | LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3) |
| #define | LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) |
| #define | LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) |
| #define | LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) |
| #define | LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) |
| #define | LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) |
| #define | LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) |
| #define | LL_SPI_DATAWIDTH_16BIT |
| #define | LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4) |
| #define | LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0) |
| #define | LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1) |
| #define | LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) |
| #define | LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2) |
| #define | LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) |
| #define | LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) |
| #define | LL_SPI_DATAWIDTH_24BIT |
| #define | LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3) |
| #define | LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) |
| #define | LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) |
| #define | LL_SPI_DATAWIDTH_28BIT |
| #define | LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) |
| #define | LL_SPI_DATAWIDTH_30BIT |
| #define | LL_SPI_DATAWIDTH_31BIT |
| #define | LL_SPI_DATAWIDTH_32BIT |
| #define | LL_SPI_FIFO_TH_01DATA (0x00000000UL) |
| #define | LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0) |
| #define | LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1) |
| #define | LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) |
| #define | LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2) |
| #define | LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) |
| #define | LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) |
| #define | LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) |
| #define | LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3) |
| #define | LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0) |
| #define | LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1) |
| #define | LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) |
| #define | LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2) |
| #define | LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) |
| #define | LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) |
| #define | LL_SPI_FIFO_TH_16DATA |
| #define | LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) |
| #define | LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) |
| #define | LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) |
| #define | LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2) |
| #define | LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) |
| #define | LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) |
| #define | LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) |
| #define | LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3) |
| #define | LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) |
| #define | LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) |
| #define | LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) |
| #define | LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) |
| #define | LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) |
| #define | LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) |
| #define | LL_SPI_CRC_16BIT |
| #define | LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4) |
| #define | LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0) |
| #define | LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1) |
| #define | LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) |
| #define | LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2) |
| #define | LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) |
| #define | LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) |
| #define | LL_SPI_CRC_24BIT |
| #define | LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3) |
| #define | LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) |
| #define | LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) |
| #define | LL_SPI_CRC_28BIT |
| #define | LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) |
| #define | LL_SPI_CRC_30BIT |
| #define | LL_SPI_CRC_31BIT |
| #define | LL_SPI_CRC_32BIT |
| #define | LL_SPI_NSS_SOFT (SPI_CFG2_SSM) |
| #define | LL_SPI_NSS_HARD_INPUT (0x00000000UL) |
| #define | LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE) |
| #define | LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ |
| #define | LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) |
| #define | LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) |
| #define | LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) |
| #define | LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| Write a value in SPI register. | |
| #define | LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| Read a value in SPI register. | |
| #define | LL_I2S_DATAFORMAT_16B (0x00000000UL) |
| #define | LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) |
| #define | LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) |
| #define | LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT) |
| #define | LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) |
| #define | LL_I2S_SLAVE_VARIABLE_CH_LENGTH (0x00000000UL) |
| #define | LL_I2S_SLAVE_FIXED_CH_LENGTH (SPI_I2SCFGR_FIXCH) |
| #define | LL_I2S_POLARITY_LOW (0x00000000UL) |
| #define | LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) |
| #define | LL_I2S_STANDARD_PHILIPS (0x00000000UL) |
| #define | LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) |
| #define | LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) |
| #define | LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) |
| #define | LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) |
| #define | LL_I2S_MODE_SLAVE_TX (0x00000000UL) |
| #define | LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) |
| #define | LL_I2S_MODE_SLAVE_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2) |
| #define | LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) |
| #define | LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0) |
| #define | LL_I2S_MODE_MASTER_FULL_DUPLEX (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0) |
| #define | LL_I2S_PRESCALER_PARITY_EVEN (0x00000000UL) |
| #define | LL_I2S_PRESCALER_PARITY_ODD (0x00000001UL) |
| #define | LL_I2S_FIFO_TH_01DATA (LL_SPI_FIFO_TH_01DATA) |
| #define | LL_I2S_FIFO_TH_02DATA (LL_SPI_FIFO_TH_02DATA) |
| #define | LL_I2S_FIFO_TH_03DATA (LL_SPI_FIFO_TH_03DATA) |
| #define | LL_I2S_FIFO_TH_04DATA (LL_SPI_FIFO_TH_04DATA) |
| #define | LL_I2S_FIFO_TH_05DATA (LL_SPI_FIFO_TH_05DATA) |
| #define | LL_I2S_FIFO_TH_06DATA (LL_SPI_FIFO_TH_06DATA) |
| #define | LL_I2S_FIFO_TH_07DATA (LL_SPI_FIFO_TH_07DATA) |
| #define | LL_I2S_FIFO_TH_08DATA (LL_SPI_FIFO_TH_08DATA) |
| #define | LL_I2S_LSB_FIRST (LL_SPI_LSB_FIRST) |
| #define | LL_I2S_MSB_FIRST (LL_SPI_MSB_FIRST) |
| #define | LL_I2S_MCLK_OUTPUT_DISABLE (0x00000000UL) |
| #define | LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SCFGR_MCKOE) |
| #define | LL_I2S_AUDIOFREQ_192K 192000UL |
| #define | LL_I2S_AUDIOFREQ_96K 96000UL |
| #define | LL_I2S_AUDIOFREQ_48K 48000UL |
| #define | LL_I2S_AUDIOFREQ_44K 44100UL |
| #define | LL_I2S_AUDIOFREQ_32K 32000UL |
| #define | LL_I2S_AUDIOFREQ_22K 22050UL |
| #define | LL_I2S_AUDIOFREQ_16K 16000UL |
| #define | LL_I2S_AUDIOFREQ_11K 11025UL |
| #define | LL_I2S_AUDIOFREQ_8K 8000UL |
| #define | LL_I2S_AUDIOFREQ_DEFAULT 0UL |
| #define | LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| Write a value in I2S register. | |
| #define | LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| Read a value in I2S register. | |
Functions | |
| __STATIC_INLINE void | LL_SPI_Enable (SPI_TypeDef *SPIx) |
| Enable SPI peripheral. | |
| __STATIC_INLINE void | LL_SPI_Disable (SPI_TypeDef *SPIx) |
| Disable SPI peripheral. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabled (SPI_TypeDef *SPIx) |
| Check if SPI peripheral is enabled. | |
| __STATIC_INLINE void | LL_SPI_EnableIOSwap (SPI_TypeDef *SPIx) |
| Swap the MOSI and MISO pin. | |
| __STATIC_INLINE void | LL_SPI_DisableIOSwap (SPI_TypeDef *SPIx) |
| Restore default function for MOSI and MISO pin. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIOSwap (SPI_TypeDef *SPIx) |
| Check if MOSI and MISO pin are swapped. | |
| __STATIC_INLINE void | LL_SPI_EnableGPIOControl (SPI_TypeDef *SPIx) |
| Enable GPIO control. | |
| __STATIC_INLINE void | LL_SPI_DisableGPIOControl (SPI_TypeDef *SPIx) |
| Disable GPIO control. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledGPIOControl (SPI_TypeDef *SPIx) |
| Check if GPIO control is active. | |
| __STATIC_INLINE void | LL_SPI_SetMode (SPI_TypeDef *SPIx, uint32_t Mode) |
| Set SPI Mode to Master or Slave. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetMode (SPI_TypeDef *SPIx) |
| Get SPI Mode (Master or Slave) | |
| __STATIC_INLINE void | LL_SPI_SetMasterSSIdleness (SPI_TypeDef *SPIx, uint32_t MasterSSIdleness) |
| Configure the Idleness applied by master between active edge of SS and first send data. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetMasterSSIdleness (SPI_TypeDef *SPIx) |
| Get the configured Idleness applied by master. | |
| __STATIC_INLINE void | LL_SPI_SetInterDataIdleness (SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness) |
| Configure the idleness applied by master between data frame. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetInterDataIdleness (SPI_TypeDef *SPIx) |
| Get the configured inter data idleness. | |
| __STATIC_INLINE void | LL_SPI_SetTransferSize (SPI_TypeDef *SPIx, uint32_t Count) |
| Set transfer size. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetTransferSize (SPI_TypeDef *SPIx) |
| Get transfer size. | |
| __STATIC_INLINE void | LL_SPI_SetReloadSize (SPI_TypeDef *SPIx, uint32_t Count) |
| Set reload transfer size. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetReloadSize (SPI_TypeDef *SPIx) |
| Get reload transfer size. | |
| __STATIC_INLINE void | LL_SPI_EnableIOLock (SPI_TypeDef *SPIx) |
| Lock the AF configuration of associated IOs. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIOLock (SPI_TypeDef *SPIx) |
| Check if the AF configuration is locked. | |
| __STATIC_INLINE void | LL_SPI_SetTxCRCInitPattern (SPI_TypeDef *SPIx, uint32_t TXCRCInitAll) |
| Set Tx CRC Initialization Pattern. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetTxCRCInitPattern (SPI_TypeDef *SPIx) |
| Get Tx CRC Initialization Pattern. | |
| __STATIC_INLINE void | LL_SPI_SetRxCRCInitPattern (SPI_TypeDef *SPIx, uint32_t RXCRCInitAll) |
| Set Rx CRC Initialization Pattern. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetRxCRCInitPattern (SPI_TypeDef *SPIx) |
| Get Rx CRC Initialization Pattern. | |
| __STATIC_INLINE void | LL_SPI_SetInternalSSLevel (SPI_TypeDef *SPIx, uint32_t SSLevel) |
| Set internal SS input level ignoring what comes from PIN. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetInternalSSLevel (SPI_TypeDef *SPIx) |
| Get internal SS input level. | |
| __STATIC_INLINE void | LL_SPI_EnableFullSizeCRC (SPI_TypeDef *SPIx) |
| Enable CRC computation on 33/17 bits. | |
| __STATIC_INLINE void | LL_SPI_DisableFullSizeCRC (SPI_TypeDef *SPIx) |
| Disable CRC computation on 33/17 bits. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledFullSizeCRC (SPI_TypeDef *SPIx) |
| Check if Enable CRC computation on 33/17 bits is enabled. | |
| __STATIC_INLINE void | LL_SPI_SuspendMasterTransfer (SPI_TypeDef *SPIx) |
| Suspend an ongoing transfer for Master configuration. | |
| __STATIC_INLINE void | LL_SPI_StartMasterTransfer (SPI_TypeDef *SPIx) |
| Start effective transfer on wire for Master configuration. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveMasterTransfer (SPI_TypeDef *SPIx) |
| Check if there is an unfinished master transfer. | |
| __STATIC_INLINE void | LL_SPI_EnableMasterRxAutoSuspend (SPI_TypeDef *SPIx) |
| Enable Master Rx auto suspend in case of overrun. | |
| __STATIC_INLINE void | LL_SPI_DisableMasterRxAutoSuspend (SPI_TypeDef *SPIx) |
| Disable Master Rx auto suspend in case of overrun. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledMasterRxAutoSuspend (SPI_TypeDef *SPIx) |
| Check if Master Rx auto suspend is activated. | |
| __STATIC_INLINE void | LL_SPI_SetUDRConfiguration (SPI_TypeDef *SPIx, uint32_t UDRConfig) |
| Set Underrun behavior. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetUDRConfiguration (SPI_TypeDef *SPIx) |
| Get Underrun behavior. | |
| __STATIC_INLINE void | LL_SPI_SetUDRDetection (SPI_TypeDef *SPIx, uint32_t UDRDetection) |
| Set Underrun Detection method. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetUDRDetection (SPI_TypeDef *SPIx) |
| Get Underrun Detection method. | |
| __STATIC_INLINE void | LL_SPI_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard) |
| Set Serial protocol used. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetStandard (SPI_TypeDef *SPIx) |
| Get Serial protocol used. | |
| __STATIC_INLINE void | LL_SPI_SetClockPhase (SPI_TypeDef *SPIx, uint32_t ClockPhase) |
| Set Clock phase. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetClockPhase (SPI_TypeDef *SPIx) |
| Get Clock phase. | |
| __STATIC_INLINE void | LL_SPI_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity) |
| Set Clock polarity. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetClockPolarity (SPI_TypeDef *SPIx) |
| Get Clock polarity. | |
| __STATIC_INLINE void | LL_SPI_SetNSSPolarity (SPI_TypeDef *SPIx, uint32_t NSSPolarity) |
| Set NSS polarity. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetNSSPolarity (SPI_TypeDef *SPIx) |
| Get NSS polarity. | |
| __STATIC_INLINE void | LL_SPI_SetBaudRatePrescaler (SPI_TypeDef *SPIx, uint32_t Baudrate) |
| Set Baudrate Prescaler. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetBaudRatePrescaler (SPI_TypeDef *SPIx) |
| Get Baudrate Prescaler. | |
| __STATIC_INLINE void | LL_SPI_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder) |
| Set Transfer Bit Order. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetTransferBitOrder (SPI_TypeDef *SPIx) |
| Get Transfer Bit Order. | |
| __STATIC_INLINE void | LL_SPI_SetTransferDirection (SPI_TypeDef *SPIx, uint32_t TransferDirection) |
| Set Transfer Mode. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetTransferDirection (SPI_TypeDef *SPIx) |
| Get Transfer Mode. | |
| __STATIC_INLINE void | LL_SPI_SetHalfDuplexDirection (SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection) |
| Set direction for Half-Duplex Mode. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetHalfDuplexDirection (SPI_TypeDef *SPIx) |
| Get direction for Half-Duplex Mode. | |
| __STATIC_INLINE void | LL_SPI_SetDataWidth (SPI_TypeDef *SPIx, uint32_t DataWidth) |
| Set Frame Data Size. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetDataWidth (SPI_TypeDef *SPIx) |
| Get Frame Data Size. | |
| __STATIC_INLINE void | LL_SPI_SetFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold) |
| Set threshold of FIFO that triggers a transfer event. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetFIFOThreshold (SPI_TypeDef *SPIx) |
| Get threshold of FIFO that triggers a transfer event. | |
| __STATIC_INLINE void | LL_SPI_EnableCRC (SPI_TypeDef *SPIx) |
| Enable CRC. | |
| __STATIC_INLINE void | LL_SPI_DisableCRC (SPI_TypeDef *SPIx) |
| Disable CRC. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledCRC (SPI_TypeDef *SPIx) |
| Check if CRC is enabled. | |
| __STATIC_INLINE void | LL_SPI_SetCRCWidth (SPI_TypeDef *SPIx, uint32_t CRCLength) |
| Set CRC Length. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetCRCWidth (SPI_TypeDef *SPIx) |
| Get CRC Length. | |
| __STATIC_INLINE void | LL_SPI_SetNSSMode (SPI_TypeDef *SPIx, uint32_t NSS) |
| Set NSS Mode. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetNSSMode (SPI_TypeDef *SPIx) |
| Set NSS Mode. | |
| __STATIC_INLINE void | LL_SPI_EnableNSSPulseMgt (SPI_TypeDef *SPIx) |
| Enable NSS pulse mgt. | |
| __STATIC_INLINE void | LL_SPI_DisableNSSPulseMgt (SPI_TypeDef *SPIx) |
| Disable NSS pulse mgt. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledNSSPulse (SPI_TypeDef *SPIx) |
| Check if NSS pulse is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXP (SPI_TypeDef *SPIx) |
| Check if there is enough data in FIFO to read a full packet. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXP (SPI_TypeDef *SPIx) |
| Check if there is enough space in FIFO to hold a full packet. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_DXP (SPI_TypeDef *SPIx) |
| Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_EOT (SPI_TypeDef *SPIx) |
| Check that end of transfer event occurred. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXTF (SPI_TypeDef *SPIx) |
| Check that all required data has been filled in the fifo according to transfer size. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_UDR (SPI_TypeDef *SPIx) |
| Get Underrun error flag. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_CRCERR (SPI_TypeDef *SPIx) |
| Get CRC error flag. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_MODF (SPI_TypeDef *SPIx) |
| Get Mode fault error flag. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_OVR (SPI_TypeDef *SPIx) |
| Get Overrun error flag. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_FRE (SPI_TypeDef *SPIx) |
| Get TI Frame format error flag. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TSER (SPI_TypeDef *SPIx) |
| Check if the additional number of data has been reloaded. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_SUSP (SPI_TypeDef *SPIx) |
| Check if a suspend operation is done. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_TXC (SPI_TypeDef *SPIx) |
| Check if last TxFIFO or CRC frame transmission is completed. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsActiveFlag_RXWNE (SPI_TypeDef *SPIx) |
| Check if at least one 32-bit data is available in RxFIFO. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetRemainingDataFrames (SPI_TypeDef *SPIx) |
| Get number of data framed remaining in current TSIZE. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetRxFIFOPackingLevel (SPI_TypeDef *SPIx) |
| Get RxFIFO packing Level. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_EOT (SPI_TypeDef *SPIx) |
| Clear End Of Transfer flag. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_TXTF (SPI_TypeDef *SPIx) |
| Clear TXTF flag. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_UDR (SPI_TypeDef *SPIx) |
| Clear Underrun error flag. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_OVR (SPI_TypeDef *SPIx) |
| Clear Overrun error flag. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_CRCERR (SPI_TypeDef *SPIx) |
| Clear CRC error flag. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_MODF (SPI_TypeDef *SPIx) |
| Clear Mode fault error flag. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_FRE (SPI_TypeDef *SPIx) |
| Clear Frame format error flag. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_TSER (SPI_TypeDef *SPIx) |
| Clear TSER flag. | |
| __STATIC_INLINE void | LL_SPI_ClearFlag_SUSP (SPI_TypeDef *SPIx) |
| Clear SUSP flag. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_RXP (SPI_TypeDef *SPIx) |
| Enable Rx Packet available IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_TXP (SPI_TypeDef *SPIx) |
| Enable Tx Packet space available IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_DXP (SPI_TypeDef *SPIx) |
| Enable Duplex Packet available IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_EOT (SPI_TypeDef *SPIx) |
| Enable End Of Transfer IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_TXTF (SPI_TypeDef *SPIx) |
| Enable TXTF IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_UDR (SPI_TypeDef *SPIx) |
| Enable Underrun IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_OVR (SPI_TypeDef *SPIx) |
| Enable Overrun IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_CRCERR (SPI_TypeDef *SPIx) |
| Enable CRC Error IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_FRE (SPI_TypeDef *SPIx) |
| Enable TI Frame Format Error IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_MODF (SPI_TypeDef *SPIx) |
| Enable MODF IT. | |
| __STATIC_INLINE void | LL_SPI_EnableIT_TSER (SPI_TypeDef *SPIx) |
| Enable TSER reload IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_RXP (SPI_TypeDef *SPIx) |
| Disable Rx Packet available IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_TXP (SPI_TypeDef *SPIx) |
| Disable Tx Packet space available IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_DXP (SPI_TypeDef *SPIx) |
| Disable Duplex Packet available IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_EOT (SPI_TypeDef *SPIx) |
| Disable End Of Transfer IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_TXTF (SPI_TypeDef *SPIx) |
| Disable TXTF IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_UDR (SPI_TypeDef *SPIx) |
| Disable Underrun IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_OVR (SPI_TypeDef *SPIx) |
| Disable Overrun IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_CRCERR (SPI_TypeDef *SPIx) |
| Disable CRC Error IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_FRE (SPI_TypeDef *SPIx) |
| Disable TI Frame Format Error IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_MODF (SPI_TypeDef *SPIx) |
| Disable MODF IT. | |
| __STATIC_INLINE void | LL_SPI_DisableIT_TSER (SPI_TypeDef *SPIx) |
| Disable TSER reload IT. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_RXP (SPI_TypeDef *SPIx) |
| Check if Rx Packet available IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXP (SPI_TypeDef *SPIx) |
| Check if Tx Packet space available IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_DXP (SPI_TypeDef *SPIx) |
| Check if Duplex Packet available IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_EOT (SPI_TypeDef *SPIx) |
| Check if End Of Transfer IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TXTF (SPI_TypeDef *SPIx) |
| Check if TXTF IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_UDR (SPI_TypeDef *SPIx) |
| Check if Underrun IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_OVR (SPI_TypeDef *SPIx) |
| Check if Overrun IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_CRCERR (SPI_TypeDef *SPIx) |
| Check if CRC Error IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_FRE (SPI_TypeDef *SPIx) |
| Check if TI Frame Format Error IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_MODF (SPI_TypeDef *SPIx) |
| Check if MODF IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledIT_TSER (SPI_TypeDef *SPIx) |
| Check if TSER reload IT is enabled. | |
| __STATIC_INLINE void | LL_SPI_EnableDMAReq_RX (SPI_TypeDef *SPIx) |
| Enable DMA Rx. | |
| __STATIC_INLINE void | LL_SPI_DisableDMAReq_RX (SPI_TypeDef *SPIx) |
| Disable DMA Rx. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx) |
| Check if DMA Rx is enabled. | |
| __STATIC_INLINE void | LL_SPI_EnableDMAReq_TX (SPI_TypeDef *SPIx) |
| Enable DMA Tx. | |
| __STATIC_INLINE void | LL_SPI_DisableDMAReq_TX (SPI_TypeDef *SPIx) |
| Disable DMA Tx. | |
| __STATIC_INLINE uint32_t | LL_SPI_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx) |
| Check if DMA Tx is enabled. | |
| __STATIC_INLINE uint8_t | LL_SPI_ReceiveData8 (SPI_TypeDef *SPIx) |
| Read Data Register. | |
| __STATIC_INLINE uint16_t | LL_SPI_ReceiveData16 (SPI_TypeDef *SPIx) |
| Read Data Register. | |
| __STATIC_INLINE uint32_t | LL_SPI_ReceiveData32 (SPI_TypeDef *SPIx) |
| Read Data Register. | |
| __STATIC_INLINE void | LL_SPI_TransmitData8 (SPI_TypeDef *SPIx, uint8_t TxData) |
| Write Data Register. | |
| __STATIC_INLINE void | LL_SPI_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData) |
| Write Data Register. | |
| __STATIC_INLINE void | LL_SPI_TransmitData32 (SPI_TypeDef *SPIx, uint32_t TxData) |
| Write Data Register. | |
| __STATIC_INLINE void | LL_SPI_SetCRCPolynomial (SPI_TypeDef *SPIx, uint32_t CRCPoly) |
| Set polynomial for CRC calcul. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetCRCPolynomial (SPI_TypeDef *SPIx) |
| Get polynomial for CRC calcul. | |
| __STATIC_INLINE void | LL_SPI_SetUDRPattern (SPI_TypeDef *SPIx, uint32_t Pattern) |
| Set the underrun pattern. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetUDRPattern (SPI_TypeDef *SPIx) |
| Get the underrun pattern. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetRxCRC (SPI_TypeDef *SPIx) |
| Get Rx CRC. | |
| __STATIC_INLINE uint32_t | LL_SPI_GetTxCRC (SPI_TypeDef *SPIx) |
| Get Tx CRC. | |
| ErrorStatus | LL_SPI_DeInit (SPI_TypeDef *SPIx) |
| De-initialize the SPI registers to their default reset values. | |
| ErrorStatus | LL_SPI_Init (SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) |
| Initialize the SPI registers according to the specified parameters in SPI_InitStruct. | |
| void | LL_SPI_StructInit (LL_SPI_InitTypeDef *SPI_InitStruct) |
| Set each LL_SPI_InitTypeDef field to default value. | |
| __STATIC_INLINE void | LL_I2S_SetDataFormat (SPI_TypeDef *SPIx, uint32_t DataLength) |
| Set I2S Data frame format. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetDataFormat (SPI_TypeDef *SPIx) |
| Get I2S Data frame format. | |
| __STATIC_INLINE void | LL_I2S_SetChannelLengthType (SPI_TypeDef *SPIx, uint32_t ChannelLengthType) |
| Set I2S Channel Length Type. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetChannelLengthType (SPI_TypeDef *SPIx) |
| Get I2S Channel Length Type. | |
| __STATIC_INLINE void | LL_I2S_EnableWordSelectInversion (SPI_TypeDef *SPIx) |
| Invert the default polarity of WS signal. | |
| __STATIC_INLINE void | LL_I2S_DisableWordSelectInversion (SPI_TypeDef *SPIx) |
| Use the default polarity of WS signal. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledWordSelectInversion (SPI_TypeDef *SPIx) |
| Check if polarity of WS signal is inverted. | |
| __STATIC_INLINE void | LL_I2S_SetClockPolarity (SPI_TypeDef *SPIx, uint32_t ClockPolarity) |
| Set 2S Clock Polarity. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetClockPolarity (SPI_TypeDef *SPIx) |
| Get 2S Clock Polarity. | |
| __STATIC_INLINE void | LL_I2S_SetStandard (SPI_TypeDef *SPIx, uint32_t Standard) |
| Set I2S standard. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetStandard (SPI_TypeDef *SPIx) |
| Get I2S standard. | |
| __STATIC_INLINE void | LL_I2S_SetTransferMode (SPI_TypeDef *SPIx, uint32_t Standard) |
| Set I2S config. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetTransferMode (SPI_TypeDef *SPIx) |
| Get I2S config. | |
| __STATIC_INLINE void | LL_I2S_Enable (SPI_TypeDef *SPIx) |
| Select I2S mode and Enable I2S peripheral. | |
| __STATIC_INLINE void | LL_I2S_Disable (SPI_TypeDef *SPIx) |
| Disable I2S peripheral and disable I2S mode. | |
| __STATIC_INLINE void | LL_I2S_EnableIOSwap (SPI_TypeDef *SPIx) |
| Swap the SDO and SDI pin. | |
| __STATIC_INLINE void | LL_I2S_DisableIOSwap (SPI_TypeDef *SPIx) |
| Restore default function for SDO and SDI pin. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledIOSwap (SPI_TypeDef *SPIx) |
| Check if SDO and SDI pin are swapped. | |
| __STATIC_INLINE void | LL_I2S_EnableGPIOControl (SPI_TypeDef *SPIx) |
| Enable GPIO control. | |
| __STATIC_INLINE void | LL_I2S_DisableGPIOControl (SPI_TypeDef *SPIx) |
| Disable GPIO control. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledGPIOControl (SPI_TypeDef *SPIx) |
| Check if GPIO control is active. | |
| __STATIC_INLINE void | LL_I2S_EnableIOLock (SPI_TypeDef *SPIx) |
| Lock the AF configuration of associated IOs. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledIOLock (SPI_TypeDef *SPIx) |
| Check if the the SPI_CFG2 register is locked. | |
| __STATIC_INLINE void | LL_I2S_SetTransferBitOrder (SPI_TypeDef *SPIx, uint32_t BitOrder) |
| Set Transfer Bit Order. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetTransferBitOrder (SPI_TypeDef *SPIx) |
| Get Transfer Bit Order. | |
| __STATIC_INLINE void | LL_I2S_StartTransfer (SPI_TypeDef *SPIx) |
| Start effective transfer on wire. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsActiveTransfer (SPI_TypeDef *SPIx) |
| Check if there is an unfinished transfer. | |
| __STATIC_INLINE void | LL_I2S_SetFIFOThreshold (SPI_TypeDef *SPIx, uint32_t Threshold) |
| Set threshold of FIFO that triggers a transfer event. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetFIFOThreshold (SPI_TypeDef *SPIx) |
| Get threshold of FIFO that triggers a transfer event. | |
| __STATIC_INLINE void | LL_I2S_SetPrescalerLinear (SPI_TypeDef *SPIx, uint32_t PrescalerLinear) |
| Set I2S linear prescaler. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetPrescalerLinear (SPI_TypeDef *SPIx) |
| Get I2S linear prescaler. | |
| __STATIC_INLINE void | LL_I2S_SetPrescalerParity (SPI_TypeDef *SPIx, uint32_t PrescalerParity) |
| Set I2S parity prescaler. | |
| __STATIC_INLINE uint32_t | LL_I2S_GetPrescalerParity (SPI_TypeDef *SPIx) |
| Get I2S parity prescaler. | |
| __STATIC_INLINE void | LL_I2S_EnableMasterClock (SPI_TypeDef *SPIx) |
| Enable the Master Clock Output (Pin MCK) | |
| __STATIC_INLINE void | LL_I2S_DisableMasterClock (SPI_TypeDef *SPIx) |
| Disable the Master Clock Output (Pin MCK) | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledMasterClock (SPI_TypeDef *SPIx) |
| Check if the master clock output (Pin MCK) is enabled. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_RXP (SPI_TypeDef *SPIx) |
| Check if there enough data in FIFO to read a full packet. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_TXP (SPI_TypeDef *SPIx) |
| Check if there enough space in FIFO to hold a full packet. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_UDR (SPI_TypeDef *SPIx) |
| Get Underrun error flag. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_OVR (SPI_TypeDef *SPIx) |
| Get Overrun error flag. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsActiveFlag_FRE (SPI_TypeDef *SPIx) |
| Get TI Frame format error flag. | |
| __STATIC_INLINE void | LL_I2S_ClearFlag_UDR (SPI_TypeDef *SPIx) |
| Clear Underrun error flag. | |
| __STATIC_INLINE void | LL_I2S_ClearFlag_OVR (SPI_TypeDef *SPIx) |
| Clear Overrun error flag. | |
| __STATIC_INLINE void | LL_I2S_ClearFlag_FRE (SPI_TypeDef *SPIx) |
| Clear Frame format error flag. | |
| __STATIC_INLINE void | LL_I2S_EnableIT_RXP (SPI_TypeDef *SPIx) |
| Enable Rx Packet available IT. | |
| __STATIC_INLINE void | LL_I2S_EnableIT_TXP (SPI_TypeDef *SPIx) |
| Enable Tx Packet space available IT. | |
| __STATIC_INLINE void | LL_I2S_EnableIT_UDR (SPI_TypeDef *SPIx) |
| Enable Underrun IT. | |
| __STATIC_INLINE void | LL_I2S_EnableIT_OVR (SPI_TypeDef *SPIx) |
| Enable Overrun IT. | |
| __STATIC_INLINE void | LL_I2S_EnableIT_FRE (SPI_TypeDef *SPIx) |
| Enable TI Frame Format Error IT. | |
| __STATIC_INLINE void | LL_I2S_DisableIT_RXP (SPI_TypeDef *SPIx) |
| Disable Rx Packet available IT. | |
| __STATIC_INLINE void | LL_I2S_DisableIT_TXP (SPI_TypeDef *SPIx) |
| Disable Tx Packet space available IT. | |
| __STATIC_INLINE void | LL_I2S_DisableIT_UDR (SPI_TypeDef *SPIx) |
| Disable Underrun IT. | |
| __STATIC_INLINE void | LL_I2S_DisableIT_OVR (SPI_TypeDef *SPIx) |
| Disable Overrun IT. | |
| __STATIC_INLINE void | LL_I2S_DisableIT_FRE (SPI_TypeDef *SPIx) |
| Disable TI Frame Format Error IT. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_RXP (SPI_TypeDef *SPIx) |
| Check if Rx Packet available IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_TXP (SPI_TypeDef *SPIx) |
| Check if Tx Packet space available IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_UDR (SPI_TypeDef *SPIx) |
| Check if Underrun IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_OVR (SPI_TypeDef *SPIx) |
| Check if Overrun IT is enabled. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledIT_FRE (SPI_TypeDef *SPIx) |
| Check if TI Frame Format Error IT is enabled. | |
| __STATIC_INLINE void | LL_I2S_EnableDMAReq_RX (SPI_TypeDef *SPIx) |
| Enable DMA Rx. | |
| __STATIC_INLINE void | LL_I2S_DisableDMAReq_RX (SPI_TypeDef *SPIx) |
| Disable DMA Rx. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_RX (SPI_TypeDef *SPIx) |
| Check if DMA Rx is enabled. | |
| __STATIC_INLINE void | LL_I2S_EnableDMAReq_TX (SPI_TypeDef *SPIx) |
| Enable DMA Tx. | |
| __STATIC_INLINE void | LL_I2S_DisableDMAReq_TX (SPI_TypeDef *SPIx) |
| Disable DMA Tx. | |
| __STATIC_INLINE uint32_t | LL_I2S_IsEnabledDMAReq_TX (SPI_TypeDef *SPIx) |
| Check if DMA Tx is enabled. | |
| __STATIC_INLINE uint16_t | LL_I2S_ReceiveData16 (SPI_TypeDef *SPIx) |
| Read Data Register. | |
| __STATIC_INLINE uint32_t | LL_I2S_ReceiveData32 (SPI_TypeDef *SPIx) |
| Read Data Register. | |
| __STATIC_INLINE void | LL_I2S_TransmitData16 (SPI_TypeDef *SPIx, uint16_t TxData) |
| Write Data Register. | |
| __STATIC_INLINE void | LL_I2S_TransmitData32 (SPI_TypeDef *SPIx, uint32_t TxData) |
| Write Data Register. | |
| ErrorStatus | LL_I2S_DeInit (SPI_TypeDef *SPIx) |
| De-initialize the SPI/I2S registers to their default reset values. | |
| ErrorStatus | LL_I2S_Init (SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) |
| Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. | |
| void | LL_I2S_StructInit (LL_I2S_InitTypeDef *I2S_InitStruct) |
| Set each LL_I2S_InitTypeDef field to default value. | |
| void | LL_I2S_ConfigPrescaler (SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) |
| Set linear and parity prescaler. | |
Header file of SPI LL module.
Copyright (c) 2017 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.
Definition in file stm32h7xx_ll_spi.h.
1.7.6.1