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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_ADC_H 00021 #define STM32L4xx_HAL_ADC_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 /* Include low level driver */ 00031 #include "stm32l4xx_ll_adc.h" 00032 00033 /** @addtogroup STM32L4xx_HAL_Driver 00034 * @{ 00035 */ 00036 00037 /** @addtogroup ADC 00038 * @{ 00039 */ 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 /** @defgroup ADC_Exported_Types ADC Exported Types 00043 * @{ 00044 */ 00045 00046 /** 00047 * @brief ADC group regular oversampling structure definition 00048 */ 00049 typedef struct 00050 { 00051 uint32_t Ratio; /*!< Configures the oversampling ratio. 00052 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 00053 00054 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 00055 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 00056 00057 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 00058 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 00059 00060 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 00061 The oversampling is either temporary stopped or reset upon an injected 00062 sequence interruption. 00063 If oversampling is enabled on both regular and injected groups, this parameter 00064 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 00065 (the oversampling buffer is zeroed during injection sequence). 00066 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 00067 00068 } ADC_OversamplingTypeDef; 00069 00070 /** 00071 * @brief Structure definition of ADC instance and ADC group regular. 00072 * @note Parameters of this structure are shared within 2 scopes: 00073 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 00074 * ScanConvMode, EOCSelection, LowPowerAutoWait. 00075 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 00076 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 00077 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 00078 * ADC state can be either: 00079 * - For all parameters: ADC disabled 00080 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 00081 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 00082 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00083 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 00084 * (which fulfills the ADC state condition) on the fly). 00085 */ 00086 typedef struct 00087 { 00088 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 00089 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 00090 Note: The ADC clock configuration is common to all ADC instances. 00091 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 00092 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 00093 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 00094 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 00095 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 00096 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 00097 Note: This parameter can be modified only if all ADC instances are disabled. */ 00098 00099 uint32_t Resolution; /*!< Configure the ADC resolution. 00100 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 00101 00102 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 00103 Refer to reference manual for alignments formats versus resolutions. 00104 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 00105 00106 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 00107 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 00108 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 00109 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 00110 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 00111 Scan direction is upward: from rank 1 to rank 'n'. 00112 This parameter can be a value of @ref ADC_Scan_mode */ 00113 00114 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 00115 This parameter can be a value of @ref ADC_EOCSelection. */ 00116 00117 FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 00118 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 00119 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 00120 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 00121 for low frequency applications. 00122 This parameter can be set to ENABLE or DISABLE. 00123 Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC flag (by CPU to free the IRQ pending event or by DMA). 00124 Auto wait will work but fort a very short time, discarding its intended benefit (except specific case of high load of CPU or DMA transfers which can justify usage of auto wait). 00125 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 00126 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. 00127 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 00128 00129 FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 00130 after the first ADC conversion start trigger occurred (software start or external trigger). 00131 This parameter can be set to ENABLE or DISABLE. */ 00132 00133 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 00134 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00135 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 00136 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 00137 continuous mode or external trigger that could launch a conversion). */ 00138 00139 FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 00140 (main sequence subdivided in successive parts). 00141 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00142 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 00143 This parameter can be set to ENABLE or DISABLE. */ 00144 00145 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 00146 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 00147 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 00148 00149 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 00150 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 00151 This parameter can be a value of @ref ADC_regular_external_trigger_source. 00152 Caution: external trigger source is common to all ADC instances. */ 00153 00154 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 00155 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 00156 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 00157 00158 FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 00159 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 00160 This parameter can be set to ENABLE or DISABLE. 00161 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 00162 00163 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 00164 This parameter applies to ADC group regular only. 00165 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 00166 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 00167 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 00168 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 00169 Note: Error reporting with respect to the conversion mode: 00170 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 00171 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 00172 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 00173 00174 FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 00175 This parameter can be set to ENABLE or DISABLE. 00176 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 00177 00178 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 00179 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 00180 00181 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00182 uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM. 00183 This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER. 00184 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00185 00186 #endif /* ADC_CFGR_DFSDMCFG */ 00187 } ADC_InitTypeDef; 00188 00189 /** 00190 * @brief Structure definition of ADC channel for regular group 00191 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 00192 * ADC state can be either: 00193 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 00194 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 00195 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 00196 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00197 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 00198 * on the fly). 00199 */ 00200 typedef struct 00201 { 00202 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 00203 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 00204 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 00205 00206 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 00207 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 00208 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 00209 the new channel setting (or parameter number of conversions adjusted) */ 00210 00211 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 00212 Unit: ADC clock cycles 00213 Conversion time is the addition of sampling time and processing time 00214 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 00215 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 00216 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 00217 It overwrites the last setting. 00218 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00219 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 00220 Refer to device datasheet for timings values. */ 00221 00222 uint32_t SingleDiff; /*!< Select single-ended or differential input. 00223 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 00224 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 00225 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 00226 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00227 It overwrites the last setting. 00228 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 00229 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 00230 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00231 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 00232 of another parameter update on the fly) */ 00233 00234 uint32_t OffsetNumber; /*!< Select the offset number 00235 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 00236 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 00237 00238 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 00239 Offset value must be a positive number. 00240 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 00241 0x3FF, 0xFF or 0x3F respectively. 00242 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00243 without continuous mode or external trigger that could launch a conversion). */ 00244 00245 } ADC_ChannelConfTypeDef; 00246 00247 /** 00248 * @brief Structure definition of ADC analog watchdog 00249 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 00250 * ADC state can be either: 00251 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 00252 */ 00253 typedef struct 00254 { 00255 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 00256 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 00257 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 00258 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 00259 00260 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 00261 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 00262 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 00263 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 00264 00265 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 00266 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 00267 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 00268 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 00269 00270 FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 00271 This parameter can be set to ENABLE or DISABLE */ 00272 00273 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 00274 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 00275 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 00276 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 00277 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 00278 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 00279 impacted: the comparison of analog watchdog thresholds is done on 00280 oversampling final computation (after ratio and shift application): 00281 ADC data register bitfield [15:4] (12 most significant bits). */ 00282 00283 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 00284 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 00285 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 00286 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 00287 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. 00288 Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are 00289 impacted: the comparison of analog watchdog thresholds is done on 00290 oversampling final computation (after ratio and shift application): 00291 ADC data register bitfield [15:4] (12 most significant bits). */ 00292 } ADC_AnalogWDGConfTypeDef; 00293 00294 /** 00295 * @brief ADC group injected contexts queue configuration 00296 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 00297 */ 00298 typedef struct 00299 { 00300 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 00301 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 00302 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 00303 00304 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 00305 } ADC_InjectionConfigTypeDef; 00306 00307 /** @defgroup ADC_States ADC States 00308 * @{ 00309 */ 00310 00311 /** 00312 * @brief HAL ADC state machine: ADC states definition (bitfields) 00313 * @note ADC state machine is managed by bitfields, state must be compared 00314 * with bit by bit. 00315 * For example: 00316 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " 00317 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " 00318 */ 00319 /* States of ADC global scope */ 00320 #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ 00321 #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ 00322 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to an internal process (initialization, calibration) */ 00323 #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ 00324 00325 /* States of ADC errors */ 00326 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ 00327 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ 00328 #define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ 00329 00330 /* States of ADC group regular */ 00331 #define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 00332 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 00333 #define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ 00334 #define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ 00335 #define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag raised */ 00336 00337 /* States of ADC group injected */ 00338 #define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 00339 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 00340 #define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Conversion data available on group injected */ 00341 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Injected queue overflow occurrence */ 00342 00343 /* States of ADC analog watchdogs */ 00344 #define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 00345 #define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 00346 #define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 00347 00348 /* States of ADC multi-mode */ 00349 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 00350 00351 /** 00352 * @} 00353 */ 00354 00355 /** 00356 * @brief ADC handle Structure definition 00357 */ 00358 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00359 typedef struct __ADC_HandleTypeDef 00360 #else 00361 typedef struct 00362 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00363 { 00364 ADC_TypeDef *Instance; /*!< Register base address */ 00365 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 00366 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 00367 HAL_LockTypeDef Lock; /*!< ADC locking object */ 00368 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 00369 __IO uint32_t ErrorCode; /*!< ADC Error code */ 00370 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 00371 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00372 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 00373 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 00374 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 00375 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 00376 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 00377 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 00378 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 00379 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 00380 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 00381 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 00382 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 00383 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00384 } ADC_HandleTypeDef; 00385 00386 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00387 /** 00388 * @brief HAL ADC Callback ID enumeration definition 00389 */ 00390 typedef enum 00391 { 00392 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 00393 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 00394 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 00395 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 00396 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 00397 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 00398 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 00399 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 00400 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 00401 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 00402 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 00403 } HAL_ADC_CallbackIDTypeDef; 00404 00405 /** 00406 * @brief HAL ADC Callback pointer definition 00407 */ 00408 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 00409 00410 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00411 00412 /** 00413 * @} 00414 */ 00415 00416 00417 /* Exported constants --------------------------------------------------------*/ 00418 00419 /** @defgroup ADC_Exported_Constants ADC Exported Constants 00420 * @{ 00421 */ 00422 00423 /** @defgroup ADC_Error_Code ADC Error Code 00424 * @{ 00425 */ 00426 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 00427 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, 00428 enable/disable, erroneous state, ...) */ 00429 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 00430 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 00431 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 00432 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00433 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 00434 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00435 /** 00436 * @} 00437 */ 00438 00439 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 00440 * @{ 00441 */ 00442 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 00443 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 00444 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 00445 00446 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 00447 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 00448 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 00449 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 00450 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 00451 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 00452 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 00453 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 00454 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 00455 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 00456 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 00457 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 00458 /** 00459 * @} 00460 */ 00461 00462 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 00463 * @{ 00464 */ 00465 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 00466 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 00467 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 00468 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 00469 /** 00470 * @} 00471 */ 00472 00473 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 00474 * @{ 00475 */ 00476 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 00477 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ 00478 /** 00479 * @} 00480 */ 00481 00482 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 00483 * @{ 00484 */ 00485 #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Scan mode disabled */ 00486 #define ADC_SCAN_ENABLE (0x00000001UL) /*!< Scan mode enabled */ 00487 /** 00488 * @} 00489 */ 00490 00491 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 00492 * @{ 00493 */ 00494 /* ADC group regular trigger sources for all ADC instances */ 00495 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 00496 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00497 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 00498 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00499 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00500 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00501 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00502 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00503 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00504 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00505 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00506 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00507 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 00508 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00509 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 00510 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 00511 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 00512 /** 00513 * @} 00514 */ 00515 00516 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 00517 * @{ 00518 */ 00519 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware trigger detection disabled */ 00520 #define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion trigger polarity set to rising edge */ 00521 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion trigger polarity set to falling edge */ 00522 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ 00523 /** 00524 * @} 00525 */ 00526 00527 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 00528 * @{ 00529 */ 00530 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 00531 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 00532 /** 00533 * @} 00534 */ 00535 00536 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 00537 * @{ 00538 */ 00539 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 00540 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 00541 /** 00542 * @} 00543 */ 00544 00545 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 00546 * @{ 00547 */ 00548 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 00549 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 00550 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 00551 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 00552 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 00553 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 00554 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 00555 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 00556 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 00557 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 00558 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 00559 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 00560 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 00561 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 00562 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 00563 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 00564 /** 00565 * @} 00566 */ 00567 00568 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 00569 * @{ 00570 */ 00571 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 00572 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 00573 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 00574 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 00575 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 00576 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 00577 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 00578 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 00579 #if defined(ADC_SMPR1_SMPPLUS) 00580 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 00581 #endif /* ADC_SMPR1_SMPPLUS */ 00582 /** 00583 * @} 00584 */ 00585 00586 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 00587 * @{ 00588 */ 00589 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 00590 /* all ADC instances (refer to Reference Manual). */ 00591 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 00592 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 00593 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 00594 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 00595 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 00596 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 00597 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 00598 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 00599 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 00600 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 00601 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 00602 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 00603 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 00604 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 00605 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 00606 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 00607 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 00608 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 00609 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 00610 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ 00611 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ 00612 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ 00613 #if defined(ADC1) && !defined(ADC2) 00614 #define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 00615 #define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 00616 #elif defined(ADC2) 00617 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 00618 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 00619 #if defined(ADC3) 00620 #define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ 00621 #define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ 00622 #endif /* ADC3 */ 00623 #endif /* ADC1 && !ADC2 */ 00624 /** 00625 * @} 00626 */ 00627 00628 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 00629 * @{ 00630 */ 00631 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 00632 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 00633 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 00634 /** 00635 * @} 00636 */ 00637 00638 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 00639 * @{ 00640 */ 00641 #define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ 00642 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 00643 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 00644 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 00645 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 00646 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 00647 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 00648 /** 00649 * @} 00650 */ 00651 00652 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 00653 * @{ 00654 */ 00655 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00656 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00657 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00658 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00659 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00660 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00661 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00662 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00663 /** 00664 * @} 00665 */ 00666 00667 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 00668 * @{ 00669 */ 00670 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 00671 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 00672 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 00673 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 00674 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 00675 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 00676 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 00677 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 00678 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 00679 /** 00680 * @} 00681 */ 00682 00683 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 00684 * @{ 00685 */ 00686 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 00687 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 00688 /** 00689 * @} 00690 */ 00691 00692 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 00693 * @{ 00694 */ 00695 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 00696 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 00697 /** 00698 * @} 00699 */ 00700 00701 /** @defgroup ADC_Event_type ADC Event type 00702 * @{ 00703 */ 00704 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 00705 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 00706 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 00707 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 00708 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 00709 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 00710 /** 00711 * @} 00712 */ 00713 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 00714 00715 /** @defgroup ADC_interrupts_definition ADC interrupts definition 00716 * @{ 00717 */ 00718 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 00719 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 00720 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 00721 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 00722 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 00723 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 00724 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 00725 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 00726 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 00727 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 00728 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 00729 00730 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 00731 00732 /** 00733 * @} 00734 */ 00735 00736 /** @defgroup ADC_flags_definition ADC flags definition 00737 * @{ 00738 */ 00739 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 00740 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 00741 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 00742 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 00743 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 00744 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 00745 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 00746 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 00747 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 00748 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 00749 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 00750 00751 #define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ 00752 00753 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ 00754 ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ 00755 ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ 00756 00757 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ 00758 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ 00759 ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ 00760 ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ 00761 00762 /** 00763 * @} 00764 */ 00765 00766 /** 00767 * @} 00768 */ 00769 00770 /* Private macro -------------------------------------------------------------*/ 00771 00772 /** @defgroup ADC_Private_Macros ADC Private Macros 00773 * @{ 00774 */ 00775 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 00776 /* code of final user. */ 00777 00778 /** 00779 * @brief Return resolution bits in CFGR register RES[1:0] field. 00780 * @param __HANDLE__ ADC handle 00781 * @retval Value of bitfield RES in CFGR register. 00782 */ 00783 #define ADC_GET_RESOLUTION(__HANDLE__) \ 00784 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 00785 00786 /** 00787 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 00788 * @param __HANDLE__ ADC handle 00789 * @retval None 00790 */ 00791 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 00792 00793 /** 00794 * @brief Verification of ADC state: enabled or disabled. 00795 * @param __HANDLE__ ADC handle 00796 * @retval SET (ADC enabled) or RESET (ADC disabled) 00797 */ 00798 #define ADC_IS_ENABLE(__HANDLE__) \ 00799 ((((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 00800 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 00801 ) ? SET : RESET) 00802 00803 /** 00804 * @brief Check if conversion is on going on regular group. 00805 * @param __HANDLE__ ADC handle 00806 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 00807 */ 00808 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 00809 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 00810 00811 /** 00812 * @brief Simultaneously clear and set specific bits of the handle State. 00813 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 00814 * the first parameter is the ADC handle State, the second parameter is the 00815 * bit field to clear, the third and last parameter is the bit field to set. 00816 * @retval None 00817 */ 00818 #define ADC_STATE_CLR_SET MODIFY_REG 00819 00820 /** 00821 * @brief Verify that a given value is aligned with the ADC resolution range. 00822 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 00823 * @param __ADC_VALUE__ value checked against the resolution. 00824 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 00825 */ 00826 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 00827 ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) 00828 00829 /** 00830 * @brief Verify the length of the scheduled regular conversions group. 00831 * @param __LENGTH__ number of programmed conversions. 00832 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 00833 */ 00834 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) 00835 00836 00837 /** 00838 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 00839 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 00840 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) 00841 */ 00842 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) 00843 00844 00845 /** 00846 * @brief Verify the ADC clock setting. 00847 * @param __ADC_CLOCK__ programmed ADC clock. 00848 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 00849 */ 00850 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 00851 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 00852 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 00853 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 00854 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 00855 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 00856 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 00857 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 00858 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 00859 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 00860 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 00861 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 00862 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 00863 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 00864 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 00865 00866 /** 00867 * @brief Verify the ADC resolution setting. 00868 * @param __RESOLUTION__ programmed ADC resolution. 00869 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 00870 */ 00871 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 00872 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 00873 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 00874 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 00875 00876 /** 00877 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 00878 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 00879 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 00880 */ 00881 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 00882 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 00883 00884 /** 00885 * @brief Verify the ADC converted data alignment. 00886 * @param __ALIGN__ programmed ADC converted data alignment. 00887 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 00888 */ 00889 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 00890 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 00891 00892 /** 00893 * @brief Verify the ADC scan mode. 00894 * @param __SCAN_MODE__ programmed ADC scan mode. 00895 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 00896 */ 00897 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 00898 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 00899 00900 /** 00901 * @brief Verify the ADC edge trigger setting for regular group. 00902 * @param __EDGE__ programmed ADC edge trigger setting. 00903 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 00904 */ 00905 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 00906 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 00907 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 00908 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 00909 00910 /** 00911 * @brief Verify the ADC regular conversions external trigger. 00912 * @param __HANDLE__ ADC handle 00913 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 00914 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 00915 */ 00916 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 00917 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 00918 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 00919 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 00920 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 00921 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 00922 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 00923 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 00924 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 00925 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 00926 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 00927 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 00928 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 00929 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 00930 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 00931 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 00932 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 00933 00934 /** 00935 * @brief Verify the ADC regular conversions check for converted data availability. 00936 * @param __EOC_SELECTION__ converted data availability check. 00937 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 00938 */ 00939 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 00940 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 00941 00942 /** 00943 * @brief Verify the ADC regular conversions overrun handling. 00944 * @param __OVR__ ADC regular conversions overrun handling. 00945 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 00946 */ 00947 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 00948 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 00949 00950 /** 00951 * @brief Verify the ADC conversions sampling time. 00952 * @param __TIME__ ADC conversions sampling time. 00953 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 00954 */ 00955 #if defined(ADC_SMPR1_SMPPLUS) 00956 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 00957 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 00958 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 00959 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 00960 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 00961 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 00962 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 00963 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 00964 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 00965 #else 00966 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 00967 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 00968 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 00969 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 00970 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 00971 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 00972 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 00973 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 00974 #endif /* ADC_SMPR1_SMPPLUS */ 00975 00976 /** 00977 * @brief Verify the ADC regular channel setting. 00978 * @param __CHANNEL__ programmed ADC regular channel. 00979 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00980 */ 00981 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 00982 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 00983 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 00984 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 00985 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 00986 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 00987 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 00988 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 00989 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 00990 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 00991 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 00992 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 00993 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 00994 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 00995 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 00996 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 00997 00998 /** 00999 * @} 01000 */ 01001 01002 01003 /* Private constants ---------------------------------------------------------*/ 01004 01005 /** @defgroup ADC_Private_Constants ADC Private Constants 01006 * @{ 01007 */ 01008 01009 /* Fixed timeout values for ADC conversion (including sampling time) */ 01010 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 01011 /* Maximum conversion time is 12.5 + Maximum sampling time */ 01012 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 01013 /* Minimum ADC Clock frequency is 0.14 MHz */ 01014 /* Maximum conversion time is */ 01015 /* 653 / 0.14 MHz = 4.66 ms */ 01016 #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ 01017 01018 /* Delay for temperature sensor stabilization time. */ 01019 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 01020 /* Unit: us */ 01021 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 01022 01023 /** 01024 * @} 01025 */ 01026 01027 /* Exported macro ------------------------------------------------------------*/ 01028 01029 /** @defgroup ADC_Exported_Macros ADC Exported Macros 01030 * @{ 01031 */ 01032 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 01033 /* final user. */ 01034 01035 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 01036 * @{ 01037 */ 01038 01039 /** @brief Reset ADC handle state. 01040 * @param __HANDLE__ ADC handle 01041 * @retval None 01042 */ 01043 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 01044 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 01045 do{ \ 01046 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 01047 (__HANDLE__)->MspInitCallback = NULL; \ 01048 (__HANDLE__)->MspDeInitCallback = NULL; \ 01049 } while(0) 01050 #else 01051 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 01052 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 01053 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 01054 01055 /** 01056 * @brief Enable ADC interrupt. 01057 * @param __HANDLE__ ADC handle 01058 * @param __INTERRUPT__ ADC Interrupt 01059 * This parameter can be one of the following values: 01060 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01061 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01062 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01063 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01064 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01065 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01066 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01067 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01068 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01069 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01070 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01071 * @retval None 01072 */ 01073 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 01074 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 01075 01076 /** 01077 * @brief Disable ADC interrupt. 01078 * @param __HANDLE__ ADC handle 01079 * @param __INTERRUPT__ ADC Interrupt 01080 * This parameter can be one of the following values: 01081 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01082 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01083 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01084 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01085 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01086 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01087 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01088 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01089 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01090 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01091 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01092 * @retval None 01093 */ 01094 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 01095 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 01096 01097 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 01098 * @param __HANDLE__ ADC handle 01099 * @param __INTERRUPT__ ADC interrupt source to check 01100 * This parameter can be one of the following values: 01101 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01102 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01103 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01104 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01105 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01106 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01107 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01108 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01109 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01110 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01111 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01112 * @retval State of interruption (SET or RESET) 01113 */ 01114 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 01115 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 01116 01117 /** 01118 * @brief Check whether the specified ADC flag is set or not. 01119 * @param __HANDLE__ ADC handle 01120 * @param __FLAG__ ADC flag 01121 * This parameter can be one of the following values: 01122 * @arg @ref ADC_FLAG_RDY ADC Ready flag 01123 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 01124 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 01125 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 01126 * @arg @ref ADC_FLAG_OVR ADC overrun flag 01127 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 01128 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 01129 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 01130 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 01131 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 01132 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 01133 * @retval State of flag (TRUE or FALSE). 01134 */ 01135 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 01136 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 01137 01138 /** 01139 * @brief Clear the specified ADC flag. 01140 * @param __HANDLE__ ADC handle 01141 * @param __FLAG__ ADC flag 01142 * This parameter can be one of the following values: 01143 * @arg @ref ADC_FLAG_RDY ADC Ready flag 01144 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 01145 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 01146 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 01147 * @arg @ref ADC_FLAG_OVR ADC overrun flag 01148 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 01149 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 01150 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 01151 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 01152 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 01153 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 01154 * @retval None 01155 */ 01156 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 01157 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 01158 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 01159 01160 /** 01161 * @} 01162 */ 01163 01164 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 01165 * @{ 01166 */ 01167 01168 /** 01169 * @brief Helper macro to get ADC channel number in decimal format 01170 * from literals ADC_CHANNEL_x. 01171 * @note Example: 01172 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 01173 * will return decimal number "4". 01174 * @note The input can be a value from functions where a channel 01175 * number is returned, either defined with number 01176 * or with bitfield (only one bit must be set). 01177 * @param __CHANNEL__ This parameter can be one of the following values: 01178 * @arg @ref ADC_CHANNEL_0 01179 * @arg @ref ADC_CHANNEL_1 (7) 01180 * @arg @ref ADC_CHANNEL_2 (7) 01181 * @arg @ref ADC_CHANNEL_3 (7) 01182 * @arg @ref ADC_CHANNEL_4 (7) 01183 * @arg @ref ADC_CHANNEL_5 (7) 01184 * @arg @ref ADC_CHANNEL_6 01185 * @arg @ref ADC_CHANNEL_7 01186 * @arg @ref ADC_CHANNEL_8 01187 * @arg @ref ADC_CHANNEL_9 01188 * @arg @ref ADC_CHANNEL_10 01189 * @arg @ref ADC_CHANNEL_11 01190 * @arg @ref ADC_CHANNEL_12 01191 * @arg @ref ADC_CHANNEL_13 01192 * @arg @ref ADC_CHANNEL_14 01193 * @arg @ref ADC_CHANNEL_15 01194 * @arg @ref ADC_CHANNEL_16 01195 * @arg @ref ADC_CHANNEL_17 01196 * @arg @ref ADC_CHANNEL_18 01197 * @arg @ref ADC_CHANNEL_VREFINT (1) 01198 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01199 * @arg @ref ADC_CHANNEL_VBAT (4) 01200 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01201 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01202 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01203 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01204 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01205 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01206 * 01207 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01208 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01209 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01210 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01211 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01212 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01213 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01214 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01215 * @retval Value between Min_Data=0 and Max_Data=18 01216 */ 01217 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 01218 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 01219 01220 /** 01221 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 01222 * from number in decimal format. 01223 * @note Example: 01224 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 01225 * will return a data equivalent to "ADC_CHANNEL_4". 01226 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 01227 * @retval Returned value can be one of the following values: 01228 * @arg @ref ADC_CHANNEL_0 01229 * @arg @ref ADC_CHANNEL_1 (7) 01230 * @arg @ref ADC_CHANNEL_2 (7) 01231 * @arg @ref ADC_CHANNEL_3 (7) 01232 * @arg @ref ADC_CHANNEL_4 (7) 01233 * @arg @ref ADC_CHANNEL_5 (7) 01234 * @arg @ref ADC_CHANNEL_6 01235 * @arg @ref ADC_CHANNEL_7 01236 * @arg @ref ADC_CHANNEL_8 01237 * @arg @ref ADC_CHANNEL_9 01238 * @arg @ref ADC_CHANNEL_10 01239 * @arg @ref ADC_CHANNEL_11 01240 * @arg @ref ADC_CHANNEL_12 01241 * @arg @ref ADC_CHANNEL_13 01242 * @arg @ref ADC_CHANNEL_14 01243 * @arg @ref ADC_CHANNEL_15 01244 * @arg @ref ADC_CHANNEL_16 01245 * @arg @ref ADC_CHANNEL_17 01246 * @arg @ref ADC_CHANNEL_18 01247 * @arg @ref ADC_CHANNEL_VREFINT (1) 01248 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01249 * @arg @ref ADC_CHANNEL_VBAT (4) 01250 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01251 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01252 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01253 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01254 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01255 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01256 * 01257 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01258 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01259 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01260 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01261 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01262 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01263 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01264 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 01265 * (1, 2, 3, 4) For ADC channel read back from ADC register, 01266 * comparison with internal channel parameter to be done 01267 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01268 */ 01269 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 01270 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 01271 01272 /** 01273 * @brief Helper macro to determine whether the selected channel 01274 * corresponds to literal definitions of driver. 01275 * @note The different literal definitions of ADC channels are: 01276 * - ADC internal channel: 01277 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 01278 * - ADC external channel (channel connected to a GPIO pin): 01279 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 01280 * @note The channel parameter must be a value defined from literal 01281 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01282 * ADC_CHANNEL_TEMPSENSOR, ...), 01283 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 01284 * must not be a value from functions where a channel number is 01285 * returned from ADC registers, 01286 * because internal and external channels share the same channel 01287 * number in ADC registers. The differentiation is made only with 01288 * parameters definitions of driver. 01289 * @param __CHANNEL__ This parameter can be one of the following values: 01290 * @arg @ref ADC_CHANNEL_0 01291 * @arg @ref ADC_CHANNEL_1 (7) 01292 * @arg @ref ADC_CHANNEL_2 (7) 01293 * @arg @ref ADC_CHANNEL_3 (7) 01294 * @arg @ref ADC_CHANNEL_4 (7) 01295 * @arg @ref ADC_CHANNEL_5 (7) 01296 * @arg @ref ADC_CHANNEL_6 01297 * @arg @ref ADC_CHANNEL_7 01298 * @arg @ref ADC_CHANNEL_8 01299 * @arg @ref ADC_CHANNEL_9 01300 * @arg @ref ADC_CHANNEL_10 01301 * @arg @ref ADC_CHANNEL_11 01302 * @arg @ref ADC_CHANNEL_12 01303 * @arg @ref ADC_CHANNEL_13 01304 * @arg @ref ADC_CHANNEL_14 01305 * @arg @ref ADC_CHANNEL_15 01306 * @arg @ref ADC_CHANNEL_16 01307 * @arg @ref ADC_CHANNEL_17 01308 * @arg @ref ADC_CHANNEL_18 01309 * @arg @ref ADC_CHANNEL_VREFINT (1) 01310 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01311 * @arg @ref ADC_CHANNEL_VBAT (4) 01312 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01313 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01314 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01315 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01316 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01317 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01318 * 01319 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01320 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01321 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01322 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01323 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01324 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01325 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01326 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01327 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 01328 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 01329 */ 01330 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 01331 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 01332 01333 /** 01334 * @brief Helper macro to convert a channel defined from parameter 01335 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01336 * ADC_CHANNEL_TEMPSENSOR, ...), 01337 * to its equivalent parameter definition of a ADC external channel 01338 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 01339 * @note The channel parameter can be, additionally to a value 01340 * defined from parameter definition of a ADC internal channel 01341 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 01342 * a value defined from parameter definition of 01343 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 01344 * or a value from functions where a channel number is returned 01345 * from ADC registers. 01346 * @param __CHANNEL__ This parameter can be one of the following values: 01347 * @arg @ref ADC_CHANNEL_0 01348 * @arg @ref ADC_CHANNEL_1 (7) 01349 * @arg @ref ADC_CHANNEL_2 (7) 01350 * @arg @ref ADC_CHANNEL_3 (7) 01351 * @arg @ref ADC_CHANNEL_4 (7) 01352 * @arg @ref ADC_CHANNEL_5 (7) 01353 * @arg @ref ADC_CHANNEL_6 01354 * @arg @ref ADC_CHANNEL_7 01355 * @arg @ref ADC_CHANNEL_8 01356 * @arg @ref ADC_CHANNEL_9 01357 * @arg @ref ADC_CHANNEL_10 01358 * @arg @ref ADC_CHANNEL_11 01359 * @arg @ref ADC_CHANNEL_12 01360 * @arg @ref ADC_CHANNEL_13 01361 * @arg @ref ADC_CHANNEL_14 01362 * @arg @ref ADC_CHANNEL_15 01363 * @arg @ref ADC_CHANNEL_16 01364 * @arg @ref ADC_CHANNEL_17 01365 * @arg @ref ADC_CHANNEL_18 01366 * @arg @ref ADC_CHANNEL_VREFINT (1) 01367 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01368 * @arg @ref ADC_CHANNEL_VBAT (4) 01369 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01370 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01371 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01372 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01373 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01374 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01375 * 01376 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01377 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01378 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01379 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01380 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01381 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01382 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01383 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01384 * @retval Returned value can be one of the following values: 01385 * @arg @ref ADC_CHANNEL_0 01386 * @arg @ref ADC_CHANNEL_1 01387 * @arg @ref ADC_CHANNEL_2 01388 * @arg @ref ADC_CHANNEL_3 01389 * @arg @ref ADC_CHANNEL_4 01390 * @arg @ref ADC_CHANNEL_5 01391 * @arg @ref ADC_CHANNEL_6 01392 * @arg @ref ADC_CHANNEL_7 01393 * @arg @ref ADC_CHANNEL_8 01394 * @arg @ref ADC_CHANNEL_9 01395 * @arg @ref ADC_CHANNEL_10 01396 * @arg @ref ADC_CHANNEL_11 01397 * @arg @ref ADC_CHANNEL_12 01398 * @arg @ref ADC_CHANNEL_13 01399 * @arg @ref ADC_CHANNEL_14 01400 * @arg @ref ADC_CHANNEL_15 01401 * @arg @ref ADC_CHANNEL_16 01402 * @arg @ref ADC_CHANNEL_17 01403 * @arg @ref ADC_CHANNEL_18 01404 */ 01405 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 01406 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 01407 01408 /** 01409 * @brief Helper macro to determine whether the internal channel 01410 * selected is available on the ADC instance selected. 01411 * @note The channel parameter must be a value defined from parameter 01412 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01413 * ADC_CHANNEL_TEMPSENSOR, ...), 01414 * must not be a value defined from parameter definition of 01415 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 01416 * or a value from functions where a channel number is 01417 * returned from ADC registers, 01418 * because internal and external channels share the same channel 01419 * number in ADC registers. The differentiation is made only with 01420 * parameters definitions of driver. 01421 * @param __ADC_INSTANCE__ ADC instance 01422 * @param __CHANNEL__ This parameter can be one of the following values: 01423 * @arg @ref ADC_CHANNEL_VREFINT (1) 01424 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01425 * @arg @ref ADC_CHANNEL_VBAT (4) 01426 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01427 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01428 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01429 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01430 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01431 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01432 * 01433 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01434 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01435 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01436 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01437 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01438 * (6) On STM32L4, parameter available on devices with several ADC instances. 01439 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 01440 * Value "1" if the internal channel selected is available on the ADC instance selected. 01441 */ 01442 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01443 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 01444 01445 #if defined(ADC_MULTIMODE_SUPPORT) 01446 /** 01447 * @brief Helper macro to get the ADC multimode conversion data of ADC master 01448 * or ADC slave from raw value with both ADC conversion data concatenated. 01449 * @note This macro is intended to be used when multimode transfer by DMA 01450 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 01451 * In this case the transferred data need to processed with this macro 01452 * to separate the conversion data of ADC master and ADC slave. 01453 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 01454 * @arg @ref LL_ADC_MULTI_MASTER 01455 * @arg @ref LL_ADC_MULTI_SLAVE 01456 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 01457 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01458 */ 01459 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 01460 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 01461 #endif /* ADC_MULTIMODE_SUPPORT */ 01462 01463 /** 01464 * @brief Helper macro to select the ADC common instance 01465 * to which is belonging the selected ADC instance. 01466 * @note ADC common register instance can be used for: 01467 * - Set parameters common to several ADC instances 01468 * - Multimode (for devices with several ADC instances) 01469 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01470 * @param __ADCx__ ADC instance 01471 * @retval ADC common register instance 01472 */ 01473 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 01474 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 01475 01476 /** 01477 * @brief Helper macro to check if all ADC instances sharing the same 01478 * ADC common instance are disabled. 01479 * @note This check is required by functions with setting conditioned to 01480 * ADC state: 01481 * All ADC instances of the ADC common group must be disabled. 01482 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01483 * @note On devices with only 1 ADC common instance, parameter of this macro 01484 * is useless and can be ignored (parameter kept for compatibility 01485 * with devices featuring several ADC common instances). 01486 * @param __ADCXY_COMMON__ ADC common instance 01487 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01488 * @retval Value "0" if all ADC instances sharing the same ADC common instance 01489 * are disabled. 01490 * Value "1" if at least one ADC instance sharing the same ADC common instance 01491 * is enabled. 01492 */ 01493 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01494 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 01495 01496 /** 01497 * @brief Helper macro to define the ADC conversion data full-scale digital 01498 * value corresponding to the selected ADC resolution. 01499 * @note ADC conversion data full-scale corresponds to voltage range 01500 * determined by analog voltage references Vref+ and Vref- 01501 * (refer to reference manual). 01502 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01503 * @arg @ref ADC_RESOLUTION_12B 01504 * @arg @ref ADC_RESOLUTION_10B 01505 * @arg @ref ADC_RESOLUTION_8B 01506 * @arg @ref ADC_RESOLUTION_6B 01507 * @retval ADC conversion data full-scale digital value 01508 */ 01509 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01510 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 01511 01512 /** 01513 * @brief Helper macro to convert the ADC conversion data from 01514 * a resolution to another resolution. 01515 * @param __DATA__ ADC conversion data to be converted 01516 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 01517 * This parameter can be one of the following values: 01518 * @arg @ref ADC_RESOLUTION_12B 01519 * @arg @ref ADC_RESOLUTION_10B 01520 * @arg @ref ADC_RESOLUTION_8B 01521 * @arg @ref ADC_RESOLUTION_6B 01522 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 01523 * This parameter can be one of the following values: 01524 * @arg @ref ADC_RESOLUTION_12B 01525 * @arg @ref ADC_RESOLUTION_10B 01526 * @arg @ref ADC_RESOLUTION_8B 01527 * @arg @ref ADC_RESOLUTION_6B 01528 * @retval ADC conversion data to the requested resolution 01529 */ 01530 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 01531 __ADC_RESOLUTION_CURRENT__,\ 01532 __ADC_RESOLUTION_TARGET__) \ 01533 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 01534 (__ADC_RESOLUTION_CURRENT__),\ 01535 (__ADC_RESOLUTION_TARGET__)) 01536 01537 /** 01538 * @brief Helper macro to calculate the voltage (unit: mVolt) 01539 * corresponding to a ADC conversion data (unit: digital value). 01540 * @note Analog reference voltage (Vref+) must be either known from 01541 * user board environment or can be calculated using ADC measurement 01542 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01543 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 01544 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 01545 * (unit: digital value). 01546 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01547 * @arg @ref ADC_RESOLUTION_12B 01548 * @arg @ref ADC_RESOLUTION_10B 01549 * @arg @ref ADC_RESOLUTION_8B 01550 * @arg @ref ADC_RESOLUTION_6B 01551 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01552 */ 01553 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 01554 __ADC_DATA__,\ 01555 __ADC_RESOLUTION__) \ 01556 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 01557 (__ADC_DATA__),\ 01558 (__ADC_RESOLUTION__)) 01559 01560 /** 01561 * @brief Helper macro to calculate analog reference voltage (Vref+) 01562 * (unit: mVolt) from ADC conversion data of internal voltage 01563 * reference VrefInt. 01564 * @note Computation is using VrefInt calibration value 01565 * stored in system memory for each device during production. 01566 * @note This voltage depends on user board environment: voltage level 01567 * connected to pin Vref+. 01568 * On devices with small package, the pin Vref+ is not present 01569 * and internally bonded to pin Vdda. 01570 * @note On this STM32 series, calibration data of internal voltage reference 01571 * VrefInt corresponds to a resolution of 12 bits, 01572 * this is the recommended ADC resolution to convert voltage of 01573 * internal voltage reference VrefInt. 01574 * Otherwise, this macro performs the processing to scale 01575 * ADC conversion data to 12 bits. 01576 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 01577 * of internal voltage reference VrefInt (unit: digital value). 01578 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01579 * @arg @ref ADC_RESOLUTION_12B 01580 * @arg @ref ADC_RESOLUTION_10B 01581 * @arg @ref ADC_RESOLUTION_8B 01582 * @arg @ref ADC_RESOLUTION_6B 01583 * @retval Analog reference voltage (unit: mV) 01584 */ 01585 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 01586 __ADC_RESOLUTION__) \ 01587 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 01588 (__ADC_RESOLUTION__)) 01589 01590 /** 01591 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01592 * from ADC conversion data of internal temperature sensor. 01593 * @note Computation is using temperature sensor calibration values 01594 * stored in system memory for each device during production. 01595 * @note Calculation formula: 01596 * Temperature = ((TS_ADC_DATA - TS_CAL1) 01597 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 01598 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 01599 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01600 * Avg_Slope = (TS_CAL2 - TS_CAL1) 01601 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 01602 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 01603 * TEMP_DEGC_CAL1 (calibrated in factory) 01604 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 01605 * TEMP_DEGC_CAL2 (calibrated in factory) 01606 * Caution: Calculation relevancy under reserve that calibration 01607 * parameters are correct (address and data). 01608 * To calculate temperature using temperature sensor 01609 * datasheet typical values (generic values less, therefore 01610 * less accurate than calibrated values), 01611 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 01612 * @note As calculation input, the analog reference voltage (Vref+) must be 01613 * defined as it impacts the ADC LSB equivalent voltage. 01614 * @note Analog reference voltage (Vref+) must be either known from 01615 * user board environment or can be calculated using ADC measurement 01616 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01617 * @note On this STM32 series, calibration data of temperature sensor 01618 * corresponds to a resolution of 12 bits, 01619 * this is the recommended ADC resolution to convert voltage of 01620 * temperature sensor. 01621 * Otherwise, this macro performs the processing to scale 01622 * ADC conversion data to 12 bits. 01623 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 01624 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 01625 * temperature sensor (unit: digital value). 01626 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 01627 * sensor voltage has been measured. 01628 * This parameter can be one of the following values: 01629 * @arg @ref ADC_RESOLUTION_12B 01630 * @arg @ref ADC_RESOLUTION_10B 01631 * @arg @ref ADC_RESOLUTION_8B 01632 * @arg @ref ADC_RESOLUTION_6B 01633 * @retval Temperature (unit: degree Celsius) 01634 */ 01635 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 01636 __TEMPSENSOR_ADC_DATA__,\ 01637 __ADC_RESOLUTION__) \ 01638 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 01639 (__TEMPSENSOR_ADC_DATA__),\ 01640 (__ADC_RESOLUTION__)) 01641 01642 /** 01643 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01644 * from ADC conversion data of internal temperature sensor. 01645 * @note Computation is using temperature sensor typical values 01646 * (refer to device datasheet). 01647 * @note Calculation formula: 01648 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 01649 * / Avg_Slope + CALx_TEMP 01650 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01651 * (unit: digital value) 01652 * Avg_Slope = temperature sensor slope 01653 * (unit: uV/Degree Celsius) 01654 * TS_TYP_CALx_VOLT = temperature sensor digital value at 01655 * temperature CALx_TEMP (unit: mV) 01656 * Caution: Calculation relevancy under reserve the temperature sensor 01657 * of the current device has characteristics in line with 01658 * datasheet typical values. 01659 * If temperature sensor calibration values are available on 01660 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 01661 * temperature calculation will be more accurate using 01662 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 01663 * @note As calculation input, the analog reference voltage (Vref+) must be 01664 * defined as it impacts the ADC LSB equivalent voltage. 01665 * @note Analog reference voltage (Vref+) must be either known from 01666 * user board environment or can be calculated using ADC measurement 01667 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01668 * @note ADC measurement data must correspond to a resolution of 12bits 01669 * (full scale digital value 4095). If not the case, the data must be 01670 * preliminarily rescaled to an equivalent resolution of 12 bits. 01671 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 01672 * On STM32L4, refer to device datasheet parameter "Avg_Slope". 01673 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 01674 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 01675 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 01676 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 01677 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 01678 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 01679 * This parameter can be one of the following values: 01680 * @arg @ref ADC_RESOLUTION_12B 01681 * @arg @ref ADC_RESOLUTION_10B 01682 * @arg @ref ADC_RESOLUTION_8B 01683 * @arg @ref ADC_RESOLUTION_6B 01684 * @retval Temperature (unit: degree Celsius) 01685 */ 01686 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 01687 __TEMPSENSOR_TYP_CALX_V__,\ 01688 __TEMPSENSOR_CALX_TEMP__,\ 01689 __VREFANALOG_VOLTAGE__,\ 01690 __TEMPSENSOR_ADC_DATA__,\ 01691 __ADC_RESOLUTION__) \ 01692 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 01693 (__TEMPSENSOR_TYP_CALX_V__),\ 01694 (__TEMPSENSOR_CALX_TEMP__),\ 01695 (__VREFANALOG_VOLTAGE__),\ 01696 (__TEMPSENSOR_ADC_DATA__),\ 01697 (__ADC_RESOLUTION__)) 01698 01699 /** 01700 * @} 01701 */ 01702 01703 /** 01704 * @} 01705 */ 01706 01707 /* Include ADC HAL Extended module */ 01708 #include "stm32l4xx_hal_adc_ex.h" 01709 01710 /* Exported functions --------------------------------------------------------*/ 01711 /** @addtogroup ADC_Exported_Functions 01712 * @{ 01713 */ 01714 01715 /** @addtogroup ADC_Exported_Functions_Group1 01716 * @brief Initialization and Configuration functions 01717 * @{ 01718 */ 01719 /* Initialization and de-initialization functions ****************************/ 01720 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); 01721 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 01722 void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); 01723 void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); 01724 01725 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 01726 /* Callbacks Register/UnRegister functions ***********************************/ 01727 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, 01728 pADC_CallbackTypeDef pCallback); 01729 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 01730 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 01731 /** 01732 * @} 01733 */ 01734 01735 /** @addtogroup ADC_Exported_Functions_Group2 01736 * @brief IO operation functions 01737 * @{ 01738 */ 01739 /* IO operation functions *****************************************************/ 01740 01741 /* Blocking mode: Polling */ 01742 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); 01743 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); 01744 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 01745 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); 01746 01747 /* Non-blocking mode: Interruption */ 01748 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); 01749 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); 01750 01751 /* Non-blocking mode: DMA */ 01752 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 01753 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); 01754 01755 /* ADC retrieve conversion value intended to be used with polling or interruption */ 01756 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); 01757 01758 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 01759 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); 01760 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); 01761 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); 01762 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); 01763 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 01764 /** 01765 * @} 01766 */ 01767 01768 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 01769 * @brief Peripheral Control functions 01770 * @{ 01771 */ 01772 /* Peripheral Control functions ***********************************************/ 01773 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig); 01774 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); 01775 01776 /** 01777 * @} 01778 */ 01779 01780 /* Peripheral State functions *************************************************/ 01781 /** @addtogroup ADC_Exported_Functions_Group4 01782 * @{ 01783 */ 01784 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); 01785 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 01786 01787 /** 01788 * @} 01789 */ 01790 01791 /** 01792 * @} 01793 */ 01794 01795 /* Private functions -----------------------------------------------------------*/ 01796 /** @addtogroup ADC_Private_Functions ADC Private Functions 01797 * @{ 01798 */ 01799 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup); 01800 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); 01801 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); 01802 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 01803 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 01804 void ADC_DMAError(DMA_HandleTypeDef *hdma); 01805 01806 /** 01807 * @} 01808 */ 01809 01810 /** 01811 * @} 01812 */ 01813 01814 /** 01815 * @} 01816 */ 01817 01818 #ifdef __cplusplus 01819 } 01820 #endif 01821 01822 01823 #endif /* STM32L4xx_HAL_ADC_H */
1.7.6.1