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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_adc_ex.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC HAL extended module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_ADC_EX_H 00021 #define STM32L4xx_HAL_ADC_EX_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 /** @addtogroup STM32L4xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup ADCEx 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup ADCEx_Exported_Types ADC Extended Exported Types 00040 * @{ 00041 */ 00042 00043 /** 00044 * @brief ADC Injected Conversion Oversampling structure definition 00045 */ 00046 typedef struct 00047 { 00048 uint32_t Ratio; /*!< Configures the oversampling ratio. 00049 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 00050 00051 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 00052 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 00053 } ADC_InjOversamplingTypeDef; 00054 00055 /** 00056 * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected 00057 * @note Parameters of this structure are shared within 2 scopes: 00058 * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset 00059 * - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode, 00060 * AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling. 00061 * @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state. 00062 * ADC state can be either: 00063 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') 00064 * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. 00065 * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. 00066 * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going 00067 * on ADC groups regular and injected. 00068 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00069 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). 00070 */ 00071 typedef struct 00072 { 00073 uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected. 00074 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 00075 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 00076 00077 uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. 00078 This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. 00079 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 00080 the new channel setting (or parameter number of conversions adjusted) */ 00081 00082 uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. 00083 Unit: ADC clock cycles. 00084 Conversion time is the addition of sampling time and processing time 00085 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 00086 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME. 00087 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00088 It overwrites the last setting. 00089 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00090 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 00091 Refer to device datasheet for timings values. */ 00092 00093 uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input. 00094 In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 00095 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 00096 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING. 00097 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00098 It overwrites the last setting. 00099 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 00100 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 00101 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00102 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 00103 of another parameter update on the fly) */ 00104 00105 uint32_t InjectedOffsetNumber; /*!< Selects the offset number. 00106 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB. 00107 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 00108 00109 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data. 00110 Offset value must be a positive number. 00111 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 00112 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 00113 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00114 without continuous mode or external trigger that could launch a conversion). */ 00115 00116 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. 00117 To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00118 This parameter must be a number between Min_Data = 1 and Max_Data = 4. 00119 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00120 configure a channel on injected group can impact the configuration of other channels previously set. */ 00121 00122 FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence 00123 (main sequence subdivided in successive parts). 00124 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00125 Discontinuous mode can be enabled only if continuous mode is disabled. 00126 This parameter can be set to ENABLE or DISABLE. 00127 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00128 Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). 00129 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00130 configure a channel on injected group can impact the configuration of other channels previously set. */ 00131 00132 FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one 00133 This parameter can be set to ENABLE or DISABLE. 00134 Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) 00135 Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) 00136 Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. 00137 To maintain JAUTO always enabled, DMA must be configured in circular mode. 00138 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00139 configure a channel on injected group can impact the configuration of other channels previously set. */ 00140 00141 FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. 00142 This parameter can be set to ENABLE or DISABLE. 00143 If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a 00144 new injected context is set when queue is full, error is triggered by interruption and through function 00145 'HAL_ADCEx_InjectedQueueOverflowCallback'. 00146 Caution: This feature request that the sequence is fully configured before injected conversion start. 00147 Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. 00148 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00149 configure a channel on injected group can impact the configuration of other channels previously set. 00150 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ 00151 00152 uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group. 00153 If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 00154 This parameter can be a value of @ref ADC_injected_external_trigger_source. 00155 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00156 configure a channel on injected group can impact the configuration of other channels previously set. */ 00157 00158 uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. 00159 This parameter can be a value of @ref ADC_injected_external_trigger_edge. 00160 If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. 00161 Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 00162 configure a channel on injected group can impact the configuration of other channels previously set. */ 00163 00164 FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. 00165 This parameter can be set to ENABLE or DISABLE. 00166 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00167 00168 ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. 00169 Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. 00170 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00171 } ADC_InjectionConfTypeDef; 00172 00173 #if defined(ADC_MULTIMODE_SUPPORT) 00174 /** 00175 * @brief Structure definition of ADC multimode 00176 * @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs). 00177 * Both Master and Slave ADCs must be disabled. 00178 */ 00179 typedef struct 00180 { 00181 uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode. 00182 This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */ 00183 00184 uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC: 00185 selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master) 00186 This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */ 00187 00188 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. 00189 This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY. 00190 Delay range depends on selected resolution: 00191 from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits, 00192 from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */ 00193 } ADC_MultiModeTypeDef; 00194 #endif /* ADC_MULTIMODE_SUPPORT */ 00195 00196 /** 00197 * @} 00198 */ 00199 00200 /* Exported constants --------------------------------------------------------*/ 00201 00202 /** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants 00203 * @{ 00204 */ 00205 00206 /** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source 00207 * @{ 00208 */ 00209 /* ADC group regular trigger sources for all ADC instances */ 00210 #define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /*!< Software triggers injected group conversion start */ 00211 #define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00212 #define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 00213 #define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00214 #define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00215 #define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00216 #define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00217 #define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00218 #define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00219 #define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00220 #define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00221 #define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 00222 #define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00223 #define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00224 #define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 00225 #define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 00226 #define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */ 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) 00232 * @{ 00233 */ 00234 #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ 00235 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ 00236 #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ 00237 #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ 00238 /** 00239 * @} 00240 */ 00241 00242 /** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending 00243 * @{ 00244 */ 00245 #define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */ 00246 #define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to differential (literal also used to set calibration mode) */ 00247 /** 00248 * @} 00249 */ 00250 00251 /** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number 00252 * @{ 00253 */ 00254 #define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */ 00255 #define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00256 #define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00257 #define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00258 #define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */ 00259 /** 00260 * @} 00261 */ 00262 00263 /** @defgroup ADC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks 00264 * @{ 00265 */ 00266 #define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */ 00267 #define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */ 00268 #define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */ 00269 #define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */ 00270 /** 00271 * @} 00272 */ 00273 00274 #if defined(ADC_MULTIMODE_SUPPORT) 00275 /** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode 00276 * @{ 00277 */ 00278 #define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /*!< ADC dual mode disabled (ADC independent mode) */ 00279 #define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */ 00280 #define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */ 00281 #define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */ 00282 #define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */ 00283 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */ 00284 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */ 00285 #define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */ 00286 00287 /** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution 00288 * @{ 00289 */ 00290 #define ADC_DMAACCESSMODE_DISABLED (0x00000000UL) /*!< DMA multimode disabled: each ADC uses its own DMA channel */ 00291 #define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution */ 00292 #define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /*!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution */ 00293 /** 00294 * @} 00295 */ 00296 00297 /** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases 00298 * @{ 00299 */ 00300 #define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */ 00301 #define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */ 00302 #define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */ 00303 #define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */ 00304 #define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */ 00305 #define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */ 00306 #define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */ 00307 #define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */ 00308 #define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */ 00309 #define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /*!< ADC multimode delay between two sampling phases: 10 ADC clock cycles */ 00310 #define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /*!< ADC multimode delay between two sampling phases: 11 ADC clock cycles */ 00311 #define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /*!< ADC multimode delay between two sampling phases: 12 ADC clock cycles */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** 00317 * @} 00318 */ 00319 #endif /* ADC_MULTIMODE_SUPPORT */ 00320 00321 /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups 00322 * @{ 00323 */ 00324 #define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ 00325 #define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /*!< ADC group injected (not available on all STM32 devices)*/ 00326 #define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */ 00327 /** 00328 * @} 00329 */ 00330 00331 /** @defgroup ADC_CFGR_fields ADCx CFGR fields 00332 * @{ 00333 */ 00334 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00335 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 00336 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 00337 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 00338 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 00339 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 00340 ADC_CFGR_RES | ADC_CFGR_DFSDMCFG | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN) 00341 #else 00342 #define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |\ 00343 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |\ 00344 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |\ 00345 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 00346 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN |\ 00347 ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN ) 00348 #endif /* ADC_CFGR_DFSDMCFG */ 00349 /** 00350 * @} 00351 */ 00352 00353 /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields 00354 * @{ 00355 */ 00356 #if defined(ADC_SMPR1_SMPPLUS) 00357 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 00358 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 00359 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 00360 ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS) 00361 #else 00362 #define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\ 00363 ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\ 00364 ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\ 00365 ADC_SMPR1_SMP0) 00366 #endif /* ADC_SMPR1_SMPPLUS */ 00367 /** 00368 * @} 00369 */ 00370 00371 /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields 00372 * @{ 00373 */ 00374 /* ADC_CFGR fields of parameters that can be updated when no conversion 00375 (neither regular nor injected) is on-going */ 00376 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00377 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY | ADC_CFGR_DFSDMCFG)) 00378 #else 00379 #define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY)) 00380 #endif /* ADC_CFGR_DFSDMCFG */ 00381 /** 00382 * @} 00383 */ 00384 00385 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00386 /** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data 00387 * @{ 00388 */ 00389 #define ADC_DFSDM_MODE_DISABLE (0x00000000UL) /*!< ADC conversions are not transferred by DFSDM. */ 00390 #define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transferred to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */ 00391 /** 00392 * @} 00393 */ 00394 #endif /* ADC_CFGR_DFSDMCFG */ 00395 00396 /** 00397 * @} 00398 */ 00399 00400 /* Exported macros -----------------------------------------------------------*/ 00401 00402 #if defined(ADC_MULTIMODE_SUPPORT) 00403 /** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros 00404 * @{ 00405 */ 00406 00407 /** @brief Force ADC instance in multimode mode independent (multimode disable). 00408 * @note This macro must be used only in case of transition from multimode 00409 * to mode independent and in case of unknown previous state, 00410 * to ensure ADC configuration is in mode independent. 00411 * @note Standard way of multimode configuration change is done from 00412 * HAL ADC handle of ADC master using function 00413 * "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )". 00414 * Usage of this macro is not the Standard way of multimode 00415 * configuration and can lead to have HAL ADC handles status 00416 * misaligned. Usage of this macro must be limited to cases 00417 * mentioned above. 00418 * @param __HANDLE__ ADC handle. 00419 * @retval None 00420 */ 00421 #define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \ 00422 LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT) 00423 00424 /** 00425 * @} 00426 */ 00427 #endif /* ADC_MULTIMODE_SUPPORT */ 00428 00429 /* Private macros ------------------------------------------------------------*/ 00430 00431 /** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros 00432 * @{ 00433 */ 00434 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 00435 /* code of final user. */ 00436 00437 /** 00438 * @brief Test if conversion trigger of injected group is software start 00439 * or external trigger. 00440 * @param __HANDLE__ ADC handle. 00441 * @retval SET (software start) or RESET (external trigger). 00442 */ 00443 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ 00444 (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL) 00445 00446 /** 00447 * @brief Check if conversion is on going on regular or injected groups. 00448 * @param __HANDLE__ ADC handle. 00449 * @retval SET (conversion is on going) or RESET (no conversion is on going). 00450 */ 00451 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \ 00452 (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \ 00453 ) ? RESET : SET) 00454 00455 /** 00456 * @brief Check if conversion is on going on injected group. 00457 * @param __HANDLE__ ADC handle. 00458 * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going) 00459 */ 00460 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \ 00461 (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance)) 00462 00463 /** 00464 * @brief Check whether or not ADC is independent. 00465 * @param __HANDLE__ ADC handle. 00466 * @note When multimode feature is not available, the macro always returns SET. 00467 * @retval SET (ADC is independent) or RESET (ADC is not). 00468 */ 00469 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00470 #define ADC_IS_INDEPENDENT(__HANDLE__) \ 00471 ( ( ( ((__HANDLE__)->Instance) == ADC3) \ 00472 )? \ 00473 SET \ 00474 : \ 00475 RESET \ 00476 ) 00477 #elif defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00478 #define ADC_IS_INDEPENDENT(__HANDLE__) (SET) 00479 #elif defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 00480 #define ADC_IS_INDEPENDENT(__HANDLE__) (RESET) 00481 #endif /* (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) */ 00482 00483 /** 00484 * @brief Set the selected injected Channel rank. 00485 * @param __CHANNELNB__ Channel number. 00486 * @param __RANKNB__ Rank number. 00487 * @retval None 00488 */ 00489 #define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__)\ 00490 & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK)) 00491 00492 /** 00493 * @brief Configure ADC injected context queue 00494 * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode. 00495 * @retval None 00496 */ 00497 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos) 00498 00499 /** 00500 * @brief Configure ADC discontinuous conversion mode for injected group 00501 * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode. 00502 * @retval None 00503 */ 00504 #define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos) 00505 00506 /** 00507 * @brief Configure ADC discontinuous conversion mode for regular group 00508 * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode. 00509 * @retval None 00510 */ 00511 #define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos) 00512 00513 /** 00514 * @brief Configure the number of discontinuous conversions for regular group. 00515 * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions. 00516 * @retval None 00517 */ 00518 #define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos) 00519 00520 /** 00521 * @brief Configure the ADC auto delay mode. 00522 * @param __AUTOWAIT__ Auto delay bit enable or disable. 00523 * @retval None 00524 */ 00525 #define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos) 00526 00527 /** 00528 * @brief Configure ADC continuous conversion mode. 00529 * @param __CONTINUOUS_MODE__ Continuous mode. 00530 * @retval None 00531 */ 00532 #define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos) 00533 00534 /** 00535 * @brief Configure the ADC DMA continuous request. 00536 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 00537 * @retval None 00538 */ 00539 #define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos) 00540 00541 /** 00542 * @brief Configure the channel number into offset OFRx register. 00543 * @param __CHANNEL__ ADC Channel. 00544 * @retval None 00545 */ 00546 #define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos) 00547 00548 /** 00549 * @brief Configure the channel number into differential mode selection register. 00550 * @param __CHANNEL__ ADC Channel. 00551 * @retval None 00552 */ 00553 #define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__)) 00554 00555 /** 00556 * @brief Configure calibration factor in differential mode to be set into calibration register. 00557 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00558 * @retval None 00559 */ 00560 #define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__)\ 00561 & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos) 00562 00563 /** 00564 * @brief Calibration factor in differential mode to be retrieved from calibration register. 00565 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00566 * @retval None 00567 */ 00568 #define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos) 00569 00570 /** 00571 * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. 00572 * @param __THRESHOLD__ Threshold value. 00573 * @retval None 00574 */ 00575 #define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL) 00576 00577 #if defined(ADC_MULTIMODE_SUPPORT) 00578 /** 00579 * @brief Configure the ADC DMA continuous request for ADC multimode. 00580 * @param __DMACONTREQ_MODE__ DMA continuous request mode. 00581 * @retval None 00582 */ 00583 #define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos) 00584 #endif /* ADC_MULTIMODE_SUPPORT */ 00585 00586 /** 00587 * @brief Shift the offset with respect to the selected ADC resolution. 00588 * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. 00589 * If resolution 12 bits, no shift. 00590 * If resolution 10 bits, shift of 2 ranks on the left. 00591 * If resolution 8 bits, shift of 4 ranks on the left. 00592 * If resolution 6 bits, shift of 6 ranks on the left. 00593 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 00594 * @param __HANDLE__ ADC handle 00595 * @param __OFFSET__ Value to be shifted 00596 * @retval None 00597 */ 00598 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ 00599 ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 00600 00601 /** 00602 * @brief Shift the AWD1 threshold with respect to the selected ADC resolution. 00603 * @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. 00604 * If resolution 12 bits, no shift. 00605 * If resolution 10 bits, shift of 2 ranks on the left. 00606 * If resolution 8 bits, shift of 4 ranks on the left. 00607 * If resolution 6 bits, shift of 6 ranks on the left. 00608 * Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)). 00609 * @param __HANDLE__ ADC handle 00610 * @param __THRESHOLD__ Value to be shifted 00611 * @retval None 00612 */ 00613 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00614 ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) 00615 00616 /** 00617 * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. 00618 * @note Thresholds have to be left-aligned on bit 7. 00619 * If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded). 00620 * If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded). 00621 * If resolution 8 bits, no shift. 00622 * If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0). 00623 * @param __HANDLE__ ADC handle 00624 * @param __THRESHOLD__ Value to be shifted 00625 * @retval None 00626 */ 00627 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ 00628 ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ 00629 ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ 00630 ((__THRESHOLD__) << 2UL) \ 00631 ) 00632 00633 /** 00634 * @brief Clear Common Control Register. 00635 * @param __HANDLE__ ADC handle. 00636 * @retval None 00637 */ 00638 #if defined(ADC_MULTIMODE_SUPPORT) 00639 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 00640 ADC_CCR_CKMODE | \ 00641 ADC_CCR_PRESC | \ 00642 ADC_CCR_VBATEN | \ 00643 ADC_CCR_TSEN | \ 00644 ADC_CCR_VREFEN | \ 00645 ADC_CCR_MDMA | \ 00646 ADC_CCR_DMACFG | \ 00647 ADC_CCR_DELAY | \ 00648 ADC_CCR_DUAL) 00649 #else 00650 #define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \ 00651 ADC_CCR_CKMODE | \ 00652 ADC_CCR_PRESC | \ 00653 ADC_CCR_VBATEN | \ 00654 ADC_CCR_TSEN | \ 00655 ADC_CCR_VREFEN) 00656 00657 #endif /* ADC_MULTIMODE_SUPPORT */ 00658 00659 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) 00660 /** 00661 * @brief Set handle instance of the ADC slave associated to the ADC master. 00662 * @param __HANDLE_MASTER__ ADC master handle. 00663 * @param __HANDLE_SLAVE__ ADC slave handle. 00664 * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL. 00665 * @retval None 00666 */ 00667 #define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \ 00668 ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) ) 00669 #endif /* defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) */ 00670 00671 00672 /** 00673 * @brief Verify the ADC instance connected to the temperature sensor. 00674 * @param __HANDLE__ ADC handle. 00675 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00676 */ 00677 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00678 /* The temperature sensor measurement path (channel 17) is available on ADC1 */ 00679 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 00680 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00681 /* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */ 00682 #define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1)\ 00683 || (((__HANDLE__)->Instance) == ADC3)) 00684 #endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ 00685 00686 /** 00687 * @brief Verify the ADC instance connected to the battery voltage VBAT. 00688 * @param __HANDLE__ ADC handle. 00689 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00690 */ 00691 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00692 /* The battery voltage measurement path (channel 18) is available on ADC1 */ 00693 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 00694 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00695 /* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */ 00696 #define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1)\ 00697 || (((__HANDLE__)->Instance) == ADC3)) 00698 #endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ 00699 00700 /** 00701 * @brief Verify the ADC instance connected to the internal voltage reference VREFINT. 00702 * @param __HANDLE__ ADC handle. 00703 * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid) 00704 */ 00705 /* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */ 00706 #define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1) 00707 00708 /** 00709 * @brief Verify the length of scheduled injected conversions group. 00710 * @param __LENGTH__ number of programmed conversions. 00711 * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) 00712 */ 00713 #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) 00714 00715 /** 00716 * @brief Calibration factor size verification (7 bits maximum). 00717 * @param __CALIBRATION_FACTOR__ Calibration factor value. 00718 * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) 00719 */ 00720 #define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) 00721 00722 00723 /** 00724 * @brief Verify the ADC channel setting. 00725 * @param __HANDLE__ ADC handle. 00726 * @param __CHANNEL__ programmed ADC channel. 00727 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00728 */ 00729 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00730 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ 00731 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00732 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00733 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00734 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00735 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00736 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00737 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00738 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00739 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00740 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00741 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00742 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00743 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00744 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00745 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00746 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00747 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 00748 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 00749 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 00750 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 00751 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 00752 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) || \ 00753 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2))) 00754 #elif defined (STM32L412xx) || defined (STM32L422xx) 00755 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 00756 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00757 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00758 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00759 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00760 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00761 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00762 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00763 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00764 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00765 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00766 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00767 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00768 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00769 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00770 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00771 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00772 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 00773 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 00774 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 00775 ((((__HANDLE__)->Instance) == ADC2) && \ 00776 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00777 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00778 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00779 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00780 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00781 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00782 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00783 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00784 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00785 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00786 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00787 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00788 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00789 ((__CHANNEL__) == ADC_CHANNEL_16) ))) 00790 #elif defined (STM32L4P5xx) || defined (STM32L4Q5xx) 00791 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 00792 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00793 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00794 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00795 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00796 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00797 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00798 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00799 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00800 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00801 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00802 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00803 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00804 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00805 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00806 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00807 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00808 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 00809 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 00810 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 00811 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 00812 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 00813 ((((__HANDLE__)->Instance) == ADC2) && \ 00814 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00815 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00816 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00817 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00818 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00819 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00820 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00821 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00822 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00823 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00824 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00825 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00826 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00827 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00828 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00829 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00830 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 00831 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 00832 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \ 00833 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2) ))) 00834 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00835 #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \ 00836 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00837 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00838 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00839 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00840 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00841 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00842 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00843 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00844 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00845 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00846 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00847 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00848 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00849 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00850 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00851 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00852 ((__CHANNEL__) == ADC_CHANNEL_VREFINT) || \ 00853 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 00854 ((__CHANNEL__) == ADC_CHANNEL_VBAT))) || \ 00855 ((((__HANDLE__)->Instance) == ADC2) && \ 00856 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00857 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00858 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00859 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00860 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00861 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00862 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00863 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00864 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00865 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00866 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00867 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00868 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00869 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00870 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00871 ((__CHANNEL__) == ADC_CHANNEL_16) || \ 00872 ((__CHANNEL__) == ADC_CHANNEL_17) || \ 00873 ((__CHANNEL__) == ADC_CHANNEL_18) || \ 00874 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) || \ 00875 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) || \ 00876 ((((__HANDLE__)->Instance) == ADC3) && \ 00877 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00878 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00879 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00880 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00881 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00882 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00883 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00884 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00885 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00886 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00887 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00888 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00889 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00890 ((__CHANNEL__) == ADC_CHANNEL_15) || \ 00891 ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) || \ 00892 ((__CHANNEL__) == ADC_CHANNEL_VBAT) || \ 00893 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) || \ 00894 ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) ))) 00895 #endif /* (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ 00896 00897 /** 00898 * @brief Verify the ADC channel setting in differential mode. 00899 * @param __HANDLE__ ADC handle. 00900 * @param __CHANNEL__ programmed ADC channel. 00901 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00902 */ 00903 #if defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00904 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00905 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00906 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00907 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00908 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00909 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00910 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00911 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00912 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00913 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00914 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00915 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00916 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00917 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00918 ((__CHANNEL__) == ADC_CHANNEL_15) ) 00919 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00920 /* For ADC1 and ADC2, channels 1 to 15 are available in differential mode, 00921 channels 0, 16 to 18 can be only used in single-ended mode. 00922 For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode, 00923 channels 4, 5 and 13 to 18 can only be used in single-ended mode. */ 00924 #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) || \ 00925 (((__HANDLE__)->Instance) == ADC2)) && \ 00926 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00927 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00928 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00929 ((__CHANNEL__) == ADC_CHANNEL_4) || \ 00930 ((__CHANNEL__) == ADC_CHANNEL_5) || \ 00931 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00932 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00933 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00934 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00935 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00936 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00937 ((__CHANNEL__) == ADC_CHANNEL_12) || \ 00938 ((__CHANNEL__) == ADC_CHANNEL_13) || \ 00939 ((__CHANNEL__) == ADC_CHANNEL_14) || \ 00940 ((__CHANNEL__) == ADC_CHANNEL_15))) || \ 00941 ((((__HANDLE__)->Instance) == ADC3) && \ 00942 (((__CHANNEL__) == ADC_CHANNEL_1) || \ 00943 ((__CHANNEL__) == ADC_CHANNEL_2) || \ 00944 ((__CHANNEL__) == ADC_CHANNEL_3) || \ 00945 ((__CHANNEL__) == ADC_CHANNEL_6) || \ 00946 ((__CHANNEL__) == ADC_CHANNEL_7) || \ 00947 ((__CHANNEL__) == ADC_CHANNEL_8) || \ 00948 ((__CHANNEL__) == ADC_CHANNEL_9) || \ 00949 ((__CHANNEL__) == ADC_CHANNEL_10) || \ 00950 ((__CHANNEL__) == ADC_CHANNEL_11) || \ 00951 ((__CHANNEL__) == ADC_CHANNEL_12) ))) 00952 #endif /* (STM32L412xx) || defined (STM32L422xx) || defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) */ 00953 00954 /** 00955 * @brief Verify the ADC single-ended input or differential mode setting. 00956 * @param __SING_DIFF__ programmed channel setting. 00957 * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) 00958 */ 00959 #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ 00960 ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) ) 00961 00962 /** 00963 * @brief Verify the ADC offset management setting. 00964 * @param __OFFSET_NUMBER__ ADC offset management. 00965 * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) 00966 */ 00967 #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ 00968 ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ 00969 ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ 00970 ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ 00971 ((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) 00972 00973 /** 00974 * @brief Verify the ADC injected channel setting. 00975 * @param __CHANNEL__ programmed ADC injected channel. 00976 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 00977 */ 00978 #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ 00979 ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ 00980 ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ 00981 ((__CHANNEL__) == ADC_INJECTED_RANK_4) ) 00982 00983 /** 00984 * @brief Verify the ADC injected conversions external trigger. 00985 * @param __HANDLE__ ADC handle. 00986 * @param __INJTRIG__ programmed ADC injected conversions external trigger. 00987 * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid) 00988 */ 00989 #define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) || \ 00990 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) || \ 00991 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) || \ 00992 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) || \ 00993 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) || \ 00994 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) || \ 00995 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) || \ 00996 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) || \ 00997 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) || \ 00998 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) || \ 00999 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) || \ 01000 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) || \ 01001 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) || \ 01002 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) || \ 01003 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) || \ 01004 ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) || \ 01005 ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) ) 01006 01007 /** 01008 * @brief Verify the ADC edge trigger setting for injected group. 01009 * @param __EDGE__ programmed ADC edge trigger setting. 01010 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 01011 */ 01012 #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ 01013 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ 01014 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ 01015 ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) 01016 01017 #if defined(ADC_MULTIMODE_SUPPORT) 01018 /** 01019 * @brief Verify the ADC multimode setting. 01020 * @param __MODE__ programmed ADC multimode setting. 01021 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01022 */ 01023 #define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) || \ 01024 ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \ 01025 ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \ 01026 ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \ 01027 ((__MODE__) == ADC_DUALMODE_INJECSIMULT) || \ 01028 ((__MODE__) == ADC_DUALMODE_REGSIMULT) || \ 01029 ((__MODE__) == ADC_DUALMODE_INTERL) || \ 01030 ((__MODE__) == ADC_DUALMODE_ALTERTRIG) ) 01031 01032 /** 01033 * @brief Verify the ADC multimode DMA access setting. 01034 * @param __MODE__ programmed ADC multimode DMA access setting. 01035 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01036 */ 01037 #define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) || \ 01038 ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \ 01039 ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) ) 01040 01041 /** 01042 * @brief Verify the ADC multimode delay setting. 01043 * @param __DELAY__ programmed ADC multimode delay setting. 01044 * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid) 01045 */ 01046 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) || \ 01047 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) || \ 01048 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) || \ 01049 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) || \ 01050 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ 01051 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ 01052 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ 01053 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ 01054 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ 01055 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ 01056 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ 01057 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) ) 01058 #endif /* ADC_MULTIMODE_SUPPORT */ 01059 01060 /** 01061 * @brief Verify the ADC analog watchdog setting. 01062 * @param __WATCHDOG__ programmed ADC analog watchdog setting. 01063 * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid) 01064 */ 01065 #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ 01066 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ 01067 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) 01068 01069 /** 01070 * @brief Verify the ADC analog watchdog mode setting. 01071 * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting. 01072 * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid) 01073 */ 01074 #define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) || \ 01075 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ 01076 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \ 01077 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ 01078 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ 01079 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ 01080 ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) 01081 01082 /** 01083 * @brief Verify the ADC conversion (regular or injected or both). 01084 * @param __CONVERSION__ ADC conversion group. 01085 * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) 01086 */ 01087 #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ 01088 ((__CONVERSION__) == ADC_INJECTED_GROUP) || \ 01089 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) 01090 01091 /** 01092 * @brief Verify the ADC event type. 01093 * @param __EVENT__ ADC event. 01094 * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) 01095 */ 01096 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ 01097 ((__EVENT__) == ADC_AWD_EVENT) || \ 01098 ((__EVENT__) == ADC_AWD2_EVENT) || \ 01099 ((__EVENT__) == ADC_AWD3_EVENT) || \ 01100 ((__EVENT__) == ADC_OVR_EVENT) || \ 01101 ((__EVENT__) == ADC_JQOVF_EVENT) ) 01102 01103 /** 01104 * @brief Verify the ADC oversampling ratio. 01105 * @param __RATIO__ programmed ADC oversampling ratio. 01106 * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) 01107 */ 01108 #define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ 01109 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ 01110 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ 01111 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ 01112 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ 01113 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ 01114 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ 01115 ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) 01116 01117 /** 01118 * @brief Verify the ADC oversampling shift. 01119 * @param __SHIFT__ programmed ADC oversampling shift. 01120 * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) 01121 */ 01122 #define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ 01123 ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ 01124 ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ 01125 ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ 01126 ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ 01127 ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ 01128 ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ 01129 ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ 01130 ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) 01131 01132 /** 01133 * @brief Verify the ADC oversampling triggered mode. 01134 * @param __MODE__ programmed ADC oversampling triggered mode. 01135 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01136 */ 01137 #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ 01138 ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) 01139 01140 /** 01141 * @brief Verify the ADC oversampling regular conversion resumed or continued mode. 01142 * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. 01143 * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) 01144 */ 01145 #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ 01146 ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) 01147 01148 /** 01149 * @brief Verify the DFSDM mode configuration. 01150 * @param __HANDLE__ ADC handle. 01151 * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For 01152 * this reason, the input parameter is the ADC handle and not the configuration parameter 01153 * directly. 01154 * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) 01155 */ 01156 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 01157 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \ 01158 ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) ) 01159 #else 01160 #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) 01161 #endif /* ADC_CFGR_DFSDMCFG */ 01162 01163 /** 01164 * @brief Return the DFSDM configuration mode. 01165 * @param __HANDLE__ ADC handle. 01166 * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). 01167 * For this reason, the input parameter is the ADC handle and not the configuration parameter 01168 * directly. 01169 * @retval DFSDM configuration mode 01170 */ 01171 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 01172 #define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig) 01173 #else 01174 #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) 01175 #endif /* ADC_CFGR_DFSDMCFG */ 01176 01177 /** 01178 * @} 01179 */ 01180 01181 01182 /* Exported functions --------------------------------------------------------*/ 01183 /** @addtogroup ADCEx_Exported_Functions 01184 * @{ 01185 */ 01186 01187 /** @addtogroup ADCEx_Exported_Functions_Group1 01188 * @{ 01189 */ 01190 /* IO operation functions *****************************************************/ 01191 01192 /* ADC calibration */ 01193 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 01194 uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); 01195 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, 01196 uint32_t CalibrationFactor); 01197 01198 /* Blocking mode: Polling */ 01199 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc); 01200 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc); 01201 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); 01202 01203 /* Non-blocking mode: Interruption */ 01204 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc); 01205 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc); 01206 01207 #if defined(ADC_MULTIMODE_SUPPORT) 01208 /* ADC multimode */ 01209 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); 01210 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc); 01211 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc); 01212 #endif /* ADC_MULTIMODE_SUPPORT */ 01213 01214 /* ADC retrieve conversion value intended to be used with polling or interruption */ 01215 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank); 01216 01217 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ 01218 void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc); 01219 void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc); 01220 void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); 01221 void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); 01222 void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); 01223 01224 /* ADC group regular conversions stop */ 01225 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc); 01226 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc); 01227 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc); 01228 #if defined(ADC_MULTIMODE_SUPPORT) 01229 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc); 01230 #endif /* ADC_MULTIMODE_SUPPORT */ 01231 01232 /** 01233 * @} 01234 */ 01235 01236 /** @addtogroup ADCEx_Exported_Functions_Group2 01237 * @{ 01238 */ 01239 /* Peripheral Control functions ***********************************************/ 01240 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc, 01241 ADC_InjectionConfTypeDef *sConfigInjected); 01242 #if defined(ADC_MULTIMODE_SUPPORT) 01243 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode); 01244 #endif /* ADC_MULTIMODE_SUPPORT */ 01245 HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc); 01246 HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc); 01247 HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); 01248 HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc); 01249 01250 /** 01251 * @} 01252 */ 01253 01254 /** 01255 * @} 01256 */ 01257 01258 /** 01259 * @} 01260 */ 01261 01262 /** 01263 * @} 01264 */ 01265 01266 #ifdef __cplusplus 01267 } 01268 #endif 01269 01270 #endif /* STM32L4xx_HAL_ADC_EX_H */
1.7.6.1