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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file in 00013 * the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_CORTEX_H 00021 #define STM32L4xx_HAL_CORTEX_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 /** @addtogroup STM32L4xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @defgroup CORTEX CORTEX 00035 * @brief CORTEX HAL module driver 00036 * @{ 00037 */ 00038 00039 /* Exported types ------------------------------------------------------------*/ 00040 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 00041 * @{ 00042 */ 00043 00044 #if (__MPU_PRESENT == 1) 00045 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 00046 * @brief MPU Region initialization structure 00047 * @{ 00048 */ 00049 typedef struct 00050 { 00051 uint8_t Enable; /*!< Specifies the status of the region. 00052 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 00053 uint8_t Number; /*!< Specifies the number of the region to protect. 00054 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 00055 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 00056 uint8_t Size; /*!< Specifies the size of the region to protect. 00057 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 00058 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 00059 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00060 uint8_t TypeExtField; /*!< Specifies the TEX field level. 00061 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 00062 uint8_t AccessPermission; /*!< Specifies the region access permission type. 00063 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 00064 uint8_t DisableExec; /*!< Specifies the instruction access status. 00065 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 00066 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 00067 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 00068 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 00069 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 00070 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 00071 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 00072 }MPU_Region_InitTypeDef; 00073 /** 00074 * @} 00075 */ 00076 #endif /* __MPU_PRESENT */ 00077 00078 /** 00079 * @} 00080 */ 00081 00082 /* Exported constants --------------------------------------------------------*/ 00083 00084 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 00085 * @{ 00086 */ 00087 00088 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 00089 * @{ 00090 */ 00091 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, 00092 4 bits for subpriority */ 00093 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, 00094 3 bits for subpriority */ 00095 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, 00096 2 bits for subpriority */ 00097 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, 00098 1 bit for subpriority */ 00099 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, 00100 0 bit for subpriority */ 00101 /** 00102 * @} 00103 */ 00104 00105 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 00106 * @{ 00107 */ 00108 #define SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U 00109 #define SYSTICK_CLKSOURCE_HCLK 0x00000004U 00110 00111 /** 00112 * @} 00113 */ 00114 00115 #if (__MPU_PRESENT == 1) 00116 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 00117 * @{ 00118 */ 00119 #define MPU_HFNMI_PRIVDEF_NONE 0x00000000U 00120 #define MPU_HARDFAULT_NMI (MPU_CTRL_HFNMIENA_Msk) 00121 #define MPU_PRIVILEGED_DEFAULT (MPU_CTRL_PRIVDEFENA_Msk) 00122 #define MPU_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) 00123 /** 00124 * @} 00125 */ 00126 00127 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 00128 * @{ 00129 */ 00130 #define MPU_REGION_ENABLE ((uint8_t)0x01) 00131 #define MPU_REGION_DISABLE ((uint8_t)0x00) 00132 /** 00133 * @} 00134 */ 00135 00136 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 00137 * @{ 00138 */ 00139 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 00140 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 00141 /** 00142 * @} 00143 */ 00144 00145 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 00146 * @{ 00147 */ 00148 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 00149 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 00150 /** 00151 * @} 00152 */ 00153 00154 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 00155 * @{ 00156 */ 00157 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 00158 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 00159 /** 00160 * @} 00161 */ 00162 00163 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 00164 * @{ 00165 */ 00166 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 00167 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 00168 /** 00169 * @} 00170 */ 00171 00172 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 00173 * @{ 00174 */ 00175 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 00176 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 00177 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 00178 #define MPU_TEX_LEVEL4 ((uint8_t)0x04) 00179 /** 00180 * @} 00181 */ 00182 00183 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 00184 * @{ 00185 */ 00186 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 00187 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 00188 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 00189 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 00190 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 00191 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 00192 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 00193 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 00194 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 00195 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 00196 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 00197 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 00198 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 00199 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 00200 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 00201 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 00202 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 00203 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 00204 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 00205 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 00206 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 00207 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 00208 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 00209 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 00210 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 00211 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 00212 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 00213 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 00214 /** 00215 * @} 00216 */ 00217 00218 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 00219 * @{ 00220 */ 00221 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 00222 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 00223 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 00224 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 00225 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 00226 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 00232 * @{ 00233 */ 00234 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 00235 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 00236 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 00237 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 00238 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 00239 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 00240 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 00241 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 00242 /** 00243 * @} 00244 */ 00245 #endif /* __MPU_PRESENT */ 00246 00247 /** 00248 * @} 00249 */ 00250 00251 /* Exported macros -----------------------------------------------------------*/ 00252 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 00253 * @{ 00254 */ 00255 00256 /** 00257 * @} 00258 */ 00259 00260 /* Exported functions --------------------------------------------------------*/ 00261 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 00262 * @{ 00263 */ 00264 00265 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 00266 * @brief Initialization and Configuration functions 00267 * @{ 00268 */ 00269 /* Initialization and Configuration functions *****************************/ 00270 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 00271 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 00272 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 00273 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 00274 void HAL_NVIC_SystemReset(void); 00275 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 00276 00277 /** 00278 * @} 00279 */ 00280 00281 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 00282 * @brief Cortex control functions 00283 * @{ 00284 */ 00285 /* Peripheral Control functions ***********************************************/ 00286 uint32_t HAL_NVIC_GetPriorityGrouping(void); 00287 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 00288 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 00289 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 00290 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 00291 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 00292 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 00293 void HAL_SYSTICK_IRQHandler(void); 00294 void HAL_SYSTICK_Callback(void); 00295 00296 #if (__MPU_PRESENT == 1) 00297 void HAL_MPU_Enable(uint32_t MPU_Control); 00298 void HAL_MPU_Disable(void); 00299 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 00300 #endif /* __MPU_PRESENT */ 00301 /** 00302 * @} 00303 */ 00304 00305 /** 00306 * @} 00307 */ 00308 00309 /* Private types -------------------------------------------------------------*/ 00310 /* Private variables ---------------------------------------------------------*/ 00311 /* Private constants ---------------------------------------------------------*/ 00312 /* Private macros ------------------------------------------------------------*/ 00313 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 00314 * @{ 00315 */ 00316 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 00317 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 00318 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 00319 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 00320 ((GROUP) == NVIC_PRIORITYGROUP_4)) 00321 00322 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 00323 00324 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 00325 00326 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 00327 00328 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 00329 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 00330 00331 #if (__MPU_PRESENT == 1) 00332 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 00333 ((STATE) == MPU_REGION_DISABLE)) 00334 00335 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 00336 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 00337 00338 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 00339 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 00340 00341 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 00342 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 00343 00344 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 00345 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 00346 00347 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 00348 ((TYPE) == MPU_TEX_LEVEL1) || \ 00349 ((TYPE) == MPU_TEX_LEVEL2) || \ 00350 ((TYPE) == MPU_TEX_LEVEL4)) 00351 00352 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 00353 ((TYPE) == MPU_REGION_PRIV_RW) || \ 00354 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 00355 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 00356 ((TYPE) == MPU_REGION_PRIV_RO) || \ 00357 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 00358 00359 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 00360 ((NUMBER) == MPU_REGION_NUMBER1) || \ 00361 ((NUMBER) == MPU_REGION_NUMBER2) || \ 00362 ((NUMBER) == MPU_REGION_NUMBER3) || \ 00363 ((NUMBER) == MPU_REGION_NUMBER4) || \ 00364 ((NUMBER) == MPU_REGION_NUMBER5) || \ 00365 ((NUMBER) == MPU_REGION_NUMBER6) || \ 00366 ((NUMBER) == MPU_REGION_NUMBER7)) 00367 00368 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 00369 ((SIZE) == MPU_REGION_SIZE_64B) || \ 00370 ((SIZE) == MPU_REGION_SIZE_128B) || \ 00371 ((SIZE) == MPU_REGION_SIZE_256B) || \ 00372 ((SIZE) == MPU_REGION_SIZE_512B) || \ 00373 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 00374 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 00375 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 00376 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 00377 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 00378 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 00379 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 00380 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 00381 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 00382 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 00383 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 00384 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 00385 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 00386 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 00387 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 00388 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 00389 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 00390 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 00391 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 00392 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 00393 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 00394 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 00395 ((SIZE) == MPU_REGION_SIZE_4GB)) 00396 00397 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 00398 #endif /* __MPU_PRESENT */ 00399 00400 /** 00401 * @} 00402 */ 00403 00404 /* Private functions ---------------------------------------------------------*/ 00405 00406 /** 00407 * @} 00408 */ 00409 00410 /** 00411 * @} 00412 */ 00413 00414 #ifdef __cplusplus 00415 } 00416 #endif 00417 00418 #endif /* STM32L4xx_HAL_CORTEX_H */ 00419 00420
1.7.6.1