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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dma2d.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA2D HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_DMA2D_H 00021 #define STM32L4xx_HAL_DMA2D_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 /** @addtogroup STM32L4xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 #if defined (DMA2D) 00035 00036 /** @addtogroup DMA2D DMA2D 00037 * @brief DMA2D HAL module driver 00038 * @{ 00039 */ 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 00043 * @{ 00044 */ 00045 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 00046 00047 /** 00048 * @brief DMA2D CLUT Structure definition 00049 */ 00050 typedef struct 00051 { 00052 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 00053 00054 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 00055 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 00056 00057 uint32_t Size; /*!< Configures the DMA2D CLUT size. 00058 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 00059 } DMA2D_CLUTCfgTypeDef; 00060 00061 /** 00062 * @brief DMA2D Init structure definition 00063 */ 00064 typedef struct 00065 { 00066 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 00067 This parameter can be one value of @ref DMA2D_Mode. */ 00068 00069 uint32_t ColorMode; /*!< Configures the color format of the output image. 00070 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 00071 00072 uint32_t OutputOffset; /*!< Specifies the Offset value. 00073 This parameter must be a number between 00074 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00075 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 00076 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 00077 00078 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 00079 for the output pixel format converter. 00080 This parameter can be one value of @ref DMA2D_RB_Swap. */ 00081 00082 00083 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 00084 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 00085 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 00086 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 00087 00088 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 00089 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset 00090 for the foreground, background and output. 00091 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 00092 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 00093 00094 } DMA2D_InitTypeDef; 00095 00096 00097 /** 00098 * @brief DMA2D Layer structure definition 00099 */ 00100 typedef struct 00101 { 00102 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 00103 This parameter must be a number between 00104 Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00105 00106 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 00107 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 00108 00109 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 00110 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 00111 00112 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value 00113 in case of A8 or A4 color mode. 00114 This parameter must be a number between Min_Data = 0x00 00115 and Max_Data = 0xFF except for the color modes detailed below. 00116 @note In case of A8 or A4 color mode (ARGB), 00117 this parameter must be a number between 00118 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 00119 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 00120 - InputAlpha[16:23] is the red value RED[0:7] 00121 - InputAlpha[8:15] is the green value GREEN[0:7] 00122 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 00123 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 00124 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 00125 00126 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 00127 This parameter can be one value of @ref DMA2D_RB_Swap. */ 00128 00129 00130 } DMA2D_LayerCfgTypeDef; 00131 00132 /** 00133 * @brief HAL DMA2D State structures definition 00134 */ 00135 typedef enum 00136 { 00137 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 00138 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00139 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00140 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00141 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 00142 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 00143 } HAL_DMA2D_StateTypeDef; 00144 00145 /** 00146 * @brief DMA2D handle Structure definition 00147 */ 00148 typedef struct __DMA2D_HandleTypeDef 00149 { 00150 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 00151 00152 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 00153 00154 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer complete callback. */ 00155 00156 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D transfer error callback. */ 00157 00158 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00159 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D line event callback. */ 00160 00161 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D CLUT loading completion callback */ 00162 00163 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp Init callback. */ 00164 00165 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d); /*!< DMA2D Msp DeInit callback. */ 00166 00167 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 00168 00169 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 00170 00171 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 00172 00173 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 00174 00175 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 00176 } DMA2D_HandleTypeDef; 00177 00178 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00179 /** 00180 * @brief HAL DMA2D Callback pointer definition 00181 */ 00182 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d); /*!< Pointer to a DMA2D common callback function */ 00183 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00184 /** 00185 * @} 00186 */ 00187 00188 /* Exported constants --------------------------------------------------------*/ 00189 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 00190 * @{ 00191 */ 00192 00193 /** @defgroup DMA2D_Error_Code DMA2D Error Code 00194 * @{ 00195 */ 00196 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 00197 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 00198 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 00199 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 00200 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00201 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00202 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 00203 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 00204 00205 /** 00206 * @} 00207 */ 00208 00209 /** @defgroup DMA2D_Mode DMA2D Mode 00210 * @{ 00211 */ 00212 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 00213 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 00214 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 00215 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 00216 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 00217 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 00218 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 00219 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 00220 /** 00221 * @} 00222 */ 00223 00224 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 00225 * @{ 00226 */ 00227 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 00228 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 00229 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 00230 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 00231 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 00232 /** 00233 * @} 00234 */ 00235 00236 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 00237 * @{ 00238 */ 00239 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 00240 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 00241 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 00242 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 00243 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 00244 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 00245 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 00246 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 00247 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 00248 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 00249 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 00250 /** 00251 * @} 00252 */ 00253 00254 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 00255 * @{ 00256 */ 00257 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 00258 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 00259 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 00260 with original alpha channel value */ 00261 /** 00262 * @} 00263 */ 00264 00265 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 00266 * @{ 00267 */ 00268 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 00269 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 00270 /** 00271 * @} 00272 */ 00273 00274 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 00275 * @{ 00276 */ 00277 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 00278 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 00279 /** 00280 * @} 00281 */ 00282 00283 00284 00285 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 00286 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 00287 * @{ 00288 */ 00289 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 00290 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 00291 /** 00292 * @} 00293 */ 00294 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 00295 00296 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 00297 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 00298 * @{ 00299 */ 00300 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 00301 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 00302 /** 00303 * @} 00304 */ 00305 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 00306 00307 00308 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 00309 * @{ 00310 */ 00311 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 00312 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 00313 /** 00314 * @} 00315 */ 00316 00317 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 00318 * @{ 00319 */ 00320 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 00321 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 00322 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 00323 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 00324 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 00325 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 00326 /** 00327 * @} 00328 */ 00329 00330 /** @defgroup DMA2D_Flags DMA2D Flags 00331 * @{ 00332 */ 00333 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 00334 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 00335 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 00336 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 00337 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 00338 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 00339 /** 00340 * @} 00341 */ 00342 00343 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00344 /** 00345 * @brief HAL DMA2D common Callback ID enumeration definition 00346 */ 00347 typedef enum 00348 { 00349 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 00350 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 00351 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 00352 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 00353 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 00354 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 00355 } HAL_DMA2D_CallbackIDTypeDef; 00356 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00357 00358 00359 /** 00360 * @} 00361 */ 00362 /* Exported macros ------------------------------------------------------------*/ 00363 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 00364 * @{ 00365 */ 00366 00367 /** @brief Reset DMA2D handle state 00368 * @param __HANDLE__ specifies the DMA2D handle. 00369 * @retval None 00370 */ 00371 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00372 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00373 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 00374 (__HANDLE__)->MspInitCallback = NULL; \ 00375 (__HANDLE__)->MspDeInitCallback = NULL; \ 00376 }while(0) 00377 #else 00378 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 00379 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00380 00381 00382 /** 00383 * @brief Enable the DMA2D. 00384 * @param __HANDLE__ DMA2D handle 00385 * @retval None. 00386 */ 00387 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 00388 00389 00390 /* Interrupt & Flag management */ 00391 /** 00392 * @brief Get the DMA2D pending flags. 00393 * @param __HANDLE__ DMA2D handle 00394 * @param __FLAG__ flag to check. 00395 * This parameter can be any combination of the following values: 00396 * @arg DMA2D_FLAG_CE: Configuration error flag 00397 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00398 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00399 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00400 * @arg DMA2D_FLAG_TC: Transfer complete flag 00401 * @arg DMA2D_FLAG_TE: Transfer error flag 00402 * @retval The state of FLAG. 00403 */ 00404 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 00405 00406 /** 00407 * @brief Clear the DMA2D pending flags. 00408 * @param __HANDLE__ DMA2D handle 00409 * @param __FLAG__ specifies the flag to clear. 00410 * This parameter can be any combination of the following values: 00411 * @arg DMA2D_FLAG_CE: Configuration error flag 00412 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00413 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00414 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00415 * @arg DMA2D_FLAG_TC: Transfer complete flag 00416 * @arg DMA2D_FLAG_TE: Transfer error flag 00417 * @retval None 00418 */ 00419 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 00420 00421 /** 00422 * @brief Enable the specified DMA2D interrupts. 00423 * @param __HANDLE__ DMA2D handle 00424 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 00425 * This parameter can be any combination of the following values: 00426 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00427 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00428 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00429 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00430 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00431 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00432 * @retval None 00433 */ 00434 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 00435 00436 /** 00437 * @brief Disable the specified DMA2D interrupts. 00438 * @param __HANDLE__ DMA2D handle 00439 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 00440 * This parameter can be any combination of the following values: 00441 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00442 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00443 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00444 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00445 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00446 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00447 * @retval None 00448 */ 00449 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 00450 00451 /** 00452 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 00453 * @param __HANDLE__ DMA2D handle 00454 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 00455 * This parameter can be one of the following values: 00456 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00457 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00458 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00459 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00460 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00461 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00462 * @retval The state of INTERRUPT source. 00463 */ 00464 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 00465 00466 /** 00467 * @} 00468 */ 00469 00470 /* Exported functions --------------------------------------------------------*/ 00471 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 00472 * @{ 00473 */ 00474 00475 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 00476 * @{ 00477 */ 00478 00479 /* Initialization and de-initialization functions *******************************/ 00480 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 00481 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d); 00482 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d); 00483 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d); 00484 /* Callbacks Register/UnRegister functions ***********************************/ 00485 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00486 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, 00487 pDMA2D_CallbackTypeDef pCallback); 00488 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 00489 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00490 00491 /** 00492 * @} 00493 */ 00494 00495 00496 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 00497 * @{ 00498 */ 00499 00500 /* IO operation functions *******************************************************/ 00501 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 00502 uint32_t Height); 00503 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 00504 uint32_t DstAddress, uint32_t Width, uint32_t Height); 00505 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, 00506 uint32_t Height); 00507 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, 00508 uint32_t DstAddress, uint32_t Width, uint32_t Height); 00509 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 00510 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 00511 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 00512 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00513 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 00514 uint32_t LayerIdx); 00515 HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, 00516 uint32_t LayerIdx); 00517 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00518 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00519 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00520 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00521 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00522 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 00523 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 00524 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 00525 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 00526 00527 /** 00528 * @} 00529 */ 00530 00531 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 00532 * @{ 00533 */ 00534 00535 /* Peripheral Control functions *************************************************/ 00536 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00537 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00538 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 00539 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00540 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00541 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 00542 00543 /** 00544 * @} 00545 */ 00546 00547 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 00548 * @{ 00549 */ 00550 00551 /* Peripheral State functions ***************************************************/ 00552 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 00553 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 00554 00555 /** 00556 * @} 00557 */ 00558 00559 /** 00560 * @} 00561 */ 00562 00563 /* Private constants ---------------------------------------------------------*/ 00564 00565 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 00566 * @{ 00567 */ 00568 00569 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 00570 * @{ 00571 */ 00572 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 00573 /** 00574 * @} 00575 */ 00576 00577 /** @defgroup DMA2D_Color_Value DMA2D Color Value 00578 * @{ 00579 */ 00580 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 00581 /** 00582 * @} 00583 */ 00584 00585 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 00586 * @{ 00587 */ 00588 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 00589 /** 00590 * @} 00591 */ 00592 00593 /** @defgroup DMA2D_Layers DMA2D Layers 00594 * @{ 00595 */ 00596 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 00597 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 00598 /** 00599 * @} 00600 */ 00601 00602 /** @defgroup DMA2D_Offset DMA2D Offset 00603 * @{ 00604 */ 00605 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 00606 /** 00607 * @} 00608 */ 00609 00610 /** @defgroup DMA2D_Size DMA2D Size 00611 * @{ 00612 */ 00613 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 00614 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 00615 /** 00616 * @} 00617 */ 00618 00619 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 00620 * @{ 00621 */ 00622 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 00623 /** 00624 * @} 00625 */ 00626 00627 /** 00628 * @} 00629 */ 00630 00631 00632 /* Private macros ------------------------------------------------------------*/ 00633 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 00634 * @{ 00635 */ 00636 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\ 00637 || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 00638 00639 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 00640 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 00641 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 00642 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 00643 #else 00644 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 00645 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 00646 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 00647 00648 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \ 00649 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 00650 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \ 00651 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 00652 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 00653 00654 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 00655 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 00656 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 00657 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 00658 00659 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \ 00660 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 00661 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \ 00662 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 00663 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \ 00664 ((INPUT_CM) == DMA2D_INPUT_L8) || \ 00665 ((INPUT_CM) == DMA2D_INPUT_AL44) || \ 00666 ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 00667 ((INPUT_CM) == DMA2D_INPUT_L4) || \ 00668 ((INPUT_CM) == DMA2D_INPUT_A8) || \ 00669 ((INPUT_CM) == DMA2D_INPUT_A4)) 00670 00671 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 00672 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 00673 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 00674 00675 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 00676 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 00677 00678 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 00679 ((RB_Swap) == DMA2D_RB_SWAP)) 00680 00681 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 00682 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 00683 ((LOM) == DMA2D_LOM_BYTES)) 00684 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 00685 00686 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 00687 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 00688 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 00689 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 00690 00691 00692 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 00693 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 00694 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 00695 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 00696 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 00697 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 00698 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 00699 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 00700 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 00701 /** 00702 * @} 00703 */ 00704 00705 /** 00706 * @} 00707 */ 00708 00709 #endif /* defined (DMA2D) */ 00710 00711 /** 00712 * @} 00713 */ 00714 00715 #ifdef __cplusplus 00716 } 00717 #endif 00718 00719 #endif /* STM32L4xx_HAL_DMA2D_H */
1.7.6.1