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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_DMA_H 00021 #define STM32L4xx_HAL_DMA_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 /** @addtogroup STM32L4xx_HAL_Driver 00031 * @{ 00032 */ 00033 00034 /** @addtogroup DMA 00035 * @{ 00036 */ 00037 00038 /* Exported types ------------------------------------------------------------*/ 00039 /** @defgroup DMA_Exported_Types DMA Exported Types 00040 * @{ 00041 */ 00042 00043 /** 00044 * @brief DMA Configuration Structure definition 00045 */ 00046 typedef struct 00047 { 00048 uint32_t Request; /*!< Specifies the request selected for the specified channel. 00049 This parameter can be a value of @ref DMA_request */ 00050 00051 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00052 from memory to memory or from peripheral to memory. 00053 This parameter can be a value of @ref DMA_Data_transfer_direction */ 00054 00055 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 00056 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 00057 00058 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 00059 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 00060 00061 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 00062 This parameter can be a value of @ref DMA_Peripheral_data_size */ 00063 00064 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 00065 This parameter can be a value of @ref DMA_Memory_data_size */ 00066 00067 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 00068 This parameter can be a value of @ref DMA_mode 00069 @note The circular buffer mode cannot be used if the memory-to-memory 00070 data transfer is configured on the selected Channel */ 00071 00072 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 00073 This parameter can be a value of @ref DMA_Priority_level */ 00074 } DMA_InitTypeDef; 00075 00076 /** 00077 * @brief HAL DMA State structures definition 00078 */ 00079 typedef enum 00080 { 00081 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 00082 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 00083 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 00084 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 00085 }HAL_DMA_StateTypeDef; 00086 00087 /** 00088 * @brief HAL DMA Error Code structure definition 00089 */ 00090 typedef enum 00091 { 00092 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 00093 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 00094 }HAL_DMA_LevelCompleteTypeDef; 00095 00096 00097 /** 00098 * @brief HAL DMA Callback ID structure definition 00099 */ 00100 typedef enum 00101 { 00102 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 00103 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 00104 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 00105 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 00106 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 00107 }HAL_DMA_CallbackIDTypeDef; 00108 00109 /** 00110 * @brief DMA handle Structure definition 00111 */ 00112 typedef struct __DMA_HandleTypeDef 00113 { 00114 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 00115 00116 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 00117 00118 HAL_LockTypeDef Lock; /*!< DMA locking object */ 00119 00120 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 00121 00122 void *Parent; /*!< Parent object state */ 00123 00124 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 00125 00126 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 00127 00128 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 00129 00130 void (* XferAbortCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 00131 00132 __IO uint32_t ErrorCode; /*!< DMA Error code */ 00133 00134 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 00135 00136 uint32_t ChannelIndex; /*!< DMA Channel Index */ 00137 00138 #if defined(DMAMUX1) 00139 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 00140 00141 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 00142 00143 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 00144 00145 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 00146 00147 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 00148 00149 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 00150 00151 #endif /* DMAMUX1 */ 00152 00153 }DMA_HandleTypeDef; 00154 /** 00155 * @} 00156 */ 00157 00158 /* Exported constants --------------------------------------------------------*/ 00159 00160 /** @defgroup DMA_Exported_Constants DMA Exported Constants 00161 * @{ 00162 */ 00163 00164 /** @defgroup DMA_Error_Code DMA Error Code 00165 * @{ 00166 */ 00167 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 00168 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 00169 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 00170 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00171 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 00172 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 00173 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 00174 00175 /** 00176 * @} 00177 */ 00178 00179 /** @defgroup DMA_request DMA request 00180 * @{ 00181 */ 00182 #if !defined (DMAMUX1) 00183 00184 #define DMA_REQUEST_0 0U 00185 #define DMA_REQUEST_1 1U 00186 #define DMA_REQUEST_2 2U 00187 #define DMA_REQUEST_3 3U 00188 #define DMA_REQUEST_4 4U 00189 #define DMA_REQUEST_5 5U 00190 #define DMA_REQUEST_6 6U 00191 #define DMA_REQUEST_7 7U 00192 00193 #endif 00194 00195 #if defined(DMAMUX1) 00196 00197 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 00198 00199 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 00200 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 00201 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 00202 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 00203 00204 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ 00205 00206 #if defined (STM32L4P5xx) || defined (STM32L4Q5xx) 00207 00208 #define DMA_REQUEST_ADC2 6U /*!< DMAMUX1 ADC1 request */ 00209 00210 #define DMA_REQUEST_DAC1_CH1 7U /*!< DMAMUX1 DAC1 CH1 request */ 00211 #define DMA_REQUEST_DAC1_CH2 8U /*!< DMAMUX1 DAC1 CH2 request */ 00212 00213 #define DMA_REQUEST_TIM6_UP 9U /*!< DMAMUX1 TIM6 UP request */ 00214 #define DMA_REQUEST_TIM7_UP 10U /*!< DMAMUX1 TIM7 UP request */ 00215 00216 #define DMA_REQUEST_SPI1_RX 11U /*!< DMAMUX1 SPI1 RX request */ 00217 #define DMA_REQUEST_SPI1_TX 12U /*!< DMAMUX1 SPI1 TX request */ 00218 #define DMA_REQUEST_SPI2_RX 13U /*!< DMAMUX1 SPI2 RX request */ 00219 #define DMA_REQUEST_SPI2_TX 14U /*!< DMAMUX1 SPI2 TX request */ 00220 #define DMA_REQUEST_SPI3_RX 15U /*!< DMAMUX1 SPI3 RX request */ 00221 #define DMA_REQUEST_SPI3_TX 16U /*!< DMAMUX1 SPI3 TX request */ 00222 00223 #define DMA_REQUEST_I2C1_RX 17U /*!< DMAMUX1 I2C1 RX request */ 00224 #define DMA_REQUEST_I2C1_TX 18U /*!< DMAMUX1 I2C1 TX request */ 00225 #define DMA_REQUEST_I2C2_RX 19U /*!< DMAMUX1 I2C2 RX request */ 00226 #define DMA_REQUEST_I2C2_TX 20U /*!< DMAMUX1 I2C2 TX request */ 00227 #define DMA_REQUEST_I2C3_RX 21U /*!< DMAMUX1 I2C3 RX request */ 00228 #define DMA_REQUEST_I2C3_TX 22U /*!< DMAMUX1 I2C3 TX request */ 00229 #define DMA_REQUEST_I2C4_RX 23U /*!< DMAMUX1 I2C4 RX request */ 00230 #define DMA_REQUEST_I2C4_TX 24U /*!< DMAMUX1 I2C4 TX request */ 00231 00232 #define DMA_REQUEST_USART1_RX 25U /*!< DMAMUX1 USART1 RX request */ 00233 #define DMA_REQUEST_USART1_TX 26U /*!< DMAMUX1 USART1 TX request */ 00234 #define DMA_REQUEST_USART2_RX 27U /*!< DMAMUX1 USART2 RX request */ 00235 #define DMA_REQUEST_USART2_TX 28U /*!< DMAMUX1 USART2 TX request */ 00236 #define DMA_REQUEST_USART3_RX 29U /*!< DMAMUX1 USART3 RX request */ 00237 #define DMA_REQUEST_USART3_TX 30U /*!< DMAMUX1 USART3 TX request */ 00238 00239 #define DMA_REQUEST_UART4_RX 31U /*!< DMAMUX1 UART4 RX request */ 00240 #define DMA_REQUEST_UART4_TX 32U /*!< DMAMUX1 UART4 TX request */ 00241 #define DMA_REQUEST_UART5_RX 33U /*!< DMAMUX1 UART5 RX request */ 00242 #define DMA_REQUEST_UART5_TX 34U /*!< DMAMUX1 UART5 TX request */ 00243 00244 #define DMA_REQUEST_LPUART1_RX 35U /*!< DMAMUX1 LP_UART1_RX request */ 00245 #define DMA_REQUEST_LPUART1_TX 36U /*!< DMAMUX1 LP_UART1_RX request */ 00246 00247 #define DMA_REQUEST_SAI1_A 37U /*!< DMAMUX1 SAI1 A request */ 00248 #define DMA_REQUEST_SAI1_B 38U /*!< DMAMUX1 SAI1 B request */ 00249 #define DMA_REQUEST_SAI2_A 39U /*!< DMAMUX1 SAI2 A request */ 00250 #define DMA_REQUEST_SAI2_B 40U /*!< DMAMUX1 SAI2 B request */ 00251 00252 #define DMA_REQUEST_OCTOSPI1 41U /*!< DMAMUX1 OCTOSPI1 request */ 00253 #define DMA_REQUEST_OCTOSPI2 42U /*!< DMAMUX1 OCTOSPI2 request */ 00254 00255 #define DMA_REQUEST_TIM1_CH1 43U /*!< DMAMUX1 TIM1 CH1 request */ 00256 #define DMA_REQUEST_TIM1_CH2 44U /*!< DMAMUX1 TIM1 CH2 request */ 00257 #define DMA_REQUEST_TIM1_CH3 45U /*!< DMAMUX1 TIM1 CH3 request */ 00258 #define DMA_REQUEST_TIM1_CH4 46U /*!< DMAMUX1 TIM1 CH4 request */ 00259 #define DMA_REQUEST_TIM1_UP 47U /*!< DMAMUX1 TIM1 UP request */ 00260 #define DMA_REQUEST_TIM1_TRIG 48U /*!< DMAMUX1 TIM1 TRIG request */ 00261 #define DMA_REQUEST_TIM1_COM 49U /*!< DMAMUX1 TIM1 COM request */ 00262 00263 #define DMA_REQUEST_TIM8_CH1 50U /*!< DMAMUX1 TIM8 CH1 request */ 00264 #define DMA_REQUEST_TIM8_CH2 51U /*!< DMAMUX1 TIM8 CH2 request */ 00265 #define DMA_REQUEST_TIM8_CH3 52U /*!< DMAMUX1 TIM8 CH3 request */ 00266 #define DMA_REQUEST_TIM8_CH4 53U /*!< DMAMUX1 TIM8 CH4 request */ 00267 #define DMA_REQUEST_TIM8_UP 54U /*!< DMAMUX1 TIM8 UP request */ 00268 #define DMA_REQUEST_TIM8_TRIG 55U /*!< DMAMUX1 TIM8 TRIG request */ 00269 #define DMA_REQUEST_TIM8_COM 56U /*!< DMAMUX1 TIM8 COM request */ 00270 00271 #define DMA_REQUEST_TIM2_CH1 57U /*!< DMAMUX1 TIM2 CH1 request */ 00272 #define DMA_REQUEST_TIM2_CH2 58U /*!< DMAMUX1 TIM2 CH2 request */ 00273 #define DMA_REQUEST_TIM2_CH3 59U /*!< DMAMUX1 TIM2 CH3 request */ 00274 #define DMA_REQUEST_TIM2_CH4 60U /*!< DMAMUX1 TIM2 CH4 request */ 00275 #define DMA_REQUEST_TIM2_UP 61U /*!< DMAMUX1 TIM2 UP request */ 00276 00277 #define DMA_REQUEST_TIM3_CH1 62U /*!< DMAMUX1 TIM3 CH1 request */ 00278 #define DMA_REQUEST_TIM3_CH2 63U /*!< DMAMUX1 TIM3 CH2 request */ 00279 #define DMA_REQUEST_TIM3_CH3 64U /*!< DMAMUX1 TIM3 CH3 request */ 00280 #define DMA_REQUEST_TIM3_CH4 65U /*!< DMAMUX1 TIM3 CH4 request */ 00281 #define DMA_REQUEST_TIM3_UP 66U /*!< DMAMUX1 TIM3 UP request */ 00282 #define DMA_REQUEST_TIM3_TRIG 67U /*!< DMAMUX1 TIM3 TRIG request */ 00283 00284 #define DMA_REQUEST_TIM4_CH1 68U /*!< DMAMUX1 TIM4 CH1 request */ 00285 #define DMA_REQUEST_TIM4_CH2 69U /*!< DMAMUX1 TIM4 CH2 request */ 00286 #define DMA_REQUEST_TIM4_CH3 70U /*!< DMAMUX1 TIM4 CH3 request */ 00287 #define DMA_REQUEST_TIM4_CH4 71U /*!< DMAMUX1 TIM4 CH4 request */ 00288 #define DMA_REQUEST_TIM4_UP 72U /*!< DMAMUX1 TIM4 UP request */ 00289 00290 #define DMA_REQUEST_TIM5_CH1 73U /*!< DMAMUX1 TIM5 CH1 request */ 00291 #define DMA_REQUEST_TIM5_CH2 74U /*!< DMAMUX1 TIM5 CH2 request */ 00292 #define DMA_REQUEST_TIM5_CH3 75U /*!< DMAMUX1 TIM5 CH3 request */ 00293 #define DMA_REQUEST_TIM5_CH4 76U /*!< DMAMUX1 TIM5 CH4 request */ 00294 #define DMA_REQUEST_TIM5_UP 77U /*!< DMAMUX1 TIM5 UP request */ 00295 #define DMA_REQUEST_TIM5_TRIG 78U /*!< DMAMUX1 TIM5 TRIG request */ 00296 00297 #define DMA_REQUEST_TIM15_CH1 79U /*!< DMAMUX1 TIM15 CH1 request */ 00298 #define DMA_REQUEST_TIM15_UP 80U /*!< DMAMUX1 TIM15 UP request */ 00299 #define DMA_REQUEST_TIM15_TRIG 81U /*!< DMAMUX1 TIM15 TRIG request */ 00300 #define DMA_REQUEST_TIM15_COM 82U /*!< DMAMUX1 TIM15 COM request */ 00301 00302 #define DMA_REQUEST_TIM16_CH1 83U /*!< DMAMUX1 TIM16 CH1 request */ 00303 #define DMA_REQUEST_TIM16_UP 84U /*!< DMAMUX1 TIM16 UP request */ 00304 #define DMA_REQUEST_TIM17_CH1 85U /*!< DMAMUX1 TIM17 CH1 request */ 00305 #define DMA_REQUEST_TIM17_UP 86U /*!< DMAMUX1 TIM17 UP request */ 00306 00307 #define DMA_REQUEST_DFSDM1_FLT0 87U /*!< DMAMUX1 DFSDM1 Filter0 request */ 00308 #define DMA_REQUEST_DFSDM1_FLT1 88U /*!< DMAMUX1 DFSDM1 Filter1 request */ 00309 00310 #define DMA_REQUEST_DCMI 91U /*!< DMAMUX1 DCMI request */ 00311 #define DMA_REQUEST_DCMI_PSSI 91U /*!< DMAMUX1 DCMI/PSSI request */ 00312 00313 #define DMA_REQUEST_AES_IN 92U /*!< DMAMUX1 AES IN request */ 00314 #define DMA_REQUEST_AES_OUT 93U /*!< DMAMUX1 AES OUT request */ 00315 00316 #define DMA_REQUEST_HASH_IN 94U /*!< DMAMUX1 HASH IN request */ 00317 00318 #else 00319 00320 #define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ 00321 #define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ 00322 00323 #define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ 00324 #define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ 00325 00326 #define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ 00327 #define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ 00328 #define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ 00329 #define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ 00330 #define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ 00331 #define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ 00332 00333 #define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ 00334 #define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ 00335 #define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ 00336 #define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ 00337 #define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ 00338 #define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ 00339 #define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ 00340 #define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ 00341 00342 #define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ 00343 #define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ 00344 #define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ 00345 #define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ 00346 #define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ 00347 #define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ 00348 00349 #define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ 00350 #define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ 00351 #define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ 00352 #define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ 00353 00354 #define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ 00355 #define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ 00356 00357 #define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ 00358 #define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ 00359 #define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ 00360 #define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ 00361 00362 #define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ 00363 #define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ 00364 00365 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ 00366 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ 00367 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ 00368 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ 00369 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ 00370 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ 00371 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ 00372 00373 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ 00374 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ 00375 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ 00376 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ 00377 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ 00378 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ 00379 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ 00380 00381 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ 00382 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ 00383 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ 00384 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ 00385 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ 00386 00387 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ 00388 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ 00389 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ 00390 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ 00391 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ 00392 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ 00393 00394 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ 00395 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ 00396 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ 00397 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ 00398 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ 00399 00400 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ 00401 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ 00402 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ 00403 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ 00404 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ 00405 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ 00406 00407 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ 00408 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ 00409 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ 00410 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ 00411 00412 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ 00413 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ 00414 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ 00415 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ 00416 00417 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ 00418 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ 00419 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ 00420 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ 00421 00422 #define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ 00423 00424 #define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ 00425 #define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ 00426 00427 #define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ 00428 #endif /* STM32L4P5xx || STM32L4Q5xx */ 00429 00430 #endif /* DMAMUX1 */ 00431 00432 /** 00433 * @} 00434 */ 00435 00436 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 00437 * @{ 00438 */ 00439 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00440 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 00441 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 00442 /** 00443 * @} 00444 */ 00445 00446 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 00447 * @{ 00448 */ 00449 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 00450 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 00451 /** 00452 * @} 00453 */ 00454 00455 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 00456 * @{ 00457 */ 00458 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 00459 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 00460 /** 00461 * @} 00462 */ 00463 00464 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 00465 * @{ 00466 */ 00467 #define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 00468 #define DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 00469 #define DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 00470 /** 00471 * @} 00472 */ 00473 00474 /** @defgroup DMA_Memory_data_size DMA Memory data size 00475 * @{ 00476 */ 00477 #define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 00478 #define DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 00479 #define DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 00480 /** 00481 * @} 00482 */ 00483 00484 /** @defgroup DMA_mode DMA mode 00485 * @{ 00486 */ 00487 #define DMA_NORMAL 0x00000000U /*!< Normal mode */ 00488 #define DMA_CIRCULAR DMA_CCR_CIRC /*!< Circular mode */ 00489 /** 00490 * @} 00491 */ 00492 00493 /** @defgroup DMA_Priority_level DMA Priority level 00494 * @{ 00495 */ 00496 #define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 00497 #define DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 00498 #define DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 00499 #define DMA_PRIORITY_VERY_HIGH DMA_CCR_PL /*!< Priority level : Very_High */ 00500 /** 00501 * @} 00502 */ 00503 00504 00505 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 00506 * @{ 00507 */ 00508 #define DMA_IT_TC DMA_CCR_TCIE 00509 #define DMA_IT_HT DMA_CCR_HTIE 00510 #define DMA_IT_TE DMA_CCR_TEIE 00511 /** 00512 * @} 00513 */ 00514 00515 /** @defgroup DMA_flag_definitions DMA flag definitions 00516 * @{ 00517 */ 00518 #define DMA_FLAG_GL1 DMA_ISR_GIF1 00519 #define DMA_FLAG_TC1 DMA_ISR_TCIF1 00520 #define DMA_FLAG_HT1 DMA_ISR_HTIF1 00521 #define DMA_FLAG_TE1 DMA_ISR_TEIF1 00522 #define DMA_FLAG_GL2 DMA_ISR_GIF2 00523 #define DMA_FLAG_TC2 DMA_ISR_TCIF2 00524 #define DMA_FLAG_HT2 DMA_ISR_HTIF2 00525 #define DMA_FLAG_TE2 DMA_ISR_TEIF2 00526 #define DMA_FLAG_GL3 DMA_ISR_GIF3 00527 #define DMA_FLAG_TC3 DMA_ISR_TCIF3 00528 #define DMA_FLAG_HT3 DMA_ISR_HTIF3 00529 #define DMA_FLAG_TE3 DMA_ISR_TEIF3 00530 #define DMA_FLAG_GL4 DMA_ISR_GIF4 00531 #define DMA_FLAG_TC4 DMA_ISR_TCIF4 00532 #define DMA_FLAG_HT4 DMA_ISR_HTIF4 00533 #define DMA_FLAG_TE4 DMA_ISR_TEIF4 00534 #define DMA_FLAG_GL5 DMA_ISR_GIF5 00535 #define DMA_FLAG_TC5 DMA_ISR_TCIF5 00536 #define DMA_FLAG_HT5 DMA_ISR_HTIF5 00537 #define DMA_FLAG_TE5 DMA_ISR_TEIF5 00538 #define DMA_FLAG_GL6 DMA_ISR_GIF6 00539 #define DMA_FLAG_TC6 DMA_ISR_TCIF6 00540 #define DMA_FLAG_HT6 DMA_ISR_HTIF6 00541 #define DMA_FLAG_TE6 DMA_ISR_TEIF6 00542 #define DMA_FLAG_GL7 DMA_ISR_GIF7 00543 #define DMA_FLAG_TC7 DMA_ISR_TCIF7 00544 #define DMA_FLAG_HT7 DMA_ISR_HTIF7 00545 #define DMA_FLAG_TE7 DMA_ISR_TEIF7 00546 /** 00547 * @} 00548 */ 00549 00550 /** 00551 * @} 00552 */ 00553 00554 /* Exported macros -----------------------------------------------------------*/ 00555 /** @defgroup DMA_Exported_Macros DMA Exported Macros 00556 * @{ 00557 */ 00558 00559 /** @brief Reset DMA handle state. 00560 * @param __HANDLE__ DMA handle 00561 * @retval None 00562 */ 00563 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 00564 00565 /** 00566 * @brief Enable the specified DMA Channel. 00567 * @param __HANDLE__ DMA handle 00568 * @retval None 00569 */ 00570 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 00571 00572 /** 00573 * @brief Disable the specified DMA Channel. 00574 * @param __HANDLE__ DMA handle 00575 * @retval None 00576 */ 00577 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 00578 00579 00580 /* Interrupt & Flag management */ 00581 00582 /** 00583 * @brief Return the current DMA Channel transfer complete flag. 00584 * @param __HANDLE__ DMA handle 00585 * @retval The specified transfer complete flag index. 00586 */ 00587 00588 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 00589 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 00590 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 00591 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 00592 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 00593 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 00594 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 00595 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 00596 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 00597 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 00598 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 00599 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 00600 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 00601 DMA_FLAG_TC7) 00602 00603 /** 00604 * @brief Return the current DMA Channel half transfer complete flag. 00605 * @param __HANDLE__ DMA handle 00606 * @retval The specified half transfer complete flag index. 00607 */ 00608 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 00609 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 00610 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 00611 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 00612 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 00613 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 00614 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 00615 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 00616 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 00617 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 00618 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 00619 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 00620 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 00621 DMA_FLAG_HT7) 00622 00623 /** 00624 * @brief Return the current DMA Channel transfer error flag. 00625 * @param __HANDLE__ DMA handle 00626 * @retval The specified transfer error flag index. 00627 */ 00628 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 00629 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 00630 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 00631 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 00632 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 00633 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 00634 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 00635 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 00636 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 00637 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 00638 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 00639 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 00640 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 00641 DMA_FLAG_TE7) 00642 00643 /** 00644 * @brief Return the current DMA Channel Global interrupt flag. 00645 * @param __HANDLE__ DMA handle 00646 * @retval The specified transfer error flag index. 00647 */ 00648 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 00649 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 00650 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 00651 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 00652 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 00653 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 00654 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 00655 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 00656 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 00657 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 00658 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 00659 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 00660 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 00661 DMA_ISR_GIF7) 00662 00663 /** 00664 * @brief Get the DMA Channel pending flags. 00665 * @param __HANDLE__ DMA handle 00666 * @param __FLAG__ Get the specified flag. 00667 * This parameter can be any combination of the following values: 00668 * @arg DMA_FLAG_TCx: Transfer complete flag 00669 * @arg DMA_FLAG_HTx: Half transfer complete flag 00670 * @arg DMA_FLAG_TEx: Transfer error flag 00671 * @arg DMA_FLAG_GLx: Global interrupt flag 00672 * Where x can be from 1 to 7 to select the DMA Channel x flag. 00673 * @retval The state of FLAG (SET or RESET). 00674 */ 00675 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 00676 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 00677 00678 /** 00679 * @brief Clear the DMA Channel pending flags. 00680 * @param __HANDLE__ DMA handle 00681 * @param __FLAG__ specifies the flag to clear. 00682 * This parameter can be any combination of the following values: 00683 * @arg DMA_FLAG_TCx: Transfer complete flag 00684 * @arg DMA_FLAG_HTx: Half transfer complete flag 00685 * @arg DMA_FLAG_TEx: Transfer error flag 00686 * @arg DMA_FLAG_GLx: Global interrupt flag 00687 * Where x can be from 1 to 7 to select the DMA Channel x flag. 00688 * @retval None 00689 */ 00690 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 00691 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 00692 00693 /** 00694 * @brief Enable the specified DMA Channel interrupts. 00695 * @param __HANDLE__ DMA handle 00696 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 00697 * This parameter can be any combination of the following values: 00698 * @arg DMA_IT_TC: Transfer complete interrupt mask 00699 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00700 * @arg DMA_IT_TE: Transfer error interrupt mask 00701 * @retval None 00702 */ 00703 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 00704 00705 /** 00706 * @brief Disable the specified DMA Channel interrupts. 00707 * @param __HANDLE__ DMA handle 00708 * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 00709 * This parameter can be any combination of the following values: 00710 * @arg DMA_IT_TC: Transfer complete interrupt mask 00711 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00712 * @arg DMA_IT_TE: Transfer error interrupt mask 00713 * @retval None 00714 */ 00715 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 00716 00717 /** 00718 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 00719 * @param __HANDLE__ DMA handle 00720 * @param __INTERRUPT__ specifies the DMA interrupt source to check. 00721 * This parameter can be one of the following values: 00722 * @arg DMA_IT_TC: Transfer complete interrupt mask 00723 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00724 * @arg DMA_IT_TE: Transfer error interrupt mask 00725 * @retval The state of DMA_IT (SET or RESET). 00726 */ 00727 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 00728 00729 /** 00730 * @brief Return the number of remaining data units in the current DMA Channel transfer. 00731 * @param __HANDLE__ DMA handle 00732 * @retval The number of remaining data units in the current DMA Channel transfer. 00733 */ 00734 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 00735 00736 /** 00737 * @} 00738 */ 00739 00740 #if defined(DMAMUX1) 00741 /* Include DMA HAL Extension module */ 00742 #include "stm32l4xx_hal_dma_ex.h" 00743 #endif /* DMAMUX1 */ 00744 00745 /* Exported functions --------------------------------------------------------*/ 00746 00747 /** @addtogroup DMA_Exported_Functions 00748 * @{ 00749 */ 00750 00751 /** @addtogroup DMA_Exported_Functions_Group1 00752 * @{ 00753 */ 00754 /* Initialization and de-initialization functions *****************************/ 00755 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 00756 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 00757 /** 00758 * @} 00759 */ 00760 00761 /** @addtogroup DMA_Exported_Functions_Group2 00762 * @{ 00763 */ 00764 /* IO operation functions *****************************************************/ 00765 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00766 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00767 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 00768 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 00769 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 00770 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 00771 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 00772 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 00773 00774 /** 00775 * @} 00776 */ 00777 00778 /** @addtogroup DMA_Exported_Functions_Group3 00779 * @{ 00780 */ 00781 /* Peripheral State and Error functions ***************************************/ 00782 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 00783 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 00784 /** 00785 * @} 00786 */ 00787 00788 /** 00789 * @} 00790 */ 00791 00792 /* Private macros ------------------------------------------------------------*/ 00793 /** @defgroup DMA_Private_Macros DMA Private Macros 00794 * @{ 00795 */ 00796 00797 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 00798 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 00799 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 00800 00801 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 00802 00803 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 00804 ((STATE) == DMA_PINC_DISABLE)) 00805 00806 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 00807 ((STATE) == DMA_MINC_DISABLE)) 00808 00809 #if !defined (DMAMUX1) 00810 00811 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 00812 ((REQUEST) == DMA_REQUEST_1) || \ 00813 ((REQUEST) == DMA_REQUEST_2) || \ 00814 ((REQUEST) == DMA_REQUEST_3) || \ 00815 ((REQUEST) == DMA_REQUEST_4) || \ 00816 ((REQUEST) == DMA_REQUEST_5) || \ 00817 ((REQUEST) == DMA_REQUEST_6) || \ 00818 ((REQUEST) == DMA_REQUEST_7)) 00819 #endif 00820 00821 #if defined(DMAMUX1) 00822 00823 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) 00824 00825 #endif /* DMAMUX1 */ 00826 00827 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 00828 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 00829 ((SIZE) == DMA_PDATAALIGN_WORD)) 00830 00831 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 00832 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 00833 ((SIZE) == DMA_MDATAALIGN_WORD )) 00834 00835 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 00836 ((MODE) == DMA_CIRCULAR)) 00837 00838 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 00839 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 00840 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 00841 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 00842 00843 /** 00844 * @} 00845 */ 00846 00847 /* Private functions ---------------------------------------------------------*/ 00848 00849 /** 00850 * @} 00851 */ 00852 00853 /** 00854 * @} 00855 */ 00856 00857 #ifdef __cplusplus 00858 } 00859 #endif 00860 00861 #endif /* STM32L4xx_HAL_DMA_H */
1.7.6.1