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STM32L443xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dsi.h 00004 * @author MCD Application Team 00005 * @brief Header file of DSI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * Copyright (c) 2017 STMicroelectronics. 00010 * All rights reserved. 00011 * 00012 * This software is licensed under terms that can be found in the LICENSE file 00013 * in the root directory of this software component. 00014 * If no LICENSE file comes with this software, it is provided AS-IS. 00015 * 00016 ****************************************************************************** 00017 */ 00018 00019 /* Define to prevent recursive inclusion -------------------------------------*/ 00020 #ifndef STM32L4xx_HAL_DSI_H 00021 #define STM32L4xx_HAL_DSI_H 00022 00023 #ifdef __cplusplus 00024 extern "C" { 00025 #endif 00026 00027 /* Includes ------------------------------------------------------------------*/ 00028 #include "stm32l4xx_hal_def.h" 00029 00030 #if defined(DSI) 00031 00032 /** @addtogroup STM32L4xx_HAL_Driver 00033 * @{ 00034 */ 00035 00036 /** @defgroup DSI DSI 00037 * @brief DSI HAL module driver 00038 * @{ 00039 */ 00040 00041 /* Exported types ------------------------------------------------------------*/ 00042 /** @defgroup DSI_Exported_Types DSI Exported Types 00043 * @{ 00044 */ 00045 /** 00046 * @brief DSI Init Structure definition 00047 */ 00048 typedef struct 00049 { 00050 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control 00051 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ 00052 00053 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division 00054 The values 0 and 1 stop the TX_ESC clock generation */ 00055 00056 uint32_t NumberOfLanes; /*!< Number of lanes 00057 This parameter can be any value of @ref DSI_Number_Of_Lanes */ 00058 00059 } DSI_InitTypeDef; 00060 00061 /** 00062 * @brief DSI PLL Clock structure definition 00063 */ 00064 typedef struct 00065 { 00066 uint32_t PLLNDIV; /*!< PLL Loop Division Factor 00067 This parameter must be a value between 10 and 125 */ 00068 00069 uint32_t PLLIDF; /*!< PLL Input Division Factor 00070 This parameter can be any value of @ref DSI_PLL_IDF */ 00071 00072 uint32_t PLLODF; /*!< PLL Output Division Factor 00073 This parameter can be any value of @ref DSI_PLL_ODF */ 00074 00075 } DSI_PLLInitTypeDef; 00076 00077 /** 00078 * @brief DSI Video mode configuration 00079 */ 00080 typedef struct 00081 { 00082 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 00083 00084 uint32_t ColorCoding; /*!< Color coding for LTDC interface 00085 This parameter can be any value of @ref DSI_Color_Coding */ 00086 00087 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using 00088 18-bit configuration). 00089 This parameter can be any value of @ref DSI_LooselyPacked */ 00090 00091 uint32_t Mode; /*!< Video mode type 00092 This parameter can be any value of @ref DSI_Video_Mode_Type */ 00093 00094 uint32_t PacketSize; /*!< Video packet size */ 00095 00096 uint32_t NumberOfChunks; /*!< Number of chunks */ 00097 00098 uint32_t NullPacketSize; /*!< Null packet size */ 00099 00100 uint32_t HSPolarity; /*!< HSYNC pin polarity 00101 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 00102 00103 uint32_t VSPolarity; /*!< VSYNC pin polarity 00104 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 00105 00106 uint32_t DEPolarity; /*!< Data Enable pin polarity 00107 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 00108 00109 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ 00110 00111 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ 00112 00113 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ 00114 00115 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ 00116 00117 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ 00118 00119 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ 00120 00121 uint32_t VerticalActive; /*!< Vertical active duration */ 00122 00123 uint32_t LPCommandEnable; /*!< Low-power command enable 00124 This parameter can be any value of @ref DSI_LP_Command */ 00125 00126 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 00127 can fit in a line during VSA, VBP and VFP regions */ 00128 00129 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 00130 can fit in a line during VACT region */ 00131 00132 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable 00133 This parameter can be any value of @ref DSI_LP_HFP */ 00134 00135 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable 00136 This parameter can be any value of @ref DSI_LP_HBP */ 00137 00138 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable 00139 This parameter can be any value of @ref DSI_LP_VACT */ 00140 00141 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable 00142 This parameter can be any value of @ref DSI_LP_VFP */ 00143 00144 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable 00145 This parameter can be any value of @ref DSI_LP_VBP */ 00146 00147 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable 00148 This parameter can be any value of @ref DSI_LP_VSYNC */ 00149 00150 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable 00151 This parameter can be any value of @ref DSI_FBTA_acknowledge */ 00152 00153 } DSI_VidCfgTypeDef; 00154 00155 /** 00156 * @brief DSI Adapted command mode configuration 00157 */ 00158 typedef struct 00159 { 00160 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 00161 00162 uint32_t ColorCoding; /*!< Color coding for LTDC interface 00163 This parameter can be any value of @ref DSI_Color_Coding */ 00164 00165 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in 00166 pixels. This parameter can be any value between 0x00 and 0xFFFFU */ 00167 00168 uint32_t TearingEffectSource; /*!< Tearing effect source 00169 This parameter can be any value of @ref DSI_TearingEffectSource */ 00170 00171 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity 00172 This parameter can be any value of @ref DSI_TearingEffectPolarity */ 00173 00174 uint32_t HSPolarity; /*!< HSYNC pin polarity 00175 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 00176 00177 uint32_t VSPolarity; /*!< VSYNC pin polarity 00178 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 00179 00180 uint32_t DEPolarity; /*!< Data Enable pin polarity 00181 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 00182 00183 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted 00184 This parameter can be any value of @ref DSI_Vsync_Polarity */ 00185 00186 uint32_t AutomaticRefresh; /*!< Automatic refresh mode 00187 This parameter can be any value of @ref DSI_AutomaticRefresh */ 00188 00189 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable 00190 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ 00191 00192 } DSI_CmdCfgTypeDef; 00193 00194 /** 00195 * @brief DSI command transmission mode configuration 00196 */ 00197 typedef struct 00198 { 00199 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission 00200 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ 00201 00202 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission 00203 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ 00204 00205 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission 00206 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ 00207 00208 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission 00209 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ 00210 00211 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission 00212 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ 00213 00214 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission 00215 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ 00216 00217 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission 00218 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ 00219 00220 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission 00221 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ 00222 00223 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission 00224 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ 00225 00226 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission 00227 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ 00228 00229 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission 00230 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ 00231 00232 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission 00233 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ 00234 00235 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable 00236 This parameter can be any value of @ref DSI_AcknowledgeRequest */ 00237 00238 } DSI_LPCmdTypeDef; 00239 00240 /** 00241 * @brief DSI PHY Timings definition 00242 */ 00243 typedef struct 00244 { 00245 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed 00246 to low-power transmission */ 00247 00248 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power 00249 to high-speed transmission */ 00250 00251 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed 00252 to low-power transmission */ 00253 00254 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power 00255 to high-speed transmission */ 00256 00257 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ 00258 00259 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the 00260 Stop state */ 00261 00262 } DSI_PHY_TimerTypeDef; 00263 00264 /** 00265 * @brief DSI HOST Timeouts definition 00266 */ 00267 typedef struct 00268 { 00269 uint32_t TimeoutCkdiv; /*!< Time-out clock division */ 00270 00271 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ 00272 00273 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ 00274 00275 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ 00276 00277 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ 00278 00279 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ 00280 00281 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode 00282 This parameter can be any value of @ref DSI_HS_PrespMode */ 00283 00284 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ 00285 00286 uint32_t BTATimeout; /*!< BTA time-out */ 00287 00288 } DSI_HOST_TimeoutTypeDef; 00289 00290 /** 00291 * @brief DSI States Structure definition 00292 */ 00293 typedef enum 00294 { 00295 HAL_DSI_STATE_RESET = 0x00U, 00296 HAL_DSI_STATE_READY = 0x01U, 00297 HAL_DSI_STATE_ERROR = 0x02U, 00298 HAL_DSI_STATE_BUSY = 0x03U, 00299 HAL_DSI_STATE_TIMEOUT = 0x04U 00300 } HAL_DSI_StateTypeDef; 00301 00302 /** 00303 * @brief DSI Handle Structure definition 00304 */ 00305 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00306 typedef struct __DSI_HandleTypeDef 00307 #else 00308 typedef struct 00309 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00310 { 00311 DSI_TypeDef *Instance; /*!< Register base address */ 00312 DSI_InitTypeDef Init; /*!< DSI required parameters */ 00313 HAL_LockTypeDef Lock; /*!< DSI peripheral status */ 00314 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ 00315 __IO uint32_t ErrorCode; /*!< DSI Error code */ 00316 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ 00317 00318 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00319 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ 00320 void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ 00321 void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ 00322 00323 void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ 00324 void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ 00325 00326 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00327 00328 } DSI_HandleTypeDef; 00329 00330 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00331 /** 00332 * @brief HAL DSI Callback ID enumeration definition 00333 */ 00334 typedef enum 00335 { 00336 HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ 00337 HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ 00338 00339 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ 00340 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ 00341 HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ 00342 00343 } HAL_DSI_CallbackIDTypeDef; 00344 00345 /** 00346 * @brief HAL DSI Callback pointer definition 00347 */ 00348 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi); /*!< pointer to an DSI callback function */ 00349 00350 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00351 /** 00352 * @} 00353 */ 00354 00355 /* Exported constants --------------------------------------------------------*/ 00356 /** @defgroup DSI_Exported_Constants DSI Exported Constants 00357 * @{ 00358 */ 00359 /** @defgroup DSI_DCS_Command DSI DCS Command 00360 * @{ 00361 */ 00362 #define DSI_ENTER_IDLE_MODE 0x39U 00363 #define DSI_ENTER_INVERT_MODE 0x21U 00364 #define DSI_ENTER_NORMAL_MODE 0x13U 00365 #define DSI_ENTER_PARTIAL_MODE 0x12U 00366 #define DSI_ENTER_SLEEP_MODE 0x10U 00367 #define DSI_EXIT_IDLE_MODE 0x38U 00368 #define DSI_EXIT_INVERT_MODE 0x20U 00369 #define DSI_EXIT_SLEEP_MODE 0x11U 00370 #define DSI_GET_3D_CONTROL 0x3FU 00371 #define DSI_GET_ADDRESS_MODE 0x0BU 00372 #define DSI_GET_BLUE_CHANNEL 0x08U 00373 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU 00374 #define DSI_GET_DISPLAY_MODE 0x0DU 00375 #define DSI_GET_GREEN_CHANNEL 0x07U 00376 #define DSI_GET_PIXEL_FORMAT 0x0CU 00377 #define DSI_GET_POWER_MODE 0x0AU 00378 #define DSI_GET_RED_CHANNEL 0x06U 00379 #define DSI_GET_SCANLINE 0x45U 00380 #define DSI_GET_SIGNAL_MODE 0x0EU 00381 #define DSI_NOP 0x00U 00382 #define DSI_READ_DDB_CONTINUE 0xA8U 00383 #define DSI_READ_DDB_START 0xA1U 00384 #define DSI_READ_MEMORY_CONTINUE 0x3EU 00385 #define DSI_READ_MEMORY_START 0x2EU 00386 #define DSI_SET_3D_CONTROL 0x3DU 00387 #define DSI_SET_ADDRESS_MODE 0x36U 00388 #define DSI_SET_COLUMN_ADDRESS 0x2AU 00389 #define DSI_SET_DISPLAY_OFF 0x28U 00390 #define DSI_SET_DISPLAY_ON 0x29U 00391 #define DSI_SET_GAMMA_CURVE 0x26U 00392 #define DSI_SET_PAGE_ADDRESS 0x2BU 00393 #define DSI_SET_PARTIAL_COLUMNS 0x31U 00394 #define DSI_SET_PARTIAL_ROWS 0x30U 00395 #define DSI_SET_PIXEL_FORMAT 0x3AU 00396 #define DSI_SET_SCROLL_AREA 0x33U 00397 #define DSI_SET_SCROLL_START 0x37U 00398 #define DSI_SET_TEAR_OFF 0x34U 00399 #define DSI_SET_TEAR_ON 0x35U 00400 #define DSI_SET_TEAR_SCANLINE 0x44U 00401 #define DSI_SET_VSYNC_TIMING 0x40U 00402 #define DSI_SOFT_RESET 0x01U 00403 #define DSI_WRITE_LUT 0x2DU 00404 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU 00405 #define DSI_WRITE_MEMORY_START 0x2CU 00406 /** 00407 * @} 00408 */ 00409 00410 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type 00411 * @{ 00412 */ 00413 #define DSI_VID_MODE_NB_PULSES 0U 00414 #define DSI_VID_MODE_NB_EVENTS 1U 00415 #define DSI_VID_MODE_BURST 2U 00416 /** 00417 * @} 00418 */ 00419 00420 /** @defgroup DSI_Color_Mode DSI Color Mode 00421 * @{ 00422 */ 00423 #define DSI_COLOR_MODE_FULL 0x00000000U 00424 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM 00425 /** 00426 * @} 00427 */ 00428 00429 /** @defgroup DSI_ShutDown DSI ShutDown 00430 * @{ 00431 */ 00432 #define DSI_DISPLAY_ON 0x00000000U 00433 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN 00434 /** 00435 * @} 00436 */ 00437 00438 /** @defgroup DSI_LP_Command DSI LP Command 00439 * @{ 00440 */ 00441 #define DSI_LP_COMMAND_DISABLE 0x00000000U 00442 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE 00443 /** 00444 * @} 00445 */ 00446 00447 /** @defgroup DSI_LP_HFP DSI LP HFP 00448 * @{ 00449 */ 00450 #define DSI_LP_HFP_DISABLE 0x00000000U 00451 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE 00452 /** 00453 * @} 00454 */ 00455 00456 /** @defgroup DSI_LP_HBP DSI LP HBP 00457 * @{ 00458 */ 00459 #define DSI_LP_HBP_DISABLE 0x00000000U 00460 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE 00461 /** 00462 * @} 00463 */ 00464 00465 /** @defgroup DSI_LP_VACT DSI LP VACT 00466 * @{ 00467 */ 00468 #define DSI_LP_VACT_DISABLE 0x00000000U 00469 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE 00470 /** 00471 * @} 00472 */ 00473 00474 /** @defgroup DSI_LP_VFP DSI LP VFP 00475 * @{ 00476 */ 00477 #define DSI_LP_VFP_DISABLE 0x00000000U 00478 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE 00479 /** 00480 * @} 00481 */ 00482 00483 /** @defgroup DSI_LP_VBP DSI LP VBP 00484 * @{ 00485 */ 00486 #define DSI_LP_VBP_DISABLE 0x00000000U 00487 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE 00488 /** 00489 * @} 00490 */ 00491 00492 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC 00493 * @{ 00494 */ 00495 #define DSI_LP_VSYNC_DISABLE 0x00000000U 00496 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE 00497 /** 00498 * @} 00499 */ 00500 00501 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge 00502 * @{ 00503 */ 00504 #define DSI_FBTAA_DISABLE 0x00000000U 00505 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE 00506 /** 00507 * @} 00508 */ 00509 00510 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source 00511 * @{ 00512 */ 00513 #define DSI_TE_DSILINK 0x00000000U 00514 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC 00515 /** 00516 * @} 00517 */ 00518 00519 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity 00520 * @{ 00521 */ 00522 #define DSI_TE_RISING_EDGE 0x00000000U 00523 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL 00524 /** 00525 * @} 00526 */ 00527 00528 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity 00529 * @{ 00530 */ 00531 #define DSI_VSYNC_FALLING 0x00000000U 00532 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL 00533 /** 00534 * @} 00535 */ 00536 00537 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh 00538 * @{ 00539 */ 00540 #define DSI_AR_DISABLE 0x00000000U 00541 #define DSI_AR_ENABLE DSI_WCFGR_AR 00542 /** 00543 * @} 00544 */ 00545 00546 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request 00547 * @{ 00548 */ 00549 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U 00550 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE 00551 /** 00552 * @} 00553 */ 00554 00555 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request 00556 * @{ 00557 */ 00558 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U 00559 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE 00560 /** 00561 * @} 00562 */ 00563 00564 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP 00565 * @{ 00566 */ 00567 #define DSI_LP_GSW0P_DISABLE 0x00000000U 00568 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX 00569 /** 00570 * @} 00571 */ 00572 00573 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP 00574 * @{ 00575 */ 00576 #define DSI_LP_GSW1P_DISABLE 0x00000000U 00577 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX 00578 /** 00579 * @} 00580 */ 00581 00582 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP 00583 * @{ 00584 */ 00585 #define DSI_LP_GSW2P_DISABLE 0x00000000U 00586 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX 00587 /** 00588 * @} 00589 */ 00590 00591 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP 00592 * @{ 00593 */ 00594 #define DSI_LP_GSR0P_DISABLE 0x00000000U 00595 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX 00596 /** 00597 * @} 00598 */ 00599 00600 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP 00601 * @{ 00602 */ 00603 #define DSI_LP_GSR1P_DISABLE 0x00000000U 00604 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX 00605 /** 00606 * @} 00607 */ 00608 00609 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP 00610 * @{ 00611 */ 00612 #define DSI_LP_GSR2P_DISABLE 0x00000000U 00613 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX 00614 /** 00615 * @} 00616 */ 00617 00618 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite 00619 * @{ 00620 */ 00621 #define DSI_LP_GLW_DISABLE 0x00000000U 00622 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX 00623 /** 00624 * @} 00625 */ 00626 00627 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP 00628 * @{ 00629 */ 00630 #define DSI_LP_DSW0P_DISABLE 0x00000000U 00631 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX 00632 /** 00633 * @} 00634 */ 00635 00636 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP 00637 * @{ 00638 */ 00639 #define DSI_LP_DSW1P_DISABLE 0x00000000U 00640 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX 00641 /** 00642 * @} 00643 */ 00644 00645 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP 00646 * @{ 00647 */ 00648 #define DSI_LP_DSR0P_DISABLE 0x00000000U 00649 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX 00650 /** 00651 * @} 00652 */ 00653 00654 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write 00655 * @{ 00656 */ 00657 #define DSI_LP_DLW_DISABLE 0x00000000U 00658 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX 00659 /** 00660 * @} 00661 */ 00662 00663 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet 00664 * @{ 00665 */ 00666 #define DSI_LP_MRDP_DISABLE 0x00000000U 00667 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS 00668 /** 00669 * @} 00670 */ 00671 00672 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode 00673 * @{ 00674 */ 00675 #define DSI_HS_PM_DISABLE 0x00000000U 00676 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM 00677 /** 00678 * @} 00679 */ 00680 00681 00682 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control 00683 * @{ 00684 */ 00685 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U 00686 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR 00687 /** 00688 * @} 00689 */ 00690 00691 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes 00692 * @{ 00693 */ 00694 #define DSI_ONE_DATA_LANE 0U 00695 #define DSI_TWO_DATA_LANES 1U 00696 /** 00697 * @} 00698 */ 00699 00700 /** @defgroup DSI_FlowControl DSI Flow Control 00701 * @{ 00702 */ 00703 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE 00704 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE 00705 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE 00706 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE 00707 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE 00708 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ 00709 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ 00710 DSI_FLOW_CONTROL_EOTP_TX) 00711 /** 00712 * @} 00713 */ 00714 00715 /** @defgroup DSI_Color_Coding DSI Color Coding 00716 * @{ 00717 */ 00718 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ 00719 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ 00720 #define DSI_RGB888 0x00000005U 00721 /** 00722 * @} 00723 */ 00724 00725 /** @defgroup DSI_LooselyPacked DSI Loosely Packed 00726 * @{ 00727 */ 00728 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE 00729 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U 00730 /** 00731 * @} 00732 */ 00733 00734 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity 00735 * @{ 00736 */ 00737 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U 00738 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP 00739 /** 00740 * @} 00741 */ 00742 00743 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity 00744 * @{ 00745 */ 00746 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U 00747 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP 00748 /** 00749 * @} 00750 */ 00751 00752 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity 00753 * @{ 00754 */ 00755 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U 00756 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP 00757 /** 00758 * @} 00759 */ 00760 00761 /** @defgroup DSI_PLL_IDF DSI PLL IDF 00762 * @{ 00763 */ 00764 #define DSI_PLL_IN_DIV1 0x00000001U 00765 #define DSI_PLL_IN_DIV2 0x00000002U 00766 #define DSI_PLL_IN_DIV3 0x00000003U 00767 #define DSI_PLL_IN_DIV4 0x00000004U 00768 #define DSI_PLL_IN_DIV5 0x00000005U 00769 #define DSI_PLL_IN_DIV6 0x00000006U 00770 #define DSI_PLL_IN_DIV7 0x00000007U 00771 /** 00772 * @} 00773 */ 00774 00775 /** @defgroup DSI_PLL_ODF DSI PLL ODF 00776 * @{ 00777 */ 00778 #define DSI_PLL_OUT_DIV1 0x00000000U 00779 #define DSI_PLL_OUT_DIV2 0x00000001U 00780 #define DSI_PLL_OUT_DIV4 0x00000002U 00781 #define DSI_PLL_OUT_DIV8 0x00000003U 00782 /** 00783 * @} 00784 */ 00785 00786 /** @defgroup DSI_Flags DSI Flags 00787 * @{ 00788 */ 00789 #define DSI_FLAG_TE DSI_WISR_TEIF 00790 #define DSI_FLAG_ER DSI_WISR_ERIF 00791 #define DSI_FLAG_BUSY DSI_WISR_BUSY 00792 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS 00793 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF 00794 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF 00795 #define DSI_FLAG_RRS DSI_WISR_RRS 00796 #define DSI_FLAG_RR DSI_WISR_RRIF 00797 /** 00798 * @} 00799 */ 00800 00801 /** @defgroup DSI_Interrupts DSI Interrupts 00802 * @{ 00803 */ 00804 #define DSI_IT_TE DSI_WIER_TEIE 00805 #define DSI_IT_ER DSI_WIER_ERIE 00806 #define DSI_IT_PLLL DSI_WIER_PLLLIE 00807 #define DSI_IT_PLLU DSI_WIER_PLLUIE 00808 #define DSI_IT_RR DSI_WIER_RRIE 00809 /** 00810 * @} 00811 */ 00812 00813 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type 00814 * @{ 00815 */ 00816 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ 00817 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ 00818 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ 00819 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ 00820 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ 00821 /** 00822 * @} 00823 */ 00824 00825 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type 00826 * @{ 00827 */ 00828 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ 00829 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ 00830 /** 00831 * @} 00832 */ 00833 00834 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type 00835 * @{ 00836 */ 00837 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ 00838 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ 00839 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ 00840 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ 00841 /** 00842 * @} 00843 */ 00844 00845 /** @defgroup DSI_Error_Data_Type DSI Error Data Type 00846 * @{ 00847 */ 00848 #define HAL_DSI_ERROR_NONE 0U 00849 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< Acknowledge errors */ 00850 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ 00851 #define HAL_DSI_ERROR_TX 0x00000004U /*!< Transmission error */ 00852 #define HAL_DSI_ERROR_RX 0x00000008U /*!< Reception error */ 00853 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ 00854 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ 00855 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ 00856 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ 00857 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ 00858 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ 00859 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00860 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ 00861 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00862 /** 00863 * @} 00864 */ 00865 00866 /** @defgroup DSI_Lane_Group DSI Lane Group 00867 * @{ 00868 */ 00869 #define DSI_CLOCK_LANE 0x00000000U 00870 #define DSI_DATA_LANES 0x00000001U 00871 /** 00872 * @} 00873 */ 00874 00875 /** @defgroup DSI_Communication_Delay DSI Communication Delay 00876 * @{ 00877 */ 00878 #define DSI_SLEW_RATE_HSTX 0x00000000U 00879 #define DSI_SLEW_RATE_LPTX 0x00000001U 00880 #define DSI_HS_DELAY 0x00000002U 00881 /** 00882 * @} 00883 */ 00884 00885 /** @defgroup DSI_CustomLane DSI CustomLane 00886 * @{ 00887 */ 00888 #define DSI_SWAP_LANE_PINS 0x00000000U 00889 #define DSI_INVERT_HS_SIGNAL 0x00000001U 00890 /** 00891 * @} 00892 */ 00893 00894 /** @defgroup DSI_Lane_Select DSI Lane Select 00895 * @{ 00896 */ 00897 #define DSI_CLK_LANE 0x00000000U 00898 #define DSI_DATA_LANE0 0x00000001U 00899 #define DSI_DATA_LANE1 0x00000002U 00900 /** 00901 * @} 00902 */ 00903 00904 /** @defgroup DSI_PHY_Timing DSI PHY Timing 00905 * @{ 00906 */ 00907 #define DSI_TCLK_POST 0x00000000U 00908 #define DSI_TLPX_CLK 0x00000001U 00909 #define DSI_THS_EXIT 0x00000002U 00910 #define DSI_TLPX_DATA 0x00000003U 00911 #define DSI_THS_ZERO 0x00000004U 00912 #define DSI_THS_TRAIL 0x00000005U 00913 #define DSI_THS_PREPARE 0x00000006U 00914 #define DSI_TCLK_ZERO 0x00000007U 00915 #define DSI_TCLK_PREPARE 0x00000008U 00916 /** 00917 * @} 00918 */ 00919 00920 00921 /** 00922 * @} 00923 */ 00924 00925 /* Exported macros -----------------------------------------------------------*/ 00926 /** @defgroup DSI_Exported_Macros DSI Exported Macros 00927 * @{ 00928 */ 00929 00930 /** 00931 * @brief Reset DSI handle state. 00932 * @param __HANDLE__ DSI handle 00933 * @retval None 00934 */ 00935 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00936 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00937 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ 00938 (__HANDLE__)->MspInitCallback = NULL; \ 00939 (__HANDLE__)->MspDeInitCallback = NULL; \ 00940 } while(0) 00941 #else 00942 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) 00943 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ 00944 00945 /** 00946 * @brief Enables the DSI host. 00947 * @param __HANDLE__ DSI handle 00948 * @retval None. 00949 */ 00950 #define __HAL_DSI_ENABLE(__HANDLE__) do { \ 00951 __IO uint32_t tmpreg = 0x00U; \ 00952 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00953 /* Delay after an DSI Host enabling */ \ 00954 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00955 UNUSED(tmpreg); \ 00956 } while(0U) 00957 00958 /** 00959 * @brief Disables the DSI host. 00960 * @param __HANDLE__ DSI handle 00961 * @retval None. 00962 */ 00963 #define __HAL_DSI_DISABLE(__HANDLE__) do { \ 00964 __IO uint32_t tmpreg = 0x00U; \ 00965 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00966 /* Delay after an DSI Host disabling */ \ 00967 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00968 UNUSED(tmpreg); \ 00969 } while(0U) 00970 00971 /** 00972 * @brief Enables the DSI wrapper. 00973 * @param __HANDLE__ DSI handle 00974 * @retval None. 00975 */ 00976 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ 00977 __IO uint32_t tmpreg = 0x00U; \ 00978 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00979 /* Delay after an DSI warpper enabling */ \ 00980 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00981 UNUSED(tmpreg); \ 00982 } while(0U) 00983 00984 /** 00985 * @brief Disable the DSI wrapper. 00986 * @param __HANDLE__ DSI handle 00987 * @retval None. 00988 */ 00989 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ 00990 __IO uint32_t tmpreg = 0x00U; \ 00991 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00992 /* Delay after an DSI warpper disabling*/ \ 00993 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00994 UNUSED(tmpreg); \ 00995 } while(0U) 00996 00997 /** 00998 * @brief Enables the DSI PLL. 00999 * @param __HANDLE__ DSI handle 01000 * @retval None. 01001 */ 01002 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ 01003 __IO uint32_t tmpreg = 0x00U; \ 01004 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01005 /* Delay after an DSI PLL enabling */ \ 01006 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01007 UNUSED(tmpreg); \ 01008 } while(0U) 01009 01010 /** 01011 * @brief Disables the DSI PLL. 01012 * @param __HANDLE__ DSI handle 01013 * @retval None. 01014 */ 01015 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ 01016 __IO uint32_t tmpreg = 0x00U; \ 01017 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01018 /* Delay after an DSI PLL disabling */ \ 01019 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01020 UNUSED(tmpreg); \ 01021 } while(0U) 01022 01023 /** 01024 * @brief Enables the DSI regulator. 01025 * @param __HANDLE__ DSI handle 01026 * @retval None. 01027 */ 01028 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ 01029 __IO uint32_t tmpreg = 0x00U; \ 01030 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01031 /* Delay after an DSI regulator enabling */ \ 01032 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01033 UNUSED(tmpreg); \ 01034 } while(0U) 01035 01036 /** 01037 * @brief Disables the DSI regulator. 01038 * @param __HANDLE__ DSI handle 01039 * @retval None. 01040 */ 01041 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ 01042 __IO uint32_t tmpreg = 0x00U; \ 01043 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01044 /* Delay after an DSI regulator disabling */ \ 01045 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01046 UNUSED(tmpreg); \ 01047 } while(0U) 01048 01049 /** 01050 * @brief Get the DSI pending flags. 01051 * @param __HANDLE__ DSI handle. 01052 * @param __FLAG__ Get the specified flag. 01053 * This parameter can be any combination of the following values: 01054 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 01055 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 01056 * @arg DSI_FLAG_BUSY : Busy Flag 01057 * @arg DSI_FLAG_PLLLS: PLL Lock Status 01058 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 01059 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 01060 * @arg DSI_FLAG_RRS : Regulator Ready Flag 01061 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 01062 * @retval The state of FLAG (SET or RESET). 01063 */ 01064 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) 01065 01066 /** 01067 * @brief Clears the DSI pending flags. 01068 * @param __HANDLE__ DSI handle. 01069 * @param __FLAG__ specifies the flag to clear. 01070 * This parameter can be any combination of the following values: 01071 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 01072 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 01073 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 01074 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 01075 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 01076 * @retval None 01077 */ 01078 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) 01079 01080 /** 01081 * @brief Enables the specified DSI interrupts. 01082 * @param __HANDLE__ DSI handle. 01083 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. 01084 * This parameter can be any combination of the following values: 01085 * @arg DSI_IT_TE : Tearing Effect Interrupt 01086 * @arg DSI_IT_ER : End of Refresh Interrupt 01087 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01088 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01089 * @arg DSI_IT_RR : Regulator Ready Interrupt 01090 * @retval None 01091 */ 01092 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) 01093 01094 /** 01095 * @brief Disables the specified DSI interrupts. 01096 * @param __HANDLE__ DSI handle 01097 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. 01098 * This parameter can be any combination of the following values: 01099 * @arg DSI_IT_TE : Tearing Effect Interrupt 01100 * @arg DSI_IT_ER : End of Refresh Interrupt 01101 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01102 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01103 * @arg DSI_IT_RR : Regulator Ready Interrupt 01104 * @retval None 01105 */ 01106 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) 01107 01108 /** 01109 * @brief Checks whether the specified DSI interrupt source is enabled or not. 01110 * @param __HANDLE__ DSI handle 01111 * @param __INTERRUPT__ specifies the DSI interrupt source to check. 01112 * This parameter can be one of the following values: 01113 * @arg DSI_IT_TE : Tearing Effect Interrupt 01114 * @arg DSI_IT_ER : End of Refresh Interrupt 01115 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01116 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01117 * @arg DSI_IT_RR : Regulator Ready Interrupt 01118 * @retval The state of INTERRUPT (SET or RESET). 01119 */ 01120 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) 01121 01122 /** 01123 * @} 01124 */ 01125 01126 /* Exported functions --------------------------------------------------------*/ 01127 /** @defgroup DSI_Exported_Functions DSI Exported Functions 01128 * @{ 01129 */ 01130 /** @defgroup DSI_Group1 Initialization and Configuration functions 01131 * @brief Initialization and Configuration functions 01132 * @{ 01133 */ 01134 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); 01135 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); 01136 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); 01137 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); 01138 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); 01139 /* Callbacks Register/UnRegister functions ***********************************/ 01140 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 01141 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, 01142 pDSI_CallbackTypeDef pCallback); 01143 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); 01144 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 01145 /** 01146 * @} 01147 */ 01148 01149 /** @defgroup DSI_Group2 IO operation functions 01150 * @brief IO operation functions 01151 * @{ 01152 */ 01153 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); 01154 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); 01155 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); 01156 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); 01157 /** 01158 * @} 01159 */ 01160 01161 /** @defgroup DSI_Group3 Peripheral Control functions 01162 * @brief Peripheral Control functions 01163 * @{ 01164 */ 01165 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); 01166 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); 01167 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); 01168 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); 01169 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); 01170 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); 01171 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); 01172 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); 01173 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); 01174 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); 01175 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); 01176 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); 01177 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 01178 uint32_t ChannelID, 01179 uint32_t Mode, 01180 uint32_t Param1, 01181 uint32_t Param2); 01182 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 01183 uint32_t ChannelID, 01184 uint32_t Mode, 01185 uint32_t NbParams, 01186 uint32_t Param1, 01187 uint8_t *ParametersTable); 01188 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 01189 uint32_t ChannelNbr, 01190 uint8_t *Array, 01191 uint32_t Size, 01192 uint32_t Mode, 01193 uint32_t DCSCmd, 01194 uint8_t *ParametersTable); 01195 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); 01196 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); 01197 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); 01198 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); 01199 01200 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); 01201 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); 01202 01203 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, 01204 uint32_t Value); 01205 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); 01206 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); 01207 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, 01208 FunctionalState State); 01209 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, 01210 uint32_t Value); 01211 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); 01212 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); 01213 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); 01214 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); 01215 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); 01216 01217 /** 01218 * @} 01219 */ 01220 01221 /** @defgroup DSI_Group4 Peripheral State and Errors functions 01222 * @brief Peripheral State and Errors functions 01223 * @{ 01224 */ 01225 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); 01226 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); 01227 01228 /** 01229 * @} 01230 */ 01231 01232 /** 01233 * @} 01234 */ 01235 01236 /* Private types -------------------------------------------------------------*/ 01237 /* Private defines -----------------------------------------------------------*/ 01238 /* Private variables ---------------------------------------------------------*/ 01239 /* Private constants ---------------------------------------------------------*/ 01240 /** @defgroup DSI_Private_Constants DSI Private Constants 01241 * @{ 01242 */ 01243 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ 01244 /** 01245 * @} 01246 */ 01247 01248 /* Private macros ------------------------------------------------------------*/ 01249 /** @defgroup DSI_Private_Macros DSI Private Macros 01250 * @{ 01251 */ 01252 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) 01253 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ 01254 ((IDF) == DSI_PLL_IN_DIV2) || \ 01255 ((IDF) == DSI_PLL_IN_DIV3) || \ 01256 ((IDF) == DSI_PLL_IN_DIV4) || \ 01257 ((IDF) == DSI_PLL_IN_DIV5) || \ 01258 ((IDF) == DSI_PLL_IN_DIV6) || \ 01259 ((IDF) == DSI_PLL_IN_DIV7)) 01260 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ 01261 ((ODF) == DSI_PLL_OUT_DIV2) || \ 01262 ((ODF) == DSI_PLL_OUT_DIV4) || \ 01263 ((ODF) == DSI_PLL_OUT_DIV8)) 01264 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE)\ 01265 || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) 01266 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE)\ 01267 || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) 01268 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) 01269 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) 01270 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE)\ 01271 || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) 01272 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH)\ 01273 || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) 01274 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH)\ 01275 || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) 01276 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH)\ 01277 || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) 01278 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ 01279 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ 01280 ((VideoModeType) == DSI_VID_MODE_BURST)) 01281 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL)\ 01282 || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) 01283 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) 01284 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE)\ 01285 || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) 01286 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) 01287 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) 01288 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE)\ 01289 || ((LPVActive) == DSI_LP_VACT_ENABLE)) 01290 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) 01291 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) 01292 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE)\ 01293 || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) 01294 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE)\ 01295 || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) 01296 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) 01297 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE)\ 01298 || ((TEPolarity) == DSI_TE_FALLING_EDGE)) 01299 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE)\ 01300 || ((AutomaticRefresh) == DSI_AR_ENABLE)) 01301 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING)\ 01302 || ((VSPolarity) == DSI_VSYNC_RISING)) 01303 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE)\ 01304 || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) 01305 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE)\ 01306 || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) 01307 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE)\ 01308 || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) 01309 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE)\ 01310 || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) 01311 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE)\ 01312 || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) 01313 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE)\ 01314 || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) 01315 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE)\ 01316 || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) 01317 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE)\ 01318 || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) 01319 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE)\ 01320 || ((LP_GLW) == DSI_LP_GLW_ENABLE)) 01321 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE)\ 01322 || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) 01323 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE)\ 01324 || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) 01325 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE)\ 01326 || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) 01327 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE)\ 01328 || ((LP_DLW) == DSI_LP_DLW_ENABLE)) 01329 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE)\ 01330 || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) 01331 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ 01332 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ 01333 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ 01334 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ 01335 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) 01336 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ 01337 ((MODE) == DSI_GEN_LONG_PKT_WRITE)) 01338 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ 01339 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ 01340 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ 01341 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) 01342 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || \ 01343 ((CommDelay) == DSI_SLEW_RATE_LPTX) || \ 01344 ((CommDelay) == DSI_HS_DELAY)) 01345 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) 01346 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS)\ 01347 || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) 01348 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || \ 01349 ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) 01350 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ 01351 ((Timing) == DSI_TLPX_CLK ) || \ 01352 ((Timing) == DSI_THS_EXIT ) || \ 01353 ((Timing) == DSI_TLPX_DATA ) || \ 01354 ((Timing) == DSI_THS_ZERO ) || \ 01355 ((Timing) == DSI_THS_TRAIL ) || \ 01356 ((Timing) == DSI_THS_PREPARE ) || \ 01357 ((Timing) == DSI_TCLK_ZERO ) || \ 01358 ((Timing) == DSI_TCLK_PREPARE)) 01359 01360 /** 01361 * @} 01362 */ 01363 01364 /** 01365 * @} 01366 */ 01367 01368 /** 01369 * @} 01370 */ 01371 #endif /* DSI */ 01372 01373 #ifdef __cplusplus 01374 } 01375 #endif 01376 01377 #endif /* STM32L4xx_HAL_DSI_H */
1.7.6.1